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i965: Set the region of LINE's src0 to <0,1,0>.

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The PRMs say that

   <src0> region must be a replicated scalar
   (with HorzStride = VertStride = 0).

but apparently that doesn't actually apply to all generations. I did
notice when implementing the optimization later in this series that G45
and ILK needed this regioning.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
This commit is contained in:
Matt Turner 2014-08-18 23:14:44 -07:00
parent 9ed8d00ab5
commit 92346db057
1 changed files with 10 additions and 1 deletions
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11
src/mesa/drivers/dri/i965/brw_eu_emit.c
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@ -1040,7 +1040,6 @@ ALU2(DP4)
ALU2(DPH)
ALU2(DP3)
ALU2(DP2)
ALU2(LINE)
ALU2(PLN)
ALU3F(MAD)
ALU3F(LRP)
@ -1135,6 +1134,16 @@ brw_MUL(struct brw_compile *p, struct brw_reg dest,
return brw_alu2(p, BRW_OPCODE_MUL, dest, src0, src1);
}
brw_inst *
brw_LINE(struct brw_compile *p, struct brw_reg dest,
struct brw_reg src0, struct brw_reg src1)
{
src0.vstride = BRW_VERTICAL_STRIDE_0;
src0.width = BRW_WIDTH_1;
src0.hstride = BRW_HORIZONTAL_STRIDE_0;
return brw_alu2(p, BRW_OPCODE_LINE, dest, src0, src1);
}
brw_inst *
brw_F32TO16(struct brw_compile *p, struct brw_reg dst, struct brw_reg src)
{