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i965: Fix sampler on sandybridge

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Sandybridge has not much change on texture sampler with Ironlake.
(cherry picked from commit 956f866030)
This commit is contained in:
Zhenyu Wang 2010-09-17 14:17:06 +08:00 • committed by Ian Romanick
parent 4afb1c8451
commit 922d7e1025
5 changed files with 45 additions and 17 deletions
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29
src/mesa/drivers/dri/i965/brw_eu_emit.c
View file

@ -548,7 +548,7 @@ static void brw_set_sampler_message(struct brw_context *brw,
assert(eot == 0);
brw_set_src1(insn, brw_imm_d(0));
if (intel->gen == 5) {
if (intel->gen >= 5) {
insn->bits3.sampler_gen5.binding_table_index = binding_table_index;
insn->bits3.sampler_gen5.sampler = sampler;
insn->bits3.sampler_gen5.msg_type = msg_type;
@ -557,8 +557,12 @@ static void brw_set_sampler_message(struct brw_context *brw,
insn->bits3.sampler_gen5.response_length = response_length;
insn->bits3.sampler_gen5.msg_length = msg_length;
insn->bits3.sampler_gen5.end_of_thread = eot;
insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_SAMPLER;
insn->bits2.send_gen5.end_of_thread = eot;
if (intel->gen >= 6)
insn->header.destreg__conditionalmod = BRW_MESSAGE_TARGET_SAMPLER;
else {
insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_SAMPLER;
insn->bits2.send_gen5.end_of_thread = eot;
}
} else if (intel->is_g4x) {
insn->bits3.sampler_g4x.binding_table_index = binding_table_index;
insn->bits3.sampler_g4x.sampler = sampler;
@ -1581,6 +1585,7 @@ void brw_SAMPLE(struct brw_compile *p,
GLuint header_present,
GLuint simd_mode)
{
struct intel_context *intel = &p->brw->intel;
GLboolean need_stall = 0;
if (writemask == 0) {
@ -1652,11 +1657,25 @@ void brw_SAMPLE(struct brw_compile *p,
}
{
struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
struct brw_instruction *insn;
/* Sandybridge doesn't have the implied move for SENDs,
* and the first message register index comes from src0.
*/
if (intel->gen >= 6) {
brw_push_insn_state(p);
brw_set_mask_control( p, BRW_MASK_DISABLE );
/* m1 contains header? */
brw_MOV(p, brw_message_reg(msg_reg_nr), src0);
brw_pop_insn_state(p);
src0 = brw_message_reg(msg_reg_nr);
}
insn = next_insn(p, BRW_OPCODE_SEND);
insn->header.predicate_control = 0; /* XXX */
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.destreg__conditionalmod = msg_reg_nr;
if (intel->gen < 6)
insn->header.destreg__conditionalmod = msg_reg_nr;
brw_set_dest(insn, dest);
brw_set_src0(insn, src0);

14
src/mesa/drivers/dri/i965/brw_structs.h
View file

@ -1073,7 +1073,7 @@ struct brw_sampler_state
GLuint mag_filter:3;
GLuint mip_filter:2;
GLuint base_level:5;
GLuint pad:1;
GLuint min_mag_neq:1;
GLuint lod_preclamp:1;
GLuint default_color_mode:1;
GLuint pad0:1;
@ -1085,7 +1085,8 @@ struct brw_sampler_state
GLuint r_wrap_mode:3;
GLuint t_wrap_mode:3;
GLuint s_wrap_mode:3;
GLuint pad:3;
GLuint cube_control_mode:1;
GLuint pad:2;
GLuint max_lod:10;
GLuint min_lod:10;
} ss1;
@ -1099,7 +1100,9 @@ struct brw_sampler_state
struct
{
GLuint pad:19;
GLuint non_normalized_coord:1;
GLuint pad:12;
GLuint address_round:6;
GLuint max_aniso:3;
GLuint chroma_key_mode:1;
GLuint chroma_key_index:2;
@ -1210,10 +1213,9 @@ struct brw_surface_state
struct {
GLuint pad1:16;
GLuint llc_mapping:1;
GLuint mlc_mapping:1;
GLuint cache_control:2;
GLuint gfdt:1;
GLuint gfdt_src:1;
GLuint encrypt:1;
GLuint y_offset:4;
GLuint pad0:1;
GLuint x_offset:7;

2
src/mesa/drivers/dri/i965/brw_tex_layout.c
View file

@ -48,7 +48,7 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
switch (mt->target) {
case GL_TEXTURE_CUBE_MAP:
if (intel->gen == 5) {
if (intel->gen >= 5) {
GLuint align_h = 2;
GLuint level;
GLuint qpitch = 0;

6
src/mesa/drivers/dri/i965/brw_wm_emit.c
View file

@ -1102,7 +1102,7 @@ void emit_tex(struct brw_wm_compile *c,
/* Fill in the shadow comparison reference value. */
if (shadow) {
if (intel->gen == 5) {
if (intel->gen >= 5) {
/* Fill in the cube map array index value. */
brw_MOV(p, brw_message_reg(cur_mrf), brw_imm_f(0));
cur_mrf += mrf_per_channel;
@ -1115,7 +1115,7 @@ void emit_tex(struct brw_wm_compile *c,
cur_mrf += mrf_per_channel;
}
if (intel->gen == 5) {
if (intel->gen >= 5) {
if (shadow)
msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5;
else
@ -1168,7 +1168,7 @@ void emit_txb(struct brw_wm_compile *c,
* from mattering.
*/
if (c->dispatch_width == 16 || intel->gen < 5) {
if (intel->gen == 5)
if (intel->gen >= 5)
msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5;
else
msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;

11
src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
View file

@ -100,10 +100,13 @@ struct wm_sampler_key {
* Sets the sampler state for a single unit based off of the sampler key
* entry.
*/
static void brw_update_sampler_state(struct wm_sampler_entry *key,
static void brw_update_sampler_state(struct brw_context *brw,
struct wm_sampler_entry *key,
drm_intel_bo *sdc_bo,
struct brw_sampler_state *sampler)
{
struct intel_context *intel = &brw->intel;
memset(sampler, 0, sizeof(*sampler));
switch (key->minfilter) {
@ -163,6 +166,10 @@ static void brw_update_sampler_state(struct wm_sampler_entry *key,
sampler->ss1.s_wrap_mode = translate_wrap_mode(key->wrap_s);
sampler->ss1.t_wrap_mode = translate_wrap_mode(key->wrap_t);
if (intel->gen >= 6 &&
sampler->ss0.min_filter != sampler->ss0.mag_filter)
sampler->ss0.min_mag_neq = 1;
/* Cube-maps on 965 and later must use the same wrap mode for all 3
* coordinate dimensions. Futher, only CUBE and CLAMP are valid.
*/
@ -329,7 +336,7 @@ static void upload_wm_samplers( struct brw_context *brw )
if (brw->wm.sdc_bo[i] == NULL)
continue;
brw_update_sampler_state(&key.sampler[i], brw->wm.sdc_bo[i],
brw_update_sampler_state(brw, &key.sampler[i], brw->wm.sdc_bo[i],
&sampler[i]);
}