diff --git a/src/amd/vpelib/inc/vpe_hw_types.h b/src/amd/vpelib/inc/vpe_hw_types.h index d34a8040dd3..1eef7a73ba6 100644 --- a/src/amd/vpelib/inc/vpe_hw_types.h +++ b/src/amd/vpelib/inc/vpe_hw_types.h @@ -79,6 +79,7 @@ union large_integer { enum vpe_plane_addr_type { VPE_PLN_ADDR_TYPE_GRAPHICS = 0, /**< For RGB planes */ VPE_PLN_ADDR_TYPE_VIDEO_PROGRESSIVE, /**< For YCbCr planes */ + VPE_PLN_ADDR_TYPE_PLANAR, /**< For RGB 3-planar case */ }; /** @struct vpe_plane_address @@ -117,6 +118,23 @@ struct vpe_plane_address { chroma_dcc_const_color; /**< DCC constant color of the chroma plane */ } video_progressive; + /** @brief Only used for RGB 3-planar case. Each plane is a struct of two \ref + * PHYSICAL_ADDRESS_LOC to store address and meta address, and one \ref large_integer to + * store dcc constant color. + */ + struct { + PHYSICAL_ADDRESS_LOC y_g_addr; /**< Address of the Y/G plane */ + PHYSICAL_ADDRESS_LOC y_g_meta_addr; /**< Meta address of the Y/G plane */ + union large_integer y_g_dcc_const_color; /**< DCC constant color of the Y/G plane */ + + PHYSICAL_ADDRESS_LOC cb_b_addr; /**< Address of the Cb/B plane */ + PHYSICAL_ADDRESS_LOC cb_b_meta_addr; /**< Meta address of the Cb/B plane */ + union large_integer cb_b_dcc_const_color; /**< DCC constant color of the Cb/B plane */ + + PHYSICAL_ADDRESS_LOC cr_r_addr; /**< Address of the Cr/R plane */ + PHYSICAL_ADDRESS_LOC cr_r_meta_addr; /**< Meta address of the Cr/R plane */ + union large_integer cr_r_dcc_const_color; /**< DCC constant color of the Cr/R plane */ + } planar; }; }; @@ -152,6 +170,14 @@ enum vpe_scan_direction { 2, /**< Right to Left, Bottom to Top. 180 Degree Rotation and no Mirroring */ VPE_SCAN_PATTERN_270_DEGREE = 3, /**< Top to Bottom, Right to Left. 270 Degree Rotation and no Mirroring */ + VPE_SCAN_PATTERN_0_DEGREE_H_MIRROR = 4, /**< Right to Left, Top to Bottom. 0 Degree Rotation and + HMirror or 180 Degree Rotation and VMirror */ + VPE_SCAN_PATTERN_90_DEGREE_V_MIRROR = 5, /**< Bottom to Top, Right to Left. 270 Degree Rotation + and HMirror or 90 Degree Rotation and VMirror */ + VPE_SCAN_PATTERN_180_DEGREE_H_MIRROR = 6, /**< Left to Right, Bottom to Top. 180 Degree Rotation + and HMirror or 0 Degree Rotation and VMirror */ + VPE_SCAN_PATTERN_270_DEGREE_V_MIRROR = 7, /**< Top to Bottom, Left to Right. 90 Degree Rotation + and HMirror or 270 Degree Rotation and VMirror */ }; /** @struct vpe_size @@ -235,6 +261,9 @@ enum vpe_surface_pixel_format { VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102, /**< Swapped and alpha rotated RGB 32 bpp A2 B10 G10 R10 */ VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616, /**< RGB 64 bpp A16 R16 G16 B16 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616, /**< RGB 64 bpp A16 B16 G16 R16 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616, /**< RGB 64 bpp R16 G16 B16 A16 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616, /**< RGB 64 bpp B16 G16 R16 A16 */ VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F, /**< Floating point RGB 64 bpp A16 R16 G16 B16 */ VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F, /**< Floating point swapped RGB 64 bpp A16 B16 G16 R16 */ @@ -253,6 +282,12 @@ enum vpe_surface_pixel_format { VPE_SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT, /**< Swapped Floating point RGB 32 bpp R11 G11 B10 */ VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE, /**< Shared Exponent RGB 32 bpp R9 G9 B9 E5 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_UNORM, /**< RGB 64 bpp UNORM A16 R16 G16 B16 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616_UNORM, /**< RGB 64 bpp UNORM R16 G16 B16 A16 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_SNORM, /**< RGB 64 bpp SNORM A16 R16 G16 B16 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616_SNORM, /**< RGB 64 bpp SNORM R16 G16 B16 A16 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_R8, /**< Monochrome 8 bpp R8 */ + VPE_SURFACE_PIXEL_FORMAT_GRPH_R16, /**< Monochrome 16 bpp R16 */ VPE_SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, /**< Start of YCbCr formats. Used internally.*/ VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr = VPE_SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, /**< Planar YUV 4:2:0 8 bpc Y Cb Cr, AKA NV12*/ @@ -268,9 +303,27 @@ enum vpe_surface_pixel_format { VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbYCr, /**< Packed YUV 4:2:2 8 bpc Y Cb Y Cr */ VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CrYCbY, /**< Packed YUV 4:2:2 8 bpc Cr Y Cb Y */ VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CbYCrY, /**< Packed YUV 4:2:2 8 bpc Cb Y Cr Y */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrYCb, /**< Packed YUV 4:2:2 10 bpc Y Cr Y Cb */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbYCr, /**< Packed YUV 4:2:2 10 bpc Y Cb Y Cr */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CrYCbY, /**< Packed YUV 4:2:2 10 bpc Cr Y Cb Y */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CbYCrY, /**< Packed YUV 4:2:2 10 bpc Cb Y Cr Y */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrYCb, /**< Packed YUV 4:2:2 12 bpc Y Cr Y Cb */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbYCr, /**< Packed YUV 4:2:2 12 bpc Y Cb Y Cr */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CrYCbY, /**< Packed YUV 4:2:2 12 bpc Cr Y Cb Y */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CbYCrY, /**< Packed YUV 4:2:2 12 bpc Cb Y Cr Y */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrCb, /**< Semi-Planar YUV 4:2:2 8 bpc Y Cr Cb */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbCr, /**< Semi-Planar YUV 4:2:2 8 bpc Y Cb Cr */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrCb, /**< Semi-Planar YUV 4:2:2 10 bpc Y Cr Cb */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbCr, /**< Semi-Planar YUV 4:2:2 10 bpc Y Cb Cr */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrCb, /**< Semi-Planar YUV 4:2:2 12 bpc Y Cr Cb */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbCr, /**< Semi-Planar YUV 4:2:2 12 bpc Y Cb Cr */ VPE_SURFACE_PIXEL_FORMAT_SUBSAMPLE_END = - VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CbYCrY, /**< End of chroma sub-sampled formats. Used - internally */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbCr, /**< End of chroma sub-sampled formats. + Used internally */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb12121212, /**< Y416 64 bpp A12 Cr12 Y12 Cb12 */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA12121212, /**< A-rotated Y416 64 bpp Cr12 Y12 Cb12 A12 */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_ALPHA_THRU_LUMA, /**< Alpha plane 8bpc passed as YUV 4:2:0 */ + VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrCbYA8888, /**< AYUV 32 bpp 8 bpc Cb8 Cr8 Y8 A8*/ VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010, /**< Y410 32 bpp A2 Cr10 Y10 Cb10 */ VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102, /**< A-rotated Y410 32 bpp Cr10 Y10 Cb10 A2 */ VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888, /**< AYUV 32 bpp 8 bpc A8 Y8 Cr8 Cb8 */ @@ -281,6 +334,17 @@ enum vpe_surface_pixel_format { VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888, /**< AYUV 32 bpp 8 bpc A8 Y8 Cb8 Cbr */ VPE_SURFACE_PIXEL_FORMAT_VIDEO_END = VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888, /**< End of YCbCr formats. Used internally. */ + + VPE_SURFACE_PIXEL_FORMAT_PLANAR_BEGIN, /**< Full 3 Plane Formats */ + VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_RGB = /**< Planar RGB 8bpc */ + VPE_SURFACE_PIXEL_FORMAT_PLANAR_BEGIN, + VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_YCbCr, /**< Planar YCbCr 8bpc */ + VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB, /**< Planar RGB 16bpc */ + VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_YCbCr, /**< Planar YCbCr 16bpc */ + VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB_FLOAT, /**< Planar RGB FP16 */ + VPE_SURFACE_PIXEL_FORMAT_PLANAR_END = + VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB_FLOAT, /**< End of PLANAR formats. Used + internally. */ VPE_SURFACE_PIXEL_FORMAT_INVALID /**< Used for the formats which are not among the recognized formats. */ }; @@ -338,6 +402,13 @@ struct vpe_scaling_taps { uint32_t h_taps_c; /**< Number of horizontal taps for chroma plane */ }; +/** @enum vpe_3dlut_mem_align + * @brief 3DLUT dma buffer alignment + */ +enum vpe_3dlut_mem_align { + VPE_3DLUT_ALIGNMENT_128 = 0, /**< 32 bytes alignment */ + VPE_3DLUT_ALIGNMENT_256 = 1, /**< 64 bytes alignment */ +}; #ifdef __cplusplus } #endif diff --git a/src/amd/vpelib/inc/vpe_types.h b/src/amd/vpelib/inc/vpe_types.h index 08401e59520..d16415f35f8 100644 --- a/src/amd/vpelib/inc/vpe_types.h +++ b/src/amd/vpelib/inc/vpe_types.h @@ -47,6 +47,7 @@ struct vpe; * VPE library supports up to 8 taps and 64 phases, only (32+1) phases needed */ #define MAX_NB_POLYPHASE_COEFFS (8 * 33) +#define VPE_FROD_MAX_STAGE 3 /** @enum vpe_status * @brief The status of VPE to indicate whether it supports the given job or not. @@ -94,6 +95,10 @@ enum vpe_status { VPE_STATUS_SCALER_NOT_SET, /**< Scaler parameters are not set. */ VPE_STATUS_GEOMETRICSCALING_ERROR, /**< Geometric scaling is not supported for the given case. */ + VPE_INVALID_HISTOGRAM_SELECTION, + VPE_STATUS_HISTOGRAM_NOT_SUPPORTED, /**< Histogram is not supported. */ + VPE_STATUS_FROD_NOT_SUPPORTED, /**< FROD is not supported. */ + VPE_STATUS_LUT_COMPOUND_NOT_SUPPORTED, /**< LUT Compound (CSC+1D+3D) is not supported. */ }; /***************************************************** @@ -125,8 +130,38 @@ enum vpe_ip_level { VPE_IP_LEVEL_UNKNOWN = (-1), VPE_IP_LEVEL_1_0, /**< vpe 1.0 */ VPE_IP_LEVEL_1_1, /**< vpe 1.1 */ + VPE_IP_LEVEL_2_0, /**< vpe 2.0 */ }; +enum vpe_mps_mode { + VPE_MPS_DISABLED = 0, + VPE_MPS_BLENDING_ONLY, + VPE_MPS_ENABLED +}; + +enum vpe_hist_collection_mode { + VPE_HISTOGRAM_NONE = 0, /**< Disable histogram collection in channel 0. */ + VPE_HISTOGRAM_R_Cr, /**< Create a histogram from R or Cr for RGB/YCbCr input surfaces respectivley. */ + VPE_HISTOGRAM_G_Y, /**< Create a histogram from G or Y for RGB/YCbCr input surfaces respectivley */ + VPE_HISTOGRAM_B_CB, /**< Create a histogram from B or Cb for RGB/YCbCr input surfaces respectivley */ + VPE_HISTOGRAM_MAX_RGB_YCbCr, /**< Create a histogram from MAX(R,G,B) or MAX(Y,Cb,Cr) for RGB/YCbCr input surfaces respectivley */ + VPE_HISTOGRAM_RGB_TRANSFORMED_Y, /**< Create a histogram of luma from transformed RGB. If the input surfae is YCbCr, this mode wll default to collecting Y directly. */ + VPE_HISTOGRAM_MIN_RGB_YCbCr, /**< Create a histogram from MIN(R,G,B) or MIN (Y,Cb,Cr) for RGB/YCbCr input surfaces respectivley */ + VPE_HISTOGRAM_LAST_TYPE +}; + +enum hist_channels { + hist_channel1 = 0, + hist_channel2, + hist_channel3, + hist_max_channel +}; + +static const enum vpe_hist_collection_mode channel_hist_allowed_mode[hist_max_channel][2] = { + {VPE_HISTOGRAM_R_Cr, VPE_HISTOGRAM_MAX_RGB_YCbCr}, + {VPE_HISTOGRAM_G_Y, VPE_HISTOGRAM_RGB_TRANSFORMED_Y}, + {VPE_HISTOGRAM_B_CB, VPE_HISTOGRAM_MIN_RGB_YCbCr} }; + /**************************************** * Plane Caps ****************************************/ @@ -142,6 +177,19 @@ struct vpe_pixel_format_support { uint32_t p016 : 1; /**< planar 4:2:0 16-bits */ uint32_t ayuv : 1; /**< packed 4:4:4 8-bits */ uint32_t yuy2 : 1; /**< packed 4:2:2 8-bits */ + uint32_t y210 : 1; /**< packed 4:2:2 10-bit */ + uint32_t y216 : 1; /**< packed 4:2:2 16-bit */ + uint32_t p210 : 1; /**< planar 4:2:2 10-bit */ + uint32_t p216 : 1; /**< planar 4:2:2 16-bit */ + uint32_t rgb8_planar : 1; /**< planar RGB 8-bit */ + uint32_t rgb16_planar : 1; /**< planar RGB 16-bit */ + uint32_t yuv8_planar : 1; /**< planar YUV 16-bit */ + uint32_t yuv16_planar : 1; /**< planar YUV 16-bit */ + uint32_t fp16_planar : 1; /**< planar RGB 8-bit */ + uint32_t rgbe : 1; /**< shared exponent R9G9B9E5 */ + uint32_t rgb111110_fix : 1; /**< fixed R11G11B10 */ + uint32_t rgb111110_float : 1; /**< float R11G11B10 */ + uint32_t argb_packed_64b : 1; /**< Packed RGBA formats 64-bits per pixel */ }; /** @struct vpe_plane_caps @@ -163,6 +211,8 @@ struct vpe_plane_caps { uint32_t pitch_alignment; /**< Pitch alignment in bytes */ uint32_t addr_alignment; /**< Plane address alignment in bytes */ uint32_t max_viewport_width; /**< Maximum viewport size */ + uint32_t max_viewport_width_64bpp; /**< Maximum viewport size for 64bpp formats with 90/270 + degrees rotation */ }; /************************* @@ -196,6 +246,40 @@ struct dpp_color_caps { struct vpe_rom_curve_caps dgam_rom_caps; /**< Dgam Rom Caps */ }; +/** @struct lut_caps + * @brief LUT (Look-Up Table) capabilities + * This structure defines the capabilities for LUT shaper and 3D LUTs. + */ +struct vpe_lut_caps { + struct { + uint32_t dma_data : 1; /**< DMA data support */ + uint32_t dma_config : 1; /**< DMA configuration support */ + uint32_t non_monotonic : 1; /**< Non-monotonic LUT support */ + uint16_t data_alignment; /**< Data alignment in bytes */ + uint16_t config_alignment; /**< Configuration alignment in bytes */ + uint16_t config_padding; /**< Configuration padding in bytes */ + uint16_t data_size; /**< Data size in bytes */ + uint16_t config_size; /**< Configuration size in bytes */ + uint16_t data_pts_per_channel; /**< Number data of points per channel */ + } lut_shaper_caps; + + struct { + uint32_t data_dim_9 : 1; /**< Support for 9x9x9 3D LUT */ + uint32_t data_dim_17 : 1; /**< Support for 17x17x17 3D LUT */ + uint32_t data_dim_33 : 1; /**< Support for 33x33x33 3D LUT */ + union { + struct { + uint32_t dma_dim_9 : 1; /**< DMA support for 9x9x9 3D LUT */ + uint32_t dma_dim_17 : 1; /**< DMA support for 17x17x17 3D LUT */ + uint32_t dma_dim_33 : 1; /**< DMA support for 33x33x33 3D LUT */ + }; + uint32_t dma; /**< Any DMA support if set */ + }; + uint16_t alignment; /**< 3D lUT Alignment in bytes */ + } lut_3dlut_caps; + + uint32_t lut_3d_compound : 1; /**< Support for 3D LUT compound */ +}; /** @struct mpc_color_caps * @brief Color management caps for mpc layer */ @@ -207,6 +291,26 @@ struct mpc_color_caps { uint32_t global_alpha : 1; /**< e.g. top plane 30 %. bottom 70 % */ uint32_t top_bottom_blending : 1; /**< two-layer blending */ + uint32_t dma_3d_lut : 1; /**< DMA mode support for 3D LUT, Legacy interface, will be replaced by + vpe_lut_caps*/ + uint32_t yuv_linear_blend : 1; /**< Support for linear blending of 3D LUT YUV output */ + struct { + uint32_t dim_9 : 1; /**< 3D LUT support for 9x9x9 ,Legacy interface, will be replaced by + vpe_lut_caps*/ + uint32_t dim_17 : 1; /**< 3D LUT support for 17x17x17, Legacy interface, will be replaced by + vpe_lut_caps */ + uint32_t dim_33 : 1; /**< 3D LUT support for 33x33x33, Legacy interface, will be replaced by + vpe_lut_caps */ + } lut_dim_caps; + + struct { + uint32_t lut_3d_17 : 1; /**< 3D LUT 17x17x17 container fastload support, default 0,Legacy + interface, will be replaced by vpe_lut_caps */ + uint32_t lut_3d_33 : 1; /**< 3D LUT 33x33x33 container fastload support, default 0,Legacy + interface, will be replaced by vpe_lut_caps */ + } fast_load_caps; + + struct vpe_lut_caps lut_caps; /**< LUT capabilities for shaper and 3D LUT configurations. */ }; /** @struct vpe_color_caps @@ -251,6 +355,22 @@ struct vpe_caps { struct vpe_color_caps color_caps; /**< Color management caps */ struct vpe_plane_caps plane_caps; /**< Plane capabilities */ + uint32_t input_dcc_support : 1; /**< Input DCC support */ + uint32_t input_internal_dcc : 1; /**< Input internal DCC */ + uint32_t output_dcc_support : 1; /**< Output DCC support */ + uint32_t output_internal_dcc : 1; /**< Output internal DCC */ + uint32_t histogram_support : 1; /**< Histogram support */ + uint32_t frod_support : 1; /**< FROD support */ + uint32_t alpha_blending_support : 1; /**< Alpha blending support */ + uint32_t easf_support : 1; /**< edge adaptive scaling support */ + struct { + bool support; /**< iSharp support */ + struct { + uint32_t min; /**< iSharp min level */ + uint32_t max; /**< iSharp max level */ + uint32_t step; /**< iSharp level steps */ + } range; + } isharp_caps; struct { uint32_t opaque : 1; uint32_t bg_color : 1; @@ -313,6 +433,7 @@ struct vpe_surface_dcc_cap { bool capable; /**< DCC capable */ bool const_color_support; /**< DCC const color support */ + bool is_internal_dcc; }; /**************************************** @@ -421,7 +542,8 @@ struct vpe_visual_confirm { struct { uint32_t input_format : 1; /**< input format, 0: disable, 1: enable*/ uint32_t output_format : 1; /**< output format, 0: disable, 1: enable*/ - uint32_t reserved : 30; /**< reserved */ + uint32_t pipe_idx : 1; /**< pipe index, 0: disable, 1: enable*/ + uint32_t reserved : 29; /**< reserved */ }; uint32_t value; /**< confirm value */ }; @@ -460,7 +582,11 @@ struct vpe_debug_options { uint32_t skip_optimal_tap_check : 1; /**< Skip optimal tap check */ uint32_t disable_lut_caching : 1; /**< disable config caching for all luts */ uint32_t disable_performance_mode : 1; /**< disable performance mode */ - uint32_t reserved : 8; + uint32_t multi_pipe_segmentation_policy : 1; /**< policy for when to use MPS feature */ + uint32_t opp_background_gen : 1; /**< generate bg color in opp (default mpc) */ + uint32_t subsampling_quality : 1; /**< subsample quality */ + uint32_t disable_3dlut_fl : 1; /**< disable 3dlut fastloading */ + uint32_t reserved : 4; } flags; /**< debug flags */ // valid only if the corresponding flag is set @@ -485,6 +611,10 @@ struct vpe_debug_options { uint32_t skip_optimal_tap_check : 1; /**< Skip optimal tap check */ uint32_t disable_lut_caching : 1; /**< disable config caching for all luts */ uint32_t disable_performance_mode : 1; /**< disable performance mode */ + uint32_t multi_pipe_segmentation_policy : 2; /**< policy mode for when to use MPS */ + uint32_t opp_background_gen : 1; /**< switch bg gen to OPP */ + uint32_t subsampling_quality : 2; /**< subsample quality */ + uint32_t disable_3dlut_fl : 1; /**< disable 3dlut fastloading */ uint32_t bg_bit_depth; /**< Background color bit depth. */ struct vpe_mem_low_power_enable_options @@ -685,6 +815,30 @@ struct vpe_blend_info { float global_alpha_value; /**< Global alpha value. In range of 0.0-1.0 */ }; +/** @struct vpe_sharpness_range + * @brief Specifies the sharpness to be applied by the scaler (DSCL) + */ +struct vpe_sharpness_range { + int sdr_rgb_min; /**< SDR RGB sharpness min */ + int sdr_rgb_max; /**< SDR RGB sharpness max */ + int sdr_rgb_mid; /**< SDR RGB sharpness mid */ + int sdr_yuv_min; /**< SDR YUV sharpness min */ + int sdr_yuv_max; /**< SDR YUV sharpness max */ + int sdr_yuv_mid; /**< SDR YUV sharpness mid */ + int hdr_rgb_min; /**< HDR RGB sharpness min */ + int hdr_rgb_max; /**< HDR RGB sharpness max */ + int hdr_rgb_mid; /**< HDR RGB sharpness mid */ +}; + +/** @struct vpe_adaptive_sharpness + * @brief Adaptive sharpness parameters + */ +struct vpe_adaptive_sharpness { + bool enable; /**< Enable adaptive sharpness */ + unsigned int sharpness_level; /**< Sharpness level */ + struct vpe_sharpness_range sharpness_range; /**< Sharpness range */ +}; + /** @struct vpe_scaling_info * @brief Data needs to calculate scaling data. */ @@ -695,6 +849,11 @@ struct vpe_scaling_info { * If taps are set to 0, vpe internally calculates the * required number of taps based on the scaling ratio. */ + // Adaptive scaling and sharpening params + struct vpe_adaptive_sharpness adaptive_sharpeness; /**< Adaptive scaler sharpness mode. */ + bool enable_easf; /**< Enable edge adaptive scaling */ + bool prefer_easf; /**< Edge adaptive scaling is prefered if + can be performed. */ }; /** @struct vpe_scaling_filter_coeffs @@ -715,6 +874,12 @@ struct vpe_scaling_filter_coeffs { vertical polyphase scaling */ }; +struct vpe_frod_param { + union { + uint8_t enable_frod; + }; +}; + /** @struct vpe_hdr_metadata * @brief HDR metadata */ @@ -742,6 +907,72 @@ struct vpe_reserved_param { uint32_t size; /**< Size of the reserved parameter */ }; +/** @struct vpe_lut_mem_layout + * @brief vpe 3D-LUT memory layout + */ +enum vpe_lut_type { + VPE_LUT_TYPE_CPU = 0, /**< CPU accessible 3D LUT data, 3 channel, 16 bits depth per channel */ + VPE_LUT_TYPE_GPU_1D_PACKED = + 1, /**< GPU accessible 3D LUT data, 1D packed, 4 channel, 16 bits depth per channel */ + VPE_LUT_TYPE_GPU_3D_SWIZZLE = + 2, /**< GPU accessible 3D LUT data, 3D surface 4 channel, 16 bits depth per channel */ +}; + +// Track offset of bkgr streams relative to first stream (alpha) +enum vpe_bkgr_stream_offset { + VPE_BKGR_STREAM_ALPHA_OFFSET = 0, /**< background stream alpha offset */ + VPE_BKGR_STREAM_VIDEO_OFFSET = 1, /**< background stream video offset */ + VPE_BKGR_STREAM_BACKGROUND_OFFSET = 2, /**< background stream background offset */ + VPE_BKGR_STREAM_INTERMEDIATE_OFFSET = 3, /**< background stream intermediate offset */ +}; + +/** @struct vpe_3dlut_compound + * This structure encapsulates auxiliary parameters required for describing a 3D LUT (Look-Up Table) + * operation - whether this is the 3d lut compound case, cositing info for upsampling, 3dlut output + * CS, and 3x4 csc matrix. + * + * @var vpe_3dlut_compound::enabled + * Indicates if the LUT Compound is enabled. + * @var vpe_3dlut_compound::upsampledChromaInput + * Chroma cositing mode for upsampling input. + * @var vpe_3dlut_compound::primaries3D + * Color primaries for the 3D LUT output. + * Note that this is different from stream input/output color space. + * @var vpe_3dlut_compound::pCscMatrix + * 3x4 color space conversion matrix. + */ +struct vpe_3dlut_compound { + bool enabled; + enum vpe_chroma_cositing upsampled_chroma_input; + enum vpe_color_primaries primaries_3D; + struct vpe_color_space out_cs_3D; + + float pCscMatrix[3][4]; +}; + +struct vpe_dma_shaper { + bool enabled; + uint64_t data; /**< Accessible to GPU. */ + uint64_t config_data; /**< Accessible to GPU. */ + uint32_t *data_cpu; /**< Accessible to CPU. */ + uint32_t *config_data_cpu; /**< Accessible to CPU. */ + uint8_t tmz; /**< tmz bits for shaper */ +}; + +struct vpe_dma_3dlut { + uint64_t data; /**< Accessible to GPU. Only for fast load */ + enum vpe_surface_pixel_format format; /**< DMA lut data format */ + enum vpe_3dlut_mem_align mem_align; /**< DMA lut memory alignment */ + float bias; /**< DMA lut bias */ + float scale; /**< DMA lut scale */ + uint8_t tmz; /**< tmz bits for 3dlut */ +}; + +struct vpe_dma_info { + struct vpe_dma_3dlut lut3d; /**< DMA 3D LUT parameters */ + struct vpe_dma_shaper shaper; /**< DMA shaper parameters */ +}; + /** @struct vpe_tonemap_params * @brief Tone mapping parameters */ @@ -760,6 +991,7 @@ struct vpe_tonemap_params { factor. */ uint16_t lut_dim; /**< Size of one dimension of the 3D-LUT data*/ uint16_t lut_container_dim; /**< Size of one dimension of the 3D-LUT container*/ + enum vpe_lut_type lut_type; /**< LUT data type. If type is GPU, use vpe_dma_info */ uint16_t *lut_data; /**< Accessible to CPU */ bool enable_3dlut; /**< Enable/Disable 3D-LUT */ }; @@ -792,6 +1024,28 @@ struct vpe_color_keyer { float upper_a_bound; /**< Alpha High Bound. Program 1.0f if no alpha channel in input format.*/ }; +/** @struct vpe_histogram +* @brief Histogram collection parameters +* VPE can collect up to 3 separate histograms with 256 bins each. +* Internally there are two binning modes. One for integer input surface formats and one for float input surface formats. +* +* Integer Mode : Pixels are evenly binned with each bin having a width of(2 ^ bitdepth) - 1 / 256 +* +* Float Mode : The internal float format used for binning is fp16(1.5.10).The bin indeces are first divided +* into two major groups. Bins 0 - 127 are for postivie pixels, bins 128 - 255 are for negative pixels. +* Each major group is further subdivided into 32 exponent bin groups. (A mantissa of 5 gives 32 possible values) +* Finally, the bin groups of size 4 are index by the two MSB of the mantissa to determine the bin index of the pixel. +*/ +struct vpe_collection_param { + enum vpe_hist_collection_mode hist_types;/**< histogram collection types*/ + struct vpe_surface_info hist_output;/**< histogram output surface*/ +}; + +struct vpe_histogram_param { + struct vpe_collection_param hist_collection_param[hist_max_channel];/**< histogram collection parameters: type and output surface*/ + uint32_t hist_format; /**< histogram collection data format:0 for integer, 1 and 2 for fp16 */ + uint32_t hist_dsets; /**< number of histogram data sets: 0, 1, 2 */ +}; /** @struct vpe_stream * @brief Input stream/frame properties to be passed to vpelib */ @@ -803,6 +1057,8 @@ struct vpe_stream { contrast, hue and saturation.*/ struct vpe_tonemap_params tm_params; /**< Tone mapping parameters*/ struct vpe_hdr_metadata hdr_metadata; /**< HDR metadata */ + struct vpe_dma_info dma_info; /**< DMA / fast load params */ + struct vpe_3dlut_compound lut_compound; /**< 3D LUT compound params */ struct vpe_scaling_filter_coeffs polyphase_scaling_coeffs; /**< Filter coefficients for polyphase scaling. */ enum vpe_rotation_angle rotation; /**< Rotation angle of the @@ -825,6 +1081,10 @@ struct vpe_stream { enum vpe_keyer_mode keyer_mode; /**< Set Keyer Behavior. * Used for both Luma & Color Keying. */ + struct vpe_surface_info intermediate_surface; /**< Intermediate stream for two pass operations + * this surface is allocated by caller. + * Set addr to 0 if unused */ + struct vpe_histogram_param hist_params; /**< Parameters related to the histogram collection*/ struct vpe_reserved_param reserved_param; /**< Reserved parameter for input surface */ /** @brief stream feature flags @@ -837,7 +1097,39 @@ struct vpe_stream { * as well as blending. * Destination rect must equal to target rect. */ - uint32_t reserved : 30; /**< reserved */ + /** + * Flags for Background Replacement (BKGR) and Alpha Combine feature + * + * BKGR requires 3 or 4 inputs: + * For one pass: + * AlphaStream, VideoStream, BackgroundStream + * For two pass: + * AlphaStream, VideoStream, BackgroundStream, Intermediate Surface + * + * For two-pass BKGR, an intermediate surface is required to store results of first pass + * + * stream[i] is the alpha stream passed as NV12. + * Format must be VPE_SURFACE_PIXEL_FORMAT_VIDEO_ALPHA_THRU_LUMA + * is_alpha_combine = 1; is_alpha_plane = 1; is_background_plane = 0; + * + * stream[i+1] is the video stream that will have its background removed (and replaced if + * BKGR) is_alpha_combine = 1; is_alpha_plane = 0; is_background_plane = 0; + * + * If only doing alpha combine, only first 2 streams are required. For BKGR: + * stream[i+2] is the background stream + * is_alpha_combine = 0; is_alpha_plane = 0; is_background_plane = 1; + * + * If two pass: stream[i+3] is the intermediate surface. Format == FP16 + * if src stream downscaling: Size == dst rect (downscaled src rect) + * else: Size == src rect + * for one pass we don't need this stream + * + * Ordering also tracked in enum vpe_bkgr_stream_offset + */ + uint32_t is_background_plane : 1; /**< is this stream the new background */ + uint32_t is_alpha_combine : 1; /**< set if part of the alpha combine operation */ + uint32_t is_alpha_plane : 1; /**< is this the alpha through luma plane */ + uint32_t reserved : 27; /**< reserved */ } flags; /**< Data flags */ }; @@ -884,6 +1176,9 @@ struct vpe_build_param { uint16_t num_instances; /**< Number of instances for the collaboration mode */ bool collaboration_mode; /**< Collaboration mode. If set, multiple instances of VPE being used. */ + bool enable_frod; + struct vpe_surface_info frod_surface[VPE_FROD_MAX_STAGE]; /**< FROD outputs */ + struct vpe_frod_param frod_param; /**< FROD parameters */ }; /** @struct vpe_bufs_req diff --git a/src/amd/vpelib/meson.build b/src/amd/vpelib/meson.build index 87085ec53e6..73e17a86b45 100644 --- a/src/amd/vpelib/meson.build +++ b/src/amd/vpelib/meson.build @@ -24,6 +24,7 @@ c_args_vpe += [ '-DVPE_BUILD_1_0', '-DVPE_BUILD_1_X', '-DVPE_BUILD_1_1', + '-DVPE_BUILD_2_0', ] vpe_files = files( @@ -124,7 +125,31 @@ vpe_files = files( 'src/chip/vpe11/inc/vpe11_vpe_desc_writer.h', 'src/chip/vpe11/vpe11_cmd_builder.c', 'src/chip/vpe11/vpe11_resource.c', - 'src/chip/vpe11/vpe11_vpe_desc_writer.c' + 'src/chip/vpe11/vpe11_vpe_desc_writer.c', + 'src/core/inc/multi_pipe_segmentation.h', + 'src/core/multi_pipe_segmentation.c', + 'src/core/vpe_spl_translation.c', + 'src/chip/vpe20/inc/vpe20_resource.h', + 'src/chip/vpe20/vpe20_cdc_be.c', + 'src/chip/vpe20/vpe20_cdc_fe.c', + 'src/chip/vpe20/vpe20_cmd_builder.c', + 'src/chip/vpe20/vpe20_config_writer.c', + 'src/chip/vpe20/vpe20_dpp_cm.c', + 'src/chip/vpe20/vpe20_dpp_dscl.c', + 'src/chip/vpe20/vpe20_dpp.c', + 'src/chip/vpe20/vpe20_mpc.c', + 'src/chip/vpe20/vpe20_opp.c', + 'src/chip/vpe20/vpe20_plane_desc_writer.c', + 'src/chip/vpe20/vpe20_resource.c', + 'src/chip/vpe20/vpe20_vpe_desc_writer.c', + 'src/imported/SPL/dc_spl.c', + 'src/imported/SPL/dc_spl.h', + 'src/imported/SPL/dc_spl_filters.c', + 'src/imported/SPL/dc_spl_isharp_filters.c', + 'src/imported/SPL/dc_spl_scl_easf_filters.c', + 'src/imported/SPL/dc_spl_scl_filters.c', + 'src/imported/SPL/spl_custom_float.c', + 'src/imported/SPL/spl_fixpt31_32.c', ) inc_amd_vpe = include_directories( @@ -135,6 +160,9 @@ inc_amd_vpe = include_directories( 'src/utils/inc', 'src/chip/vpe10/inc', 'src/chip/vpe11/inc', + 'src/chip/vpe20/inc', + 'src/imported/SPL', + 'src/imported', ) libvpe = static_library( diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_dpp.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_dpp.h index 47e2cb9009f..6d92a2a772e 100644 --- a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_dpp.h +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_dpp.h @@ -905,6 +905,8 @@ enum vpe10_coef_filter_type_sel { SCL_COEF_CHROMA_HORZ_FILTER = 3, SCL_COEF_ALPHA_VERT_FILTER = 4, SCL_COEF_ALPHA_HORZ_FILTER = 5, + SCL_COEF_VERTICAL_BLUR_SCALE = SCL_COEF_ALPHA_VERT_FILTER, + SCL_COEF_HORIZONTAL_BLUR_SCALE = SCL_COEF_ALPHA_HORZ_FILTER }; enum vpe10_dscl_autocal_mode { diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_cdc_fe.c b/src/amd/vpelib/src/chip/vpe10/vpe10_cdc_fe.c index fb45116452a..88563ec9132 100644 --- a/src/amd/vpelib/src/chip/vpe10/vpe10_cdc_fe.c +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_cdc_fe.c @@ -40,6 +40,7 @@ enum mux_sel { static struct cdc_fe_funcs cdc_fe_func = { .program_surface_config = vpe10_cdc_program_surface_config, .program_crossbar_config = vpe10_cdc_program_crossbar_config, + .program_3dlut_fl_config = NULL, .program_viewport = vpe10_cdc_program_viewport, }; diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_dpp.c b/src/amd/vpelib/src/chip/vpe10/vpe10_dpp.c index fe54218b0d7..1dc7c5cc267 100644 --- a/src/amd/vpelib/src/chip/vpe10/vpe10_dpp.c +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_dpp.c @@ -58,6 +58,10 @@ static struct dpp_funcs vpe10_dpp_funcs = { .set_frame_scaler = vpe10_dpp_set_frame_scaler, .get_line_buffer_size = vpe10_get_line_buffer_size, .validate_number_of_taps = vpe10_dpp_validate_number_of_taps, + .enable_clocks = NULL, + .dscl_program_easf = NULL, + .dscl_disable_easf = NULL, + .dscl_program_isharp = NULL, }; void vpe10_construct_dpp(struct vpe_priv *vpe_priv, struct dpp *dpp) diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_mpc.c b/src/amd/vpelib/src/chip/vpe10/vpe10_mpc.c index db1d4d4724b..1ca48cf933e 100644 --- a/src/amd/vpelib/src/chip/vpe10/vpe10_mpc.c +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_mpc.c @@ -57,6 +57,12 @@ static struct mpc_funcs mpc_funcs = { .set_blend_lut = vpe10_mpc_set_blend_lut, .program_movable_cm = vpe10_mpc_program_movable_cm, .program_crc = vpe10_mpc_program_crc, + .attach_3dlut_to_mpc_inst = NULL, + .set_gamut_remap2 = NULL, + .update_3dlut_fl_bias_scale = NULL, + .program_mpc_3dlut_fl_config = NULL, + .program_mpc_3dlut_fl = NULL, + .shaper_bypass = NULL, }; void vpe10_construct_mpc(struct vpe_priv *vpe_priv, struct mpc *mpc) diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c b/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c index 956b6158ca0..41dd009ec05 100644 --- a/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c @@ -50,6 +50,13 @@ #define LUT_ENTRY_SIZE (2) #define LUT_NUM_COMPONENT (3) #define LUT_BUFFER_SIZE (LUT_NUM_ENTRIES * LUT_ENTRY_SIZE * LUT_NUM_COMPONENT) +#define SHAPER_LUT_DATA_POINTS_PER_CHANNEL (256) +#define SHAPER_LUT_DMA_DATA_SIZE (0) +#define SHAPER_LUT_DMA_CONFIG_SIZE (0) +#define SHAPER_LUT_DMA_DATA_ALIGNMENT (0) +#define SHAPER_LUT_DMA_CONFIG_ALIGNMENT (0) +#define SHAPER_LUT_DMA_CONFIG_PADDING (0) +#define LUT_3D_DMA_ALIGNMENT (0) // set field/register/bitfield name #define SFRB(field_name, reg_name, post_fix) .field_name = reg_name##__##field_name##post_fix @@ -188,6 +195,45 @@ static struct vpe_caps .shared_3d_lut = 1, .global_alpha = 1, .top_bottom_blending = 0, + .dma_3d_lut = 0, + .yuv_linear_blend = 0, + .lut_dim_caps = + { + .dim_9 = 1, + .dim_17 = 1, + .dim_33 = 0, + }, + .fast_load_caps = + { + .lut_3d_17 = 0, + .lut_3d_33 = 0, + }, + .lut_caps = + { + .lut_shaper_caps = + { + .dma_data = 0, + .dma_config = 0, + .non_monotonic = 0, + .data_alignment = SHAPER_LUT_DMA_DATA_ALIGNMENT, + .config_alignment = SHAPER_LUT_DMA_CONFIG_ALIGNMENT, + .config_padding = SHAPER_LUT_DMA_CONFIG_PADDING, + .data_size = SHAPER_LUT_DMA_DATA_SIZE, + .config_size = SHAPER_LUT_DMA_CONFIG_SIZE, + .data_pts_per_channel = SHAPER_LUT_DATA_POINTS_PER_CHANNEL, + }, + .lut_3dlut_caps = + { + .data_dim_9 = 1, + .data_dim_17 = 1, + .data_dim_33 = 0, + .dma_dim_9 = 0, + .dma_dim_17 = 0, + .dma_dim_33 = 0, + .alignment = LUT_3D_DMA_ALIGNMENT, + }, + .lut_3d_compound = 0, + }, }}, .plane_caps = { @@ -201,6 +247,19 @@ static struct vpe_caps .p016 = 0, /**< planar 4:2:0 16-bit */ .ayuv = 0, /**< packed 4:4:4 */ .yuy2 = 0, /**< packed 4:2:2 */ + .y210 = 0, /**< packed 4:2:2 10-bit */ + .y216 = 0, /**< packed 4:2:2 16-bit */ + .p210 = 0, /**< planar 4:2:2 10-bit */ + .p216 = 0, /**< planar 4:2:2 16-bit */ + .rgb8_planar = 0, /**< planar RGB 8-bit */ + .rgb16_planar = 0, /**< planar RGB 16-bit */ + .yuv8_planar = 0, /**< planar YUV 16-bit */ + .yuv16_planar = 0, /**< planar YUV 16-bit */ + .fp16_planar = 0, /**< planar RGB 8-bit */ + .rgbe = 0, /**< shared exponent R9G9B9E5 */ + .rgb111110_fix = 0, /**< fixed R11G11B10 */ + .rgb111110_float = 0, /**< float R11G11B10 */ + .argb_packed_64b = 0, /**< Packed RGBA formats 64-bits per pixel */ }, .output_pixel_format_support = { @@ -211,6 +270,19 @@ static struct vpe_caps .p016 = 0, /**< planar 4:2:0 16-bit */ .ayuv = 0, /**< packed 4:4:4 */ .yuy2 = 0, /**< packed 4:2:2 */ + .y210 = 0, /**< packed 4:2:2 10-bit */ + .y216 = 0, /**< packed 4:2:2 16-bit */ + .p210 = 0, /**< planar 4:2:2 10-bit */ + .p216 = 0, /**< planar 4:2:2 16-bit */ + .rgb8_planar = 0, /**< planar RGB 8-bit */ + .rgb16_planar = 0, /**< planar RGB 16-bit */ + .yuv8_planar = 0, /**< planar YUV 16-bit */ + .yuv16_planar = 0, /**< planar YUV 16-bit */ + .fp16_planar = 0, /**< planar RGB 8-bit */ + .rgbe = 0, /**< shared exponent R9G9B9E5 */ + .rgb111110_fix = 0, /**< fixed R11G11B10 */ + .rgb111110_float = 0, /**< float R11G11B10 */ + .argb_packed_64b = 0, /**< Packed RGBA formats 64-bits per pixel */ }, .max_upscale_factor = 64000, @@ -225,6 +297,24 @@ static struct vpe_caps .addr_alignment = 256, .max_viewport_width = 1024, }, + .isharp_caps = + { + .support = false, + .range = + { + .min = 0, + .max = 0, + .step = 0, + }, + }, + .easf_support = 0, + .input_dcc_support = 0, + .input_internal_dcc = 0, + .output_dcc_support = 0, + .output_internal_dcc = 0, + .histogram_support = 0, + .frod_support = 0, + .alpha_blending_support = 0, .alpha_fill_caps = { .opaque = 1, @@ -453,6 +543,10 @@ enum vpe_status vpe10_construct_resource(struct vpe_priv *vpe_priv, struct resou res->update_output_gamma = vpe10_update_output_gamma; res->validate_cached_param = vpe10_validate_cached_param; res->check_alpha_fill_support = vpe10_check_alpha_fill_support; + res->reset_pipes = NULL; + res->populate_frod_param = NULL; + res->check_lut3d_compound = NULL; + res->update_opp_adjust_and_boundary = NULL; res->calculate_shaper = vpe10_calculate_shaper; return VPE_STATUS_OK; diff --git a/src/amd/vpelib/src/chip/vpe11/vpe11_resource.c b/src/amd/vpelib/src/chip/vpe11/vpe11_resource.c index c94d83200c2..c7d6446ea98 100644 --- a/src/amd/vpelib/src/chip/vpe11/vpe11_resource.c +++ b/src/amd/vpelib/src/chip/vpe11/vpe11_resource.c @@ -45,6 +45,13 @@ #define LUT_NUM_COMPONENT (3) #define LUT_BUFFER_SIZE (LUT_NUM_ENTRIES * LUT_ENTRY_SIZE * LUT_NUM_COMPONENT) +#define SHAPER_LUT_DATA_POINTS_PER_CHANNEL (256) +#define SHAPER_LUT_DMA_DATA_SIZE (0) +#define SHAPER_LUT_DMA_CONFIG_SIZE (0) +#define SHAPER_LUT_DMA_DATA_ALIGNMENT (0) +#define SHAPER_LUT_DMA_CONFIG_ALIGNMENT (0) +#define SHAPER_LUT_DMA_CONFIG_PADDING (0) +#define LUT_3D_DMA_ALIGNMENT (0) // set field/register/bitfield name #define SFRB(field_name, reg_name, post_fix) .field_name = reg_name##__##field_name##post_fix @@ -126,6 +133,45 @@ static struct vpe_caps .shared_3d_lut = 1, .global_alpha = 1, .top_bottom_blending = 0, + .dma_3d_lut = 0, + .yuv_linear_blend = 0, + .lut_dim_caps = + { + .dim_9 = 1, + .dim_17 = 1, + .dim_33 = 0, + }, + .fast_load_caps = + { + .lut_3d_17 = 0, + .lut_3d_33 = 0, + }, + .lut_caps = + { + .lut_shaper_caps = + { + .dma_data = 0, + .dma_config = 0, + .non_monotonic = 0, + .data_alignment = SHAPER_LUT_DMA_DATA_ALIGNMENT, + .config_alignment = SHAPER_LUT_DMA_CONFIG_ALIGNMENT, + .config_padding = SHAPER_LUT_DMA_CONFIG_PADDING, + .data_size = SHAPER_LUT_DMA_DATA_SIZE, + .config_size = SHAPER_LUT_DMA_CONFIG_SIZE, + .data_pts_per_channel = SHAPER_LUT_DATA_POINTS_PER_CHANNEL, + }, + .lut_3dlut_caps = + { + .data_dim_9 = 1, + .data_dim_17 = 1, + .data_dim_33 = 0, + .dma_dim_9 = 0, + .dma_dim_17 = 0, + .dma_dim_33 = 0, + .alignment = LUT_3D_DMA_ALIGNMENT, + }, + .lut_3d_compound = 0, + }, }}, .plane_caps = { @@ -139,6 +185,10 @@ static struct vpe_caps .p016 = 0, /**< planar 4:2:0 16-bit */ .ayuv = 0, /**< packed 4:4:4 */ .yuy2 = 0, /**< packed 4:2:2 */ + .y210 = 0, /**< packed 4:2:2 10-bit */ + .y216 = 0, /**< packed 4:2:2 16-bit */ + .p210 = 0, /**< planar 4:2:2 10-bit */ + .p216 = 0, /**< planar 4:2:2 16-bit */ }, .output_pixel_format_support = { @@ -148,7 +198,12 @@ static struct vpe_caps .p010 = 0, /**< planar 4:2:0 10-bit */ .p016 = 0, /**< planar 4:2:0 16-bit */ .ayuv = 0, /**< packed 4:4:4 */ - .yuy2 = 0 + .yuy2 = 0, /**< packed 4:2:2 */ + .y210 = 0, /**< packed 4:2:2 10-bit */ + .y216 = 0, /**< packed 4:2:2 16-bit */ + .p210 = 0, /**< planar 4:2:2 10-bit */ + .p216 = 0, /**< planar 4:2:2 16-bit */ + }, .max_upscale_factor = 64000, @@ -159,6 +214,24 @@ static struct vpe_caps .addr_alignment = 256, .max_viewport_width = 1024, }, + .isharp_caps = + { + .support = false, + .range = + { + .min = 0, + .max = 0, + .step = 0, + }, + }, + .easf_support = 0, + .input_dcc_support = 0, + .input_internal_dcc = 0, + .output_dcc_support = 0, + .output_internal_dcc = 0, + .histogram_support = 0, + .frod_support = 0, + .alpha_blending_support = 0, .alpha_fill_caps = { .opaque = 1, @@ -224,6 +297,9 @@ enum vpe_status vpe11_construct_resource(struct vpe_priv *vpe_priv, struct resou res->update_output_gamma = vpe10_update_output_gamma; res->validate_cached_param = vpe11_validate_cached_param; res->check_alpha_fill_support = vpe10_check_alpha_fill_support; + res->reset_pipes = NULL; + res->populate_frod_param = NULL; + res->check_lut3d_compound = NULL; res->calculate_shaper = vpe10_calculate_shaper; return VPE_STATUS_OK; diff --git a/src/amd/vpelib/src/chip/vpe20/inc/asic/chip_default.h b/src/amd/vpelib/src/chip/vpe20/inc/asic/chip_default.h new file mode 100644 index 00000000000..4e4a12198e5 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/inc/asic/chip_default.h @@ -0,0 +1,2488 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef _vpe20_chip_DEFAULT_HEADER +#define _vpe20_chip_DEFAULT_HEADER + + +// Registers from VPEC block + +#define mmVPEC_DEC_START_DEFAULT 0x0000 +#define mmVPEC_UCODE_ADDR_DEFAULT 0x0000 +#define mmVPEC_UCODE_DATA_DEFAULT 0x0000 +#define mmVPEC_F32_CNTL_DEFAULT 0x8084001 +#define mmVPEC_MMHUB_CNTL_DEFAULT 0x0000 +#define mmVPEC_MMHUB_TRUSTLVL_DEFAULT 0x77777777 +#define mmVPEC_VPEP_CTRL_DEFAULT 0x0002 +#define mmVPEC_CLK_CTRL_DEFAULT 0x0000 +#define mmVPEC_COLLABORATE_CNTL_DEFAULT 0x0000 +#define mmVPEC_COLLABORATE_CFG_DEFAULT 0x0010 +#define mmVPEC_POWER_CNTL_DEFAULT 0x240BC07 +#define mmVPEC_ZPR_CNTL_DEFAULT 0x0002 +#define mmVPEC_CNTL_DEFAULT 0xC401 +#define mmVPEC_CNTL_DCC_DEFAULT 0x0000 +#define mmVPEC_CE_OP_MULTI_64B_BURST_DEFAULT 0x0C31 +#define mmVPEC_CNTL1_DEFAULT 0xD001000 +#define mmVPEC_CNTL2_DEFAULT 0x400080C9 +#define mmVPEC_GB_ADDR_CONFIG_DEFAULT 0x0141 +#define mmVPEC_GB_ADDR_CONFIG_READ_DEFAULT 0x0141 +#define mmVPEC_GB_ADDR_CONFIG_META_DEFAULT 0x0141 +#define mmVPEC_PROCESS_QUANTUM0_DEFAULT 0x0000 +#define mmVPEC_PROCESS_QUANTUM1_DEFAULT 0x0000 +#define mmVPEC_CONTEXT_SWITCH_THRESHOLD_DEFAULT 0x006B +#define mmVPEC_GLOBAL_QUANTUM_DEFAULT 0x0000 +#define mmVPEC_HWE_MASK_DEFAULT 0x0000 +#define mmVPEC_HWE_SRC_DST_TABLE0_DEFAULT 0x0000 +#define mmVPEC_HWE_SRC_DST_TABLE1_DEFAULT 0x0000 +#define mmVPEC_WATCHDOG_CNTL_DEFAULT 0x0000 +#define mmVPEC_ATOMIC_CNTL_DEFAULT 0x0200 +#define mmVPEC_UCODE_VERSION_DEFAULT 0x0000 +#define mmVPEC_MEMREQ_BURST_CNTL_DEFAULT 0x06FF +#define mmVPEC_TIMESTAMP_CNTL_DEFAULT 0x0000 +#define mmVPEC_GLOBAL_TIMESTAMP_LO_DEFAULT 0x0000 +#define mmVPEC_GLOBAL_TIMESTAMP_HI_DEFAULT 0x0000 +#define mmVPEC_FREEZE_DEFAULT 0x0000 +#define mmVPEC_CE_CTRL_DEFAULT 0x0000 +#define mmVPEC_RELAX_ORDERING_LUT_DEFAULT 0xC0000002 +#define mmVPEC_CREDIT_CNTL_DEFAULT 0x14840 +#define mmVPEC_SCRATCH_RAM_DATA_DEFAULT 0x0000 +#define mmVPEC_SCRATCH_RAM_ADDR_DEFAULT 0x0000 +#define mmVPEC_QUEUE_RESET_REQ_DEFAULT 0x0000 +#define mmVPEC_PERFCNT_PERFCOUNTER0_CFG_DEFAULT 0xFFFF +#define mmVPEC_PERFCNT_PERFCOUNTER1_CFG_DEFAULT 0xFFFF +#define mmVPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x4000000 +#define mmVPEC_PERFCNT_MISC_CNTL_DEFAULT 0x10000 +#define mmVPEC_PERFCNT_PERFCOUNTER_LO_DEFAULT 0x0000 +#define mmVPEC_PERFCNT_PERFCOUNTER_HI_DEFAULT 0x0000 +#define mmVPEC_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPEC_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPEC_CRC_CNTL_DEFAULT 0x0000 +#define mmVPEC_CRC_INDEX_DEFAULT 0x0000 +#define mmVPEC_CRC_DATA0_DEFAULT 0x0000 +#define mmVPEC_CRC_DATA1_DEFAULT 0x0000 +#define mmVPEC_CRC_DATA2_DEFAULT 0x0000 +#define mmVPEC_MAILBOX0_DEFAULT 0x0000 +#define mmVPEC_MAILBOX1_DEFAULT 0x0000 +#define mmVPEC_MAILBOX2_DEFAULT 0x0000 +#define mmVPEC_MAILBOX3_DEFAULT 0x0000 +#define mmVPEC_MAILBOX4_DEFAULT 0x0000 +#define mmVPEC_MAILBOX5_DEFAULT 0x0000 +#define mmVPEC_MAILBOX6_DEFAULT 0x0000 +#define mmVPEC_MAILBOX7_DEFAULT 0x0000 +#define mmVPEC_MAILBOX8_DEFAULT 0x0000 +#define mmVPEC_MAILBOX9_DEFAULT 0x0000 +#define mmVPEC_MAILBOX10_DEFAULT 0x0000 +#define mmVPEC_MAILBOX11_DEFAULT 0x0000 +#define mmVPEC_MAILBOX12_DEFAULT 0x0000 +#define mmVPEC_MAILBOX13_DEFAULT 0x0000 +#define mmVPEC_MAILBOX14_DEFAULT 0x0000 +#define mmVPEC_MAILBOX15_DEFAULT 0x0000 +#define mmVPEC_PUB_DUMMY0_DEFAULT 0x0000 +#define mmVPEC_PUB_DUMMY1_DEFAULT 0x0000 +#define mmVPEC_PUB_DUMMY2_DEFAULT 0x0000 +#define mmVPEC_PUB_DUMMY3_DEFAULT 0x0000 +#define mmVPEC_PUB_DUMMY4_DEFAULT 0x0000 +#define mmVPEC_PUB_DUMMY5_DEFAULT 0x0000 +#define mmVPEC_PUB_DUMMY6_DEFAULT 0x0000 +#define mmVPEC_PUB_DUMMY7_DEFAULT 0x0000 +#define mmVPEC_PUB_DUMMY8_DEFAULT 0x0000 +#define mmVPEC_PUB_DUMMY9_DEFAULT 0x0000 +#define mmVPEC_PUB_DUMMY10_DEFAULT 0x0000 +#define mmVPEC_PUB_DUMMY11_DEFAULT 0x0000 +#define mmVPEC_UCODE1_CHECKSUM_DEFAULT 0x0000 +#define mmVPEC_VERSION_DEFAULT 0x0601 +#define mmVPEC_UCODE_CHECKSUM_DEFAULT 0x0000 +#define mmVPEC_RB_RPTR_FETCH_DEFAULT 0x0000 +#define mmVPEC_RB_RPTR_FETCH_HI_DEFAULT 0x0000 +#define mmVPEC_IB_OFFSET_FETCH_DEFAULT 0x0000 +#define mmVPEC_CMDIB_OFFSET_FETCH_DEFAULT 0x0000 +#define mmVPEC_3DLUTIB_OFFSET_FETCH_DEFAULT 0x0000 +#define mmVPEC_ATOMIC_PREOP_LO_DEFAULT 0x0000 +#define mmVPEC_ATOMIC_PREOP_HI_DEFAULT 0x0000 +#define mmVPEC_CE_BUSY_DEFAULT 0x0000 +#define mmVPEC_F32_COUNTER_DEFAULT 0x0000 +#define mmVPEC_HOLE_ADDR_LO_DEFAULT 0x0000 +#define mmVPEC_HOLE_ADDR_HI_DEFAULT 0x0000 +#define mmVPEC_ERROR_LOG_DEFAULT 0x000F +#define mmVPEC_INT_STATUS_DEFAULT 0x0000 +#define mmVPEC_STATUS_DEFAULT 0x465EE557 +#define mmVPEC_STATUS1_DEFAULT 0x0000 +#define mmVPEC_STATUS2_DEFAULT 0x0000 +#define mmVPEC_STATUS3_DEFAULT 0x100000 +#define mmVPEC_STATUS4_DEFAULT 0x0001 +#define mmVPEC_STATUS5_DEFAULT 0x0000 +#define mmVPEC_STATUS6_DEFAULT 0x0000 +#define mmVPEC_STATUS7_DEFAULT 0x0000 +#define mmVPEC_STATUS8_DEFAULT 0x3FFFF +#define mmVPEC_STATUS9_DEFAULT 0x3FFFF +#define mmVPEC_STATUS10_DEFAULT 0xFFFFF +#define mmVPEC_STATUS_DCC_DEFAULT 0x3FFFF +#define mmVPEC_STATUS11_DEFAULT 0x3FFFF +#define mmVPEC_INST_DEFAULT 0x0000 +#define mmVPEC_QUEUE_STATUS0_DEFAULT 0x22222222 +#define mmVPEC_QUEUE_HANG_STATUS_DEFAULT 0x0000 +#define mmVPEC_DPM_IDLE_TIME_DEFAULT 0x0000 +#define mmVPEC_DPM_BUSY_TIME_DEFAULT 0x0000 +#define mmVPEC_DPM_IDLE_START_LO_DEFAULT 0x0000 +#define mmVPEC_DPM_IDLE_START_HI_DEFAULT 0x0000 +#define mmVPEC_DPM_BUSY_START_LO_DEFAULT 0x0000 +#define mmVPEC_DPM_BUSY_START_HI_DEFAULT 0x0000 +#define mmVPEC_DPM_LAST_REQ_TIMESTAMP_DEFAULT 0x0000 +#define mmVPEC_DPM_NEW_JOB_DUMMY3_DEFAULT 0x0000 +#define mmVPEC_DPM_STATE_DEFAULT 0x0000 +#define mmVPEC_DPM0_FREQ_DEFAULT 0x0000 +#define mmVPEC_DPM1_FREQ_DEFAULT 0x0000 +#define mmVPEC_DPM2_FREQ_DEFAULT 0x0000 +#define mmVPEC_DPM3_FREQ_DEFAULT 0x0000 +#define mmVPEC_DPM_THRESHOLD_SKIP_DEFAULT 0x0000 +#define mmVPEC_DPM_THRESHOLD_BUSY_OVERFLOW_DEFAULT 0x0000 +#define mmVPEC_DPM_CALC_BUSY_IN_POSTPROCESS_DEFAULT 0x0000 +#define mmVPEC_DPM_IN_CHECKIDLE_LOOP_DEFAULT 0x0000 +#define mmVPEC_DPM_THRESHOLD_IDLE_OVERFLOW_DEFAULT 0x0000 +#define mmVPEC_DPM_BUSY_CLAMP_COUNT_DEFAULT 0x0000 +#define mmVPEC_DPM_IDLE_CLAMP_COUNT_DEFAULT 0x0000 +#define mmVPEC_PG_CNTL_DEFAULT 0x15151315 +#define mmVPEC_PG_STATUS_DEFAULT 0x000A +#define mmVPEC_CLOCK_GATING_STATUS_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_RB_CNTL_DEFAULT 0x40800 +#define mmVPEC_QUEUE0_SCHEDULE_CNTL_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_RB_BASE_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_RB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_RB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_RB_RPTR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_RB_WPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_RB_WPTR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_RB_RPTR_ADDR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_RB_RPTR_ADDR_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_RB_AQL_CNTL_DEFAULT 0x4000 +#define mmVPEC_QUEUE0_MINOR_PTR_UPDATE_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_CD_INFO_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_RB_PREEMPT_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_SKIP_CNTL_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_DOORBELL_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_DOORBELL_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_DUMMY0_DEFAULT 0x000F +#define mmVPEC_QUEUE0_DUMMY1_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_DUMMY2_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_DUMMY3_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_DUMMY4_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_IB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE0_IB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_IB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_IB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_IB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_IB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_CMDIB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE0_CMDIB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_CMDIB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_CMDIB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_CMDIB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_CMDIB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_3DLUTIB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE0_3DLUTIB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_3DLUTIB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_3DLUTIB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_3DLUTIB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_3DLUTIB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_CSA_ADDR_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_CSA_ADDR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_CONTEXT_STATUS_DEFAULT 0x0804 +#define mmVPEC_QUEUE0_DOORBELL_LOG_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_IB_SUB_REMAIN_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_PREEMPT_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_LOG0BUFFER_CFG_DEFAULT 0x0000 +#define mmVPEC_QUEUE0_LOG1BUFFER_CFG_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_RB_CNTL_DEFAULT 0x40800 +#define mmVPEC_QUEUE1_SCHEDULE_CNTL_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_RB_BASE_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_RB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_RB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_RB_RPTR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_RB_WPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_RB_WPTR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_RB_RPTR_ADDR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_RB_RPTR_ADDR_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_RB_AQL_CNTL_DEFAULT 0x4000 +#define mmVPEC_QUEUE1_MINOR_PTR_UPDATE_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_CD_INFO_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_RB_PREEMPT_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_SKIP_CNTL_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_DOORBELL_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_DOORBELL_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_DUMMY0_DEFAULT 0x000F +#define mmVPEC_QUEUE1_DUMMY1_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_DUMMY2_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_DUMMY3_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_DUMMY4_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_IB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE1_IB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_IB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_IB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_IB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_IB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_CMDIB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE1_CMDIB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_CMDIB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_CMDIB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_CMDIB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_CMDIB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_3DLUTIB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE1_3DLUTIB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_3DLUTIB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_3DLUTIB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_3DLUTIB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_3DLUTIB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_CSA_ADDR_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_CSA_ADDR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_CONTEXT_STATUS_DEFAULT 0x0804 +#define mmVPEC_QUEUE1_DOORBELL_LOG_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_IB_SUB_REMAIN_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_PREEMPT_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_LOG0BUFFER_CFG_DEFAULT 0x0000 +#define mmVPEC_QUEUE1_LOG1BUFFER_CFG_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_RB_CNTL_DEFAULT 0x40800 +#define mmVPEC_QUEUE2_SCHEDULE_CNTL_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_RB_BASE_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_RB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_RB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_RB_RPTR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_RB_WPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_RB_WPTR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_RB_RPTR_ADDR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_RB_RPTR_ADDR_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_RB_AQL_CNTL_DEFAULT 0x4000 +#define mmVPEC_QUEUE2_MINOR_PTR_UPDATE_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_CD_INFO_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_RB_PREEMPT_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_SKIP_CNTL_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_DOORBELL_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_DOORBELL_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_DUMMY0_DEFAULT 0x000F +#define mmVPEC_QUEUE2_DUMMY1_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_DUMMY2_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_DUMMY3_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_DUMMY4_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_IB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE2_IB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_IB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_IB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_IB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_IB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_CMDIB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE2_CMDIB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_CMDIB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_CMDIB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_CMDIB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_CMDIB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_3DLUTIB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE2_3DLUTIB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_3DLUTIB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_3DLUTIB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_3DLUTIB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_3DLUTIB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_CSA_ADDR_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_CSA_ADDR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_CONTEXT_STATUS_DEFAULT 0x0804 +#define mmVPEC_QUEUE2_DOORBELL_LOG_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_IB_SUB_REMAIN_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_PREEMPT_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_LOG0BUFFER_CFG_DEFAULT 0x0000 +#define mmVPEC_QUEUE2_LOG1BUFFER_CFG_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_RB_CNTL_DEFAULT 0x40800 +#define mmVPEC_QUEUE3_SCHEDULE_CNTL_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_RB_BASE_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_RB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_RB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_RB_RPTR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_RB_WPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_RB_WPTR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_RB_RPTR_ADDR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_RB_RPTR_ADDR_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_RB_AQL_CNTL_DEFAULT 0x4000 +#define mmVPEC_QUEUE3_MINOR_PTR_UPDATE_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_CD_INFO_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_RB_PREEMPT_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_SKIP_CNTL_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_DOORBELL_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_DOORBELL_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_DUMMY0_DEFAULT 0x000F +#define mmVPEC_QUEUE3_DUMMY1_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_DUMMY2_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_DUMMY3_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_DUMMY4_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_IB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE3_IB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_IB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_IB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_IB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_IB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_CMDIB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE3_CMDIB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_CMDIB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_CMDIB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_CMDIB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_CMDIB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_3DLUTIB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE3_3DLUTIB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_3DLUTIB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_3DLUTIB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_3DLUTIB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_3DLUTIB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_CSA_ADDR_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_CSA_ADDR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_CONTEXT_STATUS_DEFAULT 0x0804 +#define mmVPEC_QUEUE3_DOORBELL_LOG_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_IB_SUB_REMAIN_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_PREEMPT_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_LOG0BUFFER_CFG_DEFAULT 0x0000 +#define mmVPEC_QUEUE3_LOG1BUFFER_CFG_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_RB_CNTL_DEFAULT 0x40800 +#define mmVPEC_QUEUE4_SCHEDULE_CNTL_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_RB_BASE_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_RB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_RB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_RB_RPTR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_RB_WPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_RB_WPTR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_RB_RPTR_ADDR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_RB_RPTR_ADDR_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_RB_AQL_CNTL_DEFAULT 0x4000 +#define mmVPEC_QUEUE4_MINOR_PTR_UPDATE_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_CD_INFO_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_RB_PREEMPT_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_SKIP_CNTL_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_DOORBELL_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_DOORBELL_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_DUMMY0_DEFAULT 0x000F +#define mmVPEC_QUEUE4_DUMMY1_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_DUMMY2_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_DUMMY3_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_DUMMY4_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_IB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE4_IB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_IB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_IB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_IB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_IB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_CMDIB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE4_CMDIB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_CMDIB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_CMDIB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_CMDIB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_CMDIB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_3DLUTIB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE4_3DLUTIB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_3DLUTIB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_3DLUTIB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_3DLUTIB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_3DLUTIB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_CSA_ADDR_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_CSA_ADDR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_CONTEXT_STATUS_DEFAULT 0x0804 +#define mmVPEC_QUEUE4_DOORBELL_LOG_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_IB_SUB_REMAIN_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_PREEMPT_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_LOG0BUFFER_CFG_DEFAULT 0x0000 +#define mmVPEC_QUEUE4_LOG1BUFFER_CFG_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_RB_CNTL_DEFAULT 0x40800 +#define mmVPEC_QUEUE5_SCHEDULE_CNTL_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_RB_BASE_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_RB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_RB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_RB_RPTR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_RB_WPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_RB_WPTR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_RB_RPTR_ADDR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_RB_RPTR_ADDR_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_RB_AQL_CNTL_DEFAULT 0x4000 +#define mmVPEC_QUEUE5_MINOR_PTR_UPDATE_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_CD_INFO_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_RB_PREEMPT_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_SKIP_CNTL_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_DOORBELL_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_DOORBELL_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_DUMMY0_DEFAULT 0x000F +#define mmVPEC_QUEUE5_DUMMY1_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_DUMMY2_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_DUMMY3_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_DUMMY4_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_IB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE5_IB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_IB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_IB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_IB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_IB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_CMDIB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE5_CMDIB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_CMDIB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_CMDIB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_CMDIB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_CMDIB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_3DLUTIB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE5_3DLUTIB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_3DLUTIB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_3DLUTIB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_3DLUTIB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_3DLUTIB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_CSA_ADDR_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_CSA_ADDR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_CONTEXT_STATUS_DEFAULT 0x0804 +#define mmVPEC_QUEUE5_DOORBELL_LOG_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_IB_SUB_REMAIN_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_PREEMPT_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_LOG0BUFFER_CFG_DEFAULT 0x0000 +#define mmVPEC_QUEUE5_LOG1BUFFER_CFG_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_RB_CNTL_DEFAULT 0x40800 +#define mmVPEC_QUEUE6_SCHEDULE_CNTL_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_RB_BASE_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_RB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_RB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_RB_RPTR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_RB_WPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_RB_WPTR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_RB_RPTR_ADDR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_RB_RPTR_ADDR_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_RB_AQL_CNTL_DEFAULT 0x4000 +#define mmVPEC_QUEUE6_MINOR_PTR_UPDATE_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_CD_INFO_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_RB_PREEMPT_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_SKIP_CNTL_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_DOORBELL_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_DOORBELL_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_DUMMY0_DEFAULT 0x000F +#define mmVPEC_QUEUE6_DUMMY1_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_DUMMY2_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_DUMMY3_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_DUMMY4_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_IB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE6_IB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_IB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_IB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_IB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_IB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_CMDIB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE6_CMDIB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_CMDIB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_CMDIB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_CMDIB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_CMDIB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_3DLUTIB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE6_3DLUTIB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_3DLUTIB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_3DLUTIB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_3DLUTIB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_3DLUTIB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_CSA_ADDR_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_CSA_ADDR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_CONTEXT_STATUS_DEFAULT 0x0804 +#define mmVPEC_QUEUE6_DOORBELL_LOG_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_IB_SUB_REMAIN_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_PREEMPT_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_LOG0BUFFER_CFG_DEFAULT 0x0000 +#define mmVPEC_QUEUE6_LOG1BUFFER_CFG_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_RB_CNTL_DEFAULT 0x40800 +#define mmVPEC_QUEUE7_SCHEDULE_CNTL_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_RB_BASE_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_RB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_RB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_RB_RPTR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_RB_WPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_RB_WPTR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_RB_RPTR_ADDR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_RB_RPTR_ADDR_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_RB_AQL_CNTL_DEFAULT 0x4000 +#define mmVPEC_QUEUE7_MINOR_PTR_UPDATE_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_CD_INFO_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_RB_PREEMPT_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_SKIP_CNTL_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_DOORBELL_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_DOORBELL_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_DUMMY0_DEFAULT 0x000F +#define mmVPEC_QUEUE7_DUMMY1_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_DUMMY2_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_DUMMY3_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_DUMMY4_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_IB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE7_IB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_IB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_IB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_IB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_IB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_CMDIB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE7_CMDIB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_CMDIB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_CMDIB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_CMDIB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_CMDIB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_3DLUTIB_CNTL_DEFAULT 0x0101 +#define mmVPEC_QUEUE7_3DLUTIB_RPTR_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_3DLUTIB_OFFSET_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_3DLUTIB_BASE_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_3DLUTIB_BASE_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_3DLUTIB_SIZE_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_CSA_ADDR_LO_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_CSA_ADDR_HI_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_CONTEXT_STATUS_DEFAULT 0x0804 +#define mmVPEC_QUEUE7_DOORBELL_LOG_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_IB_SUB_REMAIN_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_PREEMPT_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_LOG0BUFFER_CFG_DEFAULT 0x0000 +#define mmVPEC_QUEUE7_LOG1BUFFER_CFG_DEFAULT 0x0000 + + +// Registers from CDC block + +#define mmVPEP_MGCG_CNTL_DEFAULT 0x0000 +#define mmVPCDC_SOFT_RESET_DEFAULT 0x0000 +#define mmVPCDC_FE0_SURFACE_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_FE0_CROSSBAR_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_FE0_VIEWPORT_START_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_FE0_VIEWPORT_DIMENSION_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_FE0_VIEWPORT_START_C_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_FE1_SURFACE_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_FE1_CROSSBAR_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_FE1_VIEWPORT_START_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_FE1_VIEWPORT_DIMENSION_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_FE1_VIEWPORT_START_C_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_FE1_VIEWPORT_DIMENSION_C_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_BE0_P2B_CONFIG_DEFAULT 0x0036 +#define mmVPCDC_BE0_GLOBAL_SYNC_CONFIG_DEFAULT 0x960F014 +#define mmVPCDC_BE1_P2B_CONFIG_DEFAULT 0x0036 +#define mmVPCDC_BE1_GLOBAL_SYNC_CONFIG_DEFAULT 0x960F014 +#define mmVPCDC_BE2_P2B_CONFIG_DEFAULT 0x0036 +#define mmVPCDC_BE2_GLOBAL_SYNC_CONFIG_DEFAULT 0x960F014 +#define mmVPCDC_BE3_P2B_CONFIG_DEFAULT 0x0036 +#define mmVPCDC_BE3_GLOBAL_SYNC_CONFIG_DEFAULT 0x960F014 +#define mmVPCDC_GLOBAL_SYNC_TRIGGER_DEFAULT 0x0000 +#define mmVPCDC_VREADY_STATUS_DEFAULT 0x0000 +#define mmVPEP_MEM_GLOBAL_PWR_REQ_CNTL_DEFAULT 0x0000 +#define mmVPFE0_MEM_PWR_CNTL_DEFAULT 0x0000 +#define mmVPFE1_MEM_PWR_CNTL_DEFAULT 0x0000 +#define mmVPBE0_MEM_PWR_CNTL_DEFAULT 0x0000 +#define mmVPBE1_MEM_PWR_CNTL_DEFAULT 0x0000 +#define mmVPBE2_MEM_PWR_CNTL_DEFAULT 0x0000 +#define mmVPBE3_MEM_PWR_CNTL_DEFAULT 0x0000 +#define mmVPEP_RBBMIF_TIMEOUT_DEFAULT 0x1F00100 +#define mmVPEP_RBBMIF_STATUS_DEFAULT 0x0000 +#define mmVPEP_RBBMIF_TIMEOUT_DIS_DEFAULT 0x0000 +#define mmVPCDC_DEBUG_CTRL0_DEFAULT 0x0000 +#define mmVPCDC_DEBUG_CTRL1_DEFAULT 0x0000 +#define mmVPCDC_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPCDC_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPCDC_3DLUT_FL_CONFIG_DEFAULT 0x0127 +#define mmVPCDC_CONTROL_DEFAULT 0x0000 + + + +// Registers from VPCNVC_CFG block + +#define mmVPCNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x0008 +#define mmVPCNVC_CFG0_VPCNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x0008 +#define mmVPCNVC_CFG0_VPCNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x0008 +#define mmVPCNVC_CFG1_VPCNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x0008 +#define mmVPCNVC_CFG1_VPCNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x0008 +#define mmVPCNVC_FORMAT_CONTROL_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_FORMAT_CONTROL_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_FORMAT_CONTROL_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_FORMAT_CONTROL_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_FORMAT_CONTROL_DEFAULT 0x0000 +#define mmVPCNVC_FCNV_FP_BIAS_R_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_BIAS_R_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_BIAS_R_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_BIAS_R_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_BIAS_R_DEFAULT 0x0000 +#define mmVPCNVC_FCNV_FP_BIAS_G_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_BIAS_G_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_BIAS_G_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_BIAS_G_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_BIAS_G_DEFAULT 0x0000 +#define mmVPCNVC_FCNV_FP_BIAS_B_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_BIAS_B_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_BIAS_B_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_BIAS_B_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_BIAS_B_DEFAULT 0x0000 +#define mmVPCNVC_FCNV_FP_SCALE_R_DEFAULT 0x1F000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_SCALE_R_DEFAULT 0x1F000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_SCALE_R_DEFAULT 0x1F000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_SCALE_R_DEFAULT 0x1F000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_SCALE_R_DEFAULT 0x1F000 +#define mmVPCNVC_FCNV_FP_SCALE_G_DEFAULT 0x1F000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_SCALE_G_DEFAULT 0x1F000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_SCALE_G_DEFAULT 0x1F000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_SCALE_G_DEFAULT 0x1F000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_SCALE_G_DEFAULT 0x1F000 +#define mmVPCNVC_FCNV_FP_SCALE_B_DEFAULT 0x1F000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_SCALE_B_DEFAULT 0x1F000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_SCALE_B_DEFAULT 0x1F000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_SCALE_B_DEFAULT 0x1F000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_SCALE_B_DEFAULT 0x1F000 +#define mmVPCNVC_COLOR_KEYER_CONTROL_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_CONTROL_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_CONTROL_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_CONTROL_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_CONTROL_DEFAULT 0x0000 +#define mmVPCNVC_COLOR_KEYER_ALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_ALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_ALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_ALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_ALPHA_DEFAULT 0x0000 +#define mmVPCNVC_COLOR_KEYER_RED_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_RED_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_RED_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_RED_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_RED_DEFAULT 0x0000 +#define mmVPCNVC_COLOR_KEYER_GREEN_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_GREEN_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_GREEN_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_GREEN_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_GREEN_DEFAULT 0x0000 +#define mmVPCNVC_COLOR_KEYER_BLUE_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_BLUE_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_BLUE_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_BLUE_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_BLUE_DEFAULT 0x0000 +#define mmVPCNVC_ALPHA_2BIT_LUT01_DEFAULT 0x5550000 +#define mmVPCNVC_CFG0_VPCNVC_ALPHA_2BIT_LUT01_DEFAULT 0x5550000 +#define mmVPCNVC_CFG0_VPCNVC_ALPHA_2BIT_LUT01_DEFAULT 0x5550000 +#define mmVPCNVC_CFG1_VPCNVC_ALPHA_2BIT_LUT01_DEFAULT 0x5550000 +#define mmVPCNVC_CFG1_VPCNVC_ALPHA_2BIT_LUT01_DEFAULT 0x5550000 +#define mmVPCNVC_ALPHA_2BIT_LUT23_DEFAULT 0xFFF0AAA +#define mmVPCNVC_CFG0_VPCNVC_ALPHA_2BIT_LUT23_DEFAULT 0xFFF0AAA +#define mmVPCNVC_CFG0_VPCNVC_ALPHA_2BIT_LUT23_DEFAULT 0xFFF0AAA +#define mmVPCNVC_CFG1_VPCNVC_ALPHA_2BIT_LUT23_DEFAULT 0xFFF0AAA +#define mmVPCNVC_CFG1_VPCNVC_ALPHA_2BIT_LUT23_DEFAULT 0xFFF0AAA +#define mmVPCNVC_PRE_DEALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_DEALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_DEALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_DEALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_DEALPHA_DEFAULT 0x0000 +#define mmVPCNVC_PRE_CSC_MODE_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_MODE_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_MODE_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_MODE_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_MODE_DEFAULT 0x0000 +#define mmVPCNVC_PRE_CSC_C11_C12_DEFAULT 0x2000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C11_C12_DEFAULT 0x2000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C11_C12_DEFAULT 0x2000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C11_C12_DEFAULT 0x2000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C11_C12_DEFAULT 0x2000 +#define mmVPCNVC_PRE_CSC_C13_C14_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C13_C14_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C13_C14_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C13_C14_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C13_C14_DEFAULT 0x0000 +#define mmVPCNVC_PRE_CSC_C21_C22_DEFAULT 0x20000000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C21_C22_DEFAULT 0x20000000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C21_C22_DEFAULT 0x20000000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C21_C22_DEFAULT 0x20000000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C21_C22_DEFAULT 0x20000000 +#define mmVPCNVC_PRE_CSC_C23_C24_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C23_C24_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C23_C24_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C23_C24_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C23_C24_DEFAULT 0x0000 +#define mmVPCNVC_PRE_CSC_C31_C32_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C31_C32_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C31_C32_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C31_C32_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C31_C32_DEFAULT 0x0000 +#define mmVPCNVC_PRE_CSC_C33_C34_DEFAULT 0x2000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C33_C34_DEFAULT 0x2000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C33_C34_DEFAULT 0x2000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C33_C34_DEFAULT 0x2000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C33_C34_DEFAULT 0x2000 +#define mmVPCNVC_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPCNVC_PRE_DEGAM_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_DEGAM_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_DEGAM_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_DEGAM_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_DEGAM_DEFAULT 0x0000 +#define mmVPCNVC_PRE_REALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_REALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_REALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_REALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_REALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_CFG_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_CFG_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_CFG_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_CFG_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPCNVC_CFG_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_CFG_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_CFG_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_CFG_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_CFG_TEST_DEBUG_DATA_DEFAULT 0x0000 + + +// Registers from VPDSCL block + +#define mmVPDSCL_COEF_RAM_TAP_SELECT_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_COEF_RAM_TAP_SELECT_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_COEF_RAM_TAP_SELECT_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_COEF_RAM_TAP_SELECT_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_COEF_RAM_TAP_SELECT_DEFAULT 0x0000 +#define mmVPDSCL_COEF_RAM_TAP_DATA_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_COEF_RAM_TAP_DATA_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_COEF_RAM_TAP_DATA_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_COEF_RAM_TAP_DATA_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_COEF_RAM_TAP_DATA_DEFAULT 0x0000 +#define mmVPDSCL_MODE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_MODE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_MODE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_MODE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_MODE_DEFAULT 0x0000 +#define mmVPDSCL_TAP_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_TAP_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_TAP_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_TAP_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_TAP_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL_2TAP_CONTROL_DEFAULT 0x1000100 +#define mmVPDSCL0_VPDSCL_2TAP_CONTROL_DEFAULT 0x1000100 +#define mmVPDSCL0_VPDSCL_2TAP_CONTROL_DEFAULT 0x1000100 +#define mmVPDSCL1_VPDSCL_2TAP_CONTROL_DEFAULT 0x1000100 +#define mmVPDSCL1_VPDSCL_2TAP_CONTROL_DEFAULT 0x1000100 +#define mmVPDSCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x0000 +#define mmVPDSCL_HORZ_FILTER_INIT_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_INIT_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_INIT_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_INIT_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_INIT_DEFAULT 0x1000000 +#define mmVPDSCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x0000 +#define mmVPDSCL_HORZ_FILTER_INIT_C_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_INIT_C_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_INIT_C_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_INIT_C_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_INIT_C_DEFAULT 0x1000000 +#define mmVPDSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x0000 +#define mmVPDSCL_VERT_FILTER_INIT_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_DEFAULT 0x1000000 +#define mmVPDSCL_VERT_FILTER_INIT_BOT_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_BOT_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_BOT_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_BOT_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_BOT_DEFAULT 0x1000000 +#define mmVPDSCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x0000 +#define mmVPDSCL_VERT_FILTER_INIT_C_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_C_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_C_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_C_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_C_DEFAULT 0x1000000 +#define mmVPDSCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x1000000 +#define mmVPDSCL_BLACK_COLOR_DEFAULT 0x3C000000 +#define mmVPDSCL0_VPDSCL_BLACK_COLOR_DEFAULT 0x3C000000 +#define mmVPDSCL0_VPDSCL_BLACK_COLOR_DEFAULT 0x3C000000 +#define mmVPDSCL1_VPDSCL_BLACK_COLOR_DEFAULT 0x3C000000 +#define mmVPDSCL1_VPDSCL_BLACK_COLOR_DEFAULT 0x3C000000 +#define mmVPDSCL_UPDATE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_UPDATE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_UPDATE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_UPDATE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_UPDATE_DEFAULT 0x0000 +#define mmVPDSCL_AUTOCAL_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_AUTOCAL_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_AUTOCAL_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_AUTOCAL_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_AUTOCAL_DEFAULT 0x0000 +#define mmVPDSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x0000 +#define mmVPDSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x0000 +#define mmVPOTG_H_BLANK_DEFAULT 0x0000 +#define mmVPDSCL0_VPOTG_H_BLANK_DEFAULT 0x0000 +#define mmVPDSCL0_VPOTG_H_BLANK_DEFAULT 0x0000 +#define mmVPDSCL1_VPOTG_H_BLANK_DEFAULT 0x0000 +#define mmVPDSCL1_VPOTG_H_BLANK_DEFAULT 0x0000 +#define mmVPOTG_V_BLANK_DEFAULT 0x0000 +#define mmVPDSCL0_VPOTG_V_BLANK_DEFAULT 0x0000 +#define mmVPDSCL0_VPOTG_V_BLANK_DEFAULT 0x0000 +#define mmVPDSCL1_VPOTG_V_BLANK_DEFAULT 0x0000 +#define mmVPDSCL1_VPOTG_V_BLANK_DEFAULT 0x0000 +#define mmVPDSCL_RECOUT_START_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_RECOUT_START_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_RECOUT_START_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_RECOUT_START_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_RECOUT_START_DEFAULT 0x0000 +#define mmVPDSCL_RECOUT_SIZE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_RECOUT_SIZE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_RECOUT_SIZE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_RECOUT_SIZE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_RECOUT_SIZE_DEFAULT 0x0000 +#define mmVPMPC_SIZE_DEFAULT 0x0000 +#define mmVPDSCL0_VPMPC_SIZE_DEFAULT 0x0000 +#define mmVPDSCL0_VPMPC_SIZE_DEFAULT 0x0000 +#define mmVPDSCL1_VPMPC_SIZE_DEFAULT 0x0000 +#define mmVPDSCL1_VPMPC_SIZE_DEFAULT 0x0000 +#define mmVPLB_DATA_FORMAT_DEFAULT 0x0000 +#define mmVPDSCL0_VPLB_DATA_FORMAT_DEFAULT 0x0000 +#define mmVPDSCL0_VPLB_DATA_FORMAT_DEFAULT 0x0000 +#define mmVPDSCL1_VPLB_DATA_FORMAT_DEFAULT 0x0000 +#define mmVPDSCL1_VPLB_DATA_FORMAT_DEFAULT 0x0000 +#define mmVPLB_MEMORY_CTRL_DEFAULT 0x3F00 +#define mmVPDSCL0_VPLB_MEMORY_CTRL_DEFAULT 0x3F00 +#define mmVPDSCL0_VPLB_MEMORY_CTRL_DEFAULT 0x3F00 +#define mmVPDSCL1_VPLB_MEMORY_CTRL_DEFAULT 0x3F00 +#define mmVPDSCL1_VPLB_MEMORY_CTRL_DEFAULT 0x3F00 +#define mmVPLB_V_COUNTER_DEFAULT 0x0000 +#define mmVPDSCL0_VPLB_V_COUNTER_DEFAULT 0x0000 +#define mmVPDSCL0_VPLB_V_COUNTER_DEFAULT 0x0000 +#define mmVPDSCL1_VPLB_V_COUNTER_DEFAULT 0x0000 +#define mmVPDSCL1_VPLB_V_COUNTER_DEFAULT 0x0000 +#define mmVPDSCL_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPDSCL_MEM_PWR_STATUS_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_MEM_PWR_STATUS_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_MEM_PWR_STATUS_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_MEM_PWR_STATUS_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_MEM_PWR_STATUS_DEFAULT 0x0000 +#define mmVPDSCL_EASF_H_MODE_DEFAULT 0x0100 +#define mmVPDSCL0_VPDSCL_EASF_H_MODE_DEFAULT 0x0100 +#define mmVPDSCL0_VPDSCL_EASF_H_MODE_DEFAULT 0x0100 +#define mmVPDSCL1_VPDSCL_EASF_H_MODE_DEFAULT 0x0100 +#define mmVPDSCL1_VPDSCL_EASF_H_MODE_DEFAULT 0x0100 +#define mmVPDSCL_EASF_V_MODE_DEFAULT 0x0100 +#define mmVPDSCL0_VPDSCL_EASF_V_MODE_DEFAULT 0x0100 +#define mmVPDSCL0_VPDSCL_EASF_V_MODE_DEFAULT 0x0100 +#define mmVPDSCL1_VPDSCL_EASF_V_MODE_DEFAULT 0x0100 +#define mmVPDSCL1_VPDSCL_EASF_V_MODE_DEFAULT 0x0100 +#define mmVPDSCL_SC_MODE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_SC_MODE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_SC_MODE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_SC_MODE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_SC_MODE_DEFAULT 0x0000 +#define mmVPDSCL_SC_MATRIX_C0C1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_SC_MATRIX_C0C1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_SC_MATRIX_C0C1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_SC_MATRIX_C0C1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_SC_MATRIX_C0C1_DEFAULT 0x0000 +#define mmVPDSCL_SC_MATRIX_C2C3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_SC_MATRIX_C2C3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_SC_MATRIX_C2C3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_SC_MATRIX_C2C3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_SC_MATRIX_C2C3_DEFAULT 0x0000 +#define mmVPDSCL_EASF_H_RINGEST_EVENTAP_GAIN_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN_DEFAULT 0x0000 +#define mmVPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE_DEFAULT 0x0000 +#define mmVPDSCL_EASF_V_RINGEST_EVENTAP_GAIN_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN_DEFAULT 0x0000 +#define mmVPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE_DEFAULT 0x0000 +#define mmVPDSCL_EASF_V_RINGEST_3TAP_CNTL1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_3TAP_CNTL1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_3TAP_CNTL1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_3TAP_CNTL1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_3TAP_CNTL1_DEFAULT 0x0000 +#define mmVPDSCL_EASF_V_RINGEST_3TAP_CNTL2_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_3TAP_CNTL2_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_3TAP_CNTL2_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_3TAP_CNTL2_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_3TAP_CNTL2_DEFAULT 0x0000 +#define mmVPDSCL_EASF_V_RINGEST_3TAP_CNTL3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_3TAP_CNTL3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_3TAP_CNTL3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_3TAP_CNTL3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_3TAP_CNTL3_DEFAULT 0x0000 +#define mmVPDSCL_EASF_RINGEST_FORCE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_RINGEST_FORCE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_RINGEST_FORCE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_RINGEST_FORCE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_RINGEST_FORCE_DEFAULT 0x0000 +#define mmVPDSCL_EASF_H_BF_CNTL_DEFAULT 0x11100B00 +#define mmVPDSCL0_VPDSCL_EASF_H_BF_CNTL_DEFAULT 0x11100B00 +#define mmVPDSCL0_VPDSCL_EASF_H_BF_CNTL_DEFAULT 0x11100B00 +#define mmVPDSCL1_VPDSCL_EASF_H_BF_CNTL_DEFAULT 0x11100B00 +#define mmVPDSCL1_VPDSCL_EASF_H_BF_CNTL_DEFAULT 0x11100B00 +#define mmVPDSCL_EASF_H_BF_FINAL_MAX_MIN_DEFAULT 0x3F3F +#define mmVPDSCL0_VPDSCL_EASF_H_BF_FINAL_MAX_MIN_DEFAULT 0x3F3F +#define mmVPDSCL0_VPDSCL_EASF_H_BF_FINAL_MAX_MIN_DEFAULT 0x3F3F +#define mmVPDSCL1_VPDSCL_EASF_H_BF_FINAL_MAX_MIN_DEFAULT 0x3F3F +#define mmVPDSCL1_VPDSCL_EASF_H_BF_FINAL_MAX_MIN_DEFAULT 0x3F3F +#define mmVPDSCL_EASF_V_BF_CNTL_DEFAULT 0x11100B00 +#define mmVPDSCL0_VPDSCL_EASF_V_BF_CNTL_DEFAULT 0x11100B00 +#define mmVPDSCL0_VPDSCL_EASF_V_BF_CNTL_DEFAULT 0x11100B00 +#define mmVPDSCL1_VPDSCL_EASF_V_BF_CNTL_DEFAULT 0x11100B00 +#define mmVPDSCL1_VPDSCL_EASF_V_BF_CNTL_DEFAULT 0x11100B00 +#define mmVPDSCL_EASF_V_BF_FINAL_MAX_MIN_DEFAULT 0x3F3F +#define mmVPDSCL0_VPDSCL_EASF_V_BF_FINAL_MAX_MIN_DEFAULT 0x3F3F +#define mmVPDSCL0_VPDSCL_EASF_V_BF_FINAL_MAX_MIN_DEFAULT 0x3F3F +#define mmVPDSCL1_VPDSCL_EASF_V_BF_FINAL_MAX_MIN_DEFAULT 0x3F3F +#define mmVPDSCL1_VPDSCL_EASF_V_BF_FINAL_MAX_MIN_DEFAULT 0x3F3F +#define mmVPDSCL_EASF_H_BF1_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL_EASF_H_BF1_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL_EASF_H_BF1_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL_EASF_H_BF1_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL_EASF_H_BF1_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL_EASF_H_BF1_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL_EASF_H_BF1_PWL_SEG6_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG6_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG6_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG6_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG6_DEFAULT 0x0000 +#define mmVPDSCL_EASF_H_BF1_PWL_SEG7_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG7_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG7_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG7_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG7_DEFAULT 0x0000 +#define mmVPDSCL_EASF_V_BF1_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL_EASF_V_BF1_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL_EASF_V_BF1_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL_EASF_V_BF1_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL_EASF_V_BF1_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL_EASF_V_BF1_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL_EASF_V_BF1_PWL_SEG6_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG6_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG6_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG6_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG6_DEFAULT 0x0000 +#define mmVPDSCL_EASF_V_BF1_PWL_SEG7_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG7_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG7_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG7_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG7_DEFAULT 0x0000 +#define mmVPDSCL_EASF_H_BF3_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL_EASF_H_BF3_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL_EASF_H_BF3_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL_EASF_H_BF3_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL_EASF_H_BF3_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL_EASF_H_BF3_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL_EASF_V_BF3_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL_EASF_V_BF3_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL_EASF_V_BF3_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL_EASF_V_BF3_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL_EASF_V_BF3_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL_EASF_V_BF3_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG5_DEFAULT 0x0000 +#define mmVPISHARP_MODE_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_MODE_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_MODE_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_MODE_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_MODE_DEFAULT 0x0000 +#define mmVPISHARP_DELTA_CTRL_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_DELTA_CTRL_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_DELTA_CTRL_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_DELTA_CTRL_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_DELTA_CTRL_DEFAULT 0x0000 +#define mmVPISHARP_DELTA_INDEX_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_DELTA_INDEX_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_DELTA_INDEX_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_DELTA_INDEX_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_DELTA_INDEX_DEFAULT 0x0000 +#define mmVPISHARP_DELTA_DATA_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_DELTA_DATA_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_DELTA_DATA_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_DELTA_DATA_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_DELTA_DATA_DEFAULT 0x0000 +#define mmVPISHARP_NLDELTA_SOFT_CLIP_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_NLDELTA_SOFT_CLIP_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_NLDELTA_SOFT_CLIP_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_NLDELTA_SOFT_CLIP_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_NLDELTA_SOFT_CLIP_DEFAULT 0x0000 +#define mmVPISHARP_NOISEDET_THRESHOLD_DEFAULT 0x03FF +#define mmVPDSCL0_VPISHARP_NOISEDET_THRESHOLD_DEFAULT 0x03FF +#define mmVPDSCL0_VPISHARP_NOISEDET_THRESHOLD_DEFAULT 0x03FF +#define mmVPDSCL1_VPISHARP_NOISEDET_THRESHOLD_DEFAULT 0x03FF +#define mmVPDSCL1_VPISHARP_NOISEDET_THRESHOLD_DEFAULT 0x03FF +#define mmVPISHARP_NOISE_GAIN_PWL_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_NOISE_GAIN_PWL_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_NOISE_GAIN_PWL_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_NOISE_GAIN_PWL_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_NOISE_GAIN_PWL_DEFAULT 0x0000 +#define mmVPISHARP_LBA_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG0_DEFAULT 0x0000 +#define mmVPISHARP_LBA_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG1_DEFAULT 0x0000 +#define mmVPISHARP_LBA_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG2_DEFAULT 0x0000 +#define mmVPISHARP_LBA_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG3_DEFAULT 0x0000 +#define mmVPISHARP_LBA_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG4_DEFAULT 0x0000 +#define mmVPISHARP_LBA_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG5_DEFAULT 0x0000 +#define mmVPISHARP_DELTA_LUT_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_DELTA_LUT_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_DELTA_LUT_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_DELTA_LUT_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_DELTA_LUT_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPDSCL_DEBUG_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_DEBUG_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_DEBUG_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_DEBUG_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_DEBUG_DEFAULT 0x0000 +#define mmVPDSCL_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPDSCL_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_TEST_DEBUG_DATA_DEFAULT 0x0000 + + +// Registers from VPCM block + +#define mmVPCM_CONTROL_DEFAULT 0x0000 +#define mmVPCM0_VPCM_CONTROL_DEFAULT 0x0000 +#define mmVPCM0_VPCM_CONTROL_DEFAULT 0x0000 +#define mmVPCM1_VPCM_CONTROL_DEFAULT 0x0000 +#define mmVPCM1_VPCM_CONTROL_DEFAULT 0x0000 +#define mmVPCM_POST_CSC_CONTROL_DEFAULT 0x0000 +#define mmVPCM0_VPCM_POST_CSC_CONTROL_DEFAULT 0x0000 +#define mmVPCM0_VPCM_POST_CSC_CONTROL_DEFAULT 0x0000 +#define mmVPCM1_VPCM_POST_CSC_CONTROL_DEFAULT 0x0000 +#define mmVPCM1_VPCM_POST_CSC_CONTROL_DEFAULT 0x0000 +#define mmVPCM_POST_CSC_C11_C12_DEFAULT 0x2000 +#define mmVPCM0_VPCM_POST_CSC_C11_C12_DEFAULT 0x2000 +#define mmVPCM0_VPCM_POST_CSC_C11_C12_DEFAULT 0x2000 +#define mmVPCM1_VPCM_POST_CSC_C11_C12_DEFAULT 0x2000 +#define mmVPCM1_VPCM_POST_CSC_C11_C12_DEFAULT 0x2000 +#define mmVPCM_POST_CSC_C13_C14_DEFAULT 0x0000 +#define mmVPCM0_VPCM_POST_CSC_C13_C14_DEFAULT 0x0000 +#define mmVPCM0_VPCM_POST_CSC_C13_C14_DEFAULT 0x0000 +#define mmVPCM1_VPCM_POST_CSC_C13_C14_DEFAULT 0x0000 +#define mmVPCM1_VPCM_POST_CSC_C13_C14_DEFAULT 0x0000 +#define mmVPCM_POST_CSC_C21_C22_DEFAULT 0x20000000 +#define mmVPCM0_VPCM_POST_CSC_C21_C22_DEFAULT 0x20000000 +#define mmVPCM0_VPCM_POST_CSC_C21_C22_DEFAULT 0x20000000 +#define mmVPCM1_VPCM_POST_CSC_C21_C22_DEFAULT 0x20000000 +#define mmVPCM1_VPCM_POST_CSC_C21_C22_DEFAULT 0x20000000 +#define mmVPCM_POST_CSC_C23_C24_DEFAULT 0x0000 +#define mmVPCM0_VPCM_POST_CSC_C23_C24_DEFAULT 0x0000 +#define mmVPCM0_VPCM_POST_CSC_C23_C24_DEFAULT 0x0000 +#define mmVPCM1_VPCM_POST_CSC_C23_C24_DEFAULT 0x0000 +#define mmVPCM1_VPCM_POST_CSC_C23_C24_DEFAULT 0x0000 +#define mmVPCM_POST_CSC_C31_C32_DEFAULT 0x0000 +#define mmVPCM0_VPCM_POST_CSC_C31_C32_DEFAULT 0x0000 +#define mmVPCM0_VPCM_POST_CSC_C31_C32_DEFAULT 0x0000 +#define mmVPCM1_VPCM_POST_CSC_C31_C32_DEFAULT 0x0000 +#define mmVPCM1_VPCM_POST_CSC_C31_C32_DEFAULT 0x0000 +#define mmVPCM_POST_CSC_C33_C34_DEFAULT 0x2000 +#define mmVPCM0_VPCM_POST_CSC_C33_C34_DEFAULT 0x2000 +#define mmVPCM0_VPCM_POST_CSC_C33_C34_DEFAULT 0x2000 +#define mmVPCM1_VPCM_POST_CSC_C33_C34_DEFAULT 0x2000 +#define mmVPCM1_VPCM_POST_CSC_C33_C34_DEFAULT 0x2000 +#define mmVPCM_BIAS_CR_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_BIAS_CR_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_BIAS_CR_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_BIAS_CR_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_BIAS_CR_R_DEFAULT 0x0000 +#define mmVPCM_BIAS_Y_G_CB_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_BIAS_Y_G_CB_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_BIAS_Y_G_CB_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_BIAS_Y_G_CB_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_BIAS_Y_G_CB_B_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_CONTROL_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_CONTROL_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_CONTROL_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_CONTROL_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_CONTROL_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_LUT_INDEX_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_LUT_INDEX_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_LUT_INDEX_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_LUT_INDEX_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_LUT_INDEX_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_LUT_DATA_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_LUT_DATA_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_LUT_DATA_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_LUT_DATA_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_LUT_DATA_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPCM0_VPCM_GAMCOR_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPCM0_VPCM_GAMCOR_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPCM1_VPCM_GAMCOR_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPCM1_VPCM_GAMCOR_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPCM_GAMCOR_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPCM_GAMCOR_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPCM_HDR_MULT_COEF_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_HDR_MULT_COEF_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_HDR_MULT_COEF_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HDR_MULT_COEF_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HDR_MULT_COEF_DEFAULT 0x1F000 +#define mmVPCM_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPCM0_VPCM_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPCM0_VPCM_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPCM1_VPCM_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPCM1_VPCM_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPCM_MEM_PWR_STATUS_DEFAULT 0x0000 +#define mmVPCM0_VPCM_MEM_PWR_STATUS_DEFAULT 0x0000 +#define mmVPCM0_VPCM_MEM_PWR_STATUS_DEFAULT 0x0000 +#define mmVPCM1_VPCM_MEM_PWR_STATUS_DEFAULT 0x0000 +#define mmVPCM1_VPCM_MEM_PWR_STATUS_DEFAULT 0x0000 +#define mmVPCM_DEALPHA_DEFAULT 0x0000 +#define mmVPCM0_VPCM_DEALPHA_DEFAULT 0x0000 +#define mmVPCM0_VPCM_DEALPHA_DEFAULT 0x0000 +#define mmVPCM1_VPCM_DEALPHA_DEFAULT 0x0000 +#define mmVPCM1_VPCM_DEALPHA_DEFAULT 0x0000 +#define mmVPCM_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPCM0_VPCM_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPCM0_VPCM_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPCM1_VPCM_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPCM1_VPCM_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPCM_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPCM0_VPCM_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPCM0_VPCM_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPCM1_VPCM_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPCM1_VPCM_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPCM_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPCM0_VPCM_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPCM0_VPCM_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPCM1_VPCM_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPCM1_VPCM_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPCM_HIST_CNTL_DEFAULT 0x1200 +#define mmVPCM0_VPCM_HIST_CNTL_DEFAULT 0x1200 +#define mmVPCM0_VPCM_HIST_CNTL_DEFAULT 0x1200 +#define mmVPCM1_VPCM_HIST_CNTL_DEFAULT 0x1200 +#define mmVPCM1_VPCM_HIST_CNTL_DEFAULT 0x1200 +#define mmVPCM_HIST_SCALE_SRC1_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_HIST_SCALE_SRC1_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_HIST_SCALE_SRC1_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HIST_SCALE_SRC1_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HIST_SCALE_SRC1_DEFAULT 0x1F000 +#define mmVPCM_HIST_COEFA_SRC2_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_HIST_COEFA_SRC2_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_HIST_COEFA_SRC2_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HIST_COEFA_SRC2_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HIST_COEFA_SRC2_DEFAULT 0x1F000 +#define mmVPCM_HIST_COEFB_SRC2_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_HIST_COEFB_SRC2_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_HIST_COEFB_SRC2_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HIST_COEFB_SRC2_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HIST_COEFB_SRC2_DEFAULT 0x1F000 +#define mmVPCM_HIST_COEFC_SRC2_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_HIST_COEFC_SRC2_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_HIST_COEFC_SRC2_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HIST_COEFC_SRC2_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HIST_COEFC_SRC2_DEFAULT 0x1F000 +#define mmVPCM_HIST_SCALE_SRC3_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_HIST_SCALE_SRC3_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_HIST_SCALE_SRC3_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HIST_SCALE_SRC3_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HIST_SCALE_SRC3_DEFAULT 0x1F000 +#define mmVPCM_HIST_BIAS_SRC1_DEFAULT 0x0000 +#define mmVPCM0_VPCM_HIST_BIAS_SRC1_DEFAULT 0x0000 +#define mmVPCM0_VPCM_HIST_BIAS_SRC1_DEFAULT 0x0000 +#define mmVPCM1_VPCM_HIST_BIAS_SRC1_DEFAULT 0x0000 +#define mmVPCM1_VPCM_HIST_BIAS_SRC1_DEFAULT 0x0000 +#define mmVPCM_HIST_BIAS_SRC2_DEFAULT 0x0000 +#define mmVPCM0_VPCM_HIST_BIAS_SRC2_DEFAULT 0x0000 +#define mmVPCM0_VPCM_HIST_BIAS_SRC2_DEFAULT 0x0000 +#define mmVPCM1_VPCM_HIST_BIAS_SRC2_DEFAULT 0x0000 +#define mmVPCM1_VPCM_HIST_BIAS_SRC2_DEFAULT 0x0000 +#define mmVPCM_HIST_BIAS_SRC3_DEFAULT 0x0000 +#define mmVPCM0_VPCM_HIST_BIAS_SRC3_DEFAULT 0x0000 +#define mmVPCM0_VPCM_HIST_BIAS_SRC3_DEFAULT 0x0000 +#define mmVPCM1_VPCM_HIST_BIAS_SRC3_DEFAULT 0x0000 +#define mmVPCM1_VPCM_HIST_BIAS_SRC3_DEFAULT 0x0000 +#define mmVPCM_HIST_LOCK_DEFAULT 0x0000 +#define mmVPCM0_VPCM_HIST_LOCK_DEFAULT 0x0000 +#define mmVPCM0_VPCM_HIST_LOCK_DEFAULT 0x0000 +#define mmVPCM1_VPCM_HIST_LOCK_DEFAULT 0x0000 +#define mmVPCM1_VPCM_HIST_LOCK_DEFAULT 0x0000 +#define mmVPCM_HIST_INDEX_DEFAULT 0x0000 +#define mmVPCM0_VPCM_HIST_INDEX_DEFAULT 0x0000 +#define mmVPCM0_VPCM_HIST_INDEX_DEFAULT 0x0000 +#define mmVPCM1_VPCM_HIST_INDEX_DEFAULT 0x0000 +#define mmVPCM1_VPCM_HIST_INDEX_DEFAULT 0x0000 +#define mmVPCM_HIST_DATA_DEFAULT 0x0000 +#define mmVPCM0_VPCM_HIST_DATA_DEFAULT 0x0000 +#define mmVPCM0_VPCM_HIST_DATA_DEFAULT 0x0000 +#define mmVPCM1_VPCM_HIST_DATA_DEFAULT 0x0000 +#define mmVPCM1_VPCM_HIST_DATA_DEFAULT 0x0000 +#define mmVPCM_HIST_STATUS_DEFAULT 0x0000 +#define mmVPCM0_VPCM_HIST_STATUS_DEFAULT 0x0000 +#define mmVPCM0_VPCM_HIST_STATUS_DEFAULT 0x0000 +#define mmVPCM1_VPCM_HIST_STATUS_DEFAULT 0x0000 +#define mmVPCM1_VPCM_HIST_STATUS_DEFAULT 0x0000 + + +// Registers from VPDPP_TOP block + +#define mmVPDPP_CONTROL_DEFAULT 0x70000000 +#define mmVPDPP_TOP0_VPDPP_CONTROL_DEFAULT 0x70000000 +#define mmVPDPP_TOP0_VPDPP_CONTROL_DEFAULT 0x70000000 +#define mmVPDPP_TOP1_VPDPP_CONTROL_DEFAULT 0x70000000 +#define mmVPDPP_TOP1_VPDPP_CONTROL_DEFAULT 0x70000000 +#define mmVPDPP_SOFT_RESET_DEFAULT 0x0000 +#define mmVPDPP_TOP0_VPDPP_SOFT_RESET_DEFAULT 0x0000 +#define mmVPDPP_TOP0_VPDPP_SOFT_RESET_DEFAULT 0x0000 +#define mmVPDPP_TOP1_VPDPP_SOFT_RESET_DEFAULT 0x0000 +#define mmVPDPP_TOP1_VPDPP_SOFT_RESET_DEFAULT 0x0000 +#define mmVPDPP_CRC_VAL_R_G_DEFAULT 0x0000 +#define mmVPDPP_TOP0_VPDPP_CRC_VAL_R_G_DEFAULT 0x0000 +#define mmVPDPP_TOP0_VPDPP_CRC_VAL_R_G_DEFAULT 0x0000 +#define mmVPDPP_TOP1_VPDPP_CRC_VAL_R_G_DEFAULT 0x0000 +#define mmVPDPP_TOP1_VPDPP_CRC_VAL_R_G_DEFAULT 0x0000 +#define mmVPDPP_CRC_VAL_B_A_DEFAULT 0x0000 +#define mmVPDPP_TOP0_VPDPP_CRC_VAL_B_A_DEFAULT 0x0000 +#define mmVPDPP_TOP0_VPDPP_CRC_VAL_B_A_DEFAULT 0x0000 +#define mmVPDPP_TOP1_VPDPP_CRC_VAL_B_A_DEFAULT 0x0000 +#define mmVPDPP_TOP1_VPDPP_CRC_VAL_B_A_DEFAULT 0x0000 +#define mmVPDPP_CRC_CTRL_DEFAULT 0x0000 +#define mmVPDPP_TOP0_VPDPP_CRC_CTRL_DEFAULT 0x0000 +#define mmVPDPP_TOP0_VPDPP_CRC_CTRL_DEFAULT 0x0000 +#define mmVPDPP_TOP1_VPDPP_CRC_CTRL_DEFAULT 0x0000 +#define mmVPDPP_TOP1_VPDPP_CRC_CTRL_DEFAULT 0x0000 +#define mmVPHOST_READ_CONTROL_DEFAULT 0x0000 +#define mmVPDPP_TOP0_VPHOST_READ_CONTROL_DEFAULT 0x0000 +#define mmVPDPP_TOP0_VPHOST_READ_CONTROL_DEFAULT 0x0000 +#define mmVPDPP_TOP1_VPHOST_READ_CONTROL_DEFAULT 0x0000 +#define mmVPDPP_TOP1_VPHOST_READ_CONTROL_DEFAULT 0x0000 +#define mmVPDPP_DEBUG_SEL_DEFAULT 0x0000 +#define mmVPDPP_TOP0_VPDPP_DEBUG_SEL_DEFAULT 0x0000 +#define mmVPDPP_TOP0_VPDPP_DEBUG_SEL_DEFAULT 0x0000 +#define mmVPDPP_TOP1_VPDPP_DEBUG_SEL_DEFAULT 0x0000 +#define mmVPDPP_TOP1_VPDPP_DEBUG_SEL_DEFAULT 0x0000 +#define mmVPDPP_DEBUG_SPARE_DEFAULT 0x0000 +#define mmVPDPP_TOP0_VPDPP_DEBUG_SPARE_DEFAULT 0x0000 +#define mmVPDPP_TOP0_VPDPP_DEBUG_SPARE_DEFAULT 0x0000 +#define mmVPDPP_TOP1_VPDPP_DEBUG_SPARE_DEFAULT 0x0000 +#define mmVPDPP_TOP1_VPDPP_DEBUG_SPARE_DEFAULT 0x0000 +#define mmVPDPP_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPDPP_TOP0_VPDPP_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPDPP_TOP0_VPDPP_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPDPP_TOP1_VPDPP_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPDPP_TOP1_VPDPP_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPDPP_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPDPP_TOP0_VPDPP_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPDPP_TOP0_VPDPP_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPDPP_TOP1_VPDPP_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPDPP_TOP1_VPDPP_TEST_DEBUG_DATA_DEFAULT 0x0000 + + +// Registers from VPMPC_CFG block + +#define mmVPMPC_CLOCK_CONTROL_DEFAULT 0x0000 +#define mmVPMPC_SOFT_RESET_DEFAULT 0x0000 +#define mmVPMPC_CRC_CTRL_DEFAULT 0x0000 +#define mmVPMPC_CRC_SEL_CONTROL_DEFAULT 0x0000 +#define mmVPMPC_CRC_RESULT_AR_DEFAULT 0x0000 +#define mmVPMPC_CRC_RESULT_GB_DEFAULT 0x0000 +#define mmVPMPC_CRC_RESULT_C_DEFAULT 0x0000 +#define mmVPMPC_DEBUG_CONTROL_DEFAULT 0xFF00 +#define mmVPMPCC_DEBUG_DATA_SELECT_DEFAULT 0x3F2F1F0F +#define mmVPMPC_BYPASS_BG_AR_DEFAULT 0x0000 +#define mmVPMPC_BYPASS_BG_GB_DEFAULT 0x0000 +#define mmVPMPC_HOST_READ_CONTROL_DEFAULT 0x0000 +#define mmVPMPC_PENDING_STATUS_MISC_DEFAULT 0x0000 +#define mmVPMPC_VPCDC0_3DLUT_FL_CONFIG_DEFAULT 0x0000 +#define mmVPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE_DEFAULT 0x0000 +#define mmVPMPC_CFG_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPMPC_CFG_TEST_DEBUG_DATA_DEFAULT 0x0000 + + +// Registers from VPMPC_OCSC block + +#define mmVPMPC_OUT0_MUX_DEFAULT 0x000F +#define mmVPMPC_OUT0_FLOAT_CONTROL_DEFAULT 0x0000 +#define mmVPMPC_OUT0_DENORM_CONTROL_DEFAULT 0xFFF000 +#define mmVPMPC_OUT0_DENORM_CLAMP_G_Y_DEFAULT 0xFFF000 +#define mmVPMPC_OUT0_DENORM_CLAMP_B_CB_DEFAULT 0xFFF000 +#define mmVPMPC_OUT1_MUX_DEFAULT 0x000F +#define mmVPMPC_OUT1_FLOAT_CONTROL_DEFAULT 0x0000 +#define mmVPMPC_OUT1_DENORM_CONTROL_DEFAULT 0xFFF000 +#define mmVPMPC_OUT1_DENORM_CLAMP_G_Y_DEFAULT 0xFFF000 +#define mmVPMPC_OUT1_DENORM_CLAMP_B_CB_DEFAULT 0xFFF000 +#define mmVPMPC_OUT_CSC_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPC_OUT0_CSC_MODE_DEFAULT 0x0000 +#define mmVPMPC_OUT0_CSC_C11_C12_A_DEFAULT 0x0000 +#define mmVPMPC_OUT0_CSC_C13_C14_A_DEFAULT 0x0000 +#define mmVPMPC_OUT0_CSC_C21_C22_A_DEFAULT 0x0000 +#define mmVPMPC_OUT0_CSC_C23_C24_A_DEFAULT 0x0000 +#define mmVPMPC_OUT0_CSC_C31_C32_A_DEFAULT 0x0000 +#define mmVPMPC_OUT0_CSC_C33_C34_A_DEFAULT 0x0000 +#define mmVPMPC_OUT1_CSC_MODE_DEFAULT 0x0000 +#define mmVPMPC_OUT1_CSC_C11_C12_A_DEFAULT 0x0000 +#define mmVPMPC_OUT1_CSC_C13_C14_A_DEFAULT 0x0000 +#define mmVPMPC_OUT1_CSC_C21_C22_A_DEFAULT 0x0000 +#define mmVPMPC_OUT1_CSC_C23_C24_A_DEFAULT 0x0000 +#define mmVPMPC_OUT1_CSC_C31_C32_A_DEFAULT 0x0000 +#define mmVPMPC_OUT1_CSC_C33_C34_A_DEFAULT 0x0000 +#define mmVPMPC_OCSC_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPMPC_OCSC_TEST_DEBUG_DATA_DEFAULT 0x0000 + + +// Registers from VPMPCC block + +#define mmVPMPCC_TOP_SEL_DEFAULT 0x000F +#define mmVPMPCC0_VPMPCC_TOP_SEL_DEFAULT 0x000F +#define mmVPMPCC0_VPMPCC_TOP_SEL_DEFAULT 0x000F +#define mmVPMPCC1_VPMPCC_TOP_SEL_DEFAULT 0x000F +#define mmVPMPCC1_VPMPCC_TOP_SEL_DEFAULT 0x000F +#define mmVPMPCC_BOT_SEL_DEFAULT 0x000F +#define mmVPMPCC0_VPMPCC_BOT_SEL_DEFAULT 0x000F +#define mmVPMPCC0_VPMPCC_BOT_SEL_DEFAULT 0x000F +#define mmVPMPCC1_VPMPCC_BOT_SEL_DEFAULT 0x000F +#define mmVPMPCC1_VPMPCC_BOT_SEL_DEFAULT 0x000F +#define mmVPMPCC_VPOPP_ID_DEFAULT 0x000F +#define mmVPMPCC0_VPMPCC_VPOPP_ID_DEFAULT 0x000F +#define mmVPMPCC0_VPMPCC_VPOPP_ID_DEFAULT 0x000F +#define mmVPMPCC1_VPMPCC_VPOPP_ID_DEFAULT 0x000F +#define mmVPMPCC1_VPMPCC_VPOPP_ID_DEFAULT 0x000F +#define mmVPMPCC_CONTROL_DEFAULT 0x0061 +#define mmVPMPCC0_VPMPCC_CONTROL_DEFAULT 0x0061 +#define mmVPMPCC0_VPMPCC_CONTROL_DEFAULT 0x0061 +#define mmVPMPCC1_VPMPCC_CONTROL_DEFAULT 0x0061 +#define mmVPMPCC1_VPMPCC_CONTROL_DEFAULT 0x0061 +#define mmVPMPCC_CONTROL2_DEFAULT 0xFFF0FFF +#define mmVPMPCC0_VPMPCC_CONTROL2_DEFAULT 0xFFF0FFF +#define mmVPMPCC0_VPMPCC_CONTROL2_DEFAULT 0xFFF0FFF +#define mmVPMPCC1_VPMPCC_CONTROL2_DEFAULT 0xFFF0FFF +#define mmVPMPCC1_VPMPCC_CONTROL2_DEFAULT 0xFFF0FFF +#define mmVPMPCC_TOP_GAIN_DEFAULT 0x1F000 +#define mmVPMPCC0_VPMPCC_TOP_GAIN_DEFAULT 0x1F000 +#define mmVPMPCC0_VPMPCC_TOP_GAIN_DEFAULT 0x1F000 +#define mmVPMPCC1_VPMPCC_TOP_GAIN_DEFAULT 0x1F000 +#define mmVPMPCC1_VPMPCC_TOP_GAIN_DEFAULT 0x1F000 +#define mmVPMPCC_BOT_GAIN_INSIDE_DEFAULT 0x1F000 +#define mmVPMPCC0_VPMPCC_BOT_GAIN_INSIDE_DEFAULT 0x1F000 +#define mmVPMPCC0_VPMPCC_BOT_GAIN_INSIDE_DEFAULT 0x1F000 +#define mmVPMPCC1_VPMPCC_BOT_GAIN_INSIDE_DEFAULT 0x1F000 +#define mmVPMPCC1_VPMPCC_BOT_GAIN_INSIDE_DEFAULT 0x1F000 +#define mmVPMPCC_BOT_GAIN_OUTSIDE_DEFAULT 0x1F000 +#define mmVPMPCC0_VPMPCC_BOT_GAIN_OUTSIDE_DEFAULT 0x1F000 +#define mmVPMPCC0_VPMPCC_BOT_GAIN_OUTSIDE_DEFAULT 0x1F000 +#define mmVPMPCC1_VPMPCC_BOT_GAIN_OUTSIDE_DEFAULT 0x1F000 +#define mmVPMPCC1_VPMPCC_BOT_GAIN_OUTSIDE_DEFAULT 0x1F000 +#define mmVPMPCC_MOVABLE_CM_LOCATION_CONTROL_DEFAULT 0x0001 +#define mmVPMPCC0_VPMPCC_MOVABLE_CM_LOCATION_CONTROL_DEFAULT 0x0001 +#define mmVPMPCC0_VPMPCC_MOVABLE_CM_LOCATION_CONTROL_DEFAULT 0x0001 +#define mmVPMPCC1_VPMPCC_MOVABLE_CM_LOCATION_CONTROL_DEFAULT 0x0001 +#define mmVPMPCC1_VPMPCC_MOVABLE_CM_LOCATION_CONTROL_DEFAULT 0x0001 +#define mmVPMPCC_BG_R_CR_DEFAULT 0x0000 +#define mmVPMPCC0_VPMPCC_BG_R_CR_DEFAULT 0x0000 +#define mmVPMPCC0_VPMPCC_BG_R_CR_DEFAULT 0x0000 +#define mmVPMPCC1_VPMPCC_BG_R_CR_DEFAULT 0x0000 +#define mmVPMPCC1_VPMPCC_BG_R_CR_DEFAULT 0x0000 +#define mmVPMPCC_BG_G_Y_DEFAULT 0x0000 +#define mmVPMPCC0_VPMPCC_BG_G_Y_DEFAULT 0x0000 +#define mmVPMPCC0_VPMPCC_BG_G_Y_DEFAULT 0x0000 +#define mmVPMPCC1_VPMPCC_BG_G_Y_DEFAULT 0x0000 +#define mmVPMPCC1_VPMPCC_BG_G_Y_DEFAULT 0x0000 +#define mmVPMPCC_BG_B_CB_DEFAULT 0x0000 +#define mmVPMPCC0_VPMPCC_BG_B_CB_DEFAULT 0x0000 +#define mmVPMPCC0_VPMPCC_BG_B_CB_DEFAULT 0x0000 +#define mmVPMPCC1_VPMPCC_BG_B_CB_DEFAULT 0x0000 +#define mmVPMPCC1_VPMPCC_BG_B_CB_DEFAULT 0x0000 +#define mmVPMPCC_MEM_PWR_CTRL_DEFAULT 0x0010 +#define mmVPMPCC0_VPMPCC_MEM_PWR_CTRL_DEFAULT 0x0010 +#define mmVPMPCC0_VPMPCC_MEM_PWR_CTRL_DEFAULT 0x0010 +#define mmVPMPCC1_VPMPCC_MEM_PWR_CTRL_DEFAULT 0x0010 +#define mmVPMPCC1_VPMPCC_MEM_PWR_CTRL_DEFAULT 0x0010 +#define mmVPMPCC_STATUS_DEFAULT 0x0000 +#define mmVPMPCC0_VPMPCC_STATUS_DEFAULT 0x0000 +#define mmVPMPCC0_VPMPCC_STATUS_DEFAULT 0x0000 +#define mmVPMPCC1_VPMPCC_STATUS_DEFAULT 0x0000 +#define mmVPMPCC1_VPMPCC_STATUS_DEFAULT 0x0000 +#define mmVPMPCC_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPMPCC0_VPMPCC_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPMPCC0_VPMPCC_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPMPCC1_VPMPCC_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPMPCC1_VPMPCC_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPMPCC0_VPMPCC_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPMPCC0_VPMPCC_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPMPCC1_VPMPCC_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPMPCC1_VPMPCC_TEST_DEBUG_DATA_DEFAULT 0x0000 + + +// Registers from VPMPCC_OGAM block + +#define mmVPMPCC_OGAM_CONTROL_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_CONTROL_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_CONTROL_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_CONTROL_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_CONTROL_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_LUT_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_LUT_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_LUT_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_LUT_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_LUT_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_LUT_DATA_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_LUT_DATA_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_LUT_DATA_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_LUT_DATA_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_LUT_DATA_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPMPCC_OGAM_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPMPCC_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPC_GAMUT_REMAP_C11_C12_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C11_C12_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C11_C12_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C11_C12_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C11_C12_A_DEFAULT 0x0000 +#define mmVPMPC_GAMUT_REMAP_C13_C14_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C13_C14_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C13_C14_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C13_C14_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C13_C14_A_DEFAULT 0x0000 +#define mmVPMPC_GAMUT_REMAP_C21_C22_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C21_C22_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C21_C22_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C21_C22_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C21_C22_A_DEFAULT 0x0000 +#define mmVPMPC_GAMUT_REMAP_C23_C24_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C23_C24_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C23_C24_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C23_C24_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C23_C24_A_DEFAULT 0x0000 +#define mmVPMPC_GAMUT_REMAP_C31_C32_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C31_C32_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C31_C32_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C31_C32_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C31_C32_A_DEFAULT 0x0000 +#define mmVPMPC_GAMUT_REMAP_C33_C34_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C33_C34_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C33_C34_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C33_C34_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C33_C34_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_OGAM_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_TEST_DEBUG_DATA_DEFAULT 0x0000 + + +// Registers from VPMPCC_MCM block + +#define mmVPMPCC_MCM_1DLUT_CONTROL_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_CONTROL_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_CONTROL_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_CONTROL_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_CONTROL_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_LUT_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_LUT_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_LUT_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_LUT_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_LUT_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_LUT_DATA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_LUT_DATA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_LUT_DATA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_LUT_DATA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_LUT_DATA_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPMPCC_MCM_1DLUT_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_MCM_FIRST_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA_DEFAULT 0x0000 +#define mmVPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA_DEFAULT 0x0000 +#define mmVPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA_DEFAULT 0x0000 +#define mmVPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA_DEFAULT 0x0000 +#define mmVPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA_DEFAULT 0x0000 +#define mmVPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_MCM_SECOND_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA_DEFAULT 0x0000 +#define mmVPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA_DEFAULT 0x0000 +#define mmVPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA_DEFAULT 0x0000 +#define mmVPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA_DEFAULT 0x0000 +#define mmVPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA_DEFAULT 0x0000 +#define mmVPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM_MEM_PWR_CTRL_DEFAULT 0x100000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_MEM_PWR_CTRL_DEFAULT 0x100000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_MEM_PWR_CTRL_DEFAULT 0x100000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_MEM_PWR_CTRL_DEFAULT 0x100000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_MEM_PWR_CTRL_DEFAULT 0x100000 +#define mmVPMPCC_MCM_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_MCM_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_TEST_DEBUG_DATA_DEFAULT 0x0000 + + +// Registers from VPMPC_RMCM block + +#define mmVPMPC_RMCM_SHAPER_CONTROL_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_OFFSET_R_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_OFFSET_G_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_OFFSET_B_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_SCALE_R_DEFAULT 0x7000 +#define mmVPMPC_RMCM_SHAPER_SCALE_G_B_DEFAULT 0x70007000 +#define mmVPMPC_RMCM_SHAPER_LUT_INDEX_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_LUT_DATA_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK_DEFAULT 0x0007 +#define mmVPMPC_RMCM_SHAPER_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_END_CNTL_B_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_END_CNTL_G_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_END_CNTL_R_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPMPC_RMCM_3DLUT_MODE_DEFAULT 0x0000 +#define mmVPMPC_RMCM_3DLUT_INDEX_DEFAULT 0x0000 +#define mmVPMPC_RMCM_3DLUT_DATA_DEFAULT 0x0000 +#define mmVPMPC_RMCM_3DLUT_DATA_30BIT_DEFAULT 0x0000 +#define mmVPMPC_RMCM_3DLUT_READ_WRITE_CONTROL_DEFAULT 0x000F +#define mmVPMPC_RMCM_3DLUT_OUT_NORM_FACTOR_DEFAULT 0x8008 +#define mmVPMPC_RMCM_3DLUT_OUT_OFFSET_R_DEFAULT 0x3C000000 +#define mmVPMPC_RMCM_3DLUT_OUT_OFFSET_G_DEFAULT 0x3C000000 +#define mmVPMPC_RMCM_3DLUT_OUT_OFFSET_B_DEFAULT 0x3C000000 +#define mmVPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPC_RMCM_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA_DEFAULT 0x0000 +#define mmVPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA_DEFAULT 0x0000 +#define mmVPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA_DEFAULT 0x0000 +#define mmVPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA_DEFAULT 0x0000 +#define mmVPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA_DEFAULT 0x0000 +#define mmVPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA_DEFAULT 0x0000 +#define mmVPMPC_RMCM_MEM_PWR_CTRL_DEFAULT 0x1010 +#define mmVPMPC_RMCM_3DLUT_FAST_LOAD_SELECT_DEFAULT 0x000F +#define mmVPMPC_RMCM_3DLUT_FAST_LOAD_STATUS_DEFAULT 0x0000 +#define mmVPMPC_RMCM_CNTL_DEFAULT 0x000F +#define mmVPMPC_RMCM_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPMPC_RMCM_TEST_DEBUG_DATA_DEFAULT 0x0000 + + +// Registers from VPFMT block + +#define mmVPFMT_CLAMP_COMPONENT_R_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_CLAMP_COMPONENT_R_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_CLAMP_COMPONENT_R_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_CLAMP_COMPONENT_R_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_CLAMP_COMPONENT_R_DEFAULT 0x0000 +#define mmVPFMT_CLAMP_COMPONENT_G_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_CLAMP_COMPONENT_G_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_CLAMP_COMPONENT_G_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_CLAMP_COMPONENT_G_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_CLAMP_COMPONENT_G_DEFAULT 0x0000 +#define mmVPFMT_CLAMP_COMPONENT_B_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_CLAMP_COMPONENT_B_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_CLAMP_COMPONENT_B_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_CLAMP_COMPONENT_B_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_CLAMP_COMPONENT_B_DEFAULT 0x0000 +#define mmVPFMT_DYNAMIC_EXP_CNTL_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_DYNAMIC_EXP_CNTL_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_DYNAMIC_EXP_CNTL_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_DYNAMIC_EXP_CNTL_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_DYNAMIC_EXP_CNTL_DEFAULT 0x0000 +#define mmVPFMT_CONTROL_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_CONTROL_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_CONTROL_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_CONTROL_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_CONTROL_DEFAULT 0x0000 +#define mmVPFMT_BIT_DEPTH_CONTROL_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_BIT_DEPTH_CONTROL_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_BIT_DEPTH_CONTROL_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_BIT_DEPTH_CONTROL_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_BIT_DEPTH_CONTROL_DEFAULT 0x0000 +#define mmVPFMT_DITHER_RAND_R_SEED_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_DITHER_RAND_R_SEED_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_DITHER_RAND_R_SEED_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_DITHER_RAND_R_SEED_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_DITHER_RAND_R_SEED_DEFAULT 0x0000 +#define mmVPFMT_DITHER_RAND_G_SEED_DEFAULT 0x0099 +#define mmVPFMT0_VPFMT_DITHER_RAND_G_SEED_DEFAULT 0x0099 +#define mmVPFMT0_VPFMT_DITHER_RAND_G_SEED_DEFAULT 0x0099 +#define mmVPFMT1_VPFMT_DITHER_RAND_G_SEED_DEFAULT 0x0099 +#define mmVPFMT1_VPFMT_DITHER_RAND_G_SEED_DEFAULT 0x0099 +#define mmVPFMT_DITHER_RAND_B_SEED_DEFAULT 0x00DD +#define mmVPFMT0_VPFMT_DITHER_RAND_B_SEED_DEFAULT 0x00DD +#define mmVPFMT0_VPFMT_DITHER_RAND_B_SEED_DEFAULT 0x00DD +#define mmVPFMT1_VPFMT_DITHER_RAND_B_SEED_DEFAULT 0x00DD +#define mmVPFMT1_VPFMT_DITHER_RAND_B_SEED_DEFAULT 0x00DD +#define mmVPFMT_CLAMP_CNTL_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_CLAMP_CNTL_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_CLAMP_CNTL_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_CLAMP_CNTL_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_CLAMP_CNTL_DEFAULT 0x0000 +#define mmVPFMT_SUBSAMPLER_MEMORY_CONTROL_DEFAULT 0x3000 +#define mmVPFMT0_VPFMT_SUBSAMPLER_MEMORY_CONTROL_DEFAULT 0x3000 +#define mmVPFMT0_VPFMT_SUBSAMPLER_MEMORY_CONTROL_DEFAULT 0x3000 +#define mmVPFMT1_VPFMT_SUBSAMPLER_MEMORY_CONTROL_DEFAULT 0x3000 +#define mmVPFMT1_VPFMT_SUBSAMPLER_MEMORY_CONTROL_DEFAULT 0x3000 +#define mmVPFMT_DEBUG_CNTL_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_DEBUG_CNTL_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_DEBUG_CNTL_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_DEBUG_CNTL_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_DEBUG_CNTL_DEFAULT 0x0000 +#define mmVPFMT_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPFMT_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_TEST_DEBUG_DATA_DEFAULT 0x0000 + + +// Registers from VPOPP_PIPE block + +#define mmVPOPP_PIPE_CONTROL_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_CONTROL_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_CONTROL_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_CONTROL_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_CONTROL_DEFAULT 0x0000 +#define mmVPOPP_PIPE_OUTBG_EXT1_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_EXT1_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_EXT1_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_EXT1_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_EXT1_DEFAULT 0x0000 +#define mmVPOPP_PIPE_OUTBG_EXT2_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_EXT2_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_EXT2_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_EXT2_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_EXT2_DEFAULT 0x0000 +#define mmVPOPP_PIPE_OUTBG_COL1_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_COL1_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_COL1_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_COL1_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_COL1_DEFAULT 0x0000 +#define mmVPOPP_PIPE_OUTBG_COL2_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_COL2_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_COL2_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_COL2_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_COL2_DEFAULT 0x0000 +#define mmVPOPP_PIPE_SPARE_DEBUG_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_SPARE_DEBUG_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_SPARE_DEBUG_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_SPARE_DEBUG_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_SPARE_DEBUG_DEFAULT 0x0000 +#define mmVPOPP_PIPE_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPOPP_PIPE_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_TEST_DEBUG_DATA_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_TEST_DEBUG_DATA_DEFAULT 0x0000 + + +// Registers from VPOPP_TOP block + +#define mmVPOPP_TOP_CLK_CONTROL_DEFAULT 0x0000 +#define mmVPOPP_DEBUG_CONTROL_DEFAULT 0x0000 +#define mmVPOPP_CRC_CONTROL_DEFAULT 0xFFFF00 +#define mmVPOPP_CRC_RESULT_RG_DEFAULT 0x0000 +#define mmVPOPP_CRC_RESULT_BC_DEFAULT 0x0000 +#define mmVPOPP_FROD_CONTROL_DEFAULT 0x0000 +#define mmVPOPP_FROD_MEM_PWR_CONTROL_DEFAULT 0x3000 +#define mmVPOPP_TOP_SPARE_DEBUG_DEFAULT 0x0000 +#define mmVPOPP_TOP_TEST_DEBUG_INDEX_DEFAULT 0x0000 +#define mmVPOPP_TOP_TEST_DEBUG_DATA_DEFAULT 0x0000 +#endif diff --git a/src/amd/vpelib/src/chip/vpe20/inc/asic/chip_mask.h b/src/amd/vpelib/src/chip/vpe20/inc/asic/chip_mask.h new file mode 100644 index 00000000000..ee7ef06ea3b --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/inc/asic/chip_mask.h @@ -0,0 +1,4704 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef _vpe20_MASK_HEADER +#define _vpe20_MASK_HEADER + +// VPEC_DEC_START +#define VPEC_DEC_START__START_MASK 0xffffffffUL + +// VPEC_UCODE_ADDR +#define VPEC_UCODE_ADDR__VALUE_MASK 0x00001fffUL +#define VPEC_UCODE_ADDR__THID_MASK 0x00008000UL + +// VPEC_UCODE_DATA +#define VPEC_UCODE_DATA__VALUE_MASK 0xffffffffUL + +// VPEC_F32_CNTL +#define VPEC_F32_CNTL__HALT_MASK 0x00000001UL +#define VPEC_F32_CNTL__DBG_SELECT_BITS_MASK 0x000000fcUL +#define VPEC_F32_CNTL__TH0_CHECKSUM_CLR_MASK 0x00000100UL +#define VPEC_F32_CNTL__TH0_RESET_MASK 0x00000200UL +#define VPEC_F32_CNTL__TH0_ENABLE_MASK 0x00000400UL +#define VPEC_F32_CNTL__TH1_CHECKSUM_CLR_MASK 0x00001000UL +#define VPEC_F32_CNTL__TH1_RESET_MASK 0x00002000UL +#define VPEC_F32_CNTL__TH1_ENABLE_MASK 0x00004000UL +#define VPEC_F32_CNTL__TH0_PRIORITY_MASK 0x00ff0000UL +#define VPEC_F32_CNTL__TH1_PRIORITY_MASK 0xff000000UL + +// VPEC_MMHUB_CNTL +#define VPEC_MMHUB_CNTL__UNIT_ID_MASK 0x0000003fUL + +// VPEC_MMHUB_TRUSTLVL +#define VPEC_MMHUB_TRUSTLVL__SECLVL0_MASK 0x0000000fUL +#define VPEC_MMHUB_TRUSTLVL__SECLVL1_MASK 0x000000f0UL +#define VPEC_MMHUB_TRUSTLVL__SECLVL2_MASK 0x00000f00UL +#define VPEC_MMHUB_TRUSTLVL__SECLVL3_MASK 0x0000f000UL +#define VPEC_MMHUB_TRUSTLVL__SECLVL4_MASK 0x000f0000UL +#define VPEC_MMHUB_TRUSTLVL__SECLVL5_MASK 0x00f00000UL +#define VPEC_MMHUB_TRUSTLVL__SECLVL6_MASK 0x0f000000UL +#define VPEC_MMHUB_TRUSTLVL__SECLVL7_MASK 0xf0000000UL + +// VPEC_VPEP_CTRL +#define VPEC_VPEP_CTRL__VPEP_SOCCLK_EN_MASK 0x00000001UL +#define VPEC_VPEP_CTRL__VPEP_SW_RESETB_MASK 0x00000002UL +#define VPEC_VPEP_CTRL__RESERVED_MASK 0x003ffffcUL +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P0_MASK 0x00400000UL +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P1_MASK 0x00800000UL +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P2_MASK 0x01000000UL +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P0_MASK 0x02000000UL +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P1_MASK 0x04000000UL +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P2_MASK 0x08000000UL +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_3DLUT_MASK 0x10000000UL +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEC_VPEP_REG_FGCLKEN_MASK 0x20000000UL +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEP_SOCCLK_MASK 0x40000000UL +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPECLK_MASK 0x80000000UL + +// VPEC_CLK_CTRL +#define VPEC_CLK_CTRL__VPECLK_EN_MASK 0x00000002UL +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE0_CLK_MASK 0x00000100UL +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE1_CLK_MASK 0x00000200UL +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE2_CLK_MASK 0x00000400UL +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE3_CLK_MASK 0x00000800UL +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE4_CLK_MASK 0x00001000UL +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE5_CLK_MASK 0x00002000UL +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE0_CLK_MASK 0x00010000UL +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE1_CLK_MASK 0x00020000UL +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE2_CLK_MASK 0x00040000UL +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE3_CLK_MASK 0x00080000UL +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE4_CLK_MASK 0x00100000UL +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE5_CLK_MASK 0x00200000UL +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE6_CLK_MASK 0x00400000UL +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE7_CLK_MASK 0x00800000UL +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE8_CLK_MASK 0x01000000UL +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE9_CLK_MASK 0x02000000UL +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_PERF_CLK_MASK 0x08000000UL +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_CE_CLK_MASK 0x10000000UL +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_F32_CLK_MASK 0x20000000UL +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_DYN_CLK_MASK 0x40000000UL +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_REG_CLK_MASK 0x80000000UL + +// VPEC_COLLABORATE_CNTL +#define VPEC_COLLABORATE_CNTL__COLLABORATE_MODE_EN_MASK 0x00000001UL + +// VPEC_COLLABORATE_CFG +#define VPEC_COLLABORATE_CFG__MASTER_ID_MASK 0x00000007UL +#define VPEC_COLLABORATE_CFG__MASTER_EN_MASK 0x00000008UL +#define VPEC_COLLABORATE_CFG__SLAVE0_ID_MASK 0x00000070UL +#define VPEC_COLLABORATE_CFG__SLAVE0_EN_MASK 0x00000080UL + +// VPEC_POWER_CNTL +#define VPEC_POWER_CNTL__LS_ENABLE_MASK 0x00000001UL +#define VPEC_POWER_CNTL__UCODE_SRAM_DS_EN_MASK 0x00000002UL +#define VPEC_POWER_CNTL__FISO_MASK 0x00000004UL +#define VPEC_POWER_CNTL__UCODE_SRAM_POWER_UP_RECOVER_DELAY_MASK 0x00007f00UL +#define VPEC_POWER_CNTL__UCODE_SRAM_POWER_STATUS_CHANGE_WAKEUP_TIME_MASK 0x00038000UL +#define VPEC_POWER_CNTL__UCODE_SRAM_POWER_STATUS_CHANGE_CLK_FORCE_MASK 0x00040000UL +#define VPEC_POWER_CNTL__SRAM_POWER_LS_CHANGE_DELAY_MASK 0x00700000UL +#define VPEC_POWER_CNTL__SRAM_POWER_LS_CHANGE_CLK_FORCE_MASK 0x00800000UL +#define VPEC_POWER_CNTL__SRAM_POWER_LS_CHANGE_CLK_FORCE_DELAY_MASK 0x03000000UL + +// VPEC_ZPR_CNTL +#define VPEC_ZPR_CNTL__CLK_UNGATE_DELAY_MASK 0x000000ffUL +#define VPEC_ZPR_CNTL__RESERVED_MASK 0xffffff00UL + +// VPEC_CNTL +#define VPEC_CNTL__TRAP_ENABLE_MASK 0x00000001UL +#define VPEC_CNTL__RESERVED_2_2_MASK 0x00000004UL +#define VPEC_CNTL__DATA_SWAP_MASK 0x00000018UL +#define VPEC_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000020UL +#define VPEC_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000040UL +#define VPEC_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000200UL +#define VPEC_CNTL__UMSCH_INT_ENABLE_MASK 0x00000400UL +#define VPEC_CNTL__RESERVED_13_11_MASK 0x00003800UL +#define VPEC_CNTL__NACK_GEN_ERR_INT_ENABLE_MASK 0x00004000UL +#define VPEC_CNTL__NACK_PRT_INT_ENABLE_MASK 0x00008000UL +#define VPEC_CNTL__RESERVED_16_16_MASK 0x00010000UL +#define VPEC_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000UL +#define VPEC_CNTL__RESERVED_19_19_MASK 0x00080000UL +#define VPEC_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000UL +#define VPEC_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000UL +#define VPEC_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000UL +#define VPEC_CNTL__RB_PREEMPT_INT_ENABLE_MASK 0x80000000UL + +// VPEC_CNTL_DCC +#define VPEC_CNTL_DCC__WDCC_COMP_MODE_MASK 0x00000003UL +#define VPEC_CNTL_DCC__RESERVED_3_2_MASK 0x0000000cUL +#define VPEC_CNTL_DCC__WDCC_MICRO_TILE_MODE_MASK 0x00000030UL +#define VPEC_CNTL_DCC__RESERVED_7_6_MASK 0x000000c0UL +#define VPEC_CNTL_DCC__WDCC_DATA_FORMAT_MASK 0x00001f00UL +#define VPEC_CNTL_DCC__RESERVED_15_13_MASK 0x0000e000UL +#define VPEC_CNTL_DCC__WDCC_NUM_FORMAT_EN_MASK 0x00010000UL +#define VPEC_CNTL_DCC__RESERVED_19_17_MASK 0x000e0000UL +#define VPEC_CNTL_DCC__WDCC_NUM_TYPE_MASK 0x00700000UL +#define VPEC_CNTL_DCC__RESERVED_23_23_MASK 0x00800000UL +#define VPEC_CNTL_DCC__WDCC_MAX_UNCOMP_SIZE_MASK 0x01000000UL +#define VPEC_CNTL_DCC__WDCC_MAX_COMP_SIZE_MASK 0x06000000UL +#define VPEC_CNTL_DCC__RESERVED_30_27_MASK 0x78000000UL +#define VPEC_CNTL_DCC__RDCC_COMP_MODE_MASK 0x80000000UL + +// VPEC_CE_OP_MULTI_64B_BURST +#define VPEC_CE_OP_MULTI_64B_BURST__EN_MASK 0x00000001UL +#define VPEC_CE_OP_MULTI_64B_BURST__RESERVED_3_1_MASK 0x0000000eUL +#define VPEC_CE_OP_MULTI_64B_BURST__LAZY_TIMER_DLY_MASK 0x000003f0UL +#define VPEC_CE_OP_MULTI_64B_BURST__NUM_64B_BURST_ALLOWED_MASK 0x00000c00UL +#define VPEC_CE_OP_MULTI_64B_BURST__RESERVED_31_12_MASK 0xfffff000UL + +// VPEC_CNTL1 +#define VPEC_CNTL1__RESERVED_3_1_MASK 0x0000000eUL +#define VPEC_CNTL1__SRBM_POLL_RETRYING_MASK 0x00000020UL +#define VPEC_CNTL1__RESERVED_23_10_MASK 0x00fffc00UL +#define VPEC_CNTL1__CG_STATUS_OUTPUT_MASK 0x01000000UL +#define VPEC_CNTL1__SW_FREEZE_ENABLE_MASK 0x02000000UL +#define VPEC_CNTL1__VPEP_CONFIG_INVALID_CHECK_ENABLE_MASK 0x04000000UL +#define VPEC_CNTL1__RSMU_ACCESS_OFF_VPEP_RETURN_ERROR_ENABLE_MASK 0x08000000UL +#define VPEC_CNTL1__RSMU_ACCESS_OFF_VPEP_REPORT_ERROR_ENABLE_MASK 0x10000000UL +#define VPEC_CNTL1__RESERVED_MASK 0xe0000000UL + +// VPEC_CNTL2 +#define VPEC_CNTL2__F32_CMD_PROC_DELAY_MASK 0x0000000fUL +#define VPEC_CNTL2__F32_SEND_POSTCODE_EN_MASK 0x00000010UL +#define VPEC_CNTL2__UCODE_BUF_DS_EN_MASK 0x00000040UL +#define VPEC_CNTL2__UCODE_SELFLOAD_THREAD_OVERLAP_MASK 0x00000080UL +#define VPEC_CNTL2__LUTIB_FIFO_WATERMARK_MASK 0x00000300UL +#define VPEC_CNTL2__CMDIB_FIFO_WATERMARK_MASK 0x00000c00UL +#define VPEC_CNTL2__RESERVED_14_12_MASK 0x00007000UL +#define VPEC_CNTL2__IMPROVE_CE_IP_ARBITER_MASK 0x00008000UL +#define VPEC_CNTL2__RB_FIFO_WATERMARK_MASK 0x00030000UL +#define VPEC_CNTL2__IB_FIFO_WATERMARK_MASK 0x000c0000UL +#define VPEC_CNTL2__RESERVED_22_20_MASK 0x00700000UL +#define VPEC_CNTL2__CH_RD_WATERMARK_MASK 0x01800000UL +#define VPEC_CNTL2__CH_WR_WATERMARK_MASK 0x3e000000UL +#define VPEC_CNTL2__CH_WR_WATERMARK_LSB_MASK 0x40000000UL + +// VPEC_GB_ADDR_CONFIG +#define VPEC_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007UL +#define VPEC_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038UL +#define VPEC_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000c0UL +#define VPEC_GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700UL +#define VPEC_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000UL +#define VPEC_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0c000000UL + +// VPEC_GB_ADDR_CONFIG_READ +#define VPEC_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007UL +#define VPEC_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038UL +#define VPEC_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000c0UL +#define VPEC_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK 0x00000700UL +#define VPEC_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000UL +#define VPEC_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0c000000UL + +// VPEC_GB_ADDR_CONFIG_META +#define VPEC_GB_ADDR_CONFIG_META__NUM_PIPES_MASK 0x00000007UL +#define VPEC_GB_ADDR_CONFIG_META__PIPE_INTERLEAVE_SIZE_MASK 0x00000038UL +#define VPEC_GB_ADDR_CONFIG_META__MAX_COMPRESSED_FRAGS_MASK 0x000000c0UL +#define VPEC_GB_ADDR_CONFIG_META__NUM_PKRS_MASK 0x00000700UL +#define VPEC_GB_ADDR_CONFIG_META__NUM_SHADER_ENGINES_MASK 0x00180000UL +#define VPEC_GB_ADDR_CONFIG_META__NUM_RB_PER_SE_MASK 0x0c000000UL + +// VPEC_PROCESS_QUANTUM0 +#define VPEC_PROCESS_QUANTUM0__PROCESS0_QUANTUM_MASK 0x000000ffUL +#define VPEC_PROCESS_QUANTUM0__PROCESS1_QUANTUM_MASK 0x0000ff00UL +#define VPEC_PROCESS_QUANTUM0__PROCESS2_QUANTUM_MASK 0x00ff0000UL +#define VPEC_PROCESS_QUANTUM0__PROCESS3_QUANTUM_MASK 0xff000000UL + +// VPEC_PROCESS_QUANTUM1 +#define VPEC_PROCESS_QUANTUM1__PROCESS4_QUANTUM_MASK 0x000000ffUL +#define VPEC_PROCESS_QUANTUM1__PROCESS5_QUANTUM_MASK 0x0000ff00UL +#define VPEC_PROCESS_QUANTUM1__PROCESS6_QUANTUM_MASK 0x00ff0000UL +#define VPEC_PROCESS_QUANTUM1__PROCESS7_QUANTUM_MASK 0xff000000UL + +// VPEC_CONTEXT_SWITCH_THRESHOLD +#define VPEC_CONTEXT_SWITCH_THRESHOLD__REALTIME_THRESHOLD_MASK 0x00000003UL +#define VPEC_CONTEXT_SWITCH_THRESHOLD__FOCUS_THRESHOLD_MASK 0x0000000cUL +#define VPEC_CONTEXT_SWITCH_THRESHOLD__NORMAL_THRESHOLD_MASK 0x00000030UL +#define VPEC_CONTEXT_SWITCH_THRESHOLD__IDLE_THRESHOLD_MASK 0x000000c0UL + +// VPEC_GLOBAL_QUANTUM +#define VPEC_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM_MASK 0x000000ffUL +#define VPEC_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM_MASK 0x0000ff00UL + +// VPEC_HWE_MASK +#define VPEC_HWE_MASK__HWE_MASK_MASK 0x0000ffffUL + +// VPEC_HWE_SRC_DST_TABLE0 +#define VPEC_HWE_SRC_DST_TABLE0__TABLE0_MASK 0xffffffffUL + +// VPEC_HWE_SRC_DST_TABLE1 +#define VPEC_HWE_SRC_DST_TABLE1__TABLE1_MASK 0xffffffffUL + +// VPEC_WATCHDOG_CNTL +#define VPEC_WATCHDOG_CNTL__QUEUE_HANG_COUNT_MASK 0x000000ffUL +#define VPEC_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT_MASK 0x0000ff00UL + +// VPEC_ATOMIC_CNTL +#define VPEC_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7fffffffUL +#define VPEC_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000UL + +// VPEC_UCODE_VERSION +#define VPEC_UCODE_VERSION__T0_UCODE_VERSION_MASK 0x0000ffffUL +#define VPEC_UCODE_VERSION__T1_UCODE_VERSION_MASK 0xffff0000UL + +// VPEC_MEMREQ_BURST_CNTL +#define VPEC_MEMREQ_BURST_CNTL__DATA_RD_BURST_MASK 0x00000003UL +#define VPEC_MEMREQ_BURST_CNTL__DATA_WR_BURST_MASK 0x0000000cUL +#define VPEC_MEMREQ_BURST_CNTL__RB_RD_BURST_MASK 0x00000030UL +#define VPEC_MEMREQ_BURST_CNTL__IB_RD_BURST_MASK 0x000000c0UL +#define VPEC_MEMREQ_BURST_CNTL__WR_BURST_WAIT_CYCLE_MASK 0x00000700UL + +// VPEC_TIMESTAMP_CNTL +#define VPEC_TIMESTAMP_CNTL__CAPTURE_MASK 0x00000001UL + +// VPEC_GLOBAL_TIMESTAMP_LO +#define VPEC_GLOBAL_TIMESTAMP_LO__DATA_MASK 0xffffffffUL + +// VPEC_GLOBAL_TIMESTAMP_HI +#define VPEC_GLOBAL_TIMESTAMP_HI__DATA_MASK 0xffffffffUL + +// VPEC_FREEZE +#define VPEC_FREEZE__PREEMPT_MASK 0x00000001UL +#define VPEC_FREEZE__FREEZE_MASK 0x00000010UL +#define VPEC_FREEZE__FROZEN_MASK 0x00000020UL +#define VPEC_FREEZE__F32_FREEZE_MASK 0x00000040UL + +// VPEC_CE_CTRL +#define VPEC_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007UL +#define VPEC_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018UL +#define VPEC_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000e0UL +#define VPEC_CE_CTRL__RESERVED_MASK 0xffffff00UL + +// VPEC_RELAX_ORDERING_LUT +#define VPEC_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001UL +#define VPEC_RELAX_ORDERING_LUT__VPE_MASK 0x00000002UL +#define VPEC_RELAX_ORDERING_LUT__RESERVED_2_2_MASK 0x00000004UL +#define VPEC_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008UL +#define VPEC_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010UL +#define VPEC_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020UL +#define VPEC_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000c0UL +#define VPEC_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100UL +#define VPEC_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200UL +#define VPEC_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400UL +#define VPEC_RELAX_ORDERING_LUT__RESERVED_11_11_MASK 0x00000800UL +#define VPEC_RELAX_ORDERING_LUT__RESERVED_12_12_MASK 0x00001000UL +#define VPEC_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000UL +#define VPEC_RELAX_ORDERING_LUT__NATIVE_FENCE_MASK 0x00004000UL +#define VPEC_RELAX_ORDERING_LUT__RESERVED_MASK 0x07ff8000UL +#define VPEC_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000UL +#define VPEC_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000UL +#define VPEC_RELAX_ORDERING_LUT__RESERVED_29_29_MASK 0x20000000UL +#define VPEC_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000UL +#define VPEC_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000UL + +// VPEC_CREDIT_CNTL +#define VPEC_CREDIT_CNTL__DRM_CREDIT_MASK 0x0000007fUL +#define VPEC_CREDIT_CNTL__MC_WRREQ_CREDIT_MASK 0x00001f80UL +#define VPEC_CREDIT_CNTL__MC_RDREQ_CREDIT_MASK 0x0007e000UL + +// VPEC_SCRATCH_RAM_DATA +#define VPEC_SCRATCH_RAM_DATA__DATA_MASK 0xffffffffUL + +// VPEC_SCRATCH_RAM_ADDR +#define VPEC_SCRATCH_RAM_ADDR__ADDR_MASK 0x000000ffUL + +// VPEC_QUEUE_RESET_REQ +#define VPEC_QUEUE_RESET_REQ__QUEUE0_RESET_MASK 0x00000001UL +#define VPEC_QUEUE_RESET_REQ__QUEUE1_RESET_MASK 0x00000002UL +#define VPEC_QUEUE_RESET_REQ__QUEUE2_RESET_MASK 0x00000004UL +#define VPEC_QUEUE_RESET_REQ__QUEUE3_RESET_MASK 0x00000008UL +#define VPEC_QUEUE_RESET_REQ__QUEUE4_RESET_MASK 0x00000010UL +#define VPEC_QUEUE_RESET_REQ__QUEUE5_RESET_MASK 0x00000020UL +#define VPEC_QUEUE_RESET_REQ__QUEUE6_RESET_MASK 0x00000040UL +#define VPEC_QUEUE_RESET_REQ__QUEUE7_RESET_MASK 0x00000080UL +#define VPEC_QUEUE_RESET_REQ__RESERVED_MASK 0xffffff00UL + +// VPEC_PERFCNT_PERFCOUNTER0_CFG +#define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000ffUL +#define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000ff00UL +#define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0f000000UL +#define VPEC_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000UL +#define VPEC_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000UL + +// VPEC_PERFCNT_PERFCOUNTER1_CFG +#define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000ffUL +#define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000ff00UL +#define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0f000000UL +#define VPEC_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000UL +#define VPEC_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000UL + +// VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000fUL +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000ff00UL +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00ff0000UL +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000UL +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000UL +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000UL + +// VPEC_PERFCNT_MISC_CNTL +#define VPEC_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000ffffUL +#define VPEC_PERFCNT_MISC_CNTL__MMHUB_REQ_EVENT_SELECT_MASK 0x00010000UL + +// VPEC_PERFCNT_PERFCOUNTER_LO +#define VPEC_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffffUL + +// VPEC_PERFCNT_PERFCOUNTER_HI +#define VPEC_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000ffffUL +#define VPEC_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000UL + +// VPEC_DEBUG_INDEX +#define VPEC_DEBUG_INDEX__INDEX_MASK 0xffffffffUL + +// VPEC_DEBUG_DATA +#define VPEC_DEBUG_DATA__DATA_MASK 0xffffffffUL + +// VPEC_CRC_CNTL +#define VPEC_CRC_CNTL__ENABLE_MASK 0x00000001UL +#define VPEC_CRC_CNTL__CLEAR_MASK 0x00000002UL + +// VPEC_CRC_INDEX +#define VPEC_CRC_INDEX__PIPE_MASK 0x0000000fUL +#define VPEC_CRC_INDEX__CRC_NODE_MASK 0x00000030UL + +// VPEC_CRC_DATA0 +#define VPEC_CRC_DATA0__DATA_MASK 0xffffffffUL + +// VPEC_CRC_DATA1 +#define VPEC_CRC_DATA1__DATA_MASK 0xffffffffUL + +// VPEC_CRC_DATA2 +#define VPEC_CRC_DATA2__DATA_MASK 0x00ffffffUL + +// VPEC_MAILBOX0 +#define VPEC_MAILBOX0__VALUE_MASK 0xffffffffUL + +// VPEC_MAILBOX1 +#define VPEC_MAILBOX1__VALUE_MASK 0xffffffffUL + +// VPEC_MAILBOX2 +#define VPEC_MAILBOX2__VALUE_MASK 0xffffffffUL + +// VPEC_MAILBOX3 +#define VPEC_MAILBOX3__VALUE_MASK 0xffffffffUL + +// VPEC_MAILBOX4 +#define VPEC_MAILBOX4__VALUE_MASK 0xffffffffUL + +// VPEC_MAILBOX5 +#define VPEC_MAILBOX5__VALUE_MASK 0xffffffffUL + +// VPEC_MAILBOX6 +#define VPEC_MAILBOX6__VALUE_MASK 0xffffffffUL + +// VPEC_MAILBOX7 +#define VPEC_MAILBOX7__VALUE_MASK 0xffffffffUL + +// VPEC_MAILBOX8 +#define VPEC_MAILBOX8__VALUE_MASK 0xffffffffUL + +// VPEC_MAILBOX9 +#define VPEC_MAILBOX9__VALUE_MASK 0xffffffffUL + +// VPEC_MAILBOX10 +#define VPEC_MAILBOX10__VALUE_MASK 0xffffffffUL + +// VPEC_MAILBOX11 +#define VPEC_MAILBOX11__VALUE_MASK 0xffffffffUL + +// VPEC_MAILBOX12 +#define VPEC_MAILBOX12__VALUE_MASK 0xffffffffUL + +// VPEC_MAILBOX13 +#define VPEC_MAILBOX13__VALUE_MASK 0xffffffffUL + +// VPEC_MAILBOX14 +#define VPEC_MAILBOX14__VALUE_MASK 0xffffffffUL + +// VPEC_MAILBOX15 +#define VPEC_MAILBOX15__VALUE_MASK 0xffffffffUL + +// VPEC_PUB_DUMMY0 +#define VPEC_PUB_DUMMY0__VALUE_MASK 0xffffffffUL + +// VPEC_PUB_DUMMY1 +#define VPEC_PUB_DUMMY1__VALUE_MASK 0xffffffffUL + +// VPEC_PUB_DUMMY2 +#define VPEC_PUB_DUMMY2__VALUE_MASK 0xffffffffUL + +// VPEC_PUB_DUMMY3 +#define VPEC_PUB_DUMMY3__VALUE_MASK 0xffffffffUL + +// VPEC_PUB_DUMMY4 +#define VPEC_PUB_DUMMY4__VALUE_MASK 0xffffffffUL + +// VPEC_PUB_DUMMY5 +#define VPEC_PUB_DUMMY5__VALUE_MASK 0xffffffffUL + +// VPEC_PUB_DUMMY6 +#define VPEC_PUB_DUMMY6__VALUE_MASK 0xffffffffUL + +// VPEC_PUB_DUMMY7 +#define VPEC_PUB_DUMMY7__VALUE_MASK 0xffffffffUL + +// VPEC_PUB_DUMMY8 +#define VPEC_PUB_DUMMY8__VALUE_MASK 0xffffffffUL + +// VPEC_PUB_DUMMY9 +#define VPEC_PUB_DUMMY9__VALUE_MASK 0xffffffffUL + +// VPEC_PUB_DUMMY10 +#define VPEC_PUB_DUMMY10__VALUE_MASK 0xffffffffUL + +// VPEC_PUB_DUMMY11 +#define VPEC_PUB_DUMMY11__VALUE_MASK 0xffffffffUL + +// VPEC_UCODE1_CHECKSUM +#define VPEC_UCODE1_CHECKSUM__DATA_MASK 0xffffffffUL + +// VPEC_VERSION +#define VPEC_VERSION__MINVER_MASK 0x0000007fUL +#define VPEC_VERSION__MAJVER_MASK 0x00007f00UL +#define VPEC_VERSION__REV_MASK 0x003f0000UL + +// VPEC_UCODE_CHECKSUM +#define VPEC_UCODE_CHECKSUM__DATA_MASK 0xffffffffUL + +// VPEC_RB_RPTR_FETCH +#define VPEC_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffcUL + +// VPEC_RB_RPTR_FETCH_HI +#define VPEC_RB_RPTR_FETCH_HI__OFFSET_MASK 0xffffffffUL + +// VPEC_IB_OFFSET_FETCH +#define VPEC_IB_OFFSET_FETCH__OFFSET_MASK 0x003ffffcUL + +// VPEC_CMDIB_OFFSET_FETCH +#define VPEC_CMDIB_OFFSET_FETCH__OFFSET_MASK 0x003ffffcUL + +// VPEC_3DLUTIB_OFFSET_FETCH +#define VPEC_3DLUTIB_OFFSET_FETCH__OFFSET_MASK 0x003ffffcUL + +// VPEC_ATOMIC_PREOP_LO +#define VPEC_ATOMIC_PREOP_LO__DATA_MASK 0xffffffffUL + +// VPEC_ATOMIC_PREOP_HI +#define VPEC_ATOMIC_PREOP_HI__DATA_MASK 0xffffffffUL + +// VPEC_CE_BUSY +#define VPEC_CE_BUSY__CE_IP_PIPE0_BUSY_MASK 0x00000001UL +#define VPEC_CE_BUSY__CE_IP_PIPE1_BUSY_MASK 0x00000002UL +#define VPEC_CE_BUSY__CE_IP_PIPE2_BUSY_MASK 0x00000004UL +#define VPEC_CE_BUSY__CE_IP_PIPE3_BUSY_MASK 0x00000008UL +#define VPEC_CE_BUSY__CE_IP_PIPE4_BUSY_MASK 0x00000010UL +#define VPEC_CE_BUSY__CE_IP_PIPE5_BUSY_MASK 0x00000020UL +#define VPEC_CE_BUSY__CE_OP_PIPE0_BUSY_MASK 0x00010000UL +#define VPEC_CE_BUSY__CE_OP_PIPE1_BUSY_MASK 0x00020000UL +#define VPEC_CE_BUSY__CE_OP_PIPE2_BUSY_MASK 0x00040000UL +#define VPEC_CE_BUSY__CE_OP_PIPE3_BUSY_MASK 0x00080000UL +#define VPEC_CE_BUSY__CE_OP_PIPE4_BUSY_MASK 0x00100000UL +#define VPEC_CE_BUSY__CE_OP_PIPE5_BUSY_MASK 0x00200000UL +#define VPEC_CE_BUSY__CE_OP_PIPE6_BUSY_MASK 0x00400000UL +#define VPEC_CE_BUSY__CE_OP_PIPE7_BUSY_MASK 0x00800000UL +#define VPEC_CE_BUSY__CE_OP_PIPE8_BUSY_MASK 0x01000000UL +#define VPEC_CE_BUSY__CE_OP_PIPE9_BUSY_MASK 0x02000000UL + +// VPEC_F32_COUNTER +#define VPEC_F32_COUNTER__VALUE_MASK 0xffffffffUL + +// VPEC_HOLE_ADDR_LO +#define VPEC_HOLE_ADDR_LO__VALUE_MASK 0xffffffffUL + +// VPEC_HOLE_ADDR_HI +#define VPEC_HOLE_ADDR_HI__VALUE_MASK 0xffffffffUL + +// VPEC_ERROR_LOG +#define VPEC_ERROR_LOG__OVERRIDE_MASK 0x0000ffffUL +#define VPEC_ERROR_LOG__STATUS_MASK 0xffff0000UL + +// VPEC_INT_STATUS +#define VPEC_INT_STATUS__DATA_MASK 0xffffffffUL + +// VPEC_STATUS +#define VPEC_STATUS__IDLE_MASK 0x00000001UL +#define VPEC_STATUS__REG_IDLE_MASK 0x00000002UL +#define VPEC_STATUS__RB_EMPTY_MASK 0x00000004UL +#define VPEC_STATUS__RB_FULL_MASK 0x00000008UL +#define VPEC_STATUS__RB_CMD_IDLE_MASK 0x00000010UL +#define VPEC_STATUS__RB_CMD_FULL_MASK 0x00000020UL +#define VPEC_STATUS__IB_CMD_IDLE_MASK 0x00000040UL +#define VPEC_STATUS__IB_CMD_FULL_MASK 0x00000080UL +#define VPEC_STATUS__BLOCK_IDLE_MASK 0x00000100UL +#define VPEC_STATUS__INSIDE_VPEP_CONFIG_MASK 0x00000200UL +#define VPEC_STATUS__EX_IDLE_MASK 0x00000400UL +#define VPEC_STATUS__INSIDE_VPEP_3DLUT_CONFIG_MASK 0x00000800UL +#define VPEC_STATUS__PACKET_READY_MASK 0x00001000UL +#define VPEC_STATUS__MC_WR_IDLE_MASK 0x00002000UL +#define VPEC_STATUS__SRBM_IDLE_MASK 0x00004000UL +#define VPEC_STATUS__CONTEXT_EMPTY_MASK 0x00008000UL +#define VPEC_STATUS__INSIDE_IB_MASK 0x00010000UL +#define VPEC_STATUS__RB_MC_RREQ_IDLE_MASK 0x00020000UL +#define VPEC_STATUS__IB_MC_RREQ_IDLE_MASK 0x00040000UL +#define VPEC_STATUS__MC_RD_IDLE_MASK 0x00080000UL +#define VPEC_STATUS__DELTA_RPTR_EMPTY_MASK 0x00100000UL +#define VPEC_STATUS__MC_RD_RET_STALL_MASK 0x00200000UL +#define VPEC_STATUS__LUTIB_CMD_IDLE_MASK 0x00400000UL +#define VPEC_STATUS__LUTIB_CMD_FULL_MASK 0x00800000UL +#define VPEC_STATUS__CMDIB_MC_RREQ_IDLE_MASK 0x01000000UL +#define VPEC_STATUS__PREV_CMD_IDLE_MASK 0x02000000UL +#define VPEC_STATUS__CMDIB_CMD_IDLE_MASK 0x04000000UL +#define VPEC_STATUS__CMDIB_CMD_FULL_MASK 0x08000000UL +#define VPEC_STATUS__RESERVED_29_28_MASK 0x30000000UL +#define VPEC_STATUS__INT_IDLE_MASK 0x40000000UL +#define VPEC_STATUS__INT_REQ_STALL_MASK 0x80000000UL + +// VPEC_STATUS1 +#define VPEC_STATUS1__EX_START_MASK 0x00000001UL +#define VPEC_STATUS1__VPEC_IDLE_MASK 0x00000002UL +#define VPEC_STATUS1__RESERVED_31_2_MASK 0xfffffffcUL + +// VPEC_STATUS2 +#define VPEC_STATUS2__ID_MASK 0x00000003UL +#define VPEC_STATUS2__TH0F32_INSTR_PTR_MASK 0x0000fffcUL +#define VPEC_STATUS2__CMD_OP_MASK 0xffff0000UL + +// VPEC_STATUS3 +#define VPEC_STATUS3__RESERVED_15_0_MASK 0x0000ffffUL +#define VPEC_STATUS3__RESERVED_19_16_MASK 0x000f0000UL +#define VPEC_STATUS3__EXCEPTION_IDLE_MASK 0x00100000UL +#define VPEC_STATUS3__RESERVED_21_21_MASK 0x00200000UL +#define VPEC_STATUS3__RESERVED_22_22_MASK 0x00400000UL +#define VPEC_STATUS3__RESERVED_23_23_MASK 0x00800000UL +#define VPEC_STATUS3__RESERVED_24_24_MASK 0x01000000UL +#define VPEC_STATUS3__RESERVED_25_25_MASK 0x02000000UL +#define VPEC_STATUS3__INT_QUEUE_ID_MASK 0x3c000000UL +#define VPEC_STATUS3__RESERVED_31_30_MASK 0xc0000000UL + +// VPEC_STATUS4 +#define VPEC_STATUS4__IDLE_MASK 0x00000001UL +#define VPEC_STATUS4__IH_OUTSTANDING_MASK 0x00000004UL +#define VPEC_STATUS4__RESERVED_3_3_MASK 0x00000008UL +#define VPEC_STATUS4__CH_RD_OUTSTANDING_MASK 0x00000010UL +#define VPEC_STATUS4__CH_WR_OUTSTANDING_MASK 0x00000020UL +#define VPEC_STATUS4__RESERVED_6_6_MASK 0x00000040UL +#define VPEC_STATUS4__RESERVED_7_7_MASK 0x00000080UL +#define VPEC_STATUS4__RESERVED_8_8_MASK 0x00000100UL +#define VPEC_STATUS4__RESERVED_9_9_MASK 0x00000200UL +#define VPEC_STATUS4__REG_POLLING_MASK 0x00000400UL +#define VPEC_STATUS4__MEM_POLLING_MASK 0x00000800UL +#define VPEC_STATUS4__VPEP_REG_RD_OUTSTANDING_MASK 0x00001000UL +#define VPEC_STATUS4__VPEP_REG_WR_OUTSTANDING_MASK 0x00002000UL +#define VPEC_STATUS4__RESERVED_15_14_MASK 0x0000c000UL +#define VPEC_STATUS4__ACTIVE_QUEUE_ID_MASK 0x000f0000UL +#define VPEC_STATUS4__RESERVED_27_20_MASK 0x0ff00000UL + +// VPEC_STATUS5 +#define VPEC_STATUS5__QUEUE0_RB_ENABLE_STATUS_MASK 0x00000001UL +#define VPEC_STATUS5__QUEUE1_RB_ENABLE_STATUS_MASK 0x00000002UL +#define VPEC_STATUS5__QUEUE2_RB_ENABLE_STATUS_MASK 0x00000004UL +#define VPEC_STATUS5__QUEUE3_RB_ENABLE_STATUS_MASK 0x00000008UL +#define VPEC_STATUS5__QUEUE4_RB_ENABLE_STATUS_MASK 0x00000010UL +#define VPEC_STATUS5__QUEUE5_RB_ENABLE_STATUS_MASK 0x00000020UL +#define VPEC_STATUS5__QUEUE6_RB_ENABLE_STATUS_MASK 0x00000040UL +#define VPEC_STATUS5__QUEUE7_RB_ENABLE_STATUS_MASK 0x00000080UL +#define VPEC_STATUS5__RESERVED_27_16_MASK 0x000f0000UL + +// VPEC_STATUS6 +#define VPEC_STATUS6__ID_MASK 0x00000003UL +#define VPEC_STATUS6__TH1F32_INSTR_PTR_MASK 0x0000fffcUL +#define VPEC_STATUS6__TH1_EXCEPTION_MASK 0xffff0000UL + +// VPEC_STATUS7 +#define VPEC_STATUS7__TH0_DBG_STATUS_MASK 0xffffffffUL + +// VPEC_STATUS8 +#define VPEC_STATUS8__CE_IP0_WREQ_IDLE_MASK 0x00000001UL +#define VPEC_STATUS8__CE_IP0_WR_IDLE_MASK 0x00000002UL +#define VPEC_STATUS8__CE_IP0_SPLIT_RD_IDLE_MASK 0x00000004UL +#define VPEC_STATUS8__CE_IP0_SPLIT_WR_IDLE_MASK 0x00000008UL +#define VPEC_STATUS8__CE_IP0_RREQ_IDLE_MASK 0x00000010UL +#define VPEC_STATUS8__CE_IP0_OUT_IDLE_MASK 0x00000020UL +#define VPEC_STATUS8__CE_IP0_IN_IDLE_MASK 0x00000040UL +#define VPEC_STATUS8__CE_IP0_DST_IDLE_MASK 0x00000080UL +#define VPEC_STATUS8__CE_IP0_CMD_IDLE_MASK 0x00000100UL +#define VPEC_STATUS8__CE_IP1_WREQ_IDLE_MASK 0x00000200UL +#define VPEC_STATUS8__CE_IP1_WR_IDLE_MASK 0x00000400UL +#define VPEC_STATUS8__CE_IP1_SPLIT_RD_IDLE_MASK 0x00000800UL +#define VPEC_STATUS8__CE_IP1_SPLIT_WR_IDLE_MASK 0x00001000UL +#define VPEC_STATUS8__CE_IP1_RREQ_IDLE_MASK 0x00002000UL +#define VPEC_STATUS8__CE_IP1_OUT_IDLE_MASK 0x00004000UL +#define VPEC_STATUS8__CE_IP1_IN_IDLE_MASK 0x00008000UL +#define VPEC_STATUS8__CE_IP1_DST_IDLE_MASK 0x00010000UL +#define VPEC_STATUS8__CE_IP1_CMD_IDLE_MASK 0x00020000UL +#define VPEC_STATUS8__CE_IP0_AFIFO_FULL_MASK 0x00040000UL +#define VPEC_STATUS8__CE_IP0_CMD_INFO_FULL_MASK 0x00080000UL +#define VPEC_STATUS8__CE_IP0_CMD_INFO1_FULL_MASK 0x00100000UL +#define VPEC_STATUS8__CE_IP1_AFIFO_FULL_MASK 0x00200000UL +#define VPEC_STATUS8__CE_IP1_CMD_INFO_FULL_MASK 0x00400000UL +#define VPEC_STATUS8__CE_IP1_CMD_INFO1_FULL_MASK 0x00800000UL +#define VPEC_STATUS8__CE_IP0_WR_STALL_MASK 0x01000000UL +#define VPEC_STATUS8__CE_IP1_WR_STALL_MASK 0x02000000UL +#define VPEC_STATUS8__CE_IP0_RD_STALL_MASK 0x04000000UL +#define VPEC_STATUS8__CE_IP1_RD_STALL_MASK 0x08000000UL +#define VPEC_STATUS8__RESERVED_31_28_MASK 0xf0000000UL + +// VPEC_STATUS9 +#define VPEC_STATUS9__CE_IP2_WREQ_IDLE_MASK 0x00000001UL +#define VPEC_STATUS9__CE_IP2_WR_IDLE_MASK 0x00000002UL +#define VPEC_STATUS9__CE_IP2_SPLIT_RD_IDLE_MASK 0x00000004UL +#define VPEC_STATUS9__CE_IP2_SPLIT_WR_IDLE_MASK 0x00000008UL +#define VPEC_STATUS9__CE_IP2_RREQ_IDLE_MASK 0x00000010UL +#define VPEC_STATUS9__CE_IP2_OUT_IDLE_MASK 0x00000020UL +#define VPEC_STATUS9__CE_IP2_IN_IDLE_MASK 0x00000040UL +#define VPEC_STATUS9__CE_IP2_DST_IDLE_MASK 0x00000080UL +#define VPEC_STATUS9__CE_IP2_CMD_IDLE_MASK 0x00000100UL +#define VPEC_STATUS9__CE_IP3_WREQ_IDLE_MASK 0x00000200UL +#define VPEC_STATUS9__CE_IP3_WR_IDLE_MASK 0x00000400UL +#define VPEC_STATUS9__CE_IP3_SPLIT_RD_IDLE_MASK 0x00000800UL +#define VPEC_STATUS9__CE_IP3_SPLIT_WR_IDLE_MASK 0x00001000UL +#define VPEC_STATUS9__CE_IP3_RREQ_IDLE_MASK 0x00002000UL +#define VPEC_STATUS9__CE_IP3_OUT_IDLE_MASK 0x00004000UL +#define VPEC_STATUS9__CE_IP3_IN_IDLE_MASK 0x00008000UL +#define VPEC_STATUS9__CE_IP3_DST_IDLE_MASK 0x00010000UL +#define VPEC_STATUS9__CE_IP3_CMD_IDLE_MASK 0x00020000UL +#define VPEC_STATUS9__CE_IP2_AFIFO_FULL_MASK 0x00040000UL +#define VPEC_STATUS9__CE_IP2_CMD_INFO_FULL_MASK 0x00080000UL +#define VPEC_STATUS9__CE_IP2_CMD_INFO1_FULL_MASK 0x00100000UL +#define VPEC_STATUS9__CE_IP3_AFIFO_FULL_MASK 0x00200000UL +#define VPEC_STATUS9__CE_IP3_CMD_INFO_FULL_MASK 0x00400000UL +#define VPEC_STATUS9__CE_IP3_CMD_INFO1_FULL_MASK 0x00800000UL +#define VPEC_STATUS9__CE_IP2_WR_STALL_MASK 0x01000000UL +#define VPEC_STATUS9__CE_IP3_WR_STALL_MASK 0x02000000UL +#define VPEC_STATUS9__CE_IP2_RD_STALL_MASK 0x04000000UL +#define VPEC_STATUS9__CE_IP3_RD_STALL_MASK 0x08000000UL +#define VPEC_STATUS9__RESERVED_31_28_MASK 0xf0000000UL + +// VPEC_STATUS10 +#define VPEC_STATUS10__CE_OP0_WR_IDLE_MASK 0x00000001UL +#define VPEC_STATUS10__CE_OP0_CMD_IDLE_MASK 0x00000002UL +#define VPEC_STATUS10__CE_OP1_WR_IDLE_MASK 0x00000004UL +#define VPEC_STATUS10__CE_OP1_CMD_IDLE_MASK 0x00000008UL +#define VPEC_STATUS10__CE_OP2_WR_IDLE_MASK 0x00000010UL +#define VPEC_STATUS10__CE_OP2_CMD_IDLE_MASK 0x00000020UL +#define VPEC_STATUS10__CE_OP3_WR_IDLE_MASK 0x00000040UL +#define VPEC_STATUS10__CE_OP3_CMD_IDLE_MASK 0x00000080UL +#define VPEC_STATUS10__CE_OP4_WR_IDLE_MASK 0x00000100UL +#define VPEC_STATUS10__CE_OP4_CMD_IDLE_MASK 0x00000200UL +#define VPEC_STATUS10__CE_OP5_WR_IDLE_MASK 0x00000400UL +#define VPEC_STATUS10__CE_OP5_CMD_IDLE_MASK 0x00000800UL +#define VPEC_STATUS10__CE_OP6_WR_IDLE_MASK 0x00001000UL +#define VPEC_STATUS10__CE_OP6_CMD_IDLE_MASK 0x00002000UL +#define VPEC_STATUS10__CE_OP7_WR_IDLE_MASK 0x00004000UL +#define VPEC_STATUS10__CE_OP7_CMD_IDLE_MASK 0x00008000UL +#define VPEC_STATUS10__CE_OP8_WR_IDLE_MASK 0x00010000UL +#define VPEC_STATUS10__CE_OP8_CMD_IDLE_MASK 0x00020000UL +#define VPEC_STATUS10__CE_OP9_WR_IDLE_MASK 0x00040000UL +#define VPEC_STATUS10__CE_OP9_CMD_IDLE_MASK 0x00080000UL +#define VPEC_STATUS10__RESERVED_31_28_MASK 0xf0000000UL + +// VPEC_STATUS_DCC +#define VPEC_STATUS_DCC__CE_IP0_MRQ_IDLE_MASK 0x00000001UL +#define VPEC_STATUS_DCC__CE_IP0_DCCP_IDLE_MASK 0x00000002UL +#define VPEC_STATUS_DCC__CE_IP0_DCC_RET_IDLE_MASK 0x00000004UL +#define VPEC_STATUS_DCC__CE_IP1_MRQ_IDLE_MASK 0x00000008UL +#define VPEC_STATUS_DCC__CE_IP1_DCCP_IDLE_MASK 0x00000010UL +#define VPEC_STATUS_DCC__CE_IP1_DCC_RET_IDLE_MASK 0x00000020UL +#define VPEC_STATUS_DCC__CE_IP2_MRQ_IDLE_MASK 0x00000040UL +#define VPEC_STATUS_DCC__CE_IP2_DCCP_IDLE_MASK 0x00000080UL +#define VPEC_STATUS_DCC__CE_IP2_DCC_RET_IDLE_MASK 0x00000100UL +#define VPEC_STATUS_DCC__CE_IP3_MRQ_IDLE_MASK 0x00000200UL +#define VPEC_STATUS_DCC__CE_IP3_DCCP_IDLE_MASK 0x00000400UL +#define VPEC_STATUS_DCC__CE_IP3_DCC_RET_IDLE_MASK 0x00000800UL +#define VPEC_STATUS_DCC__CE_IP4_MRQ_IDLE_MASK 0x00001000UL +#define VPEC_STATUS_DCC__CE_IP4_DCCP_IDLE_MASK 0x00002000UL +#define VPEC_STATUS_DCC__CE_IP4_DCC_RET_IDLE_MASK 0x00004000UL +#define VPEC_STATUS_DCC__CE_IP5_MRQ_IDLE_MASK 0x00008000UL +#define VPEC_STATUS_DCC__CE_IP5_DCCP_IDLE_MASK 0x00010000UL +#define VPEC_STATUS_DCC__CE_IP5_DCC_RET_IDLE_MASK 0x00020000UL +#define VPEC_STATUS_DCC__RESERVED_31_18_MASK 0xfffc0000UL + +// VPEC_STATUS11 +#define VPEC_STATUS11__CE_IP4_WREQ_IDLE_MASK 0x00000001UL +#define VPEC_STATUS11__CE_IP4_WR_IDLE_MASK 0x00000002UL +#define VPEC_STATUS11__CE_IP4_SPLIT_RD_IDLE_MASK 0x00000004UL +#define VPEC_STATUS11__CE_IP4_SPLIT_WR_IDLE_MASK 0x00000008UL +#define VPEC_STATUS11__CE_IP4_RREQ_IDLE_MASK 0x00000010UL +#define VPEC_STATUS11__CE_IP4_OUT_IDLE_MASK 0x00000020UL +#define VPEC_STATUS11__CE_IP4_IN_IDLE_MASK 0x00000040UL +#define VPEC_STATUS11__CE_IP4_DST_IDLE_MASK 0x00000080UL +#define VPEC_STATUS11__CE_IP4_CMD_IDLE_MASK 0x00000100UL +#define VPEC_STATUS11__CE_IP5_WREQ_IDLE_MASK 0x00000200UL +#define VPEC_STATUS11__CE_IP5_WR_IDLE_MASK 0x00000400UL +#define VPEC_STATUS11__CE_IP5_SPLIT_RD_IDLE_MASK 0x00000800UL +#define VPEC_STATUS11__CE_IP5_SPLIT_WR_IDLE_MASK 0x00001000UL +#define VPEC_STATUS11__CE_IP5_RREQ_IDLE_MASK 0x00002000UL +#define VPEC_STATUS11__CE_IP5_OUT_IDLE_MASK 0x00004000UL +#define VPEC_STATUS11__CE_IP5_IN_IDLE_MASK 0x00008000UL +#define VPEC_STATUS11__CE_IP5_DST_IDLE_MASK 0x00010000UL +#define VPEC_STATUS11__CE_IP5_CMD_IDLE_MASK 0x00020000UL +#define VPEC_STATUS11__CE_IP4_AFIFO_FULL_MASK 0x00040000UL +#define VPEC_STATUS11__CE_IP4_CMD_INFO_FULL_MASK 0x00080000UL +#define VPEC_STATUS11__CE_IP4_CMD_INFO1_FULL_MASK 0x00100000UL +#define VPEC_STATUS11__CE_IP5_AFIFO_FULL_MASK 0x00200000UL +#define VPEC_STATUS11__CE_IP5_CMD_INFO_FULL_MASK 0x00400000UL +#define VPEC_STATUS11__CE_IP5_CMD_INFO1_FULL_MASK 0x00800000UL +#define VPEC_STATUS11__CE_IP4_WR_STALL_MASK 0x01000000UL +#define VPEC_STATUS11__CE_IP5_WR_STALL_MASK 0x02000000UL +#define VPEC_STATUS11__CE_IP4_RD_STALL_MASK 0x04000000UL +#define VPEC_STATUS11__CE_IP5_RD_STALL_MASK 0x08000000UL +#define VPEC_STATUS11__RESERVED_31_28_MASK 0xf0000000UL + +// VPEC_INST +#define VPEC_INST__ID_MASK 0x00000007UL +#define VPEC_INST__RESERVED_MASK 0xfffffff8UL + +// VPEC_QUEUE_STATUS0 +#define VPEC_QUEUE_STATUS0__QUEUE0_STATUS_MASK 0x0000000fUL +#define VPEC_QUEUE_STATUS0__QUEUE1_STATUS_MASK 0x000000f0UL +#define VPEC_QUEUE_STATUS0__QUEUE2_STATUS_MASK 0x00000f00UL +#define VPEC_QUEUE_STATUS0__QUEUE3_STATUS_MASK 0x0000f000UL +#define VPEC_QUEUE_STATUS0__QUEUE4_STATUS_MASK 0x000f0000UL +#define VPEC_QUEUE_STATUS0__QUEUE5_STATUS_MASK 0x00f00000UL +#define VPEC_QUEUE_STATUS0__QUEUE6_STATUS_MASK 0x0f000000UL +#define VPEC_QUEUE_STATUS0__QUEUE7_STATUS_MASK 0xf0000000UL + +// VPEC_QUEUE_HANG_STATUS +#define VPEC_QUEUE_HANG_STATUS__F30T0_HANG_MASK 0x00000001UL +#define VPEC_QUEUE_HANG_STATUS__CE_HANG_MASK 0x00000002UL +#define VPEC_QUEUE_HANG_STATUS__EOF_MISMATCH_MASK 0x00000004UL +#define VPEC_QUEUE_HANG_STATUS__INVALID_PKT_FIELD_MASK 0x00000008UL +#define VPEC_QUEUE_HANG_STATUS__INVALID_VPEP_CONFIG_ADDR_MASK 0x00000010UL +#define VPEC_QUEUE_HANG_STATUS__F32_ACCESS_OFF_VPDPP1_MASK 0x00000020UL +#define VPEC_QUEUE_HANG_STATUS__RSMU_ACCESS_OFF_VPDPP1_MASK 0x00000040UL +#define VPEC_QUEUE_HANG_STATUS__EOH_MISMATCH_MASK 0x00000080UL + +// VPEC_DPM_IDLE_TIME +#define VPEC_DPM_IDLE_TIME__VALUE_MASK 0xffffffffUL + +// VPEC_DPM_BUSY_TIME +#define VPEC_DPM_BUSY_TIME__VALUE_MASK 0xffffffffUL + +// VPEC_DPM_IDLE_START_LO +#define VPEC_DPM_IDLE_START_LO__VALUE_MASK 0xffffffffUL + +// VPEC_DPM_IDLE_START_HI +#define VPEC_DPM_IDLE_START_HI__VALUE_MASK 0xffffffffUL + +// VPEC_DPM_BUSY_START_LO +#define VPEC_DPM_BUSY_START_LO__VALUE_MASK 0xffffffffUL + +// VPEC_DPM_BUSY_START_HI +#define VPEC_DPM_BUSY_START_HI__VALUE_MASK 0xffffffffUL + +// VPEC_DPM_LAST_REQ_TIMESTAMP +#define VPEC_DPM_LAST_REQ_TIMESTAMP__VALUE_MASK 0xffffffffUL + +// VPEC_DPM_NEW_JOB_DUMMY3 +#define VPEC_DPM_NEW_JOB_DUMMY3__VALUE_MASK 0xffffffffUL + +// VPEC_DPM_STATE +#define VPEC_DPM_STATE__VALUE_MASK 0xffffffffUL + +// VPEC_DPM0_FREQ +#define VPEC_DPM0_FREQ__VALUE_MASK 0xffffffffUL + +// VPEC_DPM1_FREQ +#define VPEC_DPM1_FREQ__VALUE_MASK 0xffffffffUL + +// VPEC_DPM2_FREQ +#define VPEC_DPM2_FREQ__VALUE_MASK 0xffffffffUL + +// VPEC_DPM3_FREQ +#define VPEC_DPM3_FREQ__VALUE_MASK 0xffffffffUL + +// VPEC_DPM_THRESHOLD_SKIP +#define VPEC_DPM_THRESHOLD_SKIP__VALUE_MASK 0xffffffffUL + +// VPEC_DPM_THRESHOLD_BUSY_OVERFLOW +#define VPEC_DPM_THRESHOLD_BUSY_OVERFLOW__VALUE_MASK 0xffffffffUL + +// VPEC_DPM_CALC_BUSY_IN_POSTPROCESS +#define VPEC_DPM_CALC_BUSY_IN_POSTPROCESS__VALUE_MASK 0xffffffffUL + +// VPEC_DPM_IN_CHECKIDLE_LOOP +#define VPEC_DPM_IN_CHECKIDLE_LOOP__VALUE_MASK 0xffffffffUL + +// VPEC_DPM_THRESHOLD_IDLE_OVERFLOW +#define VPEC_DPM_THRESHOLD_IDLE_OVERFLOW__VALUE_MASK 0xffffffffUL + +// VPEC_DPM_BUSY_CLAMP_COUNT +#define VPEC_DPM_BUSY_CLAMP_COUNT__VALUE_MASK 0xffffffffUL + +// VPEC_DPM_IDLE_CLAMP_COUNT +#define VPEC_DPM_IDLE_CLAMP_COUNT__VALUE_MASK 0xffffffffUL + +// VPEC_PG_CNTL +#define VPEC_PG_CNTL__PG_EN_MASK 0x00000001UL +#define VPEC_PG_CNTL__PG_HYSTERESIS_MASK 0x0000003eUL +#define VPEC_PG_CNTL__PG1_EN_MASK 0x00000100UL +#define VPEC_PG_CNTL__PG1_HYSTERESIS_MASK 0x00003e00UL +#define VPEC_PG_CNTL__ZSTATES_ENABLE_MASK 0x00010000UL +#define VPEC_PG_CNTL__ZSTATES_HYSTERESIS_MASK 0x003e0000UL +#define VPEC_PG_CNTL__FENCE_HYSTERESIS_MASK 0x0f000000UL +#define VPEC_PG_CNTL__CHECK_RSMU_UPON_POWER_UP_MASK 0x10000000UL + +// VPEC_PG_STATUS +#define VPEC_PG_STATUS__PG_STATUS_MASK 0x00000003UL +#define VPEC_PG_STATUS__PG1_STATUS_MASK 0x0000000cUL + +// VPEC_CLOCK_GATING_STATUS +#define VPEC_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS_MASK 0x00000001UL +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE0_CLK_GATE_STATUS_MASK 0x00000004UL +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE1_CLK_GATE_STATUS_MASK 0x00000008UL +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE2_CLK_GATE_STATUS_MASK 0x00000010UL +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE3_CLK_GATE_STATUS_MASK 0x00000020UL +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE0_CLK_GATE_STATUS_MASK 0x00000040UL +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE1_CLK_GATE_STATUS_MASK 0x00000080UL +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE2_CLK_GATE_STATUS_MASK 0x00000100UL +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE3_CLK_GATE_STATUS_MASK 0x00000200UL +#define VPEC_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS_MASK 0x00000400UL +#define VPEC_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS_MASK 0x00000800UL +#define VPEC_CLOCK_GATING_STATUS__USRAM_CLK_GATE_STATUS_MASK 0x00001000UL +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE4_CLK_GATE_STATUS_MASK 0x00002000UL +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE5_CLK_GATE_STATUS_MASK 0x00004000UL +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE6_CLK_GATE_STATUS_MASK 0x00008000UL +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE7_CLK_GATE_STATUS_MASK 0x00010000UL +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE4_CLK_GATE_STATUS_MASK 0x00020000UL +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE5_CLK_GATE_STATUS_MASK 0x00040000UL +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE8_CLK_GATE_STATUS_MASK 0x00080000UL +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE9_CLK_GATE_STATUS_MASK 0x00100000UL + +// VPEC_QUEUE0_RB_CNTL +#define VPEC_QUEUE0_RB_CNTL__RB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE0_RB_CNTL__RB_SIZE_MASK 0x0000003eUL +#define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100UL +#define VPEC_QUEUE0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200UL +#define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400UL +#define VPEC_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800UL +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000UL +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000UL +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001f0000UL +#define VPEC_QUEUE0_RB_CNTL__RB_PRIV_MASK 0x00800000UL +#define VPEC_QUEUE0_RB_CNTL__RB_VMID_MASK 0x0f000000UL + +// VPEC_QUEUE0_SCHEDULE_CNTL +#define VPEC_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003UL +#define VPEC_QUEUE0_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001cUL +#define VPEC_QUEUE0_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000c0UL +#define VPEC_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000ff00UL + +// VPEC_QUEUE0_RB_BASE +#define VPEC_QUEUE0_RB_BASE__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE0_RB_BASE_HI +#define VPEC_QUEUE0_RB_BASE_HI__ADDR_MASK 0x00ffffffUL + +// VPEC_QUEUE0_RB_RPTR +#define VPEC_QUEUE0_RB_RPTR__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE0_RB_RPTR_HI +#define VPEC_QUEUE0_RB_RPTR_HI__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE0_RB_WPTR +#define VPEC_QUEUE0_RB_WPTR__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE0_RB_WPTR_HI +#define VPEC_QUEUE0_RB_WPTR_HI__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE0_RB_RPTR_ADDR_HI +#define VPEC_QUEUE0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE0_RB_RPTR_ADDR_LO +#define VPEC_QUEUE0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffcUL + +// VPEC_QUEUE0_RB_AQL_CNTL +#define VPEC_QUEUE0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000feUL +#define VPEC_QUEUE0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000ff00UL +#define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000UL +#define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000UL +#define VPEC_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000UL + +// VPEC_QUEUE0_MINOR_PTR_UPDATE +#define VPEC_QUEUE0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001UL + +// VPEC_QUEUE0_CD_INFO +#define VPEC_QUEUE0_CD_INFO__CD_INFO_MASK 0xffffffffUL + +// VPEC_QUEUE0_RB_PREEMPT +#define VPEC_QUEUE0_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001UL + +// VPEC_QUEUE0_SKIP_CNTL +#define VPEC_QUEUE0_SKIP_CNTL__SKIP_COUNT_MASK 0x000fffffUL + +// VPEC_QUEUE0_DOORBELL +#define VPEC_QUEUE0_DOORBELL__ENABLE_MASK 0x10000000UL +#define VPEC_QUEUE0_DOORBELL__CAPTURED_MASK 0x40000000UL + +// VPEC_QUEUE0_DOORBELL_OFFSET +#define VPEC_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK 0x0ffffffcUL + +// VPEC_QUEUE0_DUMMY0 +#define VPEC_QUEUE0_DUMMY0__DUMMY_MASK 0xffffffffUL + +// VPEC_QUEUE0_DUMMY1 +#define VPEC_QUEUE0_DUMMY1__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE0_DUMMY2 +#define VPEC_QUEUE0_DUMMY2__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE0_DUMMY3 +#define VPEC_QUEUE0_DUMMY3__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE0_DUMMY4 +#define VPEC_QUEUE0_DUMMY4__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE0_IB_CNTL +#define VPEC_QUEUE0_IB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE0_IB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE0_IB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE0_IB_RPTR +#define VPEC_QUEUE0_IB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE0_IB_OFFSET +#define VPEC_QUEUE0_IB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE0_IB_BASE_LO +#define VPEC_QUEUE0_IB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE0_IB_BASE_HI +#define VPEC_QUEUE0_IB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE0_IB_SIZE +#define VPEC_QUEUE0_IB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE0_CMDIB_CNTL +#define VPEC_QUEUE0_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE0_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010UL +#define VPEC_QUEUE0_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE0_CMDIB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE0_CMDIB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE0_CMDIB_RPTR +#define VPEC_QUEUE0_CMDIB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE0_CMDIB_OFFSET +#define VPEC_QUEUE0_CMDIB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE0_CMDIB_BASE_LO +#define VPEC_QUEUE0_CMDIB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE0_CMDIB_BASE_HI +#define VPEC_QUEUE0_CMDIB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE0_CMDIB_SIZE +#define VPEC_QUEUE0_CMDIB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE0_3DLUTIB_CNTL +#define VPEC_QUEUE0_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE0_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE0_3DLUTIB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE0_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE0_3DLUTIB_RPTR +#define VPEC_QUEUE0_3DLUTIB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE0_3DLUTIB_OFFSET +#define VPEC_QUEUE0_3DLUTIB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE0_3DLUTIB_BASE_LO +#define VPEC_QUEUE0_3DLUTIB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE0_3DLUTIB_BASE_HI +#define VPEC_QUEUE0_3DLUTIB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE0_3DLUTIB_SIZE +#define VPEC_QUEUE0_3DLUTIB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE0_CSA_ADDR_LO +#define VPEC_QUEUE0_CSA_ADDR_LO__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE0_CSA_ADDR_HI +#define VPEC_QUEUE0_CSA_ADDR_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE0_CONTEXT_STATUS +#define VPEC_QUEUE0_CONTEXT_STATUS__SELECTED_MASK 0x00000001UL +#define VPEC_QUEUE0_CONTEXT_STATUS__USE_IB_MASK 0x00000002UL +#define VPEC_QUEUE0_CONTEXT_STATUS__IDLE_MASK 0x00000004UL +#define VPEC_QUEUE0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008UL +#define VPEC_QUEUE0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070UL +#define VPEC_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080UL +#define VPEC_QUEUE0_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100UL +#define VPEC_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400UL +#define VPEC_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800UL +#define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000UL +#define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00ff0000UL + +// VPEC_QUEUE0_DOORBELL_LOG +#define VPEC_QUEUE0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001UL +#define VPEC_QUEUE0_DOORBELL_LOG__DATA_MASK 0xfffffffcUL + +// VPEC_QUEUE0_IB_SUB_REMAIN +#define VPEC_QUEUE0_IB_SUB_REMAIN__SIZE_MASK 0x00003fffUL + +// VPEC_QUEUE0_PREEMPT +#define VPEC_QUEUE0_PREEMPT__IB_PREEMPT_MASK 0x00000001UL + +// VPEC_QUEUE0_LOG0BUFFER_CFG +#define VPEC_QUEUE0_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE0_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000ff0UL +#define VPEC_QUEUE0_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000ff000UL +#define VPEC_QUEUE0_LOG0BUFFER_CFG__RESERVED_MASK 0xfff00000UL + +// VPEC_QUEUE0_LOG1BUFFER_CFG +#define VPEC_QUEUE0_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE0_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002UL +#define VPEC_QUEUE0_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000ff0UL +#define VPEC_QUEUE0_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000ff000UL +#define VPEC_QUEUE0_LOG1BUFFER_CFG__RESERVED_MASK 0xfff00000UL + +// VPEC_QUEUE1_RB_CNTL +#define VPEC_QUEUE1_RB_CNTL__RB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE1_RB_CNTL__RB_SIZE_MASK 0x0000003eUL +#define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100UL +#define VPEC_QUEUE1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200UL +#define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400UL +#define VPEC_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800UL +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000UL +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000UL +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001f0000UL +#define VPEC_QUEUE1_RB_CNTL__RB_PRIV_MASK 0x00800000UL +#define VPEC_QUEUE1_RB_CNTL__RB_VMID_MASK 0x0f000000UL + +// VPEC_QUEUE1_SCHEDULE_CNTL +#define VPEC_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003UL +#define VPEC_QUEUE1_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001cUL +#define VPEC_QUEUE1_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000c0UL +#define VPEC_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000ff00UL + +// VPEC_QUEUE1_RB_BASE +#define VPEC_QUEUE1_RB_BASE__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE1_RB_BASE_HI +#define VPEC_QUEUE1_RB_BASE_HI__ADDR_MASK 0x00ffffffUL + +// VPEC_QUEUE1_RB_RPTR +#define VPEC_QUEUE1_RB_RPTR__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE1_RB_RPTR_HI +#define VPEC_QUEUE1_RB_RPTR_HI__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE1_RB_WPTR +#define VPEC_QUEUE1_RB_WPTR__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE1_RB_WPTR_HI +#define VPEC_QUEUE1_RB_WPTR_HI__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE1_RB_RPTR_ADDR_HI +#define VPEC_QUEUE1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE1_RB_RPTR_ADDR_LO +#define VPEC_QUEUE1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffcUL + +// VPEC_QUEUE1_RB_AQL_CNTL +#define VPEC_QUEUE1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000feUL +#define VPEC_QUEUE1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000ff00UL +#define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000UL +#define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000UL +#define VPEC_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000UL + +// VPEC_QUEUE1_MINOR_PTR_UPDATE +#define VPEC_QUEUE1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001UL + +// VPEC_QUEUE1_CD_INFO +#define VPEC_QUEUE1_CD_INFO__CD_INFO_MASK 0xffffffffUL + +// VPEC_QUEUE1_RB_PREEMPT +#define VPEC_QUEUE1_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001UL + +// VPEC_QUEUE1_SKIP_CNTL +#define VPEC_QUEUE1_SKIP_CNTL__SKIP_COUNT_MASK 0x000fffffUL + +// VPEC_QUEUE1_DOORBELL +#define VPEC_QUEUE1_DOORBELL__ENABLE_MASK 0x10000000UL +#define VPEC_QUEUE1_DOORBELL__CAPTURED_MASK 0x40000000UL + +// VPEC_QUEUE1_DOORBELL_OFFSET +#define VPEC_QUEUE1_DOORBELL_OFFSET__OFFSET_MASK 0x0ffffffcUL + +// VPEC_QUEUE1_DUMMY0 +#define VPEC_QUEUE1_DUMMY0__DUMMY_MASK 0xffffffffUL + +// VPEC_QUEUE1_DUMMY1 +#define VPEC_QUEUE1_DUMMY1__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE1_DUMMY2 +#define VPEC_QUEUE1_DUMMY2__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE1_DUMMY3 +#define VPEC_QUEUE1_DUMMY3__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE1_DUMMY4 +#define VPEC_QUEUE1_DUMMY4__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE1_IB_CNTL +#define VPEC_QUEUE1_IB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE1_IB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE1_IB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE1_IB_RPTR +#define VPEC_QUEUE1_IB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE1_IB_OFFSET +#define VPEC_QUEUE1_IB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE1_IB_BASE_LO +#define VPEC_QUEUE1_IB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE1_IB_BASE_HI +#define VPEC_QUEUE1_IB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE1_IB_SIZE +#define VPEC_QUEUE1_IB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE1_CMDIB_CNTL +#define VPEC_QUEUE1_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE1_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010UL +#define VPEC_QUEUE1_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE1_CMDIB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE1_CMDIB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE1_CMDIB_RPTR +#define VPEC_QUEUE1_CMDIB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE1_CMDIB_OFFSET +#define VPEC_QUEUE1_CMDIB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE1_CMDIB_BASE_LO +#define VPEC_QUEUE1_CMDIB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE1_CMDIB_BASE_HI +#define VPEC_QUEUE1_CMDIB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE1_CMDIB_SIZE +#define VPEC_QUEUE1_CMDIB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE1_3DLUTIB_CNTL +#define VPEC_QUEUE1_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE1_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE1_3DLUTIB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE1_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE1_3DLUTIB_RPTR +#define VPEC_QUEUE1_3DLUTIB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE1_3DLUTIB_OFFSET +#define VPEC_QUEUE1_3DLUTIB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE1_3DLUTIB_BASE_LO +#define VPEC_QUEUE1_3DLUTIB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE1_3DLUTIB_BASE_HI +#define VPEC_QUEUE1_3DLUTIB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE1_3DLUTIB_SIZE +#define VPEC_QUEUE1_3DLUTIB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE1_CSA_ADDR_LO +#define VPEC_QUEUE1_CSA_ADDR_LO__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE1_CSA_ADDR_HI +#define VPEC_QUEUE1_CSA_ADDR_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE1_CONTEXT_STATUS +#define VPEC_QUEUE1_CONTEXT_STATUS__SELECTED_MASK 0x00000001UL +#define VPEC_QUEUE1_CONTEXT_STATUS__USE_IB_MASK 0x00000002UL +#define VPEC_QUEUE1_CONTEXT_STATUS__IDLE_MASK 0x00000004UL +#define VPEC_QUEUE1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008UL +#define VPEC_QUEUE1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070UL +#define VPEC_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080UL +#define VPEC_QUEUE1_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100UL +#define VPEC_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400UL +#define VPEC_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800UL +#define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000UL +#define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00ff0000UL + +// VPEC_QUEUE1_DOORBELL_LOG +#define VPEC_QUEUE1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001UL +#define VPEC_QUEUE1_DOORBELL_LOG__DATA_MASK 0xfffffffcUL + +// VPEC_QUEUE1_IB_SUB_REMAIN +#define VPEC_QUEUE1_IB_SUB_REMAIN__SIZE_MASK 0x00003fffUL + +// VPEC_QUEUE1_PREEMPT +#define VPEC_QUEUE1_PREEMPT__IB_PREEMPT_MASK 0x00000001UL + +// VPEC_QUEUE1_LOG0BUFFER_CFG +#define VPEC_QUEUE1_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE1_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000ff0UL +#define VPEC_QUEUE1_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000ff000UL +#define VPEC_QUEUE1_LOG0BUFFER_CFG__RESERVED_MASK 0xfff00000UL + +// VPEC_QUEUE1_LOG1BUFFER_CFG +#define VPEC_QUEUE1_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE1_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002UL +#define VPEC_QUEUE1_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000ff0UL +#define VPEC_QUEUE1_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000ff000UL +#define VPEC_QUEUE1_LOG1BUFFER_CFG__RESERVED_MASK 0xfff00000UL + +// VPEC_QUEUE2_RB_CNTL +#define VPEC_QUEUE2_RB_CNTL__RB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE2_RB_CNTL__RB_SIZE_MASK 0x0000003eUL +#define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100UL +#define VPEC_QUEUE2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200UL +#define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400UL +#define VPEC_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800UL +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000UL +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000UL +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001f0000UL +#define VPEC_QUEUE2_RB_CNTL__RB_PRIV_MASK 0x00800000UL +#define VPEC_QUEUE2_RB_CNTL__RB_VMID_MASK 0x0f000000UL + +// VPEC_QUEUE2_SCHEDULE_CNTL +#define VPEC_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003UL +#define VPEC_QUEUE2_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001cUL +#define VPEC_QUEUE2_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000c0UL +#define VPEC_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000ff00UL + +// VPEC_QUEUE2_RB_BASE +#define VPEC_QUEUE2_RB_BASE__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE2_RB_BASE_HI +#define VPEC_QUEUE2_RB_BASE_HI__ADDR_MASK 0x00ffffffUL + +// VPEC_QUEUE2_RB_RPTR +#define VPEC_QUEUE2_RB_RPTR__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE2_RB_RPTR_HI +#define VPEC_QUEUE2_RB_RPTR_HI__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE2_RB_WPTR +#define VPEC_QUEUE2_RB_WPTR__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE2_RB_WPTR_HI +#define VPEC_QUEUE2_RB_WPTR_HI__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE2_RB_RPTR_ADDR_HI +#define VPEC_QUEUE2_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE2_RB_RPTR_ADDR_LO +#define VPEC_QUEUE2_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffcUL + +// VPEC_QUEUE2_RB_AQL_CNTL +#define VPEC_QUEUE2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000feUL +#define VPEC_QUEUE2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000ff00UL +#define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000UL +#define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000UL +#define VPEC_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000UL + +// VPEC_QUEUE2_MINOR_PTR_UPDATE +#define VPEC_QUEUE2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001UL + +// VPEC_QUEUE2_CD_INFO +#define VPEC_QUEUE2_CD_INFO__CD_INFO_MASK 0xffffffffUL + +// VPEC_QUEUE2_RB_PREEMPT +#define VPEC_QUEUE2_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001UL + +// VPEC_QUEUE2_SKIP_CNTL +#define VPEC_QUEUE2_SKIP_CNTL__SKIP_COUNT_MASK 0x000fffffUL + +// VPEC_QUEUE2_DOORBELL +#define VPEC_QUEUE2_DOORBELL__ENABLE_MASK 0x10000000UL +#define VPEC_QUEUE2_DOORBELL__CAPTURED_MASK 0x40000000UL + +// VPEC_QUEUE2_DOORBELL_OFFSET +#define VPEC_QUEUE2_DOORBELL_OFFSET__OFFSET_MASK 0x0ffffffcUL + +// VPEC_QUEUE2_DUMMY0 +#define VPEC_QUEUE2_DUMMY0__DUMMY_MASK 0xffffffffUL + +// VPEC_QUEUE2_DUMMY1 +#define VPEC_QUEUE2_DUMMY1__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE2_DUMMY2 +#define VPEC_QUEUE2_DUMMY2__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE2_DUMMY3 +#define VPEC_QUEUE2_DUMMY3__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE2_DUMMY4 +#define VPEC_QUEUE2_DUMMY4__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE2_IB_CNTL +#define VPEC_QUEUE2_IB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE2_IB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE2_IB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE2_IB_RPTR +#define VPEC_QUEUE2_IB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE2_IB_OFFSET +#define VPEC_QUEUE2_IB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE2_IB_BASE_LO +#define VPEC_QUEUE2_IB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE2_IB_BASE_HI +#define VPEC_QUEUE2_IB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE2_IB_SIZE +#define VPEC_QUEUE2_IB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE2_CMDIB_CNTL +#define VPEC_QUEUE2_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE2_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010UL +#define VPEC_QUEUE2_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE2_CMDIB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE2_CMDIB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE2_CMDIB_RPTR +#define VPEC_QUEUE2_CMDIB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE2_CMDIB_OFFSET +#define VPEC_QUEUE2_CMDIB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE2_CMDIB_BASE_LO +#define VPEC_QUEUE2_CMDIB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE2_CMDIB_BASE_HI +#define VPEC_QUEUE2_CMDIB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE2_CMDIB_SIZE +#define VPEC_QUEUE2_CMDIB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE2_3DLUTIB_CNTL +#define VPEC_QUEUE2_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE2_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE2_3DLUTIB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE2_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE2_3DLUTIB_RPTR +#define VPEC_QUEUE2_3DLUTIB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE2_3DLUTIB_OFFSET +#define VPEC_QUEUE2_3DLUTIB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE2_3DLUTIB_BASE_LO +#define VPEC_QUEUE2_3DLUTIB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE2_3DLUTIB_BASE_HI +#define VPEC_QUEUE2_3DLUTIB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE2_3DLUTIB_SIZE +#define VPEC_QUEUE2_3DLUTIB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE2_CSA_ADDR_LO +#define VPEC_QUEUE2_CSA_ADDR_LO__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE2_CSA_ADDR_HI +#define VPEC_QUEUE2_CSA_ADDR_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE2_CONTEXT_STATUS +#define VPEC_QUEUE2_CONTEXT_STATUS__SELECTED_MASK 0x00000001UL +#define VPEC_QUEUE2_CONTEXT_STATUS__USE_IB_MASK 0x00000002UL +#define VPEC_QUEUE2_CONTEXT_STATUS__IDLE_MASK 0x00000004UL +#define VPEC_QUEUE2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008UL +#define VPEC_QUEUE2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070UL +#define VPEC_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080UL +#define VPEC_QUEUE2_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100UL +#define VPEC_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400UL +#define VPEC_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800UL +#define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000UL +#define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00ff0000UL + +// VPEC_QUEUE2_DOORBELL_LOG +#define VPEC_QUEUE2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001UL +#define VPEC_QUEUE2_DOORBELL_LOG__DATA_MASK 0xfffffffcUL + +// VPEC_QUEUE2_IB_SUB_REMAIN +#define VPEC_QUEUE2_IB_SUB_REMAIN__SIZE_MASK 0x00003fffUL + +// VPEC_QUEUE2_PREEMPT +#define VPEC_QUEUE2_PREEMPT__IB_PREEMPT_MASK 0x00000001UL + +// VPEC_QUEUE2_LOG0BUFFER_CFG +#define VPEC_QUEUE2_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE2_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000ff0UL +#define VPEC_QUEUE2_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000ff000UL +#define VPEC_QUEUE2_LOG0BUFFER_CFG__RESERVED_MASK 0xfff00000UL + +// VPEC_QUEUE2_LOG1BUFFER_CFG +#define VPEC_QUEUE2_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE2_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002UL +#define VPEC_QUEUE2_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000ff0UL +#define VPEC_QUEUE2_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000ff000UL +#define VPEC_QUEUE2_LOG1BUFFER_CFG__RESERVED_MASK 0xfff00000UL + +// VPEC_QUEUE3_RB_CNTL +#define VPEC_QUEUE3_RB_CNTL__RB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE3_RB_CNTL__RB_SIZE_MASK 0x0000003eUL +#define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100UL +#define VPEC_QUEUE3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200UL +#define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400UL +#define VPEC_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800UL +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000UL +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000UL +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001f0000UL +#define VPEC_QUEUE3_RB_CNTL__RB_PRIV_MASK 0x00800000UL +#define VPEC_QUEUE3_RB_CNTL__RB_VMID_MASK 0x0f000000UL + +// VPEC_QUEUE3_SCHEDULE_CNTL +#define VPEC_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003UL +#define VPEC_QUEUE3_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001cUL +#define VPEC_QUEUE3_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000c0UL +#define VPEC_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000ff00UL + +// VPEC_QUEUE3_RB_BASE +#define VPEC_QUEUE3_RB_BASE__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE3_RB_BASE_HI +#define VPEC_QUEUE3_RB_BASE_HI__ADDR_MASK 0x00ffffffUL + +// VPEC_QUEUE3_RB_RPTR +#define VPEC_QUEUE3_RB_RPTR__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE3_RB_RPTR_HI +#define VPEC_QUEUE3_RB_RPTR_HI__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE3_RB_WPTR +#define VPEC_QUEUE3_RB_WPTR__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE3_RB_WPTR_HI +#define VPEC_QUEUE3_RB_WPTR_HI__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE3_RB_RPTR_ADDR_HI +#define VPEC_QUEUE3_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE3_RB_RPTR_ADDR_LO +#define VPEC_QUEUE3_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffcUL + +// VPEC_QUEUE3_RB_AQL_CNTL +#define VPEC_QUEUE3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000feUL +#define VPEC_QUEUE3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000ff00UL +#define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000UL +#define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000UL +#define VPEC_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000UL + +// VPEC_QUEUE3_MINOR_PTR_UPDATE +#define VPEC_QUEUE3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001UL + +// VPEC_QUEUE3_CD_INFO +#define VPEC_QUEUE3_CD_INFO__CD_INFO_MASK 0xffffffffUL + +// VPEC_QUEUE3_RB_PREEMPT +#define VPEC_QUEUE3_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001UL + +// VPEC_QUEUE3_SKIP_CNTL +#define VPEC_QUEUE3_SKIP_CNTL__SKIP_COUNT_MASK 0x000fffffUL + +// VPEC_QUEUE3_DOORBELL +#define VPEC_QUEUE3_DOORBELL__ENABLE_MASK 0x10000000UL +#define VPEC_QUEUE3_DOORBELL__CAPTURED_MASK 0x40000000UL + +// VPEC_QUEUE3_DOORBELL_OFFSET +#define VPEC_QUEUE3_DOORBELL_OFFSET__OFFSET_MASK 0x0ffffffcUL + +// VPEC_QUEUE3_DUMMY0 +#define VPEC_QUEUE3_DUMMY0__DUMMY_MASK 0xffffffffUL + +// VPEC_QUEUE3_DUMMY1 +#define VPEC_QUEUE3_DUMMY1__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE3_DUMMY2 +#define VPEC_QUEUE3_DUMMY2__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE3_DUMMY3 +#define VPEC_QUEUE3_DUMMY3__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE3_DUMMY4 +#define VPEC_QUEUE3_DUMMY4__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE3_IB_CNTL +#define VPEC_QUEUE3_IB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE3_IB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE3_IB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE3_IB_RPTR +#define VPEC_QUEUE3_IB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE3_IB_OFFSET +#define VPEC_QUEUE3_IB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE3_IB_BASE_LO +#define VPEC_QUEUE3_IB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE3_IB_BASE_HI +#define VPEC_QUEUE3_IB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE3_IB_SIZE +#define VPEC_QUEUE3_IB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE3_CMDIB_CNTL +#define VPEC_QUEUE3_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE3_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010UL +#define VPEC_QUEUE3_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE3_CMDIB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE3_CMDIB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE3_CMDIB_RPTR +#define VPEC_QUEUE3_CMDIB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE3_CMDIB_OFFSET +#define VPEC_QUEUE3_CMDIB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE3_CMDIB_BASE_LO +#define VPEC_QUEUE3_CMDIB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE3_CMDIB_BASE_HI +#define VPEC_QUEUE3_CMDIB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE3_CMDIB_SIZE +#define VPEC_QUEUE3_CMDIB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE3_3DLUTIB_CNTL +#define VPEC_QUEUE3_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE3_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE3_3DLUTIB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE3_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE3_3DLUTIB_RPTR +#define VPEC_QUEUE3_3DLUTIB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE3_3DLUTIB_OFFSET +#define VPEC_QUEUE3_3DLUTIB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE3_3DLUTIB_BASE_LO +#define VPEC_QUEUE3_3DLUTIB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE3_3DLUTIB_BASE_HI +#define VPEC_QUEUE3_3DLUTIB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE3_3DLUTIB_SIZE +#define VPEC_QUEUE3_3DLUTIB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE3_CSA_ADDR_LO +#define VPEC_QUEUE3_CSA_ADDR_LO__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE3_CSA_ADDR_HI +#define VPEC_QUEUE3_CSA_ADDR_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE3_CONTEXT_STATUS +#define VPEC_QUEUE3_CONTEXT_STATUS__SELECTED_MASK 0x00000001UL +#define VPEC_QUEUE3_CONTEXT_STATUS__USE_IB_MASK 0x00000002UL +#define VPEC_QUEUE3_CONTEXT_STATUS__IDLE_MASK 0x00000004UL +#define VPEC_QUEUE3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008UL +#define VPEC_QUEUE3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070UL +#define VPEC_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080UL +#define VPEC_QUEUE3_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100UL +#define VPEC_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400UL +#define VPEC_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800UL +#define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000UL +#define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00ff0000UL + +// VPEC_QUEUE3_DOORBELL_LOG +#define VPEC_QUEUE3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001UL +#define VPEC_QUEUE3_DOORBELL_LOG__DATA_MASK 0xfffffffcUL + +// VPEC_QUEUE3_IB_SUB_REMAIN +#define VPEC_QUEUE3_IB_SUB_REMAIN__SIZE_MASK 0x00003fffUL + +// VPEC_QUEUE3_PREEMPT +#define VPEC_QUEUE3_PREEMPT__IB_PREEMPT_MASK 0x00000001UL + +// VPEC_QUEUE3_LOG0BUFFER_CFG +#define VPEC_QUEUE3_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE3_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000ff0UL +#define VPEC_QUEUE3_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000ff000UL +#define VPEC_QUEUE3_LOG0BUFFER_CFG__RESERVED_MASK 0xfff00000UL + +// VPEC_QUEUE3_LOG1BUFFER_CFG +#define VPEC_QUEUE3_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE3_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002UL +#define VPEC_QUEUE3_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000ff0UL +#define VPEC_QUEUE3_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000ff000UL +#define VPEC_QUEUE3_LOG1BUFFER_CFG__RESERVED_MASK 0xfff00000UL + +// VPEC_QUEUE4_RB_CNTL +#define VPEC_QUEUE4_RB_CNTL__RB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE4_RB_CNTL__RB_SIZE_MASK 0x0000003eUL +#define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100UL +#define VPEC_QUEUE4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200UL +#define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400UL +#define VPEC_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800UL +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000UL +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000UL +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001f0000UL +#define VPEC_QUEUE4_RB_CNTL__RB_PRIV_MASK 0x00800000UL +#define VPEC_QUEUE4_RB_CNTL__RB_VMID_MASK 0x0f000000UL + +// VPEC_QUEUE4_SCHEDULE_CNTL +#define VPEC_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003UL +#define VPEC_QUEUE4_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001cUL +#define VPEC_QUEUE4_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000c0UL +#define VPEC_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000ff00UL + +// VPEC_QUEUE4_RB_BASE +#define VPEC_QUEUE4_RB_BASE__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE4_RB_BASE_HI +#define VPEC_QUEUE4_RB_BASE_HI__ADDR_MASK 0x00ffffffUL + +// VPEC_QUEUE4_RB_RPTR +#define VPEC_QUEUE4_RB_RPTR__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE4_RB_RPTR_HI +#define VPEC_QUEUE4_RB_RPTR_HI__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE4_RB_WPTR +#define VPEC_QUEUE4_RB_WPTR__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE4_RB_WPTR_HI +#define VPEC_QUEUE4_RB_WPTR_HI__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE4_RB_RPTR_ADDR_HI +#define VPEC_QUEUE4_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE4_RB_RPTR_ADDR_LO +#define VPEC_QUEUE4_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffcUL + +// VPEC_QUEUE4_RB_AQL_CNTL +#define VPEC_QUEUE4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000feUL +#define VPEC_QUEUE4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000ff00UL +#define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000UL +#define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000UL +#define VPEC_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000UL + +// VPEC_QUEUE4_MINOR_PTR_UPDATE +#define VPEC_QUEUE4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001UL + +// VPEC_QUEUE4_CD_INFO +#define VPEC_QUEUE4_CD_INFO__CD_INFO_MASK 0xffffffffUL + +// VPEC_QUEUE4_RB_PREEMPT +#define VPEC_QUEUE4_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001UL + +// VPEC_QUEUE4_SKIP_CNTL +#define VPEC_QUEUE4_SKIP_CNTL__SKIP_COUNT_MASK 0x000fffffUL + +// VPEC_QUEUE4_DOORBELL +#define VPEC_QUEUE4_DOORBELL__ENABLE_MASK 0x10000000UL +#define VPEC_QUEUE4_DOORBELL__CAPTURED_MASK 0x40000000UL + +// VPEC_QUEUE4_DOORBELL_OFFSET +#define VPEC_QUEUE4_DOORBELL_OFFSET__OFFSET_MASK 0x0ffffffcUL + +// VPEC_QUEUE4_DUMMY0 +#define VPEC_QUEUE4_DUMMY0__DUMMY_MASK 0xffffffffUL + +// VPEC_QUEUE4_DUMMY1 +#define VPEC_QUEUE4_DUMMY1__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE4_DUMMY2 +#define VPEC_QUEUE4_DUMMY2__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE4_DUMMY3 +#define VPEC_QUEUE4_DUMMY3__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE4_DUMMY4 +#define VPEC_QUEUE4_DUMMY4__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE4_IB_CNTL +#define VPEC_QUEUE4_IB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE4_IB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE4_IB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE4_IB_RPTR +#define VPEC_QUEUE4_IB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE4_IB_OFFSET +#define VPEC_QUEUE4_IB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE4_IB_BASE_LO +#define VPEC_QUEUE4_IB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE4_IB_BASE_HI +#define VPEC_QUEUE4_IB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE4_IB_SIZE +#define VPEC_QUEUE4_IB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE4_CMDIB_CNTL +#define VPEC_QUEUE4_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE4_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010UL +#define VPEC_QUEUE4_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE4_CMDIB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE4_CMDIB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE4_CMDIB_RPTR +#define VPEC_QUEUE4_CMDIB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE4_CMDIB_OFFSET +#define VPEC_QUEUE4_CMDIB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE4_CMDIB_BASE_LO +#define VPEC_QUEUE4_CMDIB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE4_CMDIB_BASE_HI +#define VPEC_QUEUE4_CMDIB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE4_CMDIB_SIZE +#define VPEC_QUEUE4_CMDIB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE4_3DLUTIB_CNTL +#define VPEC_QUEUE4_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE4_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE4_3DLUTIB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE4_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE4_3DLUTIB_RPTR +#define VPEC_QUEUE4_3DLUTIB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE4_3DLUTIB_OFFSET +#define VPEC_QUEUE4_3DLUTIB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE4_3DLUTIB_BASE_LO +#define VPEC_QUEUE4_3DLUTIB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE4_3DLUTIB_BASE_HI +#define VPEC_QUEUE4_3DLUTIB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE4_3DLUTIB_SIZE +#define VPEC_QUEUE4_3DLUTIB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE4_CSA_ADDR_LO +#define VPEC_QUEUE4_CSA_ADDR_LO__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE4_CSA_ADDR_HI +#define VPEC_QUEUE4_CSA_ADDR_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE4_CONTEXT_STATUS +#define VPEC_QUEUE4_CONTEXT_STATUS__SELECTED_MASK 0x00000001UL +#define VPEC_QUEUE4_CONTEXT_STATUS__USE_IB_MASK 0x00000002UL +#define VPEC_QUEUE4_CONTEXT_STATUS__IDLE_MASK 0x00000004UL +#define VPEC_QUEUE4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008UL +#define VPEC_QUEUE4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070UL +#define VPEC_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080UL +#define VPEC_QUEUE4_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100UL +#define VPEC_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400UL +#define VPEC_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800UL +#define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000UL +#define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00ff0000UL + +// VPEC_QUEUE4_DOORBELL_LOG +#define VPEC_QUEUE4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001UL +#define VPEC_QUEUE4_DOORBELL_LOG__DATA_MASK 0xfffffffcUL + +// VPEC_QUEUE4_IB_SUB_REMAIN +#define VPEC_QUEUE4_IB_SUB_REMAIN__SIZE_MASK 0x00003fffUL + +// VPEC_QUEUE4_PREEMPT +#define VPEC_QUEUE4_PREEMPT__IB_PREEMPT_MASK 0x00000001UL + +// VPEC_QUEUE4_LOG0BUFFER_CFG +#define VPEC_QUEUE4_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE4_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000ff0UL +#define VPEC_QUEUE4_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000ff000UL +#define VPEC_QUEUE4_LOG0BUFFER_CFG__RESERVED_MASK 0xfff00000UL + +// VPEC_QUEUE4_LOG1BUFFER_CFG +#define VPEC_QUEUE4_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE4_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002UL +#define VPEC_QUEUE4_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000ff0UL +#define VPEC_QUEUE4_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000ff000UL +#define VPEC_QUEUE4_LOG1BUFFER_CFG__RESERVED_MASK 0xfff00000UL + +// VPEC_QUEUE5_RB_CNTL +#define VPEC_QUEUE5_RB_CNTL__RB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE5_RB_CNTL__RB_SIZE_MASK 0x0000003eUL +#define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100UL +#define VPEC_QUEUE5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200UL +#define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400UL +#define VPEC_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800UL +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000UL +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000UL +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001f0000UL +#define VPEC_QUEUE5_RB_CNTL__RB_PRIV_MASK 0x00800000UL +#define VPEC_QUEUE5_RB_CNTL__RB_VMID_MASK 0x0f000000UL + +// VPEC_QUEUE5_SCHEDULE_CNTL +#define VPEC_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003UL +#define VPEC_QUEUE5_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001cUL +#define VPEC_QUEUE5_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000c0UL +#define VPEC_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000ff00UL + +// VPEC_QUEUE5_RB_BASE +#define VPEC_QUEUE5_RB_BASE__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE5_RB_BASE_HI +#define VPEC_QUEUE5_RB_BASE_HI__ADDR_MASK 0x00ffffffUL + +// VPEC_QUEUE5_RB_RPTR +#define VPEC_QUEUE5_RB_RPTR__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE5_RB_RPTR_HI +#define VPEC_QUEUE5_RB_RPTR_HI__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE5_RB_WPTR +#define VPEC_QUEUE5_RB_WPTR__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE5_RB_WPTR_HI +#define VPEC_QUEUE5_RB_WPTR_HI__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE5_RB_RPTR_ADDR_HI +#define VPEC_QUEUE5_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE5_RB_RPTR_ADDR_LO +#define VPEC_QUEUE5_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffcUL + +// VPEC_QUEUE5_RB_AQL_CNTL +#define VPEC_QUEUE5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000feUL +#define VPEC_QUEUE5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000ff00UL +#define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000UL +#define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000UL +#define VPEC_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000UL + +// VPEC_QUEUE5_MINOR_PTR_UPDATE +#define VPEC_QUEUE5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001UL + +// VPEC_QUEUE5_CD_INFO +#define VPEC_QUEUE5_CD_INFO__CD_INFO_MASK 0xffffffffUL + +// VPEC_QUEUE5_RB_PREEMPT +#define VPEC_QUEUE5_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001UL + +// VPEC_QUEUE5_SKIP_CNTL +#define VPEC_QUEUE5_SKIP_CNTL__SKIP_COUNT_MASK 0x000fffffUL + +// VPEC_QUEUE5_DOORBELL +#define VPEC_QUEUE5_DOORBELL__ENABLE_MASK 0x10000000UL +#define VPEC_QUEUE5_DOORBELL__CAPTURED_MASK 0x40000000UL + +// VPEC_QUEUE5_DOORBELL_OFFSET +#define VPEC_QUEUE5_DOORBELL_OFFSET__OFFSET_MASK 0x0ffffffcUL + +// VPEC_QUEUE5_DUMMY0 +#define VPEC_QUEUE5_DUMMY0__DUMMY_MASK 0xffffffffUL + +// VPEC_QUEUE5_DUMMY1 +#define VPEC_QUEUE5_DUMMY1__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE5_DUMMY2 +#define VPEC_QUEUE5_DUMMY2__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE5_DUMMY3 +#define VPEC_QUEUE5_DUMMY3__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE5_DUMMY4 +#define VPEC_QUEUE5_DUMMY4__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE5_IB_CNTL +#define VPEC_QUEUE5_IB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE5_IB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE5_IB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE5_IB_RPTR +#define VPEC_QUEUE5_IB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE5_IB_OFFSET +#define VPEC_QUEUE5_IB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE5_IB_BASE_LO +#define VPEC_QUEUE5_IB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE5_IB_BASE_HI +#define VPEC_QUEUE5_IB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE5_IB_SIZE +#define VPEC_QUEUE5_IB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE5_CMDIB_CNTL +#define VPEC_QUEUE5_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE5_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010UL +#define VPEC_QUEUE5_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE5_CMDIB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE5_CMDIB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE5_CMDIB_RPTR +#define VPEC_QUEUE5_CMDIB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE5_CMDIB_OFFSET +#define VPEC_QUEUE5_CMDIB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE5_CMDIB_BASE_LO +#define VPEC_QUEUE5_CMDIB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE5_CMDIB_BASE_HI +#define VPEC_QUEUE5_CMDIB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE5_CMDIB_SIZE +#define VPEC_QUEUE5_CMDIB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE5_3DLUTIB_CNTL +#define VPEC_QUEUE5_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE5_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE5_3DLUTIB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE5_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE5_3DLUTIB_RPTR +#define VPEC_QUEUE5_3DLUTIB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE5_3DLUTIB_OFFSET +#define VPEC_QUEUE5_3DLUTIB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE5_3DLUTIB_BASE_LO +#define VPEC_QUEUE5_3DLUTIB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE5_3DLUTIB_BASE_HI +#define VPEC_QUEUE5_3DLUTIB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE5_3DLUTIB_SIZE +#define VPEC_QUEUE5_3DLUTIB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE5_CSA_ADDR_LO +#define VPEC_QUEUE5_CSA_ADDR_LO__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE5_CSA_ADDR_HI +#define VPEC_QUEUE5_CSA_ADDR_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE5_CONTEXT_STATUS +#define VPEC_QUEUE5_CONTEXT_STATUS__SELECTED_MASK 0x00000001UL +#define VPEC_QUEUE5_CONTEXT_STATUS__USE_IB_MASK 0x00000002UL +#define VPEC_QUEUE5_CONTEXT_STATUS__IDLE_MASK 0x00000004UL +#define VPEC_QUEUE5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008UL +#define VPEC_QUEUE5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070UL +#define VPEC_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080UL +#define VPEC_QUEUE5_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100UL +#define VPEC_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400UL +#define VPEC_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800UL +#define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000UL +#define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00ff0000UL + +// VPEC_QUEUE5_DOORBELL_LOG +#define VPEC_QUEUE5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001UL +#define VPEC_QUEUE5_DOORBELL_LOG__DATA_MASK 0xfffffffcUL + +// VPEC_QUEUE5_IB_SUB_REMAIN +#define VPEC_QUEUE5_IB_SUB_REMAIN__SIZE_MASK 0x00003fffUL + +// VPEC_QUEUE5_PREEMPT +#define VPEC_QUEUE5_PREEMPT__IB_PREEMPT_MASK 0x00000001UL + +// VPEC_QUEUE5_LOG0BUFFER_CFG +#define VPEC_QUEUE5_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE5_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000ff0UL +#define VPEC_QUEUE5_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000ff000UL +#define VPEC_QUEUE5_LOG0BUFFER_CFG__RESERVED_MASK 0xfff00000UL + +// VPEC_QUEUE5_LOG1BUFFER_CFG +#define VPEC_QUEUE5_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE5_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002UL +#define VPEC_QUEUE5_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000ff0UL +#define VPEC_QUEUE5_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000ff000UL +#define VPEC_QUEUE5_LOG1BUFFER_CFG__RESERVED_MASK 0xfff00000UL + +// VPEC_QUEUE6_RB_CNTL +#define VPEC_QUEUE6_RB_CNTL__RB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE6_RB_CNTL__RB_SIZE_MASK 0x0000003eUL +#define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100UL +#define VPEC_QUEUE6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200UL +#define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400UL +#define VPEC_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800UL +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000UL +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000UL +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001f0000UL +#define VPEC_QUEUE6_RB_CNTL__RB_PRIV_MASK 0x00800000UL +#define VPEC_QUEUE6_RB_CNTL__RB_VMID_MASK 0x0f000000UL + +// VPEC_QUEUE6_SCHEDULE_CNTL +#define VPEC_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003UL +#define VPEC_QUEUE6_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001cUL +#define VPEC_QUEUE6_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000c0UL +#define VPEC_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000ff00UL + +// VPEC_QUEUE6_RB_BASE +#define VPEC_QUEUE6_RB_BASE__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE6_RB_BASE_HI +#define VPEC_QUEUE6_RB_BASE_HI__ADDR_MASK 0x00ffffffUL + +// VPEC_QUEUE6_RB_RPTR +#define VPEC_QUEUE6_RB_RPTR__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE6_RB_RPTR_HI +#define VPEC_QUEUE6_RB_RPTR_HI__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE6_RB_WPTR +#define VPEC_QUEUE6_RB_WPTR__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE6_RB_WPTR_HI +#define VPEC_QUEUE6_RB_WPTR_HI__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE6_RB_RPTR_ADDR_HI +#define VPEC_QUEUE6_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE6_RB_RPTR_ADDR_LO +#define VPEC_QUEUE6_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffcUL + +// VPEC_QUEUE6_RB_AQL_CNTL +#define VPEC_QUEUE6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000feUL +#define VPEC_QUEUE6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000ff00UL +#define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000UL +#define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000UL +#define VPEC_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000UL + +// VPEC_QUEUE6_MINOR_PTR_UPDATE +#define VPEC_QUEUE6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001UL + +// VPEC_QUEUE6_CD_INFO +#define VPEC_QUEUE6_CD_INFO__CD_INFO_MASK 0xffffffffUL + +// VPEC_QUEUE6_RB_PREEMPT +#define VPEC_QUEUE6_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001UL + +// VPEC_QUEUE6_SKIP_CNTL +#define VPEC_QUEUE6_SKIP_CNTL__SKIP_COUNT_MASK 0x000fffffUL + +// VPEC_QUEUE6_DOORBELL +#define VPEC_QUEUE6_DOORBELL__ENABLE_MASK 0x10000000UL +#define VPEC_QUEUE6_DOORBELL__CAPTURED_MASK 0x40000000UL + +// VPEC_QUEUE6_DOORBELL_OFFSET +#define VPEC_QUEUE6_DOORBELL_OFFSET__OFFSET_MASK 0x0ffffffcUL + +// VPEC_QUEUE6_DUMMY0 +#define VPEC_QUEUE6_DUMMY0__DUMMY_MASK 0xffffffffUL + +// VPEC_QUEUE6_DUMMY1 +#define VPEC_QUEUE6_DUMMY1__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE6_DUMMY2 +#define VPEC_QUEUE6_DUMMY2__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE6_DUMMY3 +#define VPEC_QUEUE6_DUMMY3__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE6_DUMMY4 +#define VPEC_QUEUE6_DUMMY4__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE6_IB_CNTL +#define VPEC_QUEUE6_IB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE6_IB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE6_IB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE6_IB_RPTR +#define VPEC_QUEUE6_IB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE6_IB_OFFSET +#define VPEC_QUEUE6_IB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE6_IB_BASE_LO +#define VPEC_QUEUE6_IB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE6_IB_BASE_HI +#define VPEC_QUEUE6_IB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE6_IB_SIZE +#define VPEC_QUEUE6_IB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE6_CMDIB_CNTL +#define VPEC_QUEUE6_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE6_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010UL +#define VPEC_QUEUE6_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE6_CMDIB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE6_CMDIB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE6_CMDIB_RPTR +#define VPEC_QUEUE6_CMDIB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE6_CMDIB_OFFSET +#define VPEC_QUEUE6_CMDIB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE6_CMDIB_BASE_LO +#define VPEC_QUEUE6_CMDIB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE6_CMDIB_BASE_HI +#define VPEC_QUEUE6_CMDIB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE6_CMDIB_SIZE +#define VPEC_QUEUE6_CMDIB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE6_3DLUTIB_CNTL +#define VPEC_QUEUE6_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE6_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE6_3DLUTIB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE6_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE6_3DLUTIB_RPTR +#define VPEC_QUEUE6_3DLUTIB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE6_3DLUTIB_OFFSET +#define VPEC_QUEUE6_3DLUTIB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE6_3DLUTIB_BASE_LO +#define VPEC_QUEUE6_3DLUTIB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE6_3DLUTIB_BASE_HI +#define VPEC_QUEUE6_3DLUTIB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE6_3DLUTIB_SIZE +#define VPEC_QUEUE6_3DLUTIB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE6_CSA_ADDR_LO +#define VPEC_QUEUE6_CSA_ADDR_LO__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE6_CSA_ADDR_HI +#define VPEC_QUEUE6_CSA_ADDR_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE6_CONTEXT_STATUS +#define VPEC_QUEUE6_CONTEXT_STATUS__SELECTED_MASK 0x00000001UL +#define VPEC_QUEUE6_CONTEXT_STATUS__USE_IB_MASK 0x00000002UL +#define VPEC_QUEUE6_CONTEXT_STATUS__IDLE_MASK 0x00000004UL +#define VPEC_QUEUE6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008UL +#define VPEC_QUEUE6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070UL +#define VPEC_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080UL +#define VPEC_QUEUE6_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100UL +#define VPEC_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400UL +#define VPEC_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800UL +#define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000UL +#define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00ff0000UL + +// VPEC_QUEUE6_DOORBELL_LOG +#define VPEC_QUEUE6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001UL +#define VPEC_QUEUE6_DOORBELL_LOG__DATA_MASK 0xfffffffcUL + +// VPEC_QUEUE6_IB_SUB_REMAIN +#define VPEC_QUEUE6_IB_SUB_REMAIN__SIZE_MASK 0x00003fffUL + +// VPEC_QUEUE6_PREEMPT +#define VPEC_QUEUE6_PREEMPT__IB_PREEMPT_MASK 0x00000001UL + +// VPEC_QUEUE6_LOG0BUFFER_CFG +#define VPEC_QUEUE6_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE6_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000ff0UL +#define VPEC_QUEUE6_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000ff000UL +#define VPEC_QUEUE6_LOG0BUFFER_CFG__RESERVED_MASK 0xfff00000UL + +// VPEC_QUEUE6_LOG1BUFFER_CFG +#define VPEC_QUEUE6_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE6_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002UL +#define VPEC_QUEUE6_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000ff0UL +#define VPEC_QUEUE6_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000ff000UL +#define VPEC_QUEUE6_LOG1BUFFER_CFG__RESERVED_MASK 0xfff00000UL + +// VPEC_QUEUE7_RB_CNTL +#define VPEC_QUEUE7_RB_CNTL__RB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE7_RB_CNTL__RB_SIZE_MASK 0x0000003eUL +#define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100UL +#define VPEC_QUEUE7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200UL +#define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400UL +#define VPEC_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800UL +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000UL +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000UL +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001f0000UL +#define VPEC_QUEUE7_RB_CNTL__RB_PRIV_MASK 0x00800000UL +#define VPEC_QUEUE7_RB_CNTL__RB_VMID_MASK 0x0f000000UL + +// VPEC_QUEUE7_SCHEDULE_CNTL +#define VPEC_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003UL +#define VPEC_QUEUE7_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001cUL +#define VPEC_QUEUE7_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000c0UL +#define VPEC_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000ff00UL + +// VPEC_QUEUE7_RB_BASE +#define VPEC_QUEUE7_RB_BASE__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE7_RB_BASE_HI +#define VPEC_QUEUE7_RB_BASE_HI__ADDR_MASK 0x00ffffffUL + +// VPEC_QUEUE7_RB_RPTR +#define VPEC_QUEUE7_RB_RPTR__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE7_RB_RPTR_HI +#define VPEC_QUEUE7_RB_RPTR_HI__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE7_RB_WPTR +#define VPEC_QUEUE7_RB_WPTR__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE7_RB_WPTR_HI +#define VPEC_QUEUE7_RB_WPTR_HI__OFFSET_MASK 0xffffffffUL + +// VPEC_QUEUE7_RB_RPTR_ADDR_HI +#define VPEC_QUEUE7_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE7_RB_RPTR_ADDR_LO +#define VPEC_QUEUE7_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffcUL + +// VPEC_QUEUE7_RB_AQL_CNTL +#define VPEC_QUEUE7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000feUL +#define VPEC_QUEUE7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000ff00UL +#define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000UL +#define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000UL +#define VPEC_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000UL + +// VPEC_QUEUE7_MINOR_PTR_UPDATE +#define VPEC_QUEUE7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001UL + +// VPEC_QUEUE7_CD_INFO +#define VPEC_QUEUE7_CD_INFO__CD_INFO_MASK 0xffffffffUL + +// VPEC_QUEUE7_RB_PREEMPT +#define VPEC_QUEUE7_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001UL + +// VPEC_QUEUE7_SKIP_CNTL +#define VPEC_QUEUE7_SKIP_CNTL__SKIP_COUNT_MASK 0x000fffffUL + +// VPEC_QUEUE7_DOORBELL +#define VPEC_QUEUE7_DOORBELL__ENABLE_MASK 0x10000000UL +#define VPEC_QUEUE7_DOORBELL__CAPTURED_MASK 0x40000000UL + +// VPEC_QUEUE7_DOORBELL_OFFSET +#define VPEC_QUEUE7_DOORBELL_OFFSET__OFFSET_MASK 0x0ffffffcUL + +// VPEC_QUEUE7_DUMMY0 +#define VPEC_QUEUE7_DUMMY0__DUMMY_MASK 0xffffffffUL + +// VPEC_QUEUE7_DUMMY1 +#define VPEC_QUEUE7_DUMMY1__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE7_DUMMY2 +#define VPEC_QUEUE7_DUMMY2__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE7_DUMMY3 +#define VPEC_QUEUE7_DUMMY3__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE7_DUMMY4 +#define VPEC_QUEUE7_DUMMY4__VALUE_MASK 0xffffffffUL + +// VPEC_QUEUE7_IB_CNTL +#define VPEC_QUEUE7_IB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE7_IB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE7_IB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE7_IB_RPTR +#define VPEC_QUEUE7_IB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE7_IB_OFFSET +#define VPEC_QUEUE7_IB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE7_IB_BASE_LO +#define VPEC_QUEUE7_IB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE7_IB_BASE_HI +#define VPEC_QUEUE7_IB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE7_IB_SIZE +#define VPEC_QUEUE7_IB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE7_CMDIB_CNTL +#define VPEC_QUEUE7_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE7_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010UL +#define VPEC_QUEUE7_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE7_CMDIB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE7_CMDIB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE7_CMDIB_RPTR +#define VPEC_QUEUE7_CMDIB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE7_CMDIB_OFFSET +#define VPEC_QUEUE7_CMDIB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE7_CMDIB_BASE_LO +#define VPEC_QUEUE7_CMDIB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE7_CMDIB_BASE_HI +#define VPEC_QUEUE7_CMDIB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE7_CMDIB_SIZE +#define VPEC_QUEUE7_CMDIB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE7_3DLUTIB_CNTL +#define VPEC_QUEUE7_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE7_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100UL +#define VPEC_QUEUE7_3DLUTIB_CNTL__CMD_VMID_MASK 0x000f0000UL +#define VPEC_QUEUE7_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000UL + +// VPEC_QUEUE7_3DLUTIB_RPTR +#define VPEC_QUEUE7_3DLUTIB_RPTR__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE7_3DLUTIB_OFFSET +#define VPEC_QUEUE7_3DLUTIB_OFFSET__OFFSET_MASK 0x003ffffcUL + +// VPEC_QUEUE7_3DLUTIB_BASE_LO +#define VPEC_QUEUE7_3DLUTIB_BASE_LO__ADDR_MASK 0xffffffe0UL + +// VPEC_QUEUE7_3DLUTIB_BASE_HI +#define VPEC_QUEUE7_3DLUTIB_BASE_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE7_3DLUTIB_SIZE +#define VPEC_QUEUE7_3DLUTIB_SIZE__SIZE_MASK 0x000fffffUL + +// VPEC_QUEUE7_CSA_ADDR_LO +#define VPEC_QUEUE7_CSA_ADDR_LO__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE7_CSA_ADDR_HI +#define VPEC_QUEUE7_CSA_ADDR_HI__ADDR_MASK 0xffffffffUL + +// VPEC_QUEUE7_CONTEXT_STATUS +#define VPEC_QUEUE7_CONTEXT_STATUS__SELECTED_MASK 0x00000001UL +#define VPEC_QUEUE7_CONTEXT_STATUS__USE_IB_MASK 0x00000002UL +#define VPEC_QUEUE7_CONTEXT_STATUS__IDLE_MASK 0x00000004UL +#define VPEC_QUEUE7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008UL +#define VPEC_QUEUE7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070UL +#define VPEC_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080UL +#define VPEC_QUEUE7_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100UL +#define VPEC_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400UL +#define VPEC_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800UL +#define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000UL +#define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00ff0000UL + +// VPEC_QUEUE7_DOORBELL_LOG +#define VPEC_QUEUE7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001UL +#define VPEC_QUEUE7_DOORBELL_LOG__DATA_MASK 0xfffffffcUL + +// VPEC_QUEUE7_IB_SUB_REMAIN +#define VPEC_QUEUE7_IB_SUB_REMAIN__SIZE_MASK 0x00003fffUL + +// VPEC_QUEUE7_PREEMPT +#define VPEC_QUEUE7_PREEMPT__IB_PREEMPT_MASK 0x00000001UL + +// VPEC_QUEUE7_LOG0BUFFER_CFG +#define VPEC_QUEUE7_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE7_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000ff0UL +#define VPEC_QUEUE7_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000ff000UL +#define VPEC_QUEUE7_LOG0BUFFER_CFG__RESERVED_MASK 0xfff00000UL + +// VPEC_QUEUE7_LOG1BUFFER_CFG +#define VPEC_QUEUE7_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001UL +#define VPEC_QUEUE7_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002UL +#define VPEC_QUEUE7_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000ff0UL +#define VPEC_QUEUE7_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000ff000UL +#define VPEC_QUEUE7_LOG1BUFFER_CFG__RESERVED_MASK 0xfff00000UL + +// VPEP_MGCG_CNTL +#define VPEP_MGCG_CNTL__VPDPP0_CLK_GATE_DIS_MASK 0x00000007UL +#define VPEP_MGCG_CNTL__VPDPP1_CLK_GATE_DIS_MASK 0x00000038UL +#define VPEP_MGCG_CNTL__VPMPC_CLK_GATE_DIS_MASK 0x00003000UL +#define VPEP_MGCG_CNTL__VPOPP_CLK_GATE_DIS_MASK 0x000c0000UL +#define VPEP_MGCG_CNTL__VPCDC_SOCCLK_G_GATE_DIS_MASK 0x00100000UL +#define VPEP_MGCG_CNTL__VPCDC_SOCCLK_R_GATE_DIS_MASK 0x00200000UL +#define VPEP_MGCG_CNTL__VPCDC_VPECLK_G_GATE_DIS_MASK 0x00400000UL +#define VPEP_MGCG_CNTL__VPCDC_VPECLK_R_GATE_DIS_MASK 0x00800000UL +#define VPEP_MGCG_CNTL__VPCDC_FE1_CLK_G_GATE_DIS_MASK 0x01000000UL +#define VPEP_MGCG_CNTL__VPCDC_BE1_CLK_G_GATE_DIS_MASK 0x02000000UL +#define VPEP_MGCG_CNTL__VPCDC_FGCG_REP_DIS_MASK 0x40000000UL + +// VPCDC_SOFT_RESET +#define VPCDC_SOFT_RESET__VPCDC_SOCCLK_SOFT_RESET_MASK 0x00000001UL +#define VPCDC_SOFT_RESET__VPCDC_VPECLK_SOFT_RESET_MASK 0x00000002UL + +// VPCDC_FE0_SURFACE_CONFIG +#define VPCDC_FE0_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_FE0_MASK 0x000001ffUL +#define VPCDC_FE0_SURFACE_CONFIG__ROTATION_ANGLE_FE0_MASK 0x00000600UL +#define VPCDC_FE0_SURFACE_CONFIG__H_MIRROR_EN_FE0_MASK 0x00001000UL +#define VPCDC_FE0_SURFACE_CONFIG__PIX_SURFACE_LINEAR_FE0_MASK 0x00002000UL + +// VPCDC_FE0_CROSSBAR_CONFIG +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_ALPHA_FE0_MASK 0x00000003UL +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_Y_G_FE0_MASK 0x0000000cUL +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CB_B_FE0_MASK 0x00000030UL +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CR_R_FE0_MASK 0x000000c0UL + +// VPCDC_FE0_VIEWPORT_START_CONFIG +#define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_X_START_FE0_MASK 0x00003fffUL +#define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_Y_START_FE0_MASK 0x3fff0000UL + +// VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG +#define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_WIDTH_FE0_MASK 0x00003fffUL +#define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_HEIGHT_FE0_MASK 0x3fff0000UL + +// VPCDC_FE0_VIEWPORT_START_C_CONFIG +#define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_X_START_C_FE0_MASK 0x00003fffUL +#define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_Y_START_C_FE0_MASK 0x3fff0000UL + +// VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG +#define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_WIDTH_C_FE0_MASK 0x00003fffUL +#define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_HEIGHT_C_FE0_MASK 0x3fff0000UL + +// VPCDC_FE1_SURFACE_CONFIG +#define VPCDC_FE1_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_FE1_MASK 0x000001ffUL +#define VPCDC_FE1_SURFACE_CONFIG__ROTATION_ANGLE_FE1_MASK 0x00000600UL +#define VPCDC_FE1_SURFACE_CONFIG__H_MIRROR_EN_FE1_MASK 0x00001000UL +#define VPCDC_FE1_SURFACE_CONFIG__PIX_SURFACE_LINEAR_FE1_MASK 0x00002000UL + +// VPCDC_FE1_CROSSBAR_CONFIG +#define VPCDC_FE1_CROSSBAR_CONFIG__CROSSBAR_SRC_ALPHA_FE1_MASK 0x00000003UL +#define VPCDC_FE1_CROSSBAR_CONFIG__CROSSBAR_SRC_Y_G_FE1_MASK 0x0000000cUL +#define VPCDC_FE1_CROSSBAR_CONFIG__CROSSBAR_SRC_CB_B_FE1_MASK 0x00000030UL +#define VPCDC_FE1_CROSSBAR_CONFIG__CROSSBAR_SRC_CR_R_FE1_MASK 0x000000c0UL + +// VPCDC_FE1_VIEWPORT_START_CONFIG +#define VPCDC_FE1_VIEWPORT_START_CONFIG__VIEWPORT_X_START_FE1_MASK 0x00003fffUL +#define VPCDC_FE1_VIEWPORT_START_CONFIG__VIEWPORT_Y_START_FE1_MASK 0x3fff0000UL + +// VPCDC_FE1_VIEWPORT_DIMENSION_CONFIG +#define VPCDC_FE1_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_WIDTH_FE1_MASK 0x00003fffUL +#define VPCDC_FE1_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_HEIGHT_FE1_MASK 0x3fff0000UL + +// VPCDC_FE1_VIEWPORT_START_C_CONFIG +#define VPCDC_FE1_VIEWPORT_START_C_CONFIG__VIEWPORT_X_START_C_FE1_MASK 0x00003fffUL +#define VPCDC_FE1_VIEWPORT_START_C_CONFIG__VIEWPORT_Y_START_C_FE1_MASK 0x3fff0000UL + +// VPCDC_FE1_VIEWPORT_DIMENSION_C_CONFIG +#define VPCDC_FE1_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_WIDTH_C_FE1_MASK 0x00003fffUL +#define VPCDC_FE1_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_HEIGHT_C_FE1_MASK 0x3fff0000UL + +// VPCDC_BE0_P2B_CONFIG +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL0_MASK 0x00000003UL +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL1_MASK 0x0000000cUL +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL2_MASK 0x00000030UL +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL3_MASK 0x000000c0UL +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_FORMAT_SEL_MASK 0x0001ff00UL +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_TILED_MASK 0x00020000UL +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_X_START_PLANE0_MASK 0x007c0000UL +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_X_START_PLANE1_MASK 0x0f800000UL + +// VPCDC_BE0_GLOBAL_SYNC_CONFIG +#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_OFFSET_MASK 0x000003ffUL +#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_WIDTH_MASK 0x000ffc00UL +#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VREADY_OFFSET_MASK 0x3ff00000UL + +// VPCDC_BE1_P2B_CONFIG +#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_XBAR_SEL0_MASK 0x00000003UL +#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_XBAR_SEL1_MASK 0x0000000cUL +#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_XBAR_SEL2_MASK 0x00000030UL +#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_XBAR_SEL3_MASK 0x000000c0UL +#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_FORMAT_SEL_MASK 0x0001ff00UL +#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_TILED_MASK 0x00020000UL +#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_X_START_PLANE0_MASK 0x007c0000UL +#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_X_START_PLANE1_MASK 0x0f800000UL + +// VPCDC_BE1_GLOBAL_SYNC_CONFIG +#define VPCDC_BE1_GLOBAL_SYNC_CONFIG__BE1_VUPDATE_OFFSET_MASK 0x000003ffUL +#define VPCDC_BE1_GLOBAL_SYNC_CONFIG__BE1_VUPDATE_WIDTH_MASK 0x000ffc00UL +#define VPCDC_BE1_GLOBAL_SYNC_CONFIG__BE1_VREADY_OFFSET_MASK 0x3ff00000UL + +// VPCDC_BE2_P2B_CONFIG +#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_XBAR_SEL0_MASK 0x00000003UL +#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_XBAR_SEL1_MASK 0x0000000cUL +#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_XBAR_SEL2_MASK 0x00000030UL +#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_XBAR_SEL3_MASK 0x000000c0UL +#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_FORMAT_SEL_MASK 0x0001ff00UL +#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_TILED_MASK 0x00020000UL +#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_X_START_PLANE0_MASK 0x007c0000UL +#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_X_START_PLANE1_MASK 0x0f800000UL + +// VPCDC_BE2_GLOBAL_SYNC_CONFIG +#define VPCDC_BE2_GLOBAL_SYNC_CONFIG__BE2_VUPDATE_OFFSET_MASK 0x000003ffUL +#define VPCDC_BE2_GLOBAL_SYNC_CONFIG__BE2_VUPDATE_WIDTH_MASK 0x000ffc00UL +#define VPCDC_BE2_GLOBAL_SYNC_CONFIG__BE2_VREADY_OFFSET_MASK 0x3ff00000UL + +// VPCDC_BE3_P2B_CONFIG +#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_XBAR_SEL0_MASK 0x00000003UL +#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_XBAR_SEL1_MASK 0x0000000cUL +#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_XBAR_SEL2_MASK 0x00000030UL +#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_XBAR_SEL3_MASK 0x000000c0UL +#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_FORMAT_SEL_MASK 0x0001ff00UL +#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_TILED_MASK 0x00020000UL +#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_X_START_PLANE0_MASK 0x007c0000UL +#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_X_START_PLANE1_MASK 0x0f800000UL + +// VPCDC_BE3_GLOBAL_SYNC_CONFIG +#define VPCDC_BE3_GLOBAL_SYNC_CONFIG__BE3_VUPDATE_OFFSET_MASK 0x000003ffUL +#define VPCDC_BE3_GLOBAL_SYNC_CONFIG__BE3_VUPDATE_WIDTH_MASK 0x000ffc00UL +#define VPCDC_BE3_GLOBAL_SYNC_CONFIG__BE3_VREADY_OFFSET_MASK 0x3ff00000UL + +// VPCDC_GLOBAL_SYNC_TRIGGER +#define VPCDC_GLOBAL_SYNC_TRIGGER__VPBE_GS_TRIG_MASK 0x00000003UL + +// VPCDC_VREADY_STATUS +#define VPCDC_VREADY_STATUS__VPFE_VR_STATUS_MASK 0x00000003UL + +// VPEP_MEM_GLOBAL_PWR_REQ_CNTL +#define VPEP_MEM_GLOBAL_PWR_REQ_CNTL__MEM_GLOBAL_PWR_REQ_DIS_MASK 0x00000001UL + +// VPFE0_MEM_PWR_CNTL +#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_FORCE_MASK 0x00000003UL +#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_MODE_MASK 0x0000000cUL +#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_STATE_MASK 0x00000030UL +#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_DIS_MASK 0x00000040UL + +// VPFE1_MEM_PWR_CNTL +#define VPFE1_MEM_PWR_CNTL__VPFE1_MEM_PWR_FORCE_MASK 0x00000003UL +#define VPFE1_MEM_PWR_CNTL__VPFE1_MEM_PWR_MODE_MASK 0x0000000cUL +#define VPFE1_MEM_PWR_CNTL__VPFE1_MEM_PWR_STATE_MASK 0x00000030UL +#define VPFE1_MEM_PWR_CNTL__VPFE1_MEM_PWR_DIS_MASK 0x00000040UL + +// VPBE0_MEM_PWR_CNTL +#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_FORCE_MASK 0x00000003UL +#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_MODE_MASK 0x0000000cUL +#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_STATE_MASK 0x00000030UL +#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_DIS_MASK 0x00000040UL + +// VPBE1_MEM_PWR_CNTL +#define VPBE1_MEM_PWR_CNTL__VPBE1_MEM_PWR_FORCE_MASK 0x00000003UL +#define VPBE1_MEM_PWR_CNTL__VPBE1_MEM_PWR_MODE_MASK 0x0000000cUL +#define VPBE1_MEM_PWR_CNTL__VPBE1_MEM_PWR_STATE_MASK 0x00000030UL +#define VPBE1_MEM_PWR_CNTL__VPBE1_MEM_PWR_DIS_MASK 0x00000040UL + +// VPBE2_MEM_PWR_CNTL +#define VPBE2_MEM_PWR_CNTL__VPBE2_MEM_PWR_FORCE_MASK 0x00000003UL +#define VPBE2_MEM_PWR_CNTL__VPBE2_MEM_PWR_MODE_MASK 0x0000000cUL +#define VPBE2_MEM_PWR_CNTL__VPBE2_MEM_PWR_STATE_MASK 0x00000030UL +#define VPBE2_MEM_PWR_CNTL__VPBE2_MEM_PWR_DIS_MASK 0x00000040UL + +// VPBE3_MEM_PWR_CNTL +#define VPBE3_MEM_PWR_CNTL__VPBE3_MEM_PWR_FORCE_MASK 0x00000003UL +#define VPBE3_MEM_PWR_CNTL__VPBE3_MEM_PWR_MODE_MASK 0x0000000cUL +#define VPBE3_MEM_PWR_CNTL__VPBE3_MEM_PWR_STATE_MASK 0x00000030UL +#define VPBE3_MEM_PWR_CNTL__VPBE3_MEM_PWR_DIS_MASK 0x00000040UL + +// VPEP_RBBMIF_TIMEOUT +#define VPEP_RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0x000fffffUL +#define VPEP_RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_HOLD_MASK 0xfff00000UL + +// VPEP_RBBMIF_STATUS +#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0x0000001fUL +#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000UL +#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000UL +#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000UL +#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000UL + +// VPEP_RBBMIF_TIMEOUT_DIS +#define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x00000001UL +#define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x00000002UL +#define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x00000004UL +#define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x00000008UL +#define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x00000010UL + +// VPCDC_DEBUG_CTRL0 +#define VPCDC_DEBUG_CTRL0__VPCDC_DBG_EN_MASK 0x00000001UL +#define VPCDC_DEBUG_CTRL0__VPCDC_DBGMUX_OUT_0_SEL_SOCCLK_MASK 0x00700000UL + +// VPCDC_DEBUG_CTRL1 +#define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_0_SEL_VPECLK_MASK 0x0000003fUL +#define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_1_SEL_VPECLK_MASK 0x00003f00UL +#define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_2_SEL_VPECLK_MASK 0x003f0000UL +#define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_3_SEL_VPECLK_MASK 0x3f000000UL + +// VPCDC_TEST_DEBUG_INDEX +#define VPCDC_TEST_DEBUG_INDEX__VPCDC_TEST_DEBUG_INDEX_MASK 0x000000ffUL + +// VPCDC_TEST_DEBUG_DATA +#define VPCDC_TEST_DEBUG_DATA__VPCDC_TEST_DEBUG_DATA_MASK 0xffffffffUL + +// VPCDC_3DLUT_FL_CONFIG +#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_MODE_MASK 0x00000003UL +#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_CROSSBAR_SRC_G_MASK 0x0000000cUL +#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_CROSSBAR_SRC_B_MASK 0x00000030UL +#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_CROSSBAR_SRC_R_MASK 0x000000c0UL +#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_SIZE_MASK 0x00000100UL + +// VPCDC_CONTROL +#define VPCDC_CONTROL__VPCDC_HISTOGRAM0_EN_MASK 0x00000003UL +#define VPCDC_CONTROL__VPCDC_HISTOGRAM1_EN_MASK 0x0000000cUL +#define VPCDC_CONTROL__VPCDC_FROD_EN_MASK 0x00000100UL + +// PERFCOUNTER_CNTL +#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001ffUL +#define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000e00UL +#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000UL +#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000UL +#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000UL +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000UL +#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000UL +#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000UL +#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000UL +#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000UL +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xe0000000UL + +// PERFCOUNTER_CNTL2 +#define PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003UL +#define PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004UL +#define PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008UL +#define PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003f00UL +#define PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xe0000000UL + +// PERFCOUNTER_STATE +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003UL +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004UL +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030UL +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040UL +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300UL +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400UL +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000UL +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000UL +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000UL +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000UL +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000UL +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000UL +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000UL +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000UL +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000UL +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000UL + +// VPCNVC_SURFACE_PIXEL_FORMAT +#define VPCNVC_SURFACE_PIXEL_FORMAT__VPCNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007fUL + +// VPCNVC_FORMAT_CONTROL +#define VPCNVC_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001UL +#define VPCNVC_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010UL +#define VPCNVC_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100UL +#define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS_MASK 0x00001000UL +#define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS_MSB_ALIGN_MASK 0x00002000UL +#define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000UL +#define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000UL +#define VPCNVC_FORMAT_CONTROL__VPCNVC_UPDATE_PENDING_MASK 0x00100000UL + +// VPCNVC_FCNV_FP_BIAS_R +#define VPCNVC_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007ffffUL + +// VPCNVC_FCNV_FP_BIAS_G +#define VPCNVC_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007ffffUL + +// VPCNVC_FCNV_FP_BIAS_B +#define VPCNVC_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007ffffUL + +// VPCNVC_FCNV_FP_SCALE_R +#define VPCNVC_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007ffffUL + +// VPCNVC_FCNV_FP_SCALE_G +#define VPCNVC_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007ffffUL + +// VPCNVC_FCNV_FP_SCALE_B +#define VPCNVC_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007ffffUL + +// VPCNVC_COLOR_KEYER_CONTROL +#define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001UL +#define VPCNVC_COLOR_KEYER_CONTROL__LUMA_KEYER_EN_MASK 0x00000002UL +#define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030UL + +// VPCNVC_COLOR_KEYER_ALPHA +#define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000ffffUL +#define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xffff0000UL + +// VPCNVC_COLOR_KEYER_RED +#define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000ffffUL +#define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xffff0000UL + +// VPCNVC_COLOR_KEYER_GREEN +#define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000ffffUL +#define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xffff0000UL + +// VPCNVC_COLOR_KEYER_BLUE +#define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000ffffUL +#define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xffff0000UL + +// VPCNVC_ALPHA_2BIT_LUT01 +#define VPCNVC_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT0_MASK 0x00000fffUL +#define VPCNVC_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT1_MASK 0x0fff0000UL + +// VPCNVC_ALPHA_2BIT_LUT23 +#define VPCNVC_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT2_MASK 0x00000fffUL +#define VPCNVC_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT3_MASK 0x0fff0000UL + +// VPCNVC_PRE_DEALPHA +#define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001UL +#define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010UL + +// VPCNVC_PRE_CSC_MODE +#define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000001UL +#define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x00000004UL + +// VPCNVC_PRE_CSC_C11_C12 +#define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000ffffUL +#define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xffff0000UL + +// VPCNVC_PRE_CSC_C13_C14 +#define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000ffffUL +#define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xffff0000UL + +// VPCNVC_PRE_CSC_C21_C22 +#define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000ffffUL +#define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xffff0000UL + +// VPCNVC_PRE_CSC_C23_C24 +#define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000ffffUL +#define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xffff0000UL + +// VPCNVC_PRE_CSC_C31_C32 +#define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000ffffUL +#define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xffff0000UL + +// VPCNVC_PRE_CSC_C33_C34 +#define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000ffffUL +#define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xffff0000UL + +// VPCNVC_COEF_FORMAT +#define VPCNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001UL + +// VPCNVC_PRE_DEGAM +#define VPCNVC_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003UL +#define VPCNVC_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070UL + +// VPCNVC_PRE_REALPHA +#define VPCNVC_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001UL +#define VPCNVC_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010UL + +// VPCNVC_CFG_TEST_DEBUG_INDEX +#define VPCNVC_CFG_TEST_DEBUG_INDEX__VPCNVC_CFG_TEST_DEBUG_INDEX_MASK 0x000000ffUL +#define VPCNVC_CFG_TEST_DEBUG_INDEX__VPCNVC_CFG_TEST_DEBUG_WRITE_EN_MASK 0x00000100UL + +// VPCNVC_CFG_TEST_DEBUG_DATA +#define VPCNVC_CFG_TEST_DEBUG_DATA__VPCNVC_CFG_TEST_DEBUG_DATA_MASK 0xffffffffUL + +// VPDSCL_COEF_RAM_TAP_SELECT +#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003UL +#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003f00UL +#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000UL + +// VPDSCL_COEF_RAM_TAP_DATA +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003fffUL +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000UL +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3fff0000UL +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000UL + +// VPDSCL_MODE +#define VPDSCL_MODE__VPDSCL_MODE_MASK 0x00000007UL +#define VPDSCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000UL +#define VPDSCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000UL +#define VPDSCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000UL +#define VPDSCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000UL + +// VPDSCL_TAP_CONTROL +#define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007UL +#define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070UL +#define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700UL +#define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000UL + +// VPDSCL_CONTROL +#define VPDSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001UL + +// VPDSCL_2TAP_CONTROL +#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001UL +#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010UL +#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700UL +#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000UL +#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000UL +#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000UL + +// VPDSCL_MANUAL_REPLICATE_CONTROL +#define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000fUL +#define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000f00UL + +// VPDSCL_HORZ_FILTER_SCALE_RATIO +#define VPDSCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07ffffffUL + +// VPDSCL_HORZ_FILTER_INIT +#define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00ffffffUL +#define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0f000000UL + +// VPDSCL_HORZ_FILTER_SCALE_RATIO_C +#define VPDSCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07ffffffUL + +// VPDSCL_HORZ_FILTER_INIT_C +#define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00ffffffUL +#define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0f000000UL + +// VPDSCL_VERT_FILTER_SCALE_RATIO +#define VPDSCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07ffffffUL + +// VPDSCL_VERT_FILTER_INIT +#define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00ffffffUL +#define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0f000000UL + +// VPDSCL_VERT_FILTER_INIT_BOT +#define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00ffffffUL +#define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0f000000UL + +// VPDSCL_VERT_FILTER_SCALE_RATIO_C +#define VPDSCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07ffffffUL + +// VPDSCL_VERT_FILTER_INIT_C +#define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00ffffffUL +#define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0f000000UL + +// VPDSCL_VERT_FILTER_INIT_BOT_C +#define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00ffffffUL +#define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0f000000UL + +// VPDSCL_BLACK_COLOR +#define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000ffffUL +#define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xffff0000UL + +// VPDSCL_UPDATE +#define VPDSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001UL + +// VPDSCL_AUTOCAL +#define VPDSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003UL + +// VPDSCL_EXT_OVERSCAN_LEFT_RIGHT +#define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001fffUL +#define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000UL + +// VPDSCL_EXT_OVERSCAN_TOP_BOTTOM +#define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001fffUL +#define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000UL + +// VPOTG_H_BLANK +#define VPOTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003fffUL +#define VPOTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3fff0000UL + +// VPOTG_V_BLANK +#define VPOTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003fffUL +#define VPOTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3fff0000UL + +// VPDSCL_RECOUT_START +#define VPDSCL_RECOUT_START__RECOUT_START_X_MASK 0x00001fffUL +#define VPDSCL_RECOUT_START__RECOUT_START_Y_MASK 0x1fff0000UL + +// VPDSCL_RECOUT_SIZE +#define VPDSCL_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003fffUL +#define VPDSCL_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3fff0000UL + +// VPMPC_SIZE +#define VPMPC_SIZE__VPMPC_WIDTH_MASK 0x00003fffUL +#define VPMPC_SIZE__VPMPC_HEIGHT_MASK 0x3fff0000UL + +// VPLB_DATA_FORMAT +#define VPLB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010UL + +// VPLB_MEMORY_CTRL +#define VPLB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003f00UL +#define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007f0000UL +#define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7f000000UL + +// VPLB_V_COUNTER +#define VPLB_V_COUNTER__V_COUNTER_MASK 0x00001fffUL +#define VPLB_V_COUNTER__V_COUNTER_C_MASK 0x1fff0000UL + +// VPDSCL_MEM_PWR_CTRL +#define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003UL +#define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004UL +#define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030UL +#define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040UL +#define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300UL +#define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400UL +#define VPDSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000UL + +// VPDSCL_MEM_PWR_STATUS +#define VPDSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003UL +#define VPDSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000cUL +#define VPDSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030UL + +// VPDSCL_EASF_H_MODE +#define VPDSCL_EASF_H_MODE__SCL_EASF_H_EN_MASK 0x00000001UL +#define VPDSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN_MASK 0x00000010UL +#define VPDSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR_MASK 0x00003f00UL + +// VPDSCL_EASF_V_MODE +#define VPDSCL_EASF_V_MODE__SCL_EASF_V_EN_MASK 0x00000001UL +#define VPDSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN_MASK 0x00000010UL +#define VPDSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR_MASK 0x00003f00UL + +// VPDSCL_SC_MODE +#define VPDSCL_SC_MODE__SCL_SC_MATRIX_MODE_MASK 0x00000001UL +#define VPDSCL_SC_MODE__SCL_SC_LTONL_EN_MASK 0x00000100UL + +// VPDSCL_SC_MATRIX_C0C1 +#define VPDSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0_MASK 0x0000ffffUL +#define VPDSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1_MASK 0xffff0000UL + +// VPDSCL_SC_MATRIX_C2C3 +#define VPDSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2_MASK 0x0000ffffUL +#define VPDSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3_MASK 0xffff0000UL + +// VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN +#define VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1_MASK 0x0000ffffUL +#define VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2_MASK 0xffff0000UL + +// VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE +#define VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000ffffUL +#define VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2_MASK 0xffff0000UL + +// VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN +#define VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1_MASK 0x0000ffffUL +#define VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2_MASK 0xffff0000UL + +// VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE +#define VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000ffffUL +#define VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2_MASK 0xffff0000UL + +// VPDSCL_EASF_V_RINGEST_3TAP_CNTL1 +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT_MASK 0x0000ffffUL +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL_MASK 0xffff0000UL + +// VPDSCL_EASF_V_RINGEST_3TAP_CNTL2 +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE_MASK 0x0000ffffUL +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE_MASK 0xffff0000UL + +// VPDSCL_EASF_V_RINGEST_3TAP_CNTL3 +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE_MASK 0x0000ffffUL +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET_MASK 0xffff0000UL + +// VPDSCL_EASF_RINGEST_FORCE +#define VPDSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE_MASK 0x0000ffffUL +#define VPDSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE_MASK 0xffff0000UL + +// VPDSCL_EASF_H_BF_CNTL +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN_MASK 0x00000001UL +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE_MASK 0x00000f00UL +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE_MASK 0x00030000UL +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN_MASK 0x00f00000UL +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN_MASK 0x0f000000UL +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN_MASK 0xf0000000UL + +// VPDSCL_EASF_H_BF_FINAL_MAX_MIN +#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA_MASK 0x0000003fUL +#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB_MASK 0x00003f00UL +#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA_MASK 0x003f0000UL +#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB_MASK 0x3f000000UL + +// VPDSCL_EASF_V_BF_CNTL +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN_MASK 0x00000001UL +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE_MASK 0x00000f00UL +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE_MASK 0x00030000UL +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN_MASK 0x00f00000UL +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN_MASK 0x0f000000UL +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN_MASK 0xf0000000UL + +// VPDSCL_EASF_V_BF_FINAL_MAX_MIN +#define VPDSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA_MASK 0x0000003fUL +#define VPDSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB_MASK 0x00003f00UL +#define VPDSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA_MASK 0x003f0000UL +#define VPDSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB_MASK 0x3f000000UL + +// VPDSCL_EASF_H_BF1_PWL_SEG0 +#define VPDSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0_MASK 0x000007ffUL +#define VPDSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0_MASK 0x0003f000UL +#define VPDSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0_MASK 0x7ff00000UL + +// VPDSCL_EASF_H_BF1_PWL_SEG1 +#define VPDSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1_MASK 0x000007ffUL +#define VPDSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1_MASK 0x0003f000UL +#define VPDSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1_MASK 0x7ff00000UL + +// VPDSCL_EASF_H_BF1_PWL_SEG2 +#define VPDSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2_MASK 0x000007ffUL +#define VPDSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2_MASK 0x0003f000UL +#define VPDSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2_MASK 0x7ff00000UL + +// VPDSCL_EASF_H_BF1_PWL_SEG3 +#define VPDSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3_MASK 0x000007ffUL +#define VPDSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3_MASK 0x0003f000UL +#define VPDSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3_MASK 0x7ff00000UL + +// VPDSCL_EASF_H_BF1_PWL_SEG4 +#define VPDSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4_MASK 0x000007ffUL +#define VPDSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4_MASK 0x0003f000UL +#define VPDSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4_MASK 0x7ff00000UL + +// VPDSCL_EASF_H_BF1_PWL_SEG5 +#define VPDSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5_MASK 0x000007ffUL +#define VPDSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5_MASK 0x0003f000UL +#define VPDSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5_MASK 0x7ff00000UL + +// VPDSCL_EASF_H_BF1_PWL_SEG6 +#define VPDSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6_MASK 0x000007ffUL +#define VPDSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6_MASK 0x0003f000UL +#define VPDSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6_MASK 0x7ff00000UL + +// VPDSCL_EASF_H_BF1_PWL_SEG7 +#define VPDSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7_MASK 0x000007ffUL +#define VPDSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7_MASK 0x0003f000UL + +// VPDSCL_EASF_V_BF1_PWL_SEG0 +#define VPDSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0_MASK 0x000007ffUL +#define VPDSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0_MASK 0x0003f000UL +#define VPDSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0_MASK 0x7ff00000UL + +// VPDSCL_EASF_V_BF1_PWL_SEG1 +#define VPDSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1_MASK 0x000007ffUL +#define VPDSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1_MASK 0x0003f000UL +#define VPDSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1_MASK 0x7ff00000UL + +// VPDSCL_EASF_V_BF1_PWL_SEG2 +#define VPDSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2_MASK 0x000007ffUL +#define VPDSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2_MASK 0x0003f000UL +#define VPDSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2_MASK 0x7ff00000UL + +// VPDSCL_EASF_V_BF1_PWL_SEG3 +#define VPDSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3_MASK 0x000007ffUL +#define VPDSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3_MASK 0x0003f000UL +#define VPDSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3_MASK 0x7ff00000UL + +// VPDSCL_EASF_V_BF1_PWL_SEG4 +#define VPDSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4_MASK 0x000007ffUL +#define VPDSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4_MASK 0x0003f000UL +#define VPDSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4_MASK 0x7ff00000UL + +// VPDSCL_EASF_V_BF1_PWL_SEG5 +#define VPDSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5_MASK 0x000007ffUL +#define VPDSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5_MASK 0x0003f000UL +#define VPDSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5_MASK 0x7ff00000UL + +// VPDSCL_EASF_V_BF1_PWL_SEG6 +#define VPDSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6_MASK 0x000007ffUL +#define VPDSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6_MASK 0x0003f000UL +#define VPDSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6_MASK 0x7ff00000UL + +// VPDSCL_EASF_V_BF1_PWL_SEG7 +#define VPDSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7_MASK 0x000007ffUL +#define VPDSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7_MASK 0x0003f000UL + +// VPDSCL_EASF_H_BF3_PWL_SEG0 +#define VPDSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0_MASK 0x00000fffUL +#define VPDSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0_MASK 0x0007f000UL +#define VPDSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0_MASK 0xfff80000UL + +// VPDSCL_EASF_H_BF3_PWL_SEG1 +#define VPDSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1_MASK 0x00000fffUL +#define VPDSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1_MASK 0x0007f000UL +#define VPDSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1_MASK 0xfff80000UL + +// VPDSCL_EASF_H_BF3_PWL_SEG2 +#define VPDSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2_MASK 0x00000fffUL +#define VPDSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2_MASK 0x0007f000UL +#define VPDSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2_MASK 0xfff80000UL + +// VPDSCL_EASF_H_BF3_PWL_SEG3 +#define VPDSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3_MASK 0x00000fffUL +#define VPDSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3_MASK 0x0007f000UL +#define VPDSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3_MASK 0xfff80000UL + +// VPDSCL_EASF_H_BF3_PWL_SEG4 +#define VPDSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4_MASK 0x00000fffUL +#define VPDSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4_MASK 0x0007f000UL +#define VPDSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4_MASK 0xfff80000UL + +// VPDSCL_EASF_H_BF3_PWL_SEG5 +#define VPDSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5_MASK 0x00000fffUL +#define VPDSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5_MASK 0x0007f000UL + +// VPDSCL_EASF_V_BF3_PWL_SEG0 +#define VPDSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0_MASK 0x00000fffUL +#define VPDSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0_MASK 0x0007f000UL +#define VPDSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0_MASK 0xfff80000UL + +// VPDSCL_EASF_V_BF3_PWL_SEG1 +#define VPDSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1_MASK 0x00000fffUL +#define VPDSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1_MASK 0x0007f000UL +#define VPDSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1_MASK 0xfff80000UL + +// VPDSCL_EASF_V_BF3_PWL_SEG2 +#define VPDSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2_MASK 0x00000fffUL +#define VPDSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2_MASK 0x0007f000UL +#define VPDSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2_MASK 0xfff80000UL + +// VPDSCL_EASF_V_BF3_PWL_SEG3 +#define VPDSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3_MASK 0x00000fffUL +#define VPDSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3_MASK 0x0007f000UL +#define VPDSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3_MASK 0xfff80000UL + +// VPDSCL_EASF_V_BF3_PWL_SEG4 +#define VPDSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4_MASK 0x00000fffUL +#define VPDSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4_MASK 0x0007f000UL +#define VPDSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4_MASK 0xfff80000UL + +// VPDSCL_EASF_V_BF3_PWL_SEG5 +#define VPDSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5_MASK 0x00000fffUL +#define VPDSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5_MASK 0x0007f000UL + +// VPISHARP_MODE +#define VPISHARP_MODE__ISHARP_EN_MASK 0x00000001UL +#define VPISHARP_MODE__ISHARP_NOISEDET_EN_MASK 0x00000010UL +#define VPISHARP_MODE__ISHARP_NOISEDET_MODE_MASK 0x00000060UL +#define VPISHARP_MODE__ISHARP_LBA_MODE_MASK 0x00000200UL +#define VPISHARP_MODE__ISHARP_FMT_MODE_MASK 0x00000800UL +#define VPISHARP_MODE__ISHARP_FMT_NORM_MASK 0x0ffff000UL +#define VPISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT_MASK 0x10000000UL + +// VPISHARP_DELTA_CTRL +#define VPISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT_MASK 0x00000001UL + +// VPISHARP_DELTA_INDEX +#define VPISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX_MASK 0x0000001fUL + +// VPISHARP_DELTA_DATA +#define VPISHARP_DELTA_DATA__ISHARP_DELTA_DATA_MASK 0xffffffffUL + +// VPISHARP_NLDELTA_SOFT_CLIP +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P_MASK 0x00000001UL +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P_MASK 0x000000feUL +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P_MASK 0x0000ff00UL +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N_MASK 0x00010000UL +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N_MASK 0x00fe0000UL +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N_MASK 0xff000000UL + +// VPISHARP_NOISEDET_THRESHOLD +#define VPISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE_MASK 0x000003ffUL +#define VPISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE_MASK 0x03ff0000UL + +// VPISHARP_NOISE_GAIN_PWL +#define VPISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN_MASK 0x0000001fUL +#define VPISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN_MASK 0x00001f00UL +#define VPISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE_MASK 0x3fff0000UL + +// VPISHARP_LBA_PWL_SEG0 +#define VPISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0_MASK 0x000003ffUL +#define VPISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0_MASK 0x0003f000UL +#define VPISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0_MASK 0x1ff00000UL + +// VPISHARP_LBA_PWL_SEG1 +#define VPISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1_MASK 0x000003ffUL +#define VPISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1_MASK 0x0003f000UL +#define VPISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1_MASK 0x1ff00000UL + +// VPISHARP_LBA_PWL_SEG2 +#define VPISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2_MASK 0x000003ffUL +#define VPISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2_MASK 0x0003f000UL +#define VPISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2_MASK 0x1ff00000UL + +// VPISHARP_LBA_PWL_SEG3 +#define VPISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3_MASK 0x000003ffUL +#define VPISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3_MASK 0x0003f000UL +#define VPISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3_MASK 0x1ff00000UL + +// VPISHARP_LBA_PWL_SEG4 +#define VPISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4_MASK 0x000003ffUL +#define VPISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4_MASK 0x0003f000UL +#define VPISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4_MASK 0x1ff00000UL + +// VPISHARP_LBA_PWL_SEG5 +#define VPISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5_MASK 0x000003ffUL +#define VPISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5_MASK 0x0003f000UL + +// VPISHARP_DELTA_LUT_MEM_PWR_CTRL +#define VPISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE_MASK 0x00000003UL +#define VPISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS_MASK 0x00000004UL +#define VPISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE_MASK 0x00000030UL + +// VPDSCL_DEBUG +#define VPDSCL_DEBUG__SCL_DEBUG_MASK 0xffffffffUL + +// VPDSCL_TEST_DEBUG_INDEX +#define VPDSCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0x000000ffUL +#define VPDSCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x00000100UL + +// VPDSCL_TEST_DEBUG_DATA +#define VPDSCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffffUL + +// VPCM_CONTROL +#define VPCM_CONTROL__VPCM_BYPASS_MASK 0x00000001UL +#define VPCM_CONTROL__VPCM_UPDATE_PENDING_MASK 0x00000100UL + +// VPCM_POST_CSC_CONTROL +#define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE_MASK 0x00000001UL +#define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE_CURRENT_MASK 0x00000004UL + +// VPCM_POST_CSC_C11_C12 +#define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C11_MASK 0x0000ffffUL +#define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C12_MASK 0xffff0000UL + +// VPCM_POST_CSC_C13_C14 +#define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C13_MASK 0x0000ffffUL +#define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C14_MASK 0xffff0000UL + +// VPCM_POST_CSC_C21_C22 +#define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C21_MASK 0x0000ffffUL +#define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C22_MASK 0xffff0000UL + +// VPCM_POST_CSC_C23_C24 +#define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C23_MASK 0x0000ffffUL +#define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C24_MASK 0xffff0000UL + +// VPCM_POST_CSC_C31_C32 +#define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C31_MASK 0x0000ffffUL +#define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C32_MASK 0xffff0000UL + +// VPCM_POST_CSC_C33_C34 +#define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C33_MASK 0x0000ffffUL +#define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C34_MASK 0xffff0000UL + +// VPCM_BIAS_CR_R +#define VPCM_BIAS_CR_R__VPCM_BIAS_CR_R_MASK 0x0000ffffUL + +// VPCM_BIAS_Y_G_CB_B +#define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_Y_G_MASK 0x0000ffffUL +#define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_CB_B_MASK 0xffff0000UL + +// VPCM_GAMCOR_CONTROL +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE_MASK 0x00000003UL +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_PWL_DISABLE_MASK 0x00000008UL +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE_CURRENT_MASK 0x00000030UL +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_SELECT_CURRENT_MASK 0x00000040UL + +// VPCM_GAMCOR_LUT_INDEX +#define VPCM_GAMCOR_LUT_INDEX__VPCM_GAMCOR_LUT_INDEX_MASK 0x000001ffUL + +// VPCM_GAMCOR_LUT_DATA +#define VPCM_GAMCOR_LUT_DATA__VPCM_GAMCOR_LUT_DATA_MASK 0x0003ffffUL + +// VPCM_GAMCOR_LUT_CONTROL +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007UL +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018UL +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_DBG_MASK 0x00000020UL +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040UL +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080UL + +// VPCM_GAMCOR_RAMA_START_CNTL_B +#define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003ffffUL +#define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07f00000UL + +// VPCM_GAMCOR_RAMA_START_CNTL_G +#define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003ffffUL +#define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07f00000UL + +// VPCM_GAMCOR_RAMA_START_CNTL_R +#define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003ffffUL +#define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07f00000UL + +// VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003ffffUL + +// VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003ffffUL + +// VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003ffffUL + +// VPCM_GAMCOR_RAMA_START_BASE_CNTL_B +#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003ffffUL + +// VPCM_GAMCOR_RAMA_START_BASE_CNTL_G +#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003ffffUL + +// VPCM_GAMCOR_RAMA_START_BASE_CNTL_R +#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003ffffUL + +// VPCM_GAMCOR_RAMA_END_CNTL1_B +#define VPCM_GAMCOR_RAMA_END_CNTL1_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003ffffUL + +// VPCM_GAMCOR_RAMA_END_CNTL2_B +#define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000ffffUL +#define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xffff0000UL + +// VPCM_GAMCOR_RAMA_END_CNTL1_G +#define VPCM_GAMCOR_RAMA_END_CNTL1_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003ffffUL + +// VPCM_GAMCOR_RAMA_END_CNTL2_G +#define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000ffffUL +#define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xffff0000UL + +// VPCM_GAMCOR_RAMA_END_CNTL1_R +#define VPCM_GAMCOR_RAMA_END_CNTL1_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003ffffUL + +// VPCM_GAMCOR_RAMA_END_CNTL2_R +#define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000ffffUL +#define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xffff0000UL + +// VPCM_GAMCOR_RAMA_OFFSET_B +#define VPCM_GAMCOR_RAMA_OFFSET_B__VPCM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007ffffUL + +// VPCM_GAMCOR_RAMA_OFFSET_G +#define VPCM_GAMCOR_RAMA_OFFSET_G__VPCM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007ffffUL + +// VPCM_GAMCOR_RAMA_OFFSET_R +#define VPCM_GAMCOR_RAMA_OFFSET_R__VPCM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007ffffUL + +// VPCM_GAMCOR_RAMA_REGION_0_1 +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_2_3 +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_4_5 +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_6_7 +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_8_9 +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_10_11 +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_12_13 +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_14_15 +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_16_17 +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_18_19 +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_20_21 +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_22_23 +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_24_25 +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_26_27 +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_28_29 +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_30_31 +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_32_33 +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_HDR_MULT_COEF +#define VPCM_HDR_MULT_COEF__VPCM_HDR_MULT_COEF_MASK 0x0007ffffUL + +// VPCM_MEM_PWR_CTRL +#define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003UL +#define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004UL +#define VPCM_MEM_PWR_CTRL__HIST_MEM_PWR_FORCE_MASK 0x00000100UL +#define VPCM_MEM_PWR_CTRL__HIST_MEM_PWR_DIS_MASK 0x00000200UL + +// VPCM_MEM_PWR_STATUS +#define VPCM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003UL +#define VPCM_MEM_PWR_STATUS__HIST_MEM_PWR_STATE_MASK 0x00000100UL + +// VPCM_DEALPHA +#define VPCM_DEALPHA__VPCM_DEALPHA_EN_MASK 0x00000001UL +#define VPCM_DEALPHA__VPCM_DEALPHA_ABLND_MASK 0x00000002UL + +// VPCM_COEF_FORMAT +#define VPCM_COEF_FORMAT__VPCM_BIAS_FORMAT_MASK 0x00000001UL +#define VPCM_COEF_FORMAT__VPCM_POST_CSC_COEF_FORMAT_MASK 0x00000010UL + +// VPCM_TEST_DEBUG_INDEX +#define VPCM_TEST_DEBUG_INDEX__VPCM_TEST_DEBUG_INDEX_MASK 0x000000ffUL +#define VPCM_TEST_DEBUG_INDEX__VPCM_TEST_DEBUG_WRITE_EN_MASK 0x00000100UL + +// VPCM_TEST_DEBUG_DATA +#define VPCM_TEST_DEBUG_DATA__VPCM_TEST_DEBUG_DATA_MASK 0xffffffffUL + +// VPCM_HIST_CNTL +#define VPCM_HIST_CNTL__VPCM_HIST_SEL_MASK 0x00000003UL +#define VPCM_HIST_CNTL__VPCM_HIST_CH_EN_MASK 0x0000000cUL +#define VPCM_HIST_CNTL__VPCM_HIST_SRC1_SEL_MASK 0x00000010UL +#define VPCM_HIST_CNTL__VPCM_HIST_SRC2_SEL_MASK 0x00000020UL +#define VPCM_HIST_CNTL__VPCM_HIST_SRC3_SEL_MASK 0x00000040UL +#define VPCM_HIST_CNTL__VPCM_HIST_CH1_XBAR_MASK 0x00000180UL +#define VPCM_HIST_CNTL__VPCM_HIST_CH2_XBAR_MASK 0x00000600UL +#define VPCM_HIST_CNTL__VPCM_HIST_CH3_XBAR_MASK 0x00001800UL +#define VPCM_HIST_CNTL__VPCM_HIST_FORMAT_MASK 0x00006000UL +#define VPCM_HIST_CNTL__VPCM_HIST_READ_CHANNEL_MASK_MASK 0x00038000UL + +// VPCM_HIST_SCALE_SRC1 +#define VPCM_HIST_SCALE_SRC1__VPCM_HIST_SCALE_SRC1_MASK 0x0007ffffUL + +// VPCM_HIST_COEFA_SRC2 +#define VPCM_HIST_COEFA_SRC2__VPCM_HIST_COEFA_SRC2_MASK 0x0007ffffUL + +// VPCM_HIST_COEFB_SRC2 +#define VPCM_HIST_COEFB_SRC2__VPCM_HIST_COEFB_SRC2_MASK 0x0007ffffUL + +// VPCM_HIST_COEFC_SRC2 +#define VPCM_HIST_COEFC_SRC2__VPCM_HIST_COEFC_SRC2_MASK 0x0007ffffUL + +// VPCM_HIST_SCALE_SRC3 +#define VPCM_HIST_SCALE_SRC3__VPCM_HIST_SCALE_SRC3_MASK 0x0007ffffUL + +// VPCM_HIST_BIAS_SRC1 +#define VPCM_HIST_BIAS_SRC1__VPCM_HIST_BIAS_SRC1_MASK 0x0007ffffUL + +// VPCM_HIST_BIAS_SRC2 +#define VPCM_HIST_BIAS_SRC2__VPCM_HIST_BIAS_SRC2_MASK 0x0007ffffUL + +// VPCM_HIST_BIAS_SRC3 +#define VPCM_HIST_BIAS_SRC3__VPCM_HIST_BIAS_SRC3_MASK 0x0007ffffUL + +// VPCM_HIST_LOCK +#define VPCM_HIST_LOCK__VPCM_HIST_LOCK_MASK 0x00000001UL + +// VPCM_HIST_INDEX +#define VPCM_HIST_INDEX__VPCM_HIST_INDEX_MASK 0x000000ffUL + +// VPCM_HIST_DATA +#define VPCM_HIST_DATA__VPCM_HIST_DATA_MASK 0x01ffffffUL + +// VPCM_HIST_STATUS +#define VPCM_HIST_STATUS__VPCM_HIST_RDY_STATUS_MASK 0x00000001UL +#define VPCM_HIST_STATUS__VPCM_HIST_FRAME_COLLECT_SKIPPED_MASK 0x00000010UL +#define VPCM_HIST_STATUS__VPCM_HIST_FRAME_COLLECT_SKIPPED_CURRENT_MASK 0x00000020UL +#define VPCM_HIST_STATUS__VPCM_HIST_FRAME_COLLECT_SKIPPED_CNT_MASK 0x000001c0UL +#define VPCM_HIST_STATUS__VPCM_HIST_TX_NOT_COMPLETED_MASK 0x00010000UL +#define VPCM_HIST_STATUS__VPCM_HIST_TX_NOT_COMPLETED_CURRENT_MASK 0x00020000UL +#define VPCM_HIST_STATUS__VPCM_HIST_TX_STATUS_MASK 0x000c0000UL +#define VPCM_HIST_STATUS__VPCM_HIST_COUNT_OVERFLOW_MASK 0x01000000UL +#define VPCM_HIST_STATUS__VPCM_HIST_COUNT_OVERFLOW_CURRENT_MASK 0x02000000UL +#define VPCM_HIST_STATUS__VPCM_HIST_COLLECT_INCOMPLETE_MASK 0x04000000UL +#define VPCM_HIST_STATUS__VPCM_HIST_COLLECT_INCOMPLETE_CURRENT_MASK 0x08000000UL + +// VPDPP_CONTROL +#define VPDPP_CONTROL__VPECLK_G_GATE_DISABLE_MASK 0x00000100UL +#define VPDPP_CONTROL__VPECLK_G_VPDSCL_GATE_DISABLE_MASK 0x00001000UL +#define VPDPP_CONTROL__VPECLK_R_GATE_DISABLE_MASK 0x00004000UL +#define VPDPP_CONTROL__VPDPP_FGCG_REP_DIS_MASK 0x01000000UL + +// VPDPP_SOFT_RESET +#define VPDPP_SOFT_RESET__VPCNVC_SOFT_RESET_MASK 0x00000001UL +#define VPDPP_SOFT_RESET__VPDSCL_SOFT_RESET_MASK 0x00000010UL +#define VPDPP_SOFT_RESET__VPCM_SOFT_RESET_MASK 0x00000100UL +#define VPDPP_SOFT_RESET__VPOBUF_SOFT_RESET_MASK 0x00001000UL +#define VPDPP_SOFT_RESET__VPHIST_SOFT_RESET_MASK 0x00010000UL + +// VPDPP_CRC_VAL_R_G +#define VPDPP_CRC_VAL_R_G__VPDPP_CRC_R_CR_MASK 0x0000ffffUL +#define VPDPP_CRC_VAL_R_G__VPDPP_CRC_G_Y_MASK 0xffff0000UL + +// VPDPP_CRC_VAL_B_A +#define VPDPP_CRC_VAL_B_A__VPDPP_CRC_B_CB_MASK 0x0000ffffUL +#define VPDPP_CRC_VAL_B_A__VPDPP_CRC_ALPHA_MASK 0xffff0000UL + +// VPDPP_CRC_CTRL +#define VPDPP_CRC_CTRL__VPDPP_CRC_EN_MASK 0x00000001UL +#define VPDPP_CRC_CTRL__VPDPP_CRC_CONT_EN_MASK 0x00000002UL +#define VPDPP_CRC_CTRL__VPDPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004UL +#define VPDPP_CRC_CTRL__VPDPP_CRC_420_COMP_SEL_MASK 0x00000008UL +#define VPDPP_CRC_CTRL__VPDPP_CRC_SRC_SEL_MASK 0x00000030UL +#define VPDPP_CRC_CTRL__VPDPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800UL +#define VPDPP_CRC_CTRL__VPDPP_CRC_MASK_MASK 0xffff0000UL + +// VPHOST_READ_CONTROL +#define VPHOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000ffUL + +// VPDPP_DEBUG_SEL +#define VPDPP_DEBUG_SEL__VPDPP_VPECLK_DEBUG_BUS_SEL_MASK 0x00000007UL +#define VPDPP_DEBUG_SEL__VPDPP_DBG_EN_MASK 0x80000000UL + +// VPDPP_DEBUG_SPARE +#define VPDPP_DEBUG_SPARE__VPDPP_DEBUG_SPARE_MASK 0xffffffffUL + +// VPDPP_TEST_DEBUG_INDEX +#define VPDPP_TEST_DEBUG_INDEX__VPDPP_TEST_DEBUG_INDEX_MASK 0x000000ffUL +#define VPDPP_TEST_DEBUG_INDEX__VPDPP_TEST_DEBUG_WRITE_EN_MASK 0x00000100UL + +// VPDPP_TEST_DEBUG_DATA +#define VPDPP_TEST_DEBUG_DATA__VPDPP_TEST_DEBUG_DATA_MASK 0xffffffffUL + +// VPMPC_CLOCK_CONTROL +#define VPMPC_CLOCK_CONTROL__VPECLK_G_GATE_DISABLE_MASK 0x00000001UL +#define VPMPC_CLOCK_CONTROL__VPECLK_R_GATE_DISABLE_MASK 0x00000002UL + +// VPMPC_SOFT_RESET +#define VPMPC_SOFT_RESET__VPMPCC0_SOFT_RESET_MASK 0x00000001UL +#define VPMPC_SOFT_RESET__VPMPCC1_SOFT_RESET_MASK 0x00000002UL +#define VPMPC_SOFT_RESET__VPMPC_SFR0_SOFT_RESET_MASK 0x00000400UL +#define VPMPC_SOFT_RESET__VPMPC_SFR1_SOFT_RESET_MASK 0x00000800UL +#define VPMPC_SOFT_RESET__VPMPC_SFT0_SOFT_RESET_MASK 0x00100000UL +#define VPMPC_SOFT_RESET__VPMPC_SFT1_SOFT_RESET_MASK 0x00200000UL +#define VPMPC_SOFT_RESET__VPMPC_SOFT_RESET_MASK 0x80000000UL + +// VPMPC_CRC_CTRL +#define VPMPC_CRC_CTRL__VPMPC_CRC_EN_MASK 0x00000001UL +#define VPMPC_CRC_CTRL__VPMPC_CRC_CONT_EN_MASK 0x00000010UL +#define VPMPC_CRC_CTRL__VPMPC_CRC_SRC_SEL_MASK 0x03000000UL +#define VPMPC_CRC_CTRL__VPMPC_CRC_ONE_SHOT_PENDING_MASK 0x10000000UL +#define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_ENABLED_MASK 0x40000000UL +#define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_LOCK_MASK 0x80000000UL + +// VPMPC_CRC_SEL_CONTROL +#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPDPP_SEL_MASK 0x0000000fUL +#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPOPP_SEL_MASK 0x000000f0UL +#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_MASK_MASK 0xffff0000UL + +// VPMPC_CRC_RESULT_AR +#define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_A_MASK 0x0000ffffUL +#define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_R_MASK 0xffff0000UL + +// VPMPC_CRC_RESULT_GB +#define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_G_MASK 0x0000ffffUL +#define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_B_MASK 0xffff0000UL + +// VPMPC_CRC_RESULT_C +#define VPMPC_CRC_RESULT_C__VPMPC_CRC_RESULT_C_MASK 0x0000ffffUL + +// VPMPC_DEBUG_CONTROL +#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_EN_MASK 0x00000001UL +#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_TOP_DATA_SELECT_MASK 0x00000006UL +#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_DIRECT_OUT_SELECT_MASK 0x00000070UL +#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_DIRECT_OUT_SFR_SELECT_MASK 0x00000f00UL +#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_DIRECT_OUT_SFT_SELECT_MASK 0x0000f000UL +#define VPMPC_DEBUG_CONTROL__VPMPC_RMCM_DEBUG_DATA_SELECT_MASK 0x00070000UL + +// VPMPCC_DEBUG_DATA_SELECT +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT0_MASK 0x0000000fUL +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT0_MASK 0x00000030UL +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT0_MASK 0x000000c0UL +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT1_MASK 0x00000f00UL +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT1_MASK 0x00003000UL +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT1_MASK 0x0000c000UL +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT2_MASK 0x000f0000UL +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT2_MASK 0x00300000UL +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT2_MASK 0x00c00000UL +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT3_MASK 0x0f000000UL +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT3_MASK 0x30000000UL +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT3_MASK 0xc0000000UL + +// VPMPC_BYPASS_BG_AR +#define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_ALPHA_MASK 0x0000ffffUL +#define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_R_CR_MASK 0xffff0000UL + +// VPMPC_BYPASS_BG_GB +#define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_G_Y_MASK 0x0000ffffUL +#define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_B_CB_MASK 0xffff0000UL + +// VPMPC_HOST_READ_CONTROL +#define VPMPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000ffUL + +// VPMPC_PENDING_STATUS_MISC +#define VPMPC_PENDING_STATUS_MISC__VPMPCC0_CONFIG_UPDATE_PENDING_MASK 0x00000100UL +#define VPMPC_PENDING_STATUS_MISC__VPMPCC1_CONFIG_UPDATE_PENDING_MASK 0x00000200UL + +// VPMPC_VPCDC0_3DLUT_FL_CONFIG +#define VPMPC_VPCDC0_3DLUT_FL_CONFIG__VPCDC0_3DLUT_FL_MODE_MASK 0x00000003UL +#define VPMPC_VPCDC0_3DLUT_FL_CONFIG__VPCDC0_3DLUT_FL_FORMAT_MASK 0x00000030UL + +// VPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE +#define VPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE__VPCDC0_3DLUT_FL_BIAS_MASK 0x0000ffffUL +#define VPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE__VPCDC0_3DLUT_FL_SCALE_MASK 0xffff0000UL + +// VPMPC_CFG_TEST_DEBUG_INDEX +#define VPMPC_CFG_TEST_DEBUG_INDEX__VPMPC_CFG_TEST_DEBUG_INDEX_MASK 0x000000ffUL +#define VPMPC_CFG_TEST_DEBUG_INDEX__VPMPC_CFG_TEST_DEBUG_WRITE_EN_MASK 0x00000100UL + +// VPMPC_CFG_TEST_DEBUG_DATA +#define VPMPC_CFG_TEST_DEBUG_DATA__VPMPC_CFG_TEST_DEBUG_DATA_MASK 0xffffffffUL + +// VPMPC_OUT0_MUX +#define VPMPC_OUT0_MUX__VPMPC_OUT_MUX_MASK 0x0000000fUL + +// VPMPC_OUT0_FLOAT_CONTROL +#define VPMPC_OUT0_FLOAT_CONTROL__VPMPC_OUT_FLOAT_EN_MASK 0x00000001UL + +// VPMPC_OUT0_DENORM_CONTROL +#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000fffUL +#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00fff000UL +#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_MODE_MASK 0x07000000UL + +// VPMPC_OUT0_DENORM_CLAMP_G_Y +#define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000fffUL +#define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00fff000UL + +// VPMPC_OUT0_DENORM_CLAMP_B_CB +#define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000fffUL +#define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00fff000UL + +// VPMPC_OUT1_MUX +#define VPMPC_OUT1_MUX__VPMPC_OUT_MUX_MASK 0x0000000fUL + +// VPMPC_OUT1_FLOAT_CONTROL +#define VPMPC_OUT1_FLOAT_CONTROL__VPMPC_OUT_FLOAT_EN_MASK 0x00000001UL + +// VPMPC_OUT1_DENORM_CONTROL +#define VPMPC_OUT1_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000fffUL +#define VPMPC_OUT1_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00fff000UL +#define VPMPC_OUT1_DENORM_CONTROL__VPMPC_OUT_DENORM_MODE_MASK 0x07000000UL + +// VPMPC_OUT1_DENORM_CLAMP_G_Y +#define VPMPC_OUT1_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000fffUL +#define VPMPC_OUT1_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00fff000UL + +// VPMPC_OUT1_DENORM_CLAMP_B_CB +#define VPMPC_OUT1_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000fffUL +#define VPMPC_OUT1_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00fff000UL + +// VPMPC_OUT_CSC_COEF_FORMAT +#define VPMPC_OUT_CSC_COEF_FORMAT__VPMPC_OCSC0_COEF_FORMAT_MASK 0x00000001UL +#define VPMPC_OUT_CSC_COEF_FORMAT__VPMPC_OCSC1_COEF_FORMAT_MASK 0x00000002UL + +// VPMPC_OUT0_CSC_MODE +#define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE_MASK 0x00000001UL +#define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE_CURRENT_MASK 0x00000080UL + +// VPMPC_OUT0_CSC_C11_C12_A +#define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C11_A_MASK 0x0000ffffUL +#define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C12_A_MASK 0xffff0000UL + +// VPMPC_OUT0_CSC_C13_C14_A +#define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C13_A_MASK 0x0000ffffUL +#define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C14_A_MASK 0xffff0000UL + +// VPMPC_OUT0_CSC_C21_C22_A +#define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C21_A_MASK 0x0000ffffUL +#define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C22_A_MASK 0xffff0000UL + +// VPMPC_OUT0_CSC_C23_C24_A +#define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C23_A_MASK 0x0000ffffUL +#define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C24_A_MASK 0xffff0000UL + +// VPMPC_OUT0_CSC_C31_C32_A +#define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C31_A_MASK 0x0000ffffUL +#define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C32_A_MASK 0xffff0000UL + +// VPMPC_OUT0_CSC_C33_C34_A +#define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C33_A_MASK 0x0000ffffUL +#define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C34_A_MASK 0xffff0000UL + +// VPMPC_OUT1_CSC_MODE +#define VPMPC_OUT1_CSC_MODE__VPMPC_OCSC_MODE_MASK 0x00000001UL +#define VPMPC_OUT1_CSC_MODE__VPMPC_OCSC_MODE_CURRENT_MASK 0x00000080UL + +// VPMPC_OUT1_CSC_C11_C12_A +#define VPMPC_OUT1_CSC_C11_C12_A__VPMPC_OCSC_C11_A_MASK 0x0000ffffUL +#define VPMPC_OUT1_CSC_C11_C12_A__VPMPC_OCSC_C12_A_MASK 0xffff0000UL + +// VPMPC_OUT1_CSC_C13_C14_A +#define VPMPC_OUT1_CSC_C13_C14_A__VPMPC_OCSC_C13_A_MASK 0x0000ffffUL +#define VPMPC_OUT1_CSC_C13_C14_A__VPMPC_OCSC_C14_A_MASK 0xffff0000UL + +// VPMPC_OUT1_CSC_C21_C22_A +#define VPMPC_OUT1_CSC_C21_C22_A__VPMPC_OCSC_C21_A_MASK 0x0000ffffUL +#define VPMPC_OUT1_CSC_C21_C22_A__VPMPC_OCSC_C22_A_MASK 0xffff0000UL + +// VPMPC_OUT1_CSC_C23_C24_A +#define VPMPC_OUT1_CSC_C23_C24_A__VPMPC_OCSC_C23_A_MASK 0x0000ffffUL +#define VPMPC_OUT1_CSC_C23_C24_A__VPMPC_OCSC_C24_A_MASK 0xffff0000UL + +// VPMPC_OUT1_CSC_C31_C32_A +#define VPMPC_OUT1_CSC_C31_C32_A__VPMPC_OCSC_C31_A_MASK 0x0000ffffUL +#define VPMPC_OUT1_CSC_C31_C32_A__VPMPC_OCSC_C32_A_MASK 0xffff0000UL + +// VPMPC_OUT1_CSC_C33_C34_A +#define VPMPC_OUT1_CSC_C33_C34_A__VPMPC_OCSC_C33_A_MASK 0x0000ffffUL +#define VPMPC_OUT1_CSC_C33_C34_A__VPMPC_OCSC_C34_A_MASK 0xffff0000UL + +// VPMPC_OCSC_TEST_DEBUG_INDEX +#define VPMPC_OCSC_TEST_DEBUG_INDEX__VPMPC_OCSC_TEST_DEBUG_INDEX_MASK 0x000000ffUL +#define VPMPC_OCSC_TEST_DEBUG_INDEX__VPMPC_OCSC_TEST_DEBUG_WRITE_EN_MASK 0x00000100UL + +// VPMPC_OCSC_TEST_DEBUG_DATA +#define VPMPC_OCSC_TEST_DEBUG_DATA__VPMPC_OCSC_TEST_DEBUG_DATA_MASK 0xffffffffUL + +// VPMPCC_TOP_SEL +#define VPMPCC_TOP_SEL__VPMPCC_TOP_SEL_MASK 0x0000000fUL + +// VPMPCC_BOT_SEL +#define VPMPCC_BOT_SEL__VPMPCC_BOT_SEL_MASK 0x0000000fUL + +// VPMPCC_VPOPP_ID +#define VPMPCC_VPOPP_ID__VPMPCC_VPOPP_ID_MASK 0x0000000fUL + +// VPMPCC_CONTROL +#define VPMPCC_CONTROL__VPMPCC_MODE_MASK 0x00000003UL +#define VPMPCC_CONTROL__VPMPCC_ALPHA_BLND_MODE_MASK 0x00000030UL +#define VPMPCC_CONTROL__VPMPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040UL +#define VPMPCC_CONTROL__VPMPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080UL +#define VPMPCC_CONTROL__VPMPCC_BOT_GAIN_MODE_MASK 0x00000800UL + +// VPMPCC_CONTROL2 +#define VPMPCC_CONTROL2__VPMPCC_GLOBAL_ALPHA_MASK 0x00000fffUL +#define VPMPCC_CONTROL2__VPMPCC_GLOBAL_GAIN_MASK 0x0fff0000UL + +// VPMPCC_TOP_GAIN +#define VPMPCC_TOP_GAIN__VPMPCC_TOP_GAIN_MASK 0x0007ffffUL + +// VPMPCC_BOT_GAIN_INSIDE +#define VPMPCC_BOT_GAIN_INSIDE__VPMPCC_BOT_GAIN_INSIDE_MASK 0x0007ffffUL + +// VPMPCC_BOT_GAIN_OUTSIDE +#define VPMPCC_BOT_GAIN_OUTSIDE__VPMPCC_BOT_GAIN_OUTSIDE_MASK 0x0007ffffUL + +// VPMPCC_MOVABLE_CM_LOCATION_CONTROL +#define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL_MASK 0x00000001UL +#define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK 0x00000010UL + +// VPMPCC_BG_R_CR +#define VPMPCC_BG_R_CR__VPMPCC_BG_R_CR_MASK 0x0007ffffUL + +// VPMPCC_BG_G_Y +#define VPMPCC_BG_G_Y__VPMPCC_BG_G_Y_MASK 0x0007ffffUL + +// VPMPCC_BG_B_CB +#define VPMPCC_BG_B_CB__VPMPCC_BG_B_CB_MASK 0x0007ffffUL + +// VPMPCC_MEM_PWR_CTRL +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003UL +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004UL +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030UL +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300UL + +// VPMPCC_STATUS +#define VPMPCC_STATUS__VPMPCC_IDLE_MASK 0x00000001UL +#define VPMPCC_STATUS__VPMPCC_BUSY_MASK 0x00000002UL +#define VPMPCC_STATUS__VPMPCC_DISABLED_MASK 0x00000004UL + +// VPMPCC_TEST_DEBUG_INDEX +#define VPMPCC_TEST_DEBUG_INDEX__VPMPCC_TEST_DEBUG_INDEX_MASK 0x000000ffUL +#define VPMPCC_TEST_DEBUG_INDEX__VPMPCC_TEST_DEBUG_WRITE_EN_MASK 0x00000100UL + +// VPMPCC_TEST_DEBUG_DATA +#define VPMPCC_TEST_DEBUG_DATA__VPMPCC_TEST_DEBUG_DATA_MASK 0xffffffffUL + +// VPMPCC_OGAM_CONTROL +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE_MASK 0x00000003UL +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_PWL_DISABLE_MASK 0x00000008UL +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE_CURRENT_MASK 0x00000180UL +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_SELECT_CURRENT_MASK 0x00000200UL + +// VPMPCC_OGAM_LUT_INDEX +#define VPMPCC_OGAM_LUT_INDEX__VPMPCC_OGAM_LUT_INDEX_MASK 0x000001ffUL + +// VPMPCC_OGAM_LUT_DATA +#define VPMPCC_OGAM_LUT_DATA__VPMPCC_OGAM_LUT_DATA_MASK 0x0003ffffUL + +// VPMPCC_OGAM_LUT_CONTROL +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007UL +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018UL +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_DBG_MASK 0x00000020UL +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040UL +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080UL + +// VPMPCC_OGAM_RAMA_START_CNTL_B +#define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003ffffUL +#define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07f00000UL + +// VPMPCC_OGAM_RAMA_START_CNTL_G +#define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003ffffUL +#define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07f00000UL + +// VPMPCC_OGAM_RAMA_START_CNTL_R +#define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003ffffUL +#define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07f00000UL + +// VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003ffffUL + +// VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003ffffUL + +// VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003ffffUL + +// VPMPCC_OGAM_RAMA_START_BASE_CNTL_B +#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003ffffUL + +// VPMPCC_OGAM_RAMA_START_BASE_CNTL_G +#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003ffffUL + +// VPMPCC_OGAM_RAMA_START_BASE_CNTL_R +#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003ffffUL + +// VPMPCC_OGAM_RAMA_END_CNTL1_B +#define VPMPCC_OGAM_RAMA_END_CNTL1_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003ffffUL + +// VPMPCC_OGAM_RAMA_END_CNTL2_B +#define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000ffffUL +#define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xffff0000UL + +// VPMPCC_OGAM_RAMA_END_CNTL1_G +#define VPMPCC_OGAM_RAMA_END_CNTL1_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003ffffUL + +// VPMPCC_OGAM_RAMA_END_CNTL2_G +#define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000ffffUL +#define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xffff0000UL + +// VPMPCC_OGAM_RAMA_END_CNTL1_R +#define VPMPCC_OGAM_RAMA_END_CNTL1_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003ffffUL + +// VPMPCC_OGAM_RAMA_END_CNTL2_R +#define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000ffffUL +#define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xffff0000UL + +// VPMPCC_OGAM_RAMA_OFFSET_B +#define VPMPCC_OGAM_RAMA_OFFSET_B__VPMPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007ffffUL + +// VPMPCC_OGAM_RAMA_OFFSET_G +#define VPMPCC_OGAM_RAMA_OFFSET_G__VPMPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007ffffUL + +// VPMPCC_OGAM_RAMA_OFFSET_R +#define VPMPCC_OGAM_RAMA_OFFSET_R__VPMPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007ffffUL + +// VPMPCC_OGAM_RAMA_REGION_0_1 +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_2_3 +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_4_5 +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_6_7 +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_8_9 +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_10_11 +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_12_13 +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_14_15 +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_16_17 +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_18_19 +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_20_21 +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_22_23 +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_24_25 +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_26_27 +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_28_29 +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_30_31 +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_32_33 +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_GAMUT_REMAP_COEF_FORMAT +#define VPMPCC_GAMUT_REMAP_COEF_FORMAT__VPMPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001UL + +// VPMPCC_GAMUT_REMAP_MODE +#define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE_MASK 0x00000001UL +#define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000080UL + +// VPMPC_GAMUT_REMAP_C11_C12_A +#define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C11_A_MASK 0x0000ffffUL +#define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C12_A_MASK 0xffff0000UL + +// VPMPC_GAMUT_REMAP_C13_C14_A +#define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C13_A_MASK 0x0000ffffUL +#define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C14_A_MASK 0xffff0000UL + +// VPMPC_GAMUT_REMAP_C21_C22_A +#define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C21_A_MASK 0x0000ffffUL +#define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C22_A_MASK 0xffff0000UL + +// VPMPC_GAMUT_REMAP_C23_C24_A +#define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C23_A_MASK 0x0000ffffUL +#define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C24_A_MASK 0xffff0000UL + +// VPMPC_GAMUT_REMAP_C31_C32_A +#define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C31_A_MASK 0x0000ffffUL +#define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C32_A_MASK 0xffff0000UL + +// VPMPC_GAMUT_REMAP_C33_C34_A +#define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C33_A_MASK 0x0000ffffUL +#define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C34_A_MASK 0xffff0000UL + +// VPMPCC_OGAM_TEST_DEBUG_INDEX +#define VPMPCC_OGAM_TEST_DEBUG_INDEX__VPMPCC_OGAM_TEST_DEBUG_INDEX_MASK 0x000000ffUL +#define VPMPCC_OGAM_TEST_DEBUG_INDEX__VPMPCC_OGAM_TEST_DEBUG_WRITE_EN_MASK 0x00000100UL + +// VPMPCC_OGAM_TEST_DEBUG_DATA +#define VPMPCC_OGAM_TEST_DEBUG_DATA__VPMPCC_OGAM_TEST_DEBUG_DATA_MASK 0xffffffffUL + +// VPMPCC_MCM_1DLUT_CONTROL +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE_MASK 0x00000003UL +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_PWL_DISABLE_MASK 0x00000008UL +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE_CURRENT_MASK 0x00000030UL +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_SELECT_CURRENT_MASK 0x00000040UL + +// VPMPCC_MCM_1DLUT_LUT_INDEX +#define VPMPCC_MCM_1DLUT_LUT_INDEX__VPMPCC_MCM_1DLUT_LUT_INDEX_MASK 0x000001ffUL + +// VPMPCC_MCM_1DLUT_LUT_DATA +#define VPMPCC_MCM_1DLUT_LUT_DATA__VPMPCC_MCM_1DLUT_LUT_DATA_MASK 0x0003ffffUL + +// VPMPCC_MCM_1DLUT_LUT_CONTROL +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK 0x00000007UL +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK 0x00000018UL +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_DBG_MASK 0x00000020UL +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_HOST_SEL_MASK 0x00000040UL +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK 0x00000080UL + +// VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK 0x0003ffffUL +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07f00000UL + +// VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK 0x0003ffffUL +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07f00000UL + +// VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK 0x0003ffffUL +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07f00000UL + +// VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B +#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G +#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R +#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B +#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G +#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R +#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK 0x0000ffffUL +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xffff0000UL + +// VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK 0x0000ffffUL +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xffff0000UL + +// VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK 0x0000ffffUL +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xffff0000UL + +// VPMPCC_MCM_1DLUT_RAMA_OFFSET_B +#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_B__VPMPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK 0x0007ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_OFFSET_G +#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_G__VPMPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK 0x0007ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_OFFSET_R +#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_R__VPMPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK 0x0007ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_0_1 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_2_3 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_4_5 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_6_7 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_8_9 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_10_11 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_12_13 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_14_15 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_16_17 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_18_19 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_20_21 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_22_23 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_24_25 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_26_27 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_28_29 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_30_31 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_32_33 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT +#define VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001UL + +// VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE +#define VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE__VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE_MASK 0x00000003UL +#define VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE__VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180UL + +// VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C11_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C12_SETA_MASK 0xffff0000UL + +// VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C13_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C14_SETA_MASK 0xffff0000UL + +// VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C21_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C22_SETA_MASK 0xffff0000UL + +// VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C23_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C24_SETA_MASK 0xffff0000UL + +// VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C31_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C32_SETA_MASK 0xffff0000UL + +// VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C33_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C34_SETA_MASK 0xffff0000UL + +// VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT +#define VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001UL + +// VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE +#define VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE__VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE_MASK 0x00000003UL +#define VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE__VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180UL + +// VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C11_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C12_SETA_MASK 0xffff0000UL + +// VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C13_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C14_SETA_MASK 0xffff0000UL + +// VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C21_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C22_SETA_MASK 0xffff0000UL + +// VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C23_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C24_SETA_MASK 0xffff0000UL + +// VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C31_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C32_SETA_MASK 0xffff0000UL + +// VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C33_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C34_SETA_MASK 0xffff0000UL + +// VPMPCC_MCM_MEM_PWR_CTRL +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK 0x00030000UL +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_DIS_MASK 0x00040000UL +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK 0x00300000UL +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_STATE_MASK 0x30000000UL + +// VPMPCC_MCM_TEST_DEBUG_INDEX +#define VPMPCC_MCM_TEST_DEBUG_INDEX__VPMPCC_MCM_TEST_DEBUG_INDEX_MASK 0x000000ffUL +#define VPMPCC_MCM_TEST_DEBUG_INDEX__VPMPCC_MCM_TEST_DEBUG_WRITE_EN_MASK 0x00000100UL + +// VPMPCC_MCM_TEST_DEBUG_DATA +#define VPMPCC_MCM_TEST_DEBUG_DATA__VPMPCC_MCM_TEST_DEBUG_DATA_MASK 0xffffffffUL + +// VPMPC_RMCM_SHAPER_CONTROL +#define VPMPC_RMCM_SHAPER_CONTROL__VPMPC_RMCM_SHAPER_LUT_MODE_MASK 0x00000003UL +#define VPMPC_RMCM_SHAPER_CONTROL__VPMPC_RMCM_SHAPER_MODE_CURRENT_MASK 0x0000000cUL +#define VPMPC_RMCM_SHAPER_CONTROL__VPMPC_RMCM_SHAPER_SELECT_CURRENT_MASK 0x00000010UL + +// VPMPC_RMCM_SHAPER_OFFSET_R +#define VPMPC_RMCM_SHAPER_OFFSET_R__VPMPC_RMCM_SHAPER_OFFSET_R_MASK 0x0007ffffUL + +// VPMPC_RMCM_SHAPER_OFFSET_G +#define VPMPC_RMCM_SHAPER_OFFSET_G__VPMPC_RMCM_SHAPER_OFFSET_G_MASK 0x0007ffffUL + +// VPMPC_RMCM_SHAPER_OFFSET_B +#define VPMPC_RMCM_SHAPER_OFFSET_B__VPMPC_RMCM_SHAPER_OFFSET_B_MASK 0x0007ffffUL + +// VPMPC_RMCM_SHAPER_SCALE_R +#define VPMPC_RMCM_SHAPER_SCALE_R__VPMPC_RMCM_SHAPER_SCALE_R_MASK 0x0000ffffUL + +// VPMPC_RMCM_SHAPER_SCALE_G_B +#define VPMPC_RMCM_SHAPER_SCALE_G_B__VPMPC_RMCM_SHAPER_SCALE_G_MASK 0x0000ffffUL +#define VPMPC_RMCM_SHAPER_SCALE_G_B__VPMPC_RMCM_SHAPER_SCALE_B_MASK 0xffff0000UL + +// VPMPC_RMCM_SHAPER_LUT_INDEX +#define VPMPC_RMCM_SHAPER_LUT_INDEX__VPMPC_RMCM_SHAPER_LUT_INDEX_MASK 0x000000ffUL + +// VPMPC_RMCM_SHAPER_LUT_DATA +#define VPMPC_RMCM_SHAPER_LUT_DATA__VPMPC_RMCM_SHAPER_LUT_DATA_MASK 0x00ffffffUL + +// VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK +#define VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007UL +#define VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__VPMPC_RMCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010UL + +// VPMPC_RMCM_SHAPER_RAMA_START_CNTL_B +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003ffffUL +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07f00000UL + +// VPMPC_RMCM_SHAPER_RAMA_START_CNTL_G +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003ffffUL +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07f00000UL + +// VPMPC_RMCM_SHAPER_RAMA_START_CNTL_R +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003ffffUL +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07f00000UL + +// VPMPC_RMCM_SHAPER_RAMA_END_CNTL_B +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000ffffUL +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3fff0000UL + +// VPMPC_RMCM_SHAPER_RAMA_END_CNTL_G +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000ffffUL +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3fff0000UL + +// VPMPC_RMCM_SHAPER_RAMA_END_CNTL_R +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000ffffUL +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3fff0000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_0_1 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_2_3 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_4_5 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_6_7 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_8_9 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_10_11 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_12_13 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_14_15 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_16_17 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_18_19 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_20_21 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_22_23 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_24_25 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_26_27 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_28_29 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_30_31 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_32_33 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_3DLUT_MODE +#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_MODE_MASK 0x00000003UL +#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_SIZE_MASK 0x00000030UL +#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_MODE_CURRENT_MASK 0x00000300UL +#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_SELECT_CURRENT_MASK 0x00000400UL + +// VPMPC_RMCM_3DLUT_INDEX +#define VPMPC_RMCM_3DLUT_INDEX__VPMPC_RMCM_3DLUT_INDEX_MASK 0x00003fffUL + +// VPMPC_RMCM_3DLUT_DATA +#define VPMPC_RMCM_3DLUT_DATA__VPMPC_RMCM_3DLUT_DATA0_MASK 0x0000ffffUL +#define VPMPC_RMCM_3DLUT_DATA__VPMPC_RMCM_3DLUT_DATA1_MASK 0xffff0000UL + +// VPMPC_RMCM_3DLUT_DATA_30BIT +#define VPMPC_RMCM_3DLUT_DATA_30BIT__VPMPC_RMCM_3DLUT_DATA_30BIT_MASK 0xfffffffcUL + +// VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL +#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000fUL +#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_RAM_SEL_MASK 0x00000010UL +#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_30BIT_EN_MASK 0x00000100UL +#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_READ_SEL_MASK 0x00030000UL + +// VPMPC_RMCM_3DLUT_OUT_NORM_FACTOR +#define VPMPC_RMCM_3DLUT_OUT_NORM_FACTOR__VPMPC_RMCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000ffffUL + +// VPMPC_RMCM_3DLUT_OUT_OFFSET_R +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_R__VPMPC_RMCM_3DLUT_OUT_OFFSET_R_MASK 0x0000ffffUL +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_R__VPMPC_RMCM_3DLUT_OUT_SCALE_R_MASK 0xffff0000UL + +// VPMPC_RMCM_3DLUT_OUT_OFFSET_G +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_G__VPMPC_RMCM_3DLUT_OUT_OFFSET_G_MASK 0x0000ffffUL +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_G__VPMPC_RMCM_3DLUT_OUT_SCALE_G_MASK 0xffff0000UL + +// VPMPC_RMCM_3DLUT_OUT_OFFSET_B +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_B__VPMPC_RMCM_3DLUT_OUT_OFFSET_B_MASK 0x0000ffffUL +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_B__VPMPC_RMCM_3DLUT_OUT_SCALE_B_MASK 0xffff0000UL + +// VPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT +#define VPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT__VPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001UL + +// VPMPC_RMCM_GAMUT_REMAP_MODE +#define VPMPC_RMCM_GAMUT_REMAP_MODE__VPMPC_RMCM_GAMUT_REMAP_MODE_MASK 0x00000003UL +#define VPMPC_RMCM_GAMUT_REMAP_MODE__VPMPC_RMCM_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180UL + +// VPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA +#define VPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA__VPMPC_RMCM_GAMUT_REMAP_C11_SETA_MASK 0x0000ffffUL +#define VPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA__VPMPC_RMCM_GAMUT_REMAP_C12_SETA_MASK 0xffff0000UL + +// VPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA +#define VPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA__VPMPC_RMCM_GAMUT_REMAP_C13_SETA_MASK 0x0000ffffUL +#define VPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA__VPMPC_RMCM_GAMUT_REMAP_C14_SETA_MASK 0xffff0000UL + +// VPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA +#define VPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA__VPMPC_RMCM_GAMUT_REMAP_C21_SETA_MASK 0x0000ffffUL +#define VPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA__VPMPC_RMCM_GAMUT_REMAP_C22_SETA_MASK 0xffff0000UL + +// VPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA +#define VPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA__VPMPC_RMCM_GAMUT_REMAP_C23_SETA_MASK 0x0000ffffUL +#define VPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA__VPMPC_RMCM_GAMUT_REMAP_C24_SETA_MASK 0xffff0000UL + +// VPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA +#define VPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA__VPMPC_RMCM_GAMUT_REMAP_C31_SETA_MASK 0x0000ffffUL +#define VPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA__VPMPC_RMCM_GAMUT_REMAP_C32_SETA_MASK 0xffff0000UL + +// VPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA +#define VPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA__VPMPC_RMCM_GAMUT_REMAP_C33_SETA_MASK 0x0000ffffUL +#define VPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA__VPMPC_RMCM_GAMUT_REMAP_C34_SETA_MASK 0xffff0000UL + +// VPMPC_RMCM_MEM_PWR_CTRL +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003UL +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004UL +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030UL +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300UL +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400UL +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000UL +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000UL +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_PWR_STATE_MASK 0x0c000000UL + +// VPMPC_RMCM_3DLUT_FAST_LOAD_SELECT +#define VPMPC_RMCM_3DLUT_FAST_LOAD_SELECT__VPMPC_RMCM_3DLUT_FL_SEL_MASK 0x0000000fUL + +// VPMPC_RMCM_3DLUT_FAST_LOAD_STATUS +#define VPMPC_RMCM_3DLUT_FAST_LOAD_STATUS__VPMPC_RMCM_3DLUT_FL_DONE_MASK 0x00000001UL + +// VPMPC_RMCM_CNTL +#define VPMPC_RMCM_CNTL__VPMPC_RMCM_CNTL_MASK 0x0000000fUL + +// VPMPC_RMCM_TEST_DEBUG_INDEX +#define VPMPC_RMCM_TEST_DEBUG_INDEX__VPMPC_RMCM_TEST_DEBUG_INDEX_MASK 0x000000ffUL +#define VPMPC_RMCM_TEST_DEBUG_INDEX__VPMPC_RMCM_TEST_DEBUG_WRITE_EN_MASK 0x00000100UL + +// VPMPC_RMCM_TEST_DEBUG_DATA +#define VPMPC_RMCM_TEST_DEBUG_DATA__VPMPC_RMCM_TEST_DEBUG_DATA_MASK 0xffffffffUL + +// VPFMT_CLAMP_COMPONENT_R +#define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_LOWER_R_MASK 0x0000ffffUL +#define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_UPPER_R_MASK 0xffff0000UL + +// VPFMT_CLAMP_COMPONENT_G +#define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_LOWER_G_MASK 0x0000ffffUL +#define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_UPPER_G_MASK 0xffff0000UL + +// VPFMT_CLAMP_COMPONENT_B +#define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_LOWER_B_MASK 0x0000ffffUL +#define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_UPPER_B_MASK 0xffff0000UL + +// VPFMT_DYNAMIC_EXP_CNTL +#define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_EN_MASK 0x00000001UL +#define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_MODE_MASK 0x00000010UL + +// VPFMT_CONTROL +#define VPFMT_CONTROL__VPFMT_PIXEL_ENCODING_MASK 0x00000003UL +#define VPFMT_CONTROL__VPFMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00000010UL +#define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000f00UL +#define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000UL +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_HTAPS_MASK 0x00030000UL +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_LEFT_EDGE_MASK 0x00040000UL +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_RIGHT_EDGE_MASK 0x00080000UL +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_VTAPS_MASK 0x00300000UL +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_TOP_EDGE_MASK 0x00400000UL +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_BOTTOM_EDGE_MASK 0x00800000UL +#define VPFMT_CONTROL__VPFMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000UL + +// VPFMT_BIT_DEPTH_CONTROL +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_EN_MASK 0x00000001UL +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_MODE_MASK 0x00000002UL +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_DEPTH_MASK 0x00000030UL +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_EN_MASK 0x00000100UL +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_MODE_MASK 0x00000600UL +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800UL +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_FRAME_RANDOM_ENABLE_MASK 0x00002000UL +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_RGB_RANDOM_ENABLE_MASK 0x00004000UL +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000UL + +// VPFMT_DITHER_RAND_R_SEED +#define VPFMT_DITHER_RAND_R_SEED__VPFMT_RAND_R_SEED_MASK 0x000000ffUL +#define VPFMT_DITHER_RAND_R_SEED__VPFMT_OFFSET_R_CR_MASK 0xffff0000UL + +// VPFMT_DITHER_RAND_G_SEED +#define VPFMT_DITHER_RAND_G_SEED__VPFMT_RAND_G_SEED_MASK 0x000000ffUL +#define VPFMT_DITHER_RAND_G_SEED__VPFMT_OFFSET_G_Y_MASK 0xffff0000UL + +// VPFMT_DITHER_RAND_B_SEED +#define VPFMT_DITHER_RAND_B_SEED__VPFMT_RAND_B_SEED_MASK 0x000000ffUL +#define VPFMT_DITHER_RAND_B_SEED__VPFMT_OFFSET_B_CB_MASK 0xffff0000UL + +// VPFMT_CLAMP_CNTL +#define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_DATA_EN_MASK 0x00000001UL +#define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_COLOR_FORMAT_MASK 0x00070000UL + +// VPFMT_SUBSAMPLER_MEMORY_CONTROL +#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_SUBSAMPLER_MEM_PWR_FORCE_MASK 0x00000003UL +#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_SUBSAMPLER_MEM_PWR_DIS_MASK 0x00000010UL +#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_SUBSAMPLER_MEM_PWR_STATE_MASK 0x00000300UL +#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000UL + +// VPFMT_DEBUG_CNTL +#define VPFMT_DEBUG_CNTL__VPFMT_DEBUG_COLOR_SELECT_MASK 0x00000003UL + +// VPFMT_TEST_DEBUG_INDEX +#define VPFMT_TEST_DEBUG_INDEX__VPFMT_TEST_DEBUG_INDEX_MASK 0x000000ffUL +#define VPFMT_TEST_DEBUG_INDEX__VPFMT_TEST_DEBUG_WRITE_EN_MASK 0x00000100UL + +// VPFMT_TEST_DEBUG_DATA +#define VPFMT_TEST_DEBUG_DATA__VPFMT_TEST_DEBUG_DATA_MASK 0xffffffffUL + +// VPOPP_PIPE_CONTROL +#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_CLOCK_ON_MASK 0x00000002UL +#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010UL +#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_ALPHA_SEL_MASK 0x00000020UL +#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_ALPHA_MASK 0xffff0000UL + +// VPOPP_PIPE_OUTBG_EXT1 +#define VPOPP_PIPE_OUTBG_EXT1__OUTBG_EXT_TOP_MASK 0x00003fffUL +#define VPOPP_PIPE_OUTBG_EXT1__OUTBG_EXT_BOT_MASK 0x0fffc000UL + +// VPOPP_PIPE_OUTBG_EXT2 +#define VPOPP_PIPE_OUTBG_EXT2__OUTBG_EXT_LEFT_MASK 0x000007ffUL +#define VPOPP_PIPE_OUTBG_EXT2__OUTBG_EXT_RIGHT_MASK 0x003ff800UL + +// VPOPP_PIPE_OUTBG_COL1 +#define VPOPP_PIPE_OUTBG_COL1__OUTBG_R_CR_MASK 0x0000ffffUL +#define VPOPP_PIPE_OUTBG_COL1__OUTBG_B_CB_MASK 0xffff0000UL + +// VPOPP_PIPE_OUTBG_COL2 +#define VPOPP_PIPE_OUTBG_COL2__OUTBG_Y_MASK 0x0000ffffUL + +// VPOPP_PIPE_SPARE_DEBUG +#define VPOPP_PIPE_SPARE_DEBUG__VPOPP_PIPE_SPARE_DEBUG_MASK 0xffffffffUL + +// VPOPP_PIPE_TEST_DEBUG_INDEX +#define VPOPP_PIPE_TEST_DEBUG_INDEX__VPOPP_PIPE_TEST_DEBUG_INDEX_MASK 0x000000ffUL + +// VPOPP_PIPE_TEST_DEBUG_DATA +#define VPOPP_PIPE_TEST_DEBUG_DATA__VPOPP_PIPE_TEST_DEBUG_DATA_MASK 0xffffffffUL + +// VPOPP_TOP_CLK_CONTROL +#define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_R_GATE_DIS_MASK 0x00000001UL +#define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_G_GATE_DIS_MASK 0x00000002UL + +// VPOPP_DEBUG_CONTROL +#define VPOPP_DEBUG_CONTROL__VPOPP_DBG_EN_MASK 0x00000001UL +#define VPOPP_DEBUG_CONTROL__VPOPP_VPFMT_DEBUG_BUS_SELECT_MASK 0x000000f0UL +#define VPOPP_DEBUG_CONTROL__VPOPP_VPOPP_PIPE_DEBUG_BUS_SELECT_MASK 0x00070000UL + +// VPOPP_CRC_CONTROL +#define VPOPP_CRC_CONTROL__VPOPP_CRC_EN_MASK 0x00000001UL +#define VPOPP_CRC_CONTROL__VPOPP_CRC_CONT_EN_MASK 0x00000002UL +#define VPOPP_CRC_CONTROL__VPOPP_CRC_PIXEL_SELECT_MASK 0x0000000cUL +#define VPOPP_CRC_CONTROL__VPOPP_CRC_SOURCE_SELECT_MASK 0x00000030UL +#define VPOPP_CRC_CONTROL__VPOPP_CRC_PIPE_SELECT_MASK 0x00000040UL +#define VPOPP_CRC_CONTROL__VPOPP_CRC_MASK_MASK 0x00ffff00UL +#define VPOPP_CRC_CONTROL__VPOPP_CRC_ONE_SHOT_PENDING_MASK 0x80000000UL + +// VPOPP_CRC_RESULT_RG +#define VPOPP_CRC_RESULT_RG__VPOPP_CRC_RESULT_R_MASK 0x0000ffffUL +#define VPOPP_CRC_RESULT_RG__VPOPP_CRC_RESULT_G_MASK 0xffff0000UL + +// VPOPP_CRC_RESULT_BC +#define VPOPP_CRC_RESULT_BC__VPOPP_CRC_RESULT_B_MASK 0x0000ffffUL +#define VPOPP_CRC_RESULT_BC__VPOPP_CRC_RESULT_C_MASK 0xffff0000UL + +// VPOPP_FROD_CONTROL +#define VPOPP_FROD_CONTROL__FROD_EN_MASK 0x00000001UL + +// VPOPP_FROD_MEM_PWR_CONTROL +#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_PWR_FORCE_MASK 0x00000003UL +#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_PWR_DIS_MASK 0x00000010UL +#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_PWR_STATE_MASK 0x00000300UL +#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_DEFAULT_LOW_PWR_STATE_MASK 0x00003000UL + +// VPOPP_TOP_SPARE_DEBUG +#define VPOPP_TOP_SPARE_DEBUG__VPOPP_TOP_SPARE_DEBUG_MASK 0xffffffffUL + +// VPOPP_TOP_TEST_DEBUG_INDEX +#define VPOPP_TOP_TEST_DEBUG_INDEX__VPOPP_TOP_TEST_DEBUG_INDEX_MASK 0x000000ffUL + +// VPOPP_TOP_TEST_DEBUG_DATA +#define VPOPP_TOP_TEST_DEBUG_DATA__VPOPP_TOP_TEST_DEBUG_DATA_MASK 0xffffffffUL + +#endif diff --git a/src/amd/vpelib/src/chip/vpe20/inc/asic/chip_offset.h b/src/amd/vpelib/src/chip/vpe20/inc/asic/chip_offset.h new file mode 100644 index 00000000000..9c1b15dd783 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/inc/asic/chip_offset.h @@ -0,0 +1,1795 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef _vpe20_chip_OFFSET_HEADER +#define _vpe20_chip_OFFSET_HEADER + +// Registers from VPEC block + +#define mmVPEC_DEC_START 0x11800 +#define mmVPEC_UCODE_ADDR 0x11801 +#define mmVPEC_UCODE_DATA 0x11802 +#define mmVPEC_F32_CNTL 0x11803 +#define mmVPEC_MMHUB_CNTL 0x11804 +#define mmVPEC_MMHUB_TRUSTLVL 0x11805 +#define mmVPEC_VPEP_CTRL 0x11810 +#define mmVPEC_CLK_CTRL 0x11811 +#define mmVPEC_COLLABORATE_CNTL 0x11812 +#define mmVPEC_COLLABORATE_CFG 0x11813 +#define mmVPEC_POWER_CNTL 0x11814 +#define mmVPEC_ZPR_CNTL 0x11815 +#define mmVPEC_CNTL 0x11816 +#define mmVPEC_CNTL_DCC 0x11817 +#define mmVPEC_CE_OP_MULTI_64B_BURST 0x11818 +#define mmVPEC_CNTL1 0x11819 +#define mmVPEC_CNTL2 0x1181A +#define mmVPEC_GB_ADDR_CONFIG 0x1181B +#define mmVPEC_GB_ADDR_CONFIG_READ 0x1181C +#define mmVPEC_GB_ADDR_CONFIG_META 0x1181D +#define mmVPEC_PROCESS_QUANTUM0 0x1181E +#define mmVPEC_PROCESS_QUANTUM1 0x1181F +#define mmVPEC_CONTEXT_SWITCH_THRESHOLD 0x11820 +#define mmVPEC_GLOBAL_QUANTUM 0x11821 +#define mmVPEC_HWE_MASK 0x11822 +#define mmVPEC_HWE_SRC_DST_TABLE0 0x11823 +#define mmVPEC_HWE_SRC_DST_TABLE1 0x11824 +#define mmVPEC_WATCHDOG_CNTL 0x11825 +#define mmVPEC_ATOMIC_CNTL 0x11826 +#define mmVPEC_UCODE_VERSION 0x11827 +#define mmVPEC_MEMREQ_BURST_CNTL 0x11828 +#define mmVPEC_TIMESTAMP_CNTL 0x11829 +#define mmVPEC_GLOBAL_TIMESTAMP_LO 0x1182A +#define mmVPEC_GLOBAL_TIMESTAMP_HI 0x1182B +#define mmVPEC_FREEZE 0x1182C +#define mmVPEC_CE_CTRL 0x1182D +#define mmVPEC_RELAX_ORDERING_LUT 0x1182E +#define mmVPEC_CREDIT_CNTL 0x1182F +#define mmVPEC_SCRATCH_RAM_DATA 0x11830 +#define mmVPEC_SCRATCH_RAM_ADDR 0x11831 +#define mmVPEC_QUEUE_RESET_REQ 0x11832 +#define mmVPEC_PERFCNT_PERFCOUNTER0_CFG 0x11833 +#define mmVPEC_PERFCNT_PERFCOUNTER1_CFG 0x11834 +#define mmVPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x11835 +#define mmVPEC_PERFCNT_MISC_CNTL 0x11836 +#define mmVPEC_PERFCNT_PERFCOUNTER_LO 0x11837 +#define mmVPEC_PERFCNT_PERFCOUNTER_HI 0x11838 +#define mmVPEC_DEBUG_INDEX 0x11839 +#define mmVPEC_DEBUG_DATA 0x1183A +#define mmVPEC_CRC_CNTL 0x1183B +#define mmVPEC_CRC_INDEX 0x1183C +#define mmVPEC_CRC_DATA0 0x1183D +#define mmVPEC_CRC_DATA1 0x1183E +#define mmVPEC_CRC_DATA2 0x1183F +#define mmVPEC_MAILBOX0 0x11840 +#define mmVPEC_MAILBOX1 0x11841 +#define mmVPEC_MAILBOX2 0x11842 +#define mmVPEC_MAILBOX3 0x11843 +#define mmVPEC_MAILBOX4 0x11844 +#define mmVPEC_MAILBOX5 0x11845 +#define mmVPEC_MAILBOX6 0x11846 +#define mmVPEC_MAILBOX7 0x11847 +#define mmVPEC_MAILBOX8 0x11848 +#define mmVPEC_MAILBOX9 0x11849 +#define mmVPEC_MAILBOX10 0x1184A +#define mmVPEC_MAILBOX11 0x1184B +#define mmVPEC_MAILBOX12 0x1184C +#define mmVPEC_MAILBOX13 0x1184D +#define mmVPEC_MAILBOX14 0x1184E +#define mmVPEC_MAILBOX15 0x1184F +#define mmVPEC_PUB_DUMMY0 0x11850 +#define mmVPEC_PUB_DUMMY1 0x11851 +#define mmVPEC_PUB_DUMMY2 0x11852 +#define mmVPEC_PUB_DUMMY3 0x11853 +#define mmVPEC_PUB_DUMMY4 0x11854 +#define mmVPEC_PUB_DUMMY5 0x11855 +#define mmVPEC_PUB_DUMMY6 0x11856 +#define mmVPEC_PUB_DUMMY7 0x11857 +#define mmVPEC_PUB_DUMMY8 0x11858 +#define mmVPEC_PUB_DUMMY9 0x11859 +#define mmVPEC_PUB_DUMMY10 0x1185A +#define mmVPEC_PUB_DUMMY11 0x1185B +#define mmVPEC_UCODE1_CHECKSUM 0x1185C +#define mmVPEC_VERSION 0x1185D +#define mmVPEC_UCODE_CHECKSUM 0x1185E +#define mmVPEC_RB_RPTR_FETCH 0x1185F +#define mmVPEC_RB_RPTR_FETCH_HI 0x11860 +#define mmVPEC_IB_OFFSET_FETCH 0x11861 +#define mmVPEC_CMDIB_OFFSET_FETCH 0x11862 +#define mmVPEC_3DLUTIB_OFFSET_FETCH 0x11863 +#define mmVPEC_ATOMIC_PREOP_LO 0x11864 +#define mmVPEC_ATOMIC_PREOP_HI 0x11865 +#define mmVPEC_CE_BUSY 0x11866 +#define mmVPEC_F32_COUNTER 0x11867 +#define mmVPEC_HOLE_ADDR_LO 0x11868 +#define mmVPEC_HOLE_ADDR_HI 0x11869 +#define mmVPEC_ERROR_LOG 0x1186A +#define mmVPEC_INT_STATUS 0x1186B +#define mmVPEC_STATUS 0x1186C +#define mmVPEC_STATUS1 0x1186D +#define mmVPEC_STATUS2 0x1186E +#define mmVPEC_STATUS3 0x1186F +#define mmVPEC_STATUS4 0x11870 +#define mmVPEC_STATUS5 0x11871 +#define mmVPEC_STATUS6 0x11872 +#define mmVPEC_STATUS7 0x11873 +#define mmVPEC_STATUS8 0x11874 +#define mmVPEC_STATUS9 0x11875 +#define mmVPEC_STATUS10 0x11876 +#define mmVPEC_STATUS_DCC 0x11877 +#define mmVPEC_STATUS11 0x11878 +#define mmVPEC_INST 0x11879 +#define mmVPEC_QUEUE_STATUS0 0x1187A +#define mmVPEC_QUEUE_HANG_STATUS 0x1187B +#define mmVPEC_DPM_IDLE_TIME 0x1187C +#define mmVPEC_DPM_BUSY_TIME 0x1187D +#define mmVPEC_DPM_IDLE_START_LO 0x1187E +#define mmVPEC_DPM_IDLE_START_HI 0x1187F +#define mmVPEC_DPM_BUSY_START_LO 0x11880 +#define mmVPEC_DPM_BUSY_START_HI 0x11881 +#define mmVPEC_DPM_LAST_REQ_TIMESTAMP 0x11882 +#define mmVPEC_DPM_NEW_JOB_DUMMY3 0x11883 +#define mmVPEC_DPM_STATE 0x11884 +#define mmVPEC_DPM0_FREQ 0x11885 +#define mmVPEC_DPM1_FREQ 0x11886 +#define mmVPEC_DPM2_FREQ 0x11887 +#define mmVPEC_DPM3_FREQ 0x11888 +#define mmVPEC_DPM_THRESHOLD_SKIP 0x11889 +#define mmVPEC_DPM_THRESHOLD_BUSY_OVERFLOW 0x1188A +#define mmVPEC_DPM_CALC_BUSY_IN_POSTPROCESS 0x1188B +#define mmVPEC_DPM_IN_CHECKIDLE_LOOP 0x1188C +#define mmVPEC_DPM_THRESHOLD_IDLE_OVERFLOW 0x1188D +#define mmVPEC_DPM_BUSY_CLAMP_COUNT 0x1188E +#define mmVPEC_DPM_IDLE_CLAMP_COUNT 0x1188F +#define mmVPEC_PG_CNTL 0x118B8 +#define mmVPEC_PG_STATUS 0x118B9 +#define mmVPEC_CLOCK_GATING_STATUS 0x118BA +#define mmVPEC_QUEUE0_RB_CNTL 0x118C0 +#define mmVPEC_QUEUE0_SCHEDULE_CNTL 0x118C1 +#define mmVPEC_QUEUE0_RB_BASE 0x118C2 +#define mmVPEC_QUEUE0_RB_BASE_HI 0x118C3 +#define mmVPEC_QUEUE0_RB_RPTR 0x118C4 +#define mmVPEC_QUEUE0_RB_RPTR_HI 0x118C5 +#define mmVPEC_QUEUE0_RB_WPTR 0x118C6 +#define mmVPEC_QUEUE0_RB_WPTR_HI 0x118C7 +#define mmVPEC_QUEUE0_RB_RPTR_ADDR_HI 0x118C8 +#define mmVPEC_QUEUE0_RB_RPTR_ADDR_LO 0x118C9 +#define mmVPEC_QUEUE0_RB_AQL_CNTL 0x118CA +#define mmVPEC_QUEUE0_MINOR_PTR_UPDATE 0x118CB +#define mmVPEC_QUEUE0_CD_INFO 0x118CC +#define mmVPEC_QUEUE0_RB_PREEMPT 0x118CD +#define mmVPEC_QUEUE0_SKIP_CNTL 0x118CE +#define mmVPEC_QUEUE0_DOORBELL 0x118CF +#define mmVPEC_QUEUE0_DOORBELL_OFFSET 0x118D0 +#define mmVPEC_QUEUE0_DUMMY0 0x118D1 +#define mmVPEC_QUEUE0_DUMMY1 0x118D2 +#define mmVPEC_QUEUE0_DUMMY2 0x118D3 +#define mmVPEC_QUEUE0_DUMMY3 0x118D4 +#define mmVPEC_QUEUE0_DUMMY4 0x118D5 +#define mmVPEC_QUEUE0_IB_CNTL 0x118EC +#define mmVPEC_QUEUE0_IB_RPTR 0x118ED +#define mmVPEC_QUEUE0_IB_OFFSET 0x118EE +#define mmVPEC_QUEUE0_IB_BASE_LO 0x118EF +#define mmVPEC_QUEUE0_IB_BASE_HI 0x118F0 +#define mmVPEC_QUEUE0_IB_SIZE 0x118F1 +#define mmVPEC_QUEUE0_CMDIB_CNTL 0x118F2 +#define mmVPEC_QUEUE0_CMDIB_RPTR 0x118F3 +#define mmVPEC_QUEUE0_CMDIB_OFFSET 0x118F4 +#define mmVPEC_QUEUE0_CMDIB_BASE_LO 0x118F5 +#define mmVPEC_QUEUE0_CMDIB_BASE_HI 0x118F6 +#define mmVPEC_QUEUE0_CMDIB_SIZE 0x118F7 +#define mmVPEC_QUEUE0_3DLUTIB_CNTL 0x118F8 +#define mmVPEC_QUEUE0_3DLUTIB_RPTR 0x118F9 +#define mmVPEC_QUEUE0_3DLUTIB_OFFSET 0x118FA +#define mmVPEC_QUEUE0_3DLUTIB_BASE_LO 0x118FB +#define mmVPEC_QUEUE0_3DLUTIB_BASE_HI 0x118FC +#define mmVPEC_QUEUE0_3DLUTIB_SIZE 0x118FD +#define mmVPEC_QUEUE0_CSA_ADDR_LO 0x118FE +#define mmVPEC_QUEUE0_CSA_ADDR_HI 0x118FF +#define mmVPEC_QUEUE0_CONTEXT_STATUS 0x11900 +#define mmVPEC_QUEUE0_DOORBELL_LOG 0x11901 +#define mmVPEC_QUEUE0_IB_SUB_REMAIN 0x11902 +#define mmVPEC_QUEUE0_PREEMPT 0x11903 +#define mmVPEC_QUEUE0_LOG0BUFFER_CFG 0x11904 +#define mmVPEC_QUEUE0_LOG1BUFFER_CFG 0x11905 +#define mmVPEC_QUEUE1_RB_CNTL 0x11918 +#define mmVPEC_QUEUE1_SCHEDULE_CNTL 0x11919 +#define mmVPEC_QUEUE1_RB_BASE 0x1191A +#define mmVPEC_QUEUE1_RB_BASE_HI 0x1191B +#define mmVPEC_QUEUE1_RB_RPTR 0x1191C +#define mmVPEC_QUEUE1_RB_RPTR_HI 0x1191D +#define mmVPEC_QUEUE1_RB_WPTR 0x1191E +#define mmVPEC_QUEUE1_RB_WPTR_HI 0x1191F +#define mmVPEC_QUEUE1_RB_RPTR_ADDR_HI 0x11920 +#define mmVPEC_QUEUE1_RB_RPTR_ADDR_LO 0x11921 +#define mmVPEC_QUEUE1_RB_AQL_CNTL 0x11922 +#define mmVPEC_QUEUE1_MINOR_PTR_UPDATE 0x11923 +#define mmVPEC_QUEUE1_CD_INFO 0x11924 +#define mmVPEC_QUEUE1_RB_PREEMPT 0x11925 +#define mmVPEC_QUEUE1_SKIP_CNTL 0x11926 +#define mmVPEC_QUEUE1_DOORBELL 0x11927 +#define mmVPEC_QUEUE1_DOORBELL_OFFSET 0x11928 +#define mmVPEC_QUEUE1_DUMMY0 0x11929 +#define mmVPEC_QUEUE1_DUMMY1 0x1192A +#define mmVPEC_QUEUE1_DUMMY2 0x1192B +#define mmVPEC_QUEUE1_DUMMY3 0x1192C +#define mmVPEC_QUEUE1_DUMMY4 0x1192D +#define mmVPEC_QUEUE1_IB_CNTL 0x11944 +#define mmVPEC_QUEUE1_IB_RPTR 0x11945 +#define mmVPEC_QUEUE1_IB_OFFSET 0x11946 +#define mmVPEC_QUEUE1_IB_BASE_LO 0x11947 +#define mmVPEC_QUEUE1_IB_BASE_HI 0x11948 +#define mmVPEC_QUEUE1_IB_SIZE 0x11949 +#define mmVPEC_QUEUE1_CMDIB_CNTL 0x1194A +#define mmVPEC_QUEUE1_CMDIB_RPTR 0x1194B +#define mmVPEC_QUEUE1_CMDIB_OFFSET 0x1194C +#define mmVPEC_QUEUE1_CMDIB_BASE_LO 0x1194D +#define mmVPEC_QUEUE1_CMDIB_BASE_HI 0x1194E +#define mmVPEC_QUEUE1_CMDIB_SIZE 0x1194F +#define mmVPEC_QUEUE1_3DLUTIB_CNTL 0x11950 +#define mmVPEC_QUEUE1_3DLUTIB_RPTR 0x11951 +#define mmVPEC_QUEUE1_3DLUTIB_OFFSET 0x11952 +#define mmVPEC_QUEUE1_3DLUTIB_BASE_LO 0x11953 +#define mmVPEC_QUEUE1_3DLUTIB_BASE_HI 0x11954 +#define mmVPEC_QUEUE1_3DLUTIB_SIZE 0x11955 +#define mmVPEC_QUEUE1_CSA_ADDR_LO 0x11956 +#define mmVPEC_QUEUE1_CSA_ADDR_HI 0x11957 +#define mmVPEC_QUEUE1_CONTEXT_STATUS 0x11958 +#define mmVPEC_QUEUE1_DOORBELL_LOG 0x11959 +#define mmVPEC_QUEUE1_IB_SUB_REMAIN 0x1195A +#define mmVPEC_QUEUE1_PREEMPT 0x1195B +#define mmVPEC_QUEUE1_LOG0BUFFER_CFG 0x1195C +#define mmVPEC_QUEUE1_LOG1BUFFER_CFG 0x1195D +#define mmVPEC_QUEUE2_RB_CNTL 0x11970 +#define mmVPEC_QUEUE2_SCHEDULE_CNTL 0x11971 +#define mmVPEC_QUEUE2_RB_BASE 0x11972 +#define mmVPEC_QUEUE2_RB_BASE_HI 0x11973 +#define mmVPEC_QUEUE2_RB_RPTR 0x11974 +#define mmVPEC_QUEUE2_RB_RPTR_HI 0x11975 +#define mmVPEC_QUEUE2_RB_WPTR 0x11976 +#define mmVPEC_QUEUE2_RB_WPTR_HI 0x11977 +#define mmVPEC_QUEUE2_RB_RPTR_ADDR_HI 0x11978 +#define mmVPEC_QUEUE2_RB_RPTR_ADDR_LO 0x11979 +#define mmVPEC_QUEUE2_RB_AQL_CNTL 0x1197A +#define mmVPEC_QUEUE2_MINOR_PTR_UPDATE 0x1197B +#define mmVPEC_QUEUE2_CD_INFO 0x1197C +#define mmVPEC_QUEUE2_RB_PREEMPT 0x1197D +#define mmVPEC_QUEUE2_SKIP_CNTL 0x1197E +#define mmVPEC_QUEUE2_DOORBELL 0x1197F +#define mmVPEC_QUEUE2_DOORBELL_OFFSET 0x11980 +#define mmVPEC_QUEUE2_DUMMY0 0x11981 +#define mmVPEC_QUEUE2_DUMMY1 0x11982 +#define mmVPEC_QUEUE2_DUMMY2 0x11983 +#define mmVPEC_QUEUE2_DUMMY3 0x11984 +#define mmVPEC_QUEUE2_DUMMY4 0x11985 +#define mmVPEC_QUEUE2_IB_CNTL 0x1199C +#define mmVPEC_QUEUE2_IB_RPTR 0x1199D +#define mmVPEC_QUEUE2_IB_OFFSET 0x1199E +#define mmVPEC_QUEUE2_IB_BASE_LO 0x1199F +#define mmVPEC_QUEUE2_IB_BASE_HI 0x119A0 +#define mmVPEC_QUEUE2_IB_SIZE 0x119A1 +#define mmVPEC_QUEUE2_CMDIB_CNTL 0x119A2 +#define mmVPEC_QUEUE2_CMDIB_RPTR 0x119A3 +#define mmVPEC_QUEUE2_CMDIB_OFFSET 0x119A4 +#define mmVPEC_QUEUE2_CMDIB_BASE_LO 0x119A5 +#define mmVPEC_QUEUE2_CMDIB_BASE_HI 0x119A6 +#define mmVPEC_QUEUE2_CMDIB_SIZE 0x119A7 +#define mmVPEC_QUEUE2_3DLUTIB_CNTL 0x119A8 +#define mmVPEC_QUEUE2_3DLUTIB_RPTR 0x119A9 +#define mmVPEC_QUEUE2_3DLUTIB_OFFSET 0x119AA +#define mmVPEC_QUEUE2_3DLUTIB_BASE_LO 0x119AB +#define mmVPEC_QUEUE2_3DLUTIB_BASE_HI 0x119AC +#define mmVPEC_QUEUE2_3DLUTIB_SIZE 0x119AD +#define mmVPEC_QUEUE2_CSA_ADDR_LO 0x119AE +#define mmVPEC_QUEUE2_CSA_ADDR_HI 0x119AF +#define mmVPEC_QUEUE2_CONTEXT_STATUS 0x119B0 +#define mmVPEC_QUEUE2_DOORBELL_LOG 0x119B1 +#define mmVPEC_QUEUE2_IB_SUB_REMAIN 0x119B2 +#define mmVPEC_QUEUE2_PREEMPT 0x119B3 +#define mmVPEC_QUEUE2_LOG0BUFFER_CFG 0x119B4 +#define mmVPEC_QUEUE2_LOG1BUFFER_CFG 0x119B5 +#define mmVPEC_QUEUE3_RB_CNTL 0x119C8 +#define mmVPEC_QUEUE3_SCHEDULE_CNTL 0x119C9 +#define mmVPEC_QUEUE3_RB_BASE 0x119CA +#define mmVPEC_QUEUE3_RB_BASE_HI 0x119CB +#define mmVPEC_QUEUE3_RB_RPTR 0x119CC +#define mmVPEC_QUEUE3_RB_RPTR_HI 0x119CD +#define mmVPEC_QUEUE3_RB_WPTR 0x119CE +#define mmVPEC_QUEUE3_RB_WPTR_HI 0x119CF +#define mmVPEC_QUEUE3_RB_RPTR_ADDR_HI 0x119D0 +#define mmVPEC_QUEUE3_RB_RPTR_ADDR_LO 0x119D1 +#define mmVPEC_QUEUE3_RB_AQL_CNTL 0x119D2 +#define mmVPEC_QUEUE3_MINOR_PTR_UPDATE 0x119D3 +#define mmVPEC_QUEUE3_CD_INFO 0x119D4 +#define mmVPEC_QUEUE3_RB_PREEMPT 0x119D5 +#define mmVPEC_QUEUE3_SKIP_CNTL 0x119D6 +#define mmVPEC_QUEUE3_DOORBELL 0x119D7 +#define mmVPEC_QUEUE3_DOORBELL_OFFSET 0x119D8 +#define mmVPEC_QUEUE3_DUMMY0 0x119D9 +#define mmVPEC_QUEUE3_DUMMY1 0x119DA +#define mmVPEC_QUEUE3_DUMMY2 0x119DB +#define mmVPEC_QUEUE3_DUMMY3 0x119DC +#define mmVPEC_QUEUE3_DUMMY4 0x119DD +#define mmVPEC_QUEUE3_IB_CNTL 0x119F4 +#define mmVPEC_QUEUE3_IB_RPTR 0x119F5 +#define mmVPEC_QUEUE3_IB_OFFSET 0x119F6 +#define mmVPEC_QUEUE3_IB_BASE_LO 0x119F7 +#define mmVPEC_QUEUE3_IB_BASE_HI 0x119F8 +#define mmVPEC_QUEUE3_IB_SIZE 0x119F9 +#define mmVPEC_QUEUE3_CMDIB_CNTL 0x119FA +#define mmVPEC_QUEUE3_CMDIB_RPTR 0x119FB +#define mmVPEC_QUEUE3_CMDIB_OFFSET 0x119FC +#define mmVPEC_QUEUE3_CMDIB_BASE_LO 0x119FD +#define mmVPEC_QUEUE3_CMDIB_BASE_HI 0x119FE +#define mmVPEC_QUEUE3_CMDIB_SIZE 0x119FF +#define mmVPEC_QUEUE3_3DLUTIB_CNTL 0x11A00 +#define mmVPEC_QUEUE3_3DLUTIB_RPTR 0x11A01 +#define mmVPEC_QUEUE3_3DLUTIB_OFFSET 0x11A02 +#define mmVPEC_QUEUE3_3DLUTIB_BASE_LO 0x11A03 +#define mmVPEC_QUEUE3_3DLUTIB_BASE_HI 0x11A04 +#define mmVPEC_QUEUE3_3DLUTIB_SIZE 0x11A05 +#define mmVPEC_QUEUE3_CSA_ADDR_LO 0x11A06 +#define mmVPEC_QUEUE3_CSA_ADDR_HI 0x11A07 +#define mmVPEC_QUEUE3_CONTEXT_STATUS 0x11A08 +#define mmVPEC_QUEUE3_DOORBELL_LOG 0x11A09 +#define mmVPEC_QUEUE3_IB_SUB_REMAIN 0x11A0A +#define mmVPEC_QUEUE3_PREEMPT 0x11A0B +#define mmVPEC_QUEUE3_LOG0BUFFER_CFG 0x11A0C +#define mmVPEC_QUEUE3_LOG1BUFFER_CFG 0x11A0D +#define mmVPEC_QUEUE4_RB_CNTL 0x11A20 +#define mmVPEC_QUEUE4_SCHEDULE_CNTL 0x11A21 +#define mmVPEC_QUEUE4_RB_BASE 0x11A22 +#define mmVPEC_QUEUE4_RB_BASE_HI 0x11A23 +#define mmVPEC_QUEUE4_RB_RPTR 0x11A24 +#define mmVPEC_QUEUE4_RB_RPTR_HI 0x11A25 +#define mmVPEC_QUEUE4_RB_WPTR 0x11A26 +#define mmVPEC_QUEUE4_RB_WPTR_HI 0x11A27 +#define mmVPEC_QUEUE4_RB_RPTR_ADDR_HI 0x11A28 +#define mmVPEC_QUEUE4_RB_RPTR_ADDR_LO 0x11A29 +#define mmVPEC_QUEUE4_RB_AQL_CNTL 0x11A2A +#define mmVPEC_QUEUE4_MINOR_PTR_UPDATE 0x11A2B +#define mmVPEC_QUEUE4_CD_INFO 0x11A2C +#define mmVPEC_QUEUE4_RB_PREEMPT 0x11A2D +#define mmVPEC_QUEUE4_SKIP_CNTL 0x11A2E +#define mmVPEC_QUEUE4_DOORBELL 0x11A2F +#define mmVPEC_QUEUE4_DOORBELL_OFFSET 0x11A30 +#define mmVPEC_QUEUE4_DUMMY0 0x11A31 +#define mmVPEC_QUEUE4_DUMMY1 0x11A32 +#define mmVPEC_QUEUE4_DUMMY2 0x11A33 +#define mmVPEC_QUEUE4_DUMMY3 0x11A34 +#define mmVPEC_QUEUE4_DUMMY4 0x11A35 +#define mmVPEC_QUEUE4_IB_CNTL 0x11A4C +#define mmVPEC_QUEUE4_IB_RPTR 0x11A4D +#define mmVPEC_QUEUE4_IB_OFFSET 0x11A4E +#define mmVPEC_QUEUE4_IB_BASE_LO 0x11A4F +#define mmVPEC_QUEUE4_IB_BASE_HI 0x11A50 +#define mmVPEC_QUEUE4_IB_SIZE 0x11A51 +#define mmVPEC_QUEUE4_CMDIB_CNTL 0x11A52 +#define mmVPEC_QUEUE4_CMDIB_RPTR 0x11A53 +#define mmVPEC_QUEUE4_CMDIB_OFFSET 0x11A54 +#define mmVPEC_QUEUE4_CMDIB_BASE_LO 0x11A55 +#define mmVPEC_QUEUE4_CMDIB_BASE_HI 0x11A56 +#define mmVPEC_QUEUE4_CMDIB_SIZE 0x11A57 +#define mmVPEC_QUEUE4_3DLUTIB_CNTL 0x11A58 +#define mmVPEC_QUEUE4_3DLUTIB_RPTR 0x11A59 +#define mmVPEC_QUEUE4_3DLUTIB_OFFSET 0x11A5A +#define mmVPEC_QUEUE4_3DLUTIB_BASE_LO 0x11A5B +#define mmVPEC_QUEUE4_3DLUTIB_BASE_HI 0x11A5C +#define mmVPEC_QUEUE4_3DLUTIB_SIZE 0x11A5D +#define mmVPEC_QUEUE4_CSA_ADDR_LO 0x11A5E +#define mmVPEC_QUEUE4_CSA_ADDR_HI 0x11A5F +#define mmVPEC_QUEUE4_CONTEXT_STATUS 0x11A60 +#define mmVPEC_QUEUE4_DOORBELL_LOG 0x11A61 +#define mmVPEC_QUEUE4_IB_SUB_REMAIN 0x11A62 +#define mmVPEC_QUEUE4_PREEMPT 0x11A63 +#define mmVPEC_QUEUE4_LOG0BUFFER_CFG 0x11A64 +#define mmVPEC_QUEUE4_LOG1BUFFER_CFG 0x11A65 +#define mmVPEC_QUEUE5_RB_CNTL 0x11A78 +#define mmVPEC_QUEUE5_SCHEDULE_CNTL 0x11A79 +#define mmVPEC_QUEUE5_RB_BASE 0x11A7A +#define mmVPEC_QUEUE5_RB_BASE_HI 0x11A7B +#define mmVPEC_QUEUE5_RB_RPTR 0x11A7C +#define mmVPEC_QUEUE5_RB_RPTR_HI 0x11A7D +#define mmVPEC_QUEUE5_RB_WPTR 0x11A7E +#define mmVPEC_QUEUE5_RB_WPTR_HI 0x11A7F +#define mmVPEC_QUEUE5_RB_RPTR_ADDR_HI 0x11A80 +#define mmVPEC_QUEUE5_RB_RPTR_ADDR_LO 0x11A81 +#define mmVPEC_QUEUE5_RB_AQL_CNTL 0x11A82 +#define mmVPEC_QUEUE5_MINOR_PTR_UPDATE 0x11A83 +#define mmVPEC_QUEUE5_CD_INFO 0x11A84 +#define mmVPEC_QUEUE5_RB_PREEMPT 0x11A85 +#define mmVPEC_QUEUE5_SKIP_CNTL 0x11A86 +#define mmVPEC_QUEUE5_DOORBELL 0x11A87 +#define mmVPEC_QUEUE5_DOORBELL_OFFSET 0x11A88 +#define mmVPEC_QUEUE5_DUMMY0 0x11A89 +#define mmVPEC_QUEUE5_DUMMY1 0x11A8A +#define mmVPEC_QUEUE5_DUMMY2 0x11A8B +#define mmVPEC_QUEUE5_DUMMY3 0x11A8C +#define mmVPEC_QUEUE5_DUMMY4 0x11A8D +#define mmVPEC_QUEUE5_IB_CNTL 0x11AA4 +#define mmVPEC_QUEUE5_IB_RPTR 0x11AA5 +#define mmVPEC_QUEUE5_IB_OFFSET 0x11AA6 +#define mmVPEC_QUEUE5_IB_BASE_LO 0x11AA7 +#define mmVPEC_QUEUE5_IB_BASE_HI 0x11AA8 +#define mmVPEC_QUEUE5_IB_SIZE 0x11AA9 +#define mmVPEC_QUEUE5_CMDIB_CNTL 0x11AAA +#define mmVPEC_QUEUE5_CMDIB_RPTR 0x11AAB +#define mmVPEC_QUEUE5_CMDIB_OFFSET 0x11AAC +#define mmVPEC_QUEUE5_CMDIB_BASE_LO 0x11AAD +#define mmVPEC_QUEUE5_CMDIB_BASE_HI 0x11AAE +#define mmVPEC_QUEUE5_CMDIB_SIZE 0x11AAF +#define mmVPEC_QUEUE5_3DLUTIB_CNTL 0x11AB0 +#define mmVPEC_QUEUE5_3DLUTIB_RPTR 0x11AB1 +#define mmVPEC_QUEUE5_3DLUTIB_OFFSET 0x11AB2 +#define mmVPEC_QUEUE5_3DLUTIB_BASE_LO 0x11AB3 +#define mmVPEC_QUEUE5_3DLUTIB_BASE_HI 0x11AB4 +#define mmVPEC_QUEUE5_3DLUTIB_SIZE 0x11AB5 +#define mmVPEC_QUEUE5_CSA_ADDR_LO 0x11AB6 +#define mmVPEC_QUEUE5_CSA_ADDR_HI 0x11AB7 +#define mmVPEC_QUEUE5_CONTEXT_STATUS 0x11AB8 +#define mmVPEC_QUEUE5_DOORBELL_LOG 0x11AB9 +#define mmVPEC_QUEUE5_IB_SUB_REMAIN 0x11ABA +#define mmVPEC_QUEUE5_PREEMPT 0x11ABB +#define mmVPEC_QUEUE5_LOG0BUFFER_CFG 0x11ABC +#define mmVPEC_QUEUE5_LOG1BUFFER_CFG 0x11ABD +#define mmVPEC_QUEUE6_RB_CNTL 0x11AD0 +#define mmVPEC_QUEUE6_SCHEDULE_CNTL 0x11AD1 +#define mmVPEC_QUEUE6_RB_BASE 0x11AD2 +#define mmVPEC_QUEUE6_RB_BASE_HI 0x11AD3 +#define mmVPEC_QUEUE6_RB_RPTR 0x11AD4 +#define mmVPEC_QUEUE6_RB_RPTR_HI 0x11AD5 +#define mmVPEC_QUEUE6_RB_WPTR 0x11AD6 +#define mmVPEC_QUEUE6_RB_WPTR_HI 0x11AD7 +#define mmVPEC_QUEUE6_RB_RPTR_ADDR_HI 0x11AD8 +#define mmVPEC_QUEUE6_RB_RPTR_ADDR_LO 0x11AD9 +#define mmVPEC_QUEUE6_RB_AQL_CNTL 0x11ADA +#define mmVPEC_QUEUE6_MINOR_PTR_UPDATE 0x11ADB +#define mmVPEC_QUEUE6_CD_INFO 0x11ADC +#define mmVPEC_QUEUE6_RB_PREEMPT 0x11ADD +#define mmVPEC_QUEUE6_SKIP_CNTL 0x11ADE +#define mmVPEC_QUEUE6_DOORBELL 0x11ADF +#define mmVPEC_QUEUE6_DOORBELL_OFFSET 0x11AE0 +#define mmVPEC_QUEUE6_DUMMY0 0x11AE1 +#define mmVPEC_QUEUE6_DUMMY1 0x11AE2 +#define mmVPEC_QUEUE6_DUMMY2 0x11AE3 +#define mmVPEC_QUEUE6_DUMMY3 0x11AE4 +#define mmVPEC_QUEUE6_DUMMY4 0x11AE5 +#define mmVPEC_QUEUE6_IB_CNTL 0x11AFC +#define mmVPEC_QUEUE6_IB_RPTR 0x11AFD +#define mmVPEC_QUEUE6_IB_OFFSET 0x11AFE +#define mmVPEC_QUEUE6_IB_BASE_LO 0x11AFF +#define mmVPEC_QUEUE6_IB_BASE_HI 0x11B00 +#define mmVPEC_QUEUE6_IB_SIZE 0x11B01 +#define mmVPEC_QUEUE6_CMDIB_CNTL 0x11B02 +#define mmVPEC_QUEUE6_CMDIB_RPTR 0x11B03 +#define mmVPEC_QUEUE6_CMDIB_OFFSET 0x11B04 +#define mmVPEC_QUEUE6_CMDIB_BASE_LO 0x11B05 +#define mmVPEC_QUEUE6_CMDIB_BASE_HI 0x11B06 +#define mmVPEC_QUEUE6_CMDIB_SIZE 0x11B07 +#define mmVPEC_QUEUE6_3DLUTIB_CNTL 0x11B08 +#define mmVPEC_QUEUE6_3DLUTIB_RPTR 0x11B09 +#define mmVPEC_QUEUE6_3DLUTIB_OFFSET 0x11B0A +#define mmVPEC_QUEUE6_3DLUTIB_BASE_LO 0x11B0B +#define mmVPEC_QUEUE6_3DLUTIB_BASE_HI 0x11B0C +#define mmVPEC_QUEUE6_3DLUTIB_SIZE 0x11B0D +#define mmVPEC_QUEUE6_CSA_ADDR_LO 0x11B0E +#define mmVPEC_QUEUE6_CSA_ADDR_HI 0x11B0F +#define mmVPEC_QUEUE6_CONTEXT_STATUS 0x11B10 +#define mmVPEC_QUEUE6_DOORBELL_LOG 0x11B11 +#define mmVPEC_QUEUE6_IB_SUB_REMAIN 0x11B12 +#define mmVPEC_QUEUE6_PREEMPT 0x11B13 +#define mmVPEC_QUEUE6_LOG0BUFFER_CFG 0x11B14 +#define mmVPEC_QUEUE6_LOG1BUFFER_CFG 0x11B15 +#define mmVPEC_QUEUE7_RB_CNTL 0x11B28 +#define mmVPEC_QUEUE7_SCHEDULE_CNTL 0x11B29 +#define mmVPEC_QUEUE7_RB_BASE 0x11B2A +#define mmVPEC_QUEUE7_RB_BASE_HI 0x11B2B +#define mmVPEC_QUEUE7_RB_RPTR 0x11B2C +#define mmVPEC_QUEUE7_RB_RPTR_HI 0x11B2D +#define mmVPEC_QUEUE7_RB_WPTR 0x11B2E +#define mmVPEC_QUEUE7_RB_WPTR_HI 0x11B2F +#define mmVPEC_QUEUE7_RB_RPTR_ADDR_HI 0x11B30 +#define mmVPEC_QUEUE7_RB_RPTR_ADDR_LO 0x11B31 +#define mmVPEC_QUEUE7_RB_AQL_CNTL 0x11B32 +#define mmVPEC_QUEUE7_MINOR_PTR_UPDATE 0x11B33 +#define mmVPEC_QUEUE7_CD_INFO 0x11B34 +#define mmVPEC_QUEUE7_RB_PREEMPT 0x11B35 +#define mmVPEC_QUEUE7_SKIP_CNTL 0x11B36 +#define mmVPEC_QUEUE7_DOORBELL 0x11B37 +#define mmVPEC_QUEUE7_DOORBELL_OFFSET 0x11B38 +#define mmVPEC_QUEUE7_DUMMY0 0x11B39 +#define mmVPEC_QUEUE7_DUMMY1 0x11B3A +#define mmVPEC_QUEUE7_DUMMY2 0x11B3B +#define mmVPEC_QUEUE7_DUMMY3 0x11B3C +#define mmVPEC_QUEUE7_DUMMY4 0x11B3D +#define mmVPEC_QUEUE7_IB_CNTL 0x11B54 +#define mmVPEC_QUEUE7_IB_RPTR 0x11B55 +#define mmVPEC_QUEUE7_IB_OFFSET 0x11B56 +#define mmVPEC_QUEUE7_IB_BASE_LO 0x11B57 +#define mmVPEC_QUEUE7_IB_BASE_HI 0x11B58 +#define mmVPEC_QUEUE7_IB_SIZE 0x11B59 +#define mmVPEC_QUEUE7_CMDIB_CNTL 0x11B5A +#define mmVPEC_QUEUE7_CMDIB_RPTR 0x11B5B +#define mmVPEC_QUEUE7_CMDIB_OFFSET 0x11B5C +#define mmVPEC_QUEUE7_CMDIB_BASE_LO 0x11B5D +#define mmVPEC_QUEUE7_CMDIB_BASE_HI 0x11B5E +#define mmVPEC_QUEUE7_CMDIB_SIZE 0x11B5F +#define mmVPEC_QUEUE7_3DLUTIB_CNTL 0x11B60 +#define mmVPEC_QUEUE7_3DLUTIB_RPTR 0x11B61 +#define mmVPEC_QUEUE7_3DLUTIB_OFFSET 0x11B62 +#define mmVPEC_QUEUE7_3DLUTIB_BASE_LO 0x11B63 +#define mmVPEC_QUEUE7_3DLUTIB_BASE_HI 0x11B64 +#define mmVPEC_QUEUE7_3DLUTIB_SIZE 0x11B65 +#define mmVPEC_QUEUE7_CSA_ADDR_LO 0x11B66 +#define mmVPEC_QUEUE7_CSA_ADDR_HI 0x11B67 +#define mmVPEC_QUEUE7_CONTEXT_STATUS 0x11B68 +#define mmVPEC_QUEUE7_DOORBELL_LOG 0x11B69 +#define mmVPEC_QUEUE7_IB_SUB_REMAIN 0x11B6A +#define mmVPEC_QUEUE7_PREEMPT 0x11B6B +#define mmVPEC_QUEUE7_LOG0BUFFER_CFG 0x11B6C +#define mmVPEC_QUEUE7_LOG1BUFFER_CFG 0x11B6D + + +// Registers from CDC block + +#define mmVPEP_MGCG_CNTL 0x11E00 +#define mmVPCDC_SOFT_RESET 0x11E01 +#define mmVPCDC_FE0_SURFACE_CONFIG 0x11E02 +#define mmVPCDC_FE0_CROSSBAR_CONFIG 0x11E03 +#define mmVPCDC_FE0_VIEWPORT_START_CONFIG 0x11E04 +#define mmVPCDC_FE0_VIEWPORT_DIMENSION_CONFIG 0x11E05 +#define mmVPCDC_FE0_VIEWPORT_START_C_CONFIG 0x11E06 +#define mmVPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG 0x11E07 +#define mmVPCDC_FE1_SURFACE_CONFIG 0x11E08 +#define mmVPCDC_FE1_CROSSBAR_CONFIG 0x11E09 +#define mmVPCDC_FE1_VIEWPORT_START_CONFIG 0x11E0A +#define mmVPCDC_FE1_VIEWPORT_DIMENSION_CONFIG 0x11E0B +#define mmVPCDC_FE1_VIEWPORT_START_C_CONFIG 0x11E0C +#define mmVPCDC_FE1_VIEWPORT_DIMENSION_C_CONFIG 0x11E0D +#define mmVPCDC_BE0_P2B_CONFIG 0x11E0E +#define mmVPCDC_BE0_GLOBAL_SYNC_CONFIG 0x11E0F +#define mmVPCDC_BE1_P2B_CONFIG 0x11E10 +#define mmVPCDC_BE1_GLOBAL_SYNC_CONFIG 0x11E11 +#define mmVPCDC_BE2_P2B_CONFIG 0x11E12 +#define mmVPCDC_BE2_GLOBAL_SYNC_CONFIG 0x11E13 +#define mmVPCDC_BE3_P2B_CONFIG 0x11E14 +#define mmVPCDC_BE3_GLOBAL_SYNC_CONFIG 0x11E15 +#define mmVPCDC_GLOBAL_SYNC_TRIGGER 0x11E16 +#define mmVPCDC_VREADY_STATUS 0x11E17 +#define mmVPEP_MEM_GLOBAL_PWR_REQ_CNTL 0x11E18 +#define mmVPFE0_MEM_PWR_CNTL 0x11E19 +#define mmVPFE1_MEM_PWR_CNTL 0x11E1A +#define mmVPBE0_MEM_PWR_CNTL 0x11E1B +#define mmVPBE1_MEM_PWR_CNTL 0x11E1C +#define mmVPBE2_MEM_PWR_CNTL 0x11E1D +#define mmVPBE3_MEM_PWR_CNTL 0x11E1E +#define mmVPEP_RBBMIF_TIMEOUT 0x11E1F +#define mmVPEP_RBBMIF_STATUS 0x11E20 +#define mmVPEP_RBBMIF_TIMEOUT_DIS 0x11E21 +#define mmVPCDC_DEBUG_CTRL0 0x11E22 +#define mmVPCDC_DEBUG_CTRL1 0x11E23 +#define mmVPCDC_TEST_DEBUG_INDEX 0x11E24 +#define mmVPCDC_TEST_DEBUG_DATA 0x11E25 +#define mmVPCDC_3DLUT_FL_CONFIG 0x11E26 +#define mmVPCDC_CONTROL 0x11E27 + + +// Registers from VPCNVC_CFG block + +#define mmVPCNVC_SURFACE_PIXEL_FORMAT 0x11F44 +#define mmVPCNVC_CFG0_VPCNVC_SURFACE_PIXEL_FORMAT 0x11F44 +#define mmVPCNVC_CFG1_VPCNVC_SURFACE_PIXEL_FORMAT 0x120E0 +#define mmVPCNVC_FORMAT_CONTROL 0x11F45 +#define mmVPCNVC_CFG0_VPCNVC_FORMAT_CONTROL 0x11F45 +#define mmVPCNVC_CFG1_VPCNVC_FORMAT_CONTROL 0x120E1 +#define mmVPCNVC_FCNV_FP_BIAS_R 0x11F46 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_BIAS_R 0x11F46 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_BIAS_R 0x120E2 +#define mmVPCNVC_FCNV_FP_BIAS_G 0x11F47 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_BIAS_G 0x11F47 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_BIAS_G 0x120E3 +#define mmVPCNVC_FCNV_FP_BIAS_B 0x11F48 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_BIAS_B 0x11F48 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_BIAS_B 0x120E4 +#define mmVPCNVC_FCNV_FP_SCALE_R 0x11F49 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_SCALE_R 0x11F49 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_SCALE_R 0x120E5 +#define mmVPCNVC_FCNV_FP_SCALE_G 0x11F4A +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_SCALE_G 0x11F4A +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_SCALE_G 0x120E6 +#define mmVPCNVC_FCNV_FP_SCALE_B 0x11F4B +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_SCALE_B 0x11F4B +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_SCALE_B 0x120E7 +#define mmVPCNVC_COLOR_KEYER_CONTROL 0x11F4C +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_CONTROL 0x11F4C +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_CONTROL 0x120E8 +#define mmVPCNVC_COLOR_KEYER_ALPHA 0x11F4D +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_ALPHA 0x11F4D +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_ALPHA 0x120E9 +#define mmVPCNVC_COLOR_KEYER_RED 0x11F4E +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_RED 0x11F4E +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_RED 0x120EA +#define mmVPCNVC_COLOR_KEYER_GREEN 0x11F4F +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_GREEN 0x11F4F +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_GREEN 0x120EB +#define mmVPCNVC_COLOR_KEYER_BLUE 0x11F50 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_BLUE 0x11F50 +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_BLUE 0x120EC +#define mmVPCNVC_ALPHA_2BIT_LUT01 0x11F52 +#define mmVPCNVC_CFG0_VPCNVC_ALPHA_2BIT_LUT01 0x11F52 +#define mmVPCNVC_CFG1_VPCNVC_ALPHA_2BIT_LUT01 0x120EE +#define mmVPCNVC_ALPHA_2BIT_LUT23 0x11F53 +#define mmVPCNVC_CFG0_VPCNVC_ALPHA_2BIT_LUT23 0x11F53 +#define mmVPCNVC_CFG1_VPCNVC_ALPHA_2BIT_LUT23 0x120EF +#define mmVPCNVC_PRE_DEALPHA 0x11F54 +#define mmVPCNVC_CFG0_VPCNVC_PRE_DEALPHA 0x11F54 +#define mmVPCNVC_CFG1_VPCNVC_PRE_DEALPHA 0x120F0 +#define mmVPCNVC_PRE_CSC_MODE 0x11F55 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_MODE 0x11F55 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_MODE 0x120F1 +#define mmVPCNVC_PRE_CSC_C11_C12 0x11F56 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C11_C12 0x11F56 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C11_C12 0x120F2 +#define mmVPCNVC_PRE_CSC_C13_C14 0x11F57 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C13_C14 0x11F57 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C13_C14 0x120F3 +#define mmVPCNVC_PRE_CSC_C21_C22 0x11F58 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C21_C22 0x11F58 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C21_C22 0x120F4 +#define mmVPCNVC_PRE_CSC_C23_C24 0x11F59 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C23_C24 0x11F59 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C23_C24 0x120F5 +#define mmVPCNVC_PRE_CSC_C31_C32 0x11F5A +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C31_C32 0x11F5A +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C31_C32 0x120F6 +#define mmVPCNVC_PRE_CSC_C33_C34 0x11F5B +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C33_C34 0x11F5B +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C33_C34 0x120F7 +#define mmVPCNVC_COEF_FORMAT 0x11F5C +#define mmVPCNVC_CFG0_VPCNVC_COEF_FORMAT 0x11F5C +#define mmVPCNVC_CFG1_VPCNVC_COEF_FORMAT 0x120F8 +#define mmVPCNVC_PRE_DEGAM 0x11F5D +#define mmVPCNVC_CFG0_VPCNVC_PRE_DEGAM 0x11F5D +#define mmVPCNVC_CFG1_VPCNVC_PRE_DEGAM 0x120F9 +#define mmVPCNVC_PRE_REALPHA 0x11F5E +#define mmVPCNVC_CFG0_VPCNVC_PRE_REALPHA 0x11F5E +#define mmVPCNVC_CFG1_VPCNVC_PRE_REALPHA 0x120FA +#define mmVPCNVC_CFG_TEST_DEBUG_INDEX 0x11F5F +#define mmVPCNVC_CFG0_VPCNVC_CFG_TEST_DEBUG_INDEX 0x11F5F +#define mmVPCNVC_CFG1_VPCNVC_CFG_TEST_DEBUG_INDEX 0x120FB +#define mmVPCNVC_CFG_TEST_DEBUG_DATA 0x11F60 +#define mmVPCNVC_CFG0_VPCNVC_CFG_TEST_DEBUG_DATA 0x11F60 +#define mmVPCNVC_CFG1_VPCNVC_CFG_TEST_DEBUG_DATA 0x120FC + + +// Registers from VPDSCL block + +#define mmVPDSCL_COEF_RAM_TAP_SELECT 0x11F68 +#define mmVPDSCL0_VPDSCL_COEF_RAM_TAP_SELECT 0x11F68 +#define mmVPDSCL1_VPDSCL_COEF_RAM_TAP_SELECT 0x12104 +#define mmVPDSCL_COEF_RAM_TAP_DATA 0x11F69 +#define mmVPDSCL0_VPDSCL_COEF_RAM_TAP_DATA 0x11F69 +#define mmVPDSCL1_VPDSCL_COEF_RAM_TAP_DATA 0x12105 +#define mmVPDSCL_MODE 0x11F6A +#define mmVPDSCL0_VPDSCL_MODE 0x11F6A +#define mmVPDSCL1_VPDSCL_MODE 0x12106 +#define mmVPDSCL_TAP_CONTROL 0x11F6B +#define mmVPDSCL0_VPDSCL_TAP_CONTROL 0x11F6B +#define mmVPDSCL1_VPDSCL_TAP_CONTROL 0x12107 +#define mmVPDSCL_CONTROL 0x11F6C +#define mmVPDSCL0_VPDSCL_CONTROL 0x11F6C +#define mmVPDSCL1_VPDSCL_CONTROL 0x12108 +#define mmVPDSCL_2TAP_CONTROL 0x11F6D +#define mmVPDSCL0_VPDSCL_2TAP_CONTROL 0x11F6D +#define mmVPDSCL1_VPDSCL_2TAP_CONTROL 0x12109 +#define mmVPDSCL_MANUAL_REPLICATE_CONTROL 0x11F6E +#define mmVPDSCL0_VPDSCL_MANUAL_REPLICATE_CONTROL 0x11F6E +#define mmVPDSCL1_VPDSCL_MANUAL_REPLICATE_CONTROL 0x1210A +#define mmVPDSCL_HORZ_FILTER_SCALE_RATIO 0x11F6F +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_SCALE_RATIO 0x11F6F +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_SCALE_RATIO 0x1210B +#define mmVPDSCL_HORZ_FILTER_INIT 0x11F70 +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_INIT 0x11F70 +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_INIT 0x1210C +#define mmVPDSCL_HORZ_FILTER_SCALE_RATIO_C 0x11F71 +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_SCALE_RATIO_C 0x11F71 +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_SCALE_RATIO_C 0x1210D +#define mmVPDSCL_HORZ_FILTER_INIT_C 0x11F72 +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_INIT_C 0x11F72 +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_INIT_C 0x1210E +#define mmVPDSCL_VERT_FILTER_SCALE_RATIO 0x11F73 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_SCALE_RATIO 0x11F73 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_SCALE_RATIO 0x1210F +#define mmVPDSCL_VERT_FILTER_INIT 0x11F74 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT 0x11F74 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT 0x12110 +#define mmVPDSCL_VERT_FILTER_INIT_BOT 0x11F75 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_BOT 0x11F75 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_BOT 0x12111 +#define mmVPDSCL_VERT_FILTER_SCALE_RATIO_C 0x11F76 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_SCALE_RATIO_C 0x11F76 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_SCALE_RATIO_C 0x12112 +#define mmVPDSCL_VERT_FILTER_INIT_C 0x11F77 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_C 0x11F77 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_C 0x12113 +#define mmVPDSCL_VERT_FILTER_INIT_BOT_C 0x11F78 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_BOT_C 0x11F78 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_BOT_C 0x12114 +#define mmVPDSCL_BLACK_COLOR 0x11F79 +#define mmVPDSCL0_VPDSCL_BLACK_COLOR 0x11F79 +#define mmVPDSCL1_VPDSCL_BLACK_COLOR 0x12115 +#define mmVPDSCL_UPDATE 0x11F7A +#define mmVPDSCL0_VPDSCL_UPDATE 0x11F7A +#define mmVPDSCL1_VPDSCL_UPDATE 0x12116 +#define mmVPDSCL_AUTOCAL 0x11F7B +#define mmVPDSCL0_VPDSCL_AUTOCAL 0x11F7B +#define mmVPDSCL1_VPDSCL_AUTOCAL 0x12117 +#define mmVPDSCL_EXT_OVERSCAN_LEFT_RIGHT 0x11F7C +#define mmVPDSCL0_VPDSCL_EXT_OVERSCAN_LEFT_RIGHT 0x11F7C +#define mmVPDSCL1_VPDSCL_EXT_OVERSCAN_LEFT_RIGHT 0x12118 +#define mmVPDSCL_EXT_OVERSCAN_TOP_BOTTOM 0x11F7D +#define mmVPDSCL0_VPDSCL_EXT_OVERSCAN_TOP_BOTTOM 0x11F7D +#define mmVPDSCL1_VPDSCL_EXT_OVERSCAN_TOP_BOTTOM 0x12119 +#define mmVPOTG_H_BLANK 0x11F7E +#define mmVPDSCL0_VPOTG_H_BLANK 0x11F7E +#define mmVPDSCL1_VPOTG_H_BLANK 0x1211A +#define mmVPOTG_V_BLANK 0x11F7F +#define mmVPDSCL0_VPOTG_V_BLANK 0x11F7F +#define mmVPDSCL1_VPOTG_V_BLANK 0x1211B +#define mmVPDSCL_RECOUT_START 0x11F80 +#define mmVPDSCL0_VPDSCL_RECOUT_START 0x11F80 +#define mmVPDSCL1_VPDSCL_RECOUT_START 0x1211C +#define mmVPDSCL_RECOUT_SIZE 0x11F81 +#define mmVPDSCL0_VPDSCL_RECOUT_SIZE 0x11F81 +#define mmVPDSCL1_VPDSCL_RECOUT_SIZE 0x1211D +#define mmVPMPC_SIZE 0x11F82 +#define mmVPDSCL0_VPMPC_SIZE 0x11F82 +#define mmVPDSCL1_VPMPC_SIZE 0x1211E +#define mmVPLB_DATA_FORMAT 0x11F83 +#define mmVPDSCL0_VPLB_DATA_FORMAT 0x11F83 +#define mmVPDSCL1_VPLB_DATA_FORMAT 0x1211F +#define mmVPLB_MEMORY_CTRL 0x11F84 +#define mmVPDSCL0_VPLB_MEMORY_CTRL 0x11F84 +#define mmVPDSCL1_VPLB_MEMORY_CTRL 0x12120 +#define mmVPLB_V_COUNTER 0x11F85 +#define mmVPDSCL0_VPLB_V_COUNTER 0x11F85 +#define mmVPDSCL1_VPLB_V_COUNTER 0x12121 +#define mmVPDSCL_MEM_PWR_CTRL 0x11F86 +#define mmVPDSCL0_VPDSCL_MEM_PWR_CTRL 0x11F86 +#define mmVPDSCL1_VPDSCL_MEM_PWR_CTRL 0x12122 +#define mmVPDSCL_MEM_PWR_STATUS 0x11F87 +#define mmVPDSCL0_VPDSCL_MEM_PWR_STATUS 0x11F87 +#define mmVPDSCL1_VPDSCL_MEM_PWR_STATUS 0x12123 +#define mmVPDSCL_EASF_H_MODE 0x11F88 +#define mmVPDSCL0_VPDSCL_EASF_H_MODE 0x11F88 +#define mmVPDSCL1_VPDSCL_EASF_H_MODE 0x12124 +#define mmVPDSCL_EASF_V_MODE 0x11F89 +#define mmVPDSCL0_VPDSCL_EASF_V_MODE 0x11F89 +#define mmVPDSCL1_VPDSCL_EASF_V_MODE 0x12125 +#define mmVPDSCL_SC_MODE 0x11F8A +#define mmVPDSCL0_VPDSCL_SC_MODE 0x11F8A +#define mmVPDSCL1_VPDSCL_SC_MODE 0x12126 +#define mmVPDSCL_SC_MATRIX_C0C1 0x11F8B +#define mmVPDSCL0_VPDSCL_SC_MATRIX_C0C1 0x11F8B +#define mmVPDSCL1_VPDSCL_SC_MATRIX_C0C1 0x12127 +#define mmVPDSCL_SC_MATRIX_C2C3 0x11F8C +#define mmVPDSCL0_VPDSCL_SC_MATRIX_C2C3 0x11F8C +#define mmVPDSCL1_VPDSCL_SC_MATRIX_C2C3 0x12128 +#define mmVPDSCL_EASF_H_RINGEST_EVENTAP_GAIN 0x11F8D +#define mmVPDSCL0_VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN 0x11F8D +#define mmVPDSCL1_VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN 0x12129 +#define mmVPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE 0x11F8E +#define mmVPDSCL0_VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE 0x11F8E +#define mmVPDSCL1_VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE 0x1212A +#define mmVPDSCL_EASF_V_RINGEST_EVENTAP_GAIN 0x11F8F +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN 0x11F8F +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN 0x1212B +#define mmVPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE 0x11F90 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE 0x11F90 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE 0x1212C +#define mmVPDSCL_EASF_V_RINGEST_3TAP_CNTL1 0x11F91 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_3TAP_CNTL1 0x11F91 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_3TAP_CNTL1 0x1212D +#define mmVPDSCL_EASF_V_RINGEST_3TAP_CNTL2 0x11F92 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_3TAP_CNTL2 0x11F92 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_3TAP_CNTL2 0x1212E +#define mmVPDSCL_EASF_V_RINGEST_3TAP_CNTL3 0x11F93 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_3TAP_CNTL3 0x11F93 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_3TAP_CNTL3 0x1212F +#define mmVPDSCL_EASF_RINGEST_FORCE 0x11F94 +#define mmVPDSCL0_VPDSCL_EASF_RINGEST_FORCE 0x11F94 +#define mmVPDSCL1_VPDSCL_EASF_RINGEST_FORCE 0x12130 +#define mmVPDSCL_EASF_H_BF_CNTL 0x11F95 +#define mmVPDSCL0_VPDSCL_EASF_H_BF_CNTL 0x11F95 +#define mmVPDSCL1_VPDSCL_EASF_H_BF_CNTL 0x12131 +#define mmVPDSCL_EASF_H_BF_FINAL_MAX_MIN 0x11F96 +#define mmVPDSCL0_VPDSCL_EASF_H_BF_FINAL_MAX_MIN 0x11F96 +#define mmVPDSCL1_VPDSCL_EASF_H_BF_FINAL_MAX_MIN 0x12132 +#define mmVPDSCL_EASF_V_BF_CNTL 0x11F97 +#define mmVPDSCL0_VPDSCL_EASF_V_BF_CNTL 0x11F97 +#define mmVPDSCL1_VPDSCL_EASF_V_BF_CNTL 0x12133 +#define mmVPDSCL_EASF_V_BF_FINAL_MAX_MIN 0x11F98 +#define mmVPDSCL0_VPDSCL_EASF_V_BF_FINAL_MAX_MIN 0x11F98 +#define mmVPDSCL1_VPDSCL_EASF_V_BF_FINAL_MAX_MIN 0x12134 +#define mmVPDSCL_EASF_H_BF1_PWL_SEG0 0x11F99 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG0 0x11F99 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG0 0x12135 +#define mmVPDSCL_EASF_H_BF1_PWL_SEG1 0x11F9A +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG1 0x11F9A +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG1 0x12136 +#define mmVPDSCL_EASF_H_BF1_PWL_SEG2 0x11F9B +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG2 0x11F9B +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG2 0x12137 +#define mmVPDSCL_EASF_H_BF1_PWL_SEG3 0x11F9C +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG3 0x11F9C +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG3 0x12138 +#define mmVPDSCL_EASF_H_BF1_PWL_SEG4 0x11F9D +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG4 0x11F9D +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG4 0x12139 +#define mmVPDSCL_EASF_H_BF1_PWL_SEG5 0x11F9E +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG5 0x11F9E +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG5 0x1213A +#define mmVPDSCL_EASF_H_BF1_PWL_SEG6 0x11F9F +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG6 0x11F9F +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG6 0x1213B +#define mmVPDSCL_EASF_H_BF1_PWL_SEG7 0x11FA0 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG7 0x11FA0 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG7 0x1213C +#define mmVPDSCL_EASF_V_BF1_PWL_SEG0 0x11FA1 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG0 0x11FA1 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG0 0x1213D +#define mmVPDSCL_EASF_V_BF1_PWL_SEG1 0x11FA2 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG1 0x11FA2 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG1 0x1213E +#define mmVPDSCL_EASF_V_BF1_PWL_SEG2 0x11FA3 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG2 0x11FA3 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG2 0x1213F +#define mmVPDSCL_EASF_V_BF1_PWL_SEG3 0x11FA4 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG3 0x11FA4 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG3 0x12140 +#define mmVPDSCL_EASF_V_BF1_PWL_SEG4 0x11FA5 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG4 0x11FA5 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG4 0x12141 +#define mmVPDSCL_EASF_V_BF1_PWL_SEG5 0x11FA6 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG5 0x11FA6 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG5 0x12142 +#define mmVPDSCL_EASF_V_BF1_PWL_SEG6 0x11FA7 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG6 0x11FA7 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG6 0x12143 +#define mmVPDSCL_EASF_V_BF1_PWL_SEG7 0x11FA8 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG7 0x11FA8 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG7 0x12144 +#define mmVPDSCL_EASF_H_BF3_PWL_SEG0 0x11FA9 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG0 0x11FA9 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG0 0x12145 +#define mmVPDSCL_EASF_H_BF3_PWL_SEG1 0x11FAA +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG1 0x11FAA +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG1 0x12146 +#define mmVPDSCL_EASF_H_BF3_PWL_SEG2 0x11FAB +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG2 0x11FAB +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG2 0x12147 +#define mmVPDSCL_EASF_H_BF3_PWL_SEG3 0x11FAC +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG3 0x11FAC +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG3 0x12148 +#define mmVPDSCL_EASF_H_BF3_PWL_SEG4 0x11FAD +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG4 0x11FAD +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG4 0x12149 +#define mmVPDSCL_EASF_H_BF3_PWL_SEG5 0x11FAE +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG5 0x11FAE +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG5 0x1214A +#define mmVPDSCL_EASF_V_BF3_PWL_SEG0 0x11FAF +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG0 0x11FAF +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG0 0x1214B +#define mmVPDSCL_EASF_V_BF3_PWL_SEG1 0x11FB0 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG1 0x11FB0 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG1 0x1214C +#define mmVPDSCL_EASF_V_BF3_PWL_SEG2 0x11FB1 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG2 0x11FB1 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG2 0x1214D +#define mmVPDSCL_EASF_V_BF3_PWL_SEG3 0x11FB2 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG3 0x11FB2 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG3 0x1214E +#define mmVPDSCL_EASF_V_BF3_PWL_SEG4 0x11FB3 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG4 0x11FB3 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG4 0x1214F +#define mmVPDSCL_EASF_V_BF3_PWL_SEG5 0x11FB4 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG5 0x11FB4 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG5 0x12150 +#define mmVPISHARP_MODE 0x11FB5 +#define mmVPDSCL0_VPISHARP_MODE 0x11FB5 +#define mmVPDSCL1_VPISHARP_MODE 0x12151 +#define mmVPISHARP_DELTA_CTRL 0x11FB6 +#define mmVPDSCL0_VPISHARP_DELTA_CTRL 0x11FB6 +#define mmVPDSCL1_VPISHARP_DELTA_CTRL 0x12152 +#define mmVPISHARP_DELTA_INDEX 0x11FB7 +#define mmVPDSCL0_VPISHARP_DELTA_INDEX 0x11FB7 +#define mmVPDSCL1_VPISHARP_DELTA_INDEX 0x12153 +#define mmVPISHARP_DELTA_DATA 0x11FB8 +#define mmVPDSCL0_VPISHARP_DELTA_DATA 0x11FB8 +#define mmVPDSCL1_VPISHARP_DELTA_DATA 0x12154 +#define mmVPISHARP_NLDELTA_SOFT_CLIP 0x11FB9 +#define mmVPDSCL0_VPISHARP_NLDELTA_SOFT_CLIP 0x11FB9 +#define mmVPDSCL1_VPISHARP_NLDELTA_SOFT_CLIP 0x12155 +#define mmVPISHARP_NOISEDET_THRESHOLD 0x11FBA +#define mmVPDSCL0_VPISHARP_NOISEDET_THRESHOLD 0x11FBA +#define mmVPDSCL1_VPISHARP_NOISEDET_THRESHOLD 0x12156 +#define mmVPISHARP_NOISE_GAIN_PWL 0x11FBB +#define mmVPDSCL0_VPISHARP_NOISE_GAIN_PWL 0x11FBB +#define mmVPDSCL1_VPISHARP_NOISE_GAIN_PWL 0x12157 +#define mmVPISHARP_LBA_PWL_SEG0 0x11FBC +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG0 0x11FBC +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG0 0x12158 +#define mmVPISHARP_LBA_PWL_SEG1 0x11FBD +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG1 0x11FBD +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG1 0x12159 +#define mmVPISHARP_LBA_PWL_SEG2 0x11FBE +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG2 0x11FBE +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG2 0x1215A +#define mmVPISHARP_LBA_PWL_SEG3 0x11FBF +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG3 0x11FBF +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG3 0x1215B +#define mmVPISHARP_LBA_PWL_SEG4 0x11FC0 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG4 0x11FC0 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG4 0x1215C +#define mmVPISHARP_LBA_PWL_SEG5 0x11FC1 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG5 0x11FC1 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG5 0x1215D +#define mmVPISHARP_DELTA_LUT_MEM_PWR_CTRL 0x11FC2 +#define mmVPDSCL0_VPISHARP_DELTA_LUT_MEM_PWR_CTRL 0x11FC2 +#define mmVPDSCL1_VPISHARP_DELTA_LUT_MEM_PWR_CTRL 0x1215E +#define mmVPDSCL_DEBUG 0x11FC3 +#define mmVPDSCL0_VPDSCL_DEBUG 0x11FC3 +#define mmVPDSCL1_VPDSCL_DEBUG 0x1215F +#define mmVPDSCL_TEST_DEBUG_INDEX 0x11FC4 +#define mmVPDSCL0_VPDSCL_TEST_DEBUG_INDEX 0x11FC4 +#define mmVPDSCL1_VPDSCL_TEST_DEBUG_INDEX 0x12160 +#define mmVPDSCL_TEST_DEBUG_DATA 0x11FC5 +#define mmVPDSCL0_VPDSCL_TEST_DEBUG_DATA 0x11FC5 +#define mmVPDSCL1_VPDSCL_TEST_DEBUG_DATA 0x12161 + + +// Registers from VPCM block + +#define mmVPCM_CONTROL 0x1201C +#define mmVPCM0_VPCM_CONTROL 0x1201C +#define mmVPCM1_VPCM_CONTROL 0x121B8 +#define mmVPCM_POST_CSC_CONTROL 0x1201D +#define mmVPCM0_VPCM_POST_CSC_CONTROL 0x1201D +#define mmVPCM1_VPCM_POST_CSC_CONTROL 0x121B9 +#define mmVPCM_POST_CSC_C11_C12 0x1201E +#define mmVPCM0_VPCM_POST_CSC_C11_C12 0x1201E +#define mmVPCM1_VPCM_POST_CSC_C11_C12 0x121BA +#define mmVPCM_POST_CSC_C13_C14 0x1201F +#define mmVPCM0_VPCM_POST_CSC_C13_C14 0x1201F +#define mmVPCM1_VPCM_POST_CSC_C13_C14 0x121BB +#define mmVPCM_POST_CSC_C21_C22 0x12020 +#define mmVPCM0_VPCM_POST_CSC_C21_C22 0x12020 +#define mmVPCM1_VPCM_POST_CSC_C21_C22 0x121BC +#define mmVPCM_POST_CSC_C23_C24 0x12021 +#define mmVPCM0_VPCM_POST_CSC_C23_C24 0x12021 +#define mmVPCM1_VPCM_POST_CSC_C23_C24 0x121BD +#define mmVPCM_POST_CSC_C31_C32 0x12022 +#define mmVPCM0_VPCM_POST_CSC_C31_C32 0x12022 +#define mmVPCM1_VPCM_POST_CSC_C31_C32 0x121BE +#define mmVPCM_POST_CSC_C33_C34 0x12023 +#define mmVPCM0_VPCM_POST_CSC_C33_C34 0x12023 +#define mmVPCM1_VPCM_POST_CSC_C33_C34 0x121BF +#define mmVPCM_BIAS_CR_R 0x12024 +#define mmVPCM0_VPCM_BIAS_CR_R 0x12024 +#define mmVPCM1_VPCM_BIAS_CR_R 0x121C0 +#define mmVPCM_BIAS_Y_G_CB_B 0x12025 +#define mmVPCM0_VPCM_BIAS_Y_G_CB_B 0x12025 +#define mmVPCM1_VPCM_BIAS_Y_G_CB_B 0x121C1 +#define mmVPCM_GAMCOR_CONTROL 0x12026 +#define mmVPCM0_VPCM_GAMCOR_CONTROL 0x12026 +#define mmVPCM1_VPCM_GAMCOR_CONTROL 0x121C2 +#define mmVPCM_GAMCOR_LUT_INDEX 0x12027 +#define mmVPCM0_VPCM_GAMCOR_LUT_INDEX 0x12027 +#define mmVPCM1_VPCM_GAMCOR_LUT_INDEX 0x121C3 +#define mmVPCM_GAMCOR_LUT_DATA 0x12028 +#define mmVPCM0_VPCM_GAMCOR_LUT_DATA 0x12028 +#define mmVPCM1_VPCM_GAMCOR_LUT_DATA 0x121C4 +#define mmVPCM_GAMCOR_LUT_CONTROL 0x12029 +#define mmVPCM0_VPCM_GAMCOR_LUT_CONTROL 0x12029 +#define mmVPCM1_VPCM_GAMCOR_LUT_CONTROL 0x121C5 +#define mmVPCM_GAMCOR_RAMA_START_CNTL_B 0x1202A +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_CNTL_B 0x1202A +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_CNTL_B 0x121C6 +#define mmVPCM_GAMCOR_RAMA_START_CNTL_G 0x1202B +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_CNTL_G 0x1202B +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_CNTL_G 0x121C7 +#define mmVPCM_GAMCOR_RAMA_START_CNTL_R 0x1202C +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_CNTL_R 0x1202C +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_CNTL_R 0x121C8 +#define mmVPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1202D +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1202D +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x121C9 +#define mmVPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1202E +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1202E +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x121CA +#define mmVPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1202F +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1202F +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x121CB +#define mmVPCM_GAMCOR_RAMA_START_BASE_CNTL_B 0x12030 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_BASE_CNTL_B 0x12030 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_BASE_CNTL_B 0x121CC +#define mmVPCM_GAMCOR_RAMA_START_BASE_CNTL_G 0x12031 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_BASE_CNTL_G 0x12031 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_BASE_CNTL_G 0x121CD +#define mmVPCM_GAMCOR_RAMA_START_BASE_CNTL_R 0x12032 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_BASE_CNTL_R 0x12032 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_BASE_CNTL_R 0x121CE +#define mmVPCM_GAMCOR_RAMA_END_CNTL1_B 0x12033 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL1_B 0x12033 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL1_B 0x121CF +#define mmVPCM_GAMCOR_RAMA_END_CNTL2_B 0x12034 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL2_B 0x12034 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL2_B 0x121D0 +#define mmVPCM_GAMCOR_RAMA_END_CNTL1_G 0x12035 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL1_G 0x12035 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL1_G 0x121D1 +#define mmVPCM_GAMCOR_RAMA_END_CNTL2_G 0x12036 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL2_G 0x12036 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL2_G 0x121D2 +#define mmVPCM_GAMCOR_RAMA_END_CNTL1_R 0x12037 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL1_R 0x12037 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL1_R 0x121D3 +#define mmVPCM_GAMCOR_RAMA_END_CNTL2_R 0x12038 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL2_R 0x12038 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL2_R 0x121D4 +#define mmVPCM_GAMCOR_RAMA_OFFSET_B 0x12039 +#define mmVPCM0_VPCM_GAMCOR_RAMA_OFFSET_B 0x12039 +#define mmVPCM1_VPCM_GAMCOR_RAMA_OFFSET_B 0x121D5 +#define mmVPCM_GAMCOR_RAMA_OFFSET_G 0x1203A +#define mmVPCM0_VPCM_GAMCOR_RAMA_OFFSET_G 0x1203A +#define mmVPCM1_VPCM_GAMCOR_RAMA_OFFSET_G 0x121D6 +#define mmVPCM_GAMCOR_RAMA_OFFSET_R 0x1203B +#define mmVPCM0_VPCM_GAMCOR_RAMA_OFFSET_R 0x1203B +#define mmVPCM1_VPCM_GAMCOR_RAMA_OFFSET_R 0x121D7 +#define mmVPCM_GAMCOR_RAMA_REGION_0_1 0x1203C +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_0_1 0x1203C +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_0_1 0x121D8 +#define mmVPCM_GAMCOR_RAMA_REGION_2_3 0x1203D +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_2_3 0x1203D +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_2_3 0x121D9 +#define mmVPCM_GAMCOR_RAMA_REGION_4_5 0x1203E +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_4_5 0x1203E +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_4_5 0x121DA +#define mmVPCM_GAMCOR_RAMA_REGION_6_7 0x1203F +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_6_7 0x1203F +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_6_7 0x121DB +#define mmVPCM_GAMCOR_RAMA_REGION_8_9 0x12040 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_8_9 0x12040 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_8_9 0x121DC +#define mmVPCM_GAMCOR_RAMA_REGION_10_11 0x12041 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_10_11 0x12041 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_10_11 0x121DD +#define mmVPCM_GAMCOR_RAMA_REGION_12_13 0x12042 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_12_13 0x12042 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_12_13 0x121DE +#define mmVPCM_GAMCOR_RAMA_REGION_14_15 0x12043 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_14_15 0x12043 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_14_15 0x121DF +#define mmVPCM_GAMCOR_RAMA_REGION_16_17 0x12044 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_16_17 0x12044 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_16_17 0x121E0 +#define mmVPCM_GAMCOR_RAMA_REGION_18_19 0x12045 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_18_19 0x12045 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_18_19 0x121E1 +#define mmVPCM_GAMCOR_RAMA_REGION_20_21 0x12046 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_20_21 0x12046 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_20_21 0x121E2 +#define mmVPCM_GAMCOR_RAMA_REGION_22_23 0x12047 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_22_23 0x12047 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_22_23 0x121E3 +#define mmVPCM_GAMCOR_RAMA_REGION_24_25 0x12048 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_24_25 0x12048 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_24_25 0x121E4 +#define mmVPCM_GAMCOR_RAMA_REGION_26_27 0x12049 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_26_27 0x12049 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_26_27 0x121E5 +#define mmVPCM_GAMCOR_RAMA_REGION_28_29 0x1204A +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_28_29 0x1204A +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_28_29 0x121E6 +#define mmVPCM_GAMCOR_RAMA_REGION_30_31 0x1204B +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_30_31 0x1204B +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_30_31 0x121E7 +#define mmVPCM_GAMCOR_RAMA_REGION_32_33 0x1204C +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_32_33 0x1204C +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_32_33 0x121E8 +#define mmVPCM_HDR_MULT_COEF 0x1204D +#define mmVPCM0_VPCM_HDR_MULT_COEF 0x1204D +#define mmVPCM1_VPCM_HDR_MULT_COEF 0x121E9 +#define mmVPCM_MEM_PWR_CTRL 0x1204E +#define mmVPCM0_VPCM_MEM_PWR_CTRL 0x1204E +#define mmVPCM1_VPCM_MEM_PWR_CTRL 0x121EA +#define mmVPCM_MEM_PWR_STATUS 0x1204F +#define mmVPCM0_VPCM_MEM_PWR_STATUS 0x1204F +#define mmVPCM1_VPCM_MEM_PWR_STATUS 0x121EB +#define mmVPCM_DEALPHA 0x12051 +#define mmVPCM0_VPCM_DEALPHA 0x12051 +#define mmVPCM1_VPCM_DEALPHA 0x121ED +#define mmVPCM_COEF_FORMAT 0x12052 +#define mmVPCM0_VPCM_COEF_FORMAT 0x12052 +#define mmVPCM1_VPCM_COEF_FORMAT 0x121EE +#define mmVPCM_TEST_DEBUG_INDEX 0x12053 +#define mmVPCM0_VPCM_TEST_DEBUG_INDEX 0x12053 +#define mmVPCM1_VPCM_TEST_DEBUG_INDEX 0x121EF +#define mmVPCM_TEST_DEBUG_DATA 0x12054 +#define mmVPCM0_VPCM_TEST_DEBUG_DATA 0x12054 +#define mmVPCM1_VPCM_TEST_DEBUG_DATA 0x121F0 +#define mmVPCM_HIST_CNTL 0x12055 +#define mmVPCM0_VPCM_HIST_CNTL 0x12055 +#define mmVPCM1_VPCM_HIST_CNTL 0x121F1 +#define mmVPCM_HIST_SCALE_SRC1 0x12056 +#define mmVPCM0_VPCM_HIST_SCALE_SRC1 0x12056 +#define mmVPCM1_VPCM_HIST_SCALE_SRC1 0x121F2 +#define mmVPCM_HIST_COEFA_SRC2 0x12057 +#define mmVPCM0_VPCM_HIST_COEFA_SRC2 0x12057 +#define mmVPCM1_VPCM_HIST_COEFA_SRC2 0x121F3 +#define mmVPCM_HIST_COEFB_SRC2 0x12058 +#define mmVPCM0_VPCM_HIST_COEFB_SRC2 0x12058 +#define mmVPCM1_VPCM_HIST_COEFB_SRC2 0x121F4 +#define mmVPCM_HIST_COEFC_SRC2 0x12059 +#define mmVPCM0_VPCM_HIST_COEFC_SRC2 0x12059 +#define mmVPCM1_VPCM_HIST_COEFC_SRC2 0x121F5 +#define mmVPCM_HIST_SCALE_SRC3 0x1205A +#define mmVPCM0_VPCM_HIST_SCALE_SRC3 0x1205A +#define mmVPCM1_VPCM_HIST_SCALE_SRC3 0x121F6 +#define mmVPCM_HIST_BIAS_SRC1 0x1205B +#define mmVPCM0_VPCM_HIST_BIAS_SRC1 0x1205B +#define mmVPCM1_VPCM_HIST_BIAS_SRC1 0x121F7 +#define mmVPCM_HIST_BIAS_SRC2 0x1205C +#define mmVPCM0_VPCM_HIST_BIAS_SRC2 0x1205C +#define mmVPCM1_VPCM_HIST_BIAS_SRC2 0x121F8 +#define mmVPCM_HIST_BIAS_SRC3 0x1205D +#define mmVPCM0_VPCM_HIST_BIAS_SRC3 0x1205D +#define mmVPCM1_VPCM_HIST_BIAS_SRC3 0x121F9 +#define mmVPCM_HIST_LOCK 0x1205E +#define mmVPCM0_VPCM_HIST_LOCK 0x1205E +#define mmVPCM1_VPCM_HIST_LOCK 0x121FA +#define mmVPCM_HIST_INDEX 0x1205F +#define mmVPCM0_VPCM_HIST_INDEX 0x1205F +#define mmVPCM1_VPCM_HIST_INDEX 0x121FB +#define mmVPCM_HIST_DATA 0x12060 +#define mmVPCM0_VPCM_HIST_DATA 0x12060 +#define mmVPCM1_VPCM_HIST_DATA 0x121FC +#define mmVPCM_HIST_STATUS 0x12061 +#define mmVPCM0_VPCM_HIST_STATUS 0x12061 +#define mmVPCM1_VPCM_HIST_STATUS 0x121FD + + +// Registers from VPDPP_TOP block + +#define mmVPDPP_CONTROL 0x11F38 +#define mmVPDPP_TOP0_VPDPP_CONTROL 0x11F38 +#define mmVPDPP_TOP1_VPDPP_CONTROL 0x120D4 +#define mmVPDPP_SOFT_RESET 0x11F39 +#define mmVPDPP_TOP0_VPDPP_SOFT_RESET 0x11F39 +#define mmVPDPP_TOP1_VPDPP_SOFT_RESET 0x120D5 +#define mmVPDPP_CRC_VAL_R_G 0x11F3A +#define mmVPDPP_TOP0_VPDPP_CRC_VAL_R_G 0x11F3A +#define mmVPDPP_TOP1_VPDPP_CRC_VAL_R_G 0x120D6 +#define mmVPDPP_CRC_VAL_B_A 0x11F3B +#define mmVPDPP_TOP0_VPDPP_CRC_VAL_B_A 0x11F3B +#define mmVPDPP_TOP1_VPDPP_CRC_VAL_B_A 0x120D7 +#define mmVPDPP_CRC_CTRL 0x11F3C +#define mmVPDPP_TOP0_VPDPP_CRC_CTRL 0x11F3C +#define mmVPDPP_TOP1_VPDPP_CRC_CTRL 0x120D8 +#define mmVPHOST_READ_CONTROL 0x11F3D +#define mmVPDPP_TOP0_VPHOST_READ_CONTROL 0x11F3D +#define mmVPDPP_TOP1_VPHOST_READ_CONTROL 0x120D9 +#define mmVPDPP_DEBUG_SEL 0x11F3E +#define mmVPDPP_TOP0_VPDPP_DEBUG_SEL 0x11F3E +#define mmVPDPP_TOP1_VPDPP_DEBUG_SEL 0x120DA +#define mmVPDPP_DEBUG_SPARE 0x11F3F +#define mmVPDPP_TOP0_VPDPP_DEBUG_SPARE 0x11F3F +#define mmVPDPP_TOP1_VPDPP_DEBUG_SPARE 0x120DB +#define mmVPDPP_TEST_DEBUG_INDEX 0x11F40 +#define mmVPDPP_TOP0_VPDPP_TEST_DEBUG_INDEX 0x11F40 +#define mmVPDPP_TOP1_VPDPP_TEST_DEBUG_INDEX 0x120DC +#define mmVPDPP_TEST_DEBUG_DATA 0x11F41 +#define mmVPDPP_TOP0_VPDPP_TEST_DEBUG_DATA 0x11F41 +#define mmVPDPP_TOP1_VPDPP_TEST_DEBUG_DATA 0x120DD + + +// Registers from VPMPC_CFG block + +#define mmVPMPC_CLOCK_CONTROL 0x12768 +#define mmVPMPC_SOFT_RESET 0x12769 +#define mmVPMPC_CRC_CTRL 0x1276A +#define mmVPMPC_CRC_SEL_CONTROL 0x1276B +#define mmVPMPC_CRC_RESULT_AR 0x1276C +#define mmVPMPC_CRC_RESULT_GB 0x1276D +#define mmVPMPC_CRC_RESULT_C 0x1276E +#define mmVPMPC_DEBUG_CONTROL 0x1276F +#define mmVPMPCC_DEBUG_DATA_SELECT 0x12770 +#define mmVPMPC_BYPASS_BG_AR 0x12771 +#define mmVPMPC_BYPASS_BG_GB 0x12772 +#define mmVPMPC_HOST_READ_CONTROL 0x12773 +#define mmVPMPC_PENDING_STATUS_MISC 0x12774 +#define mmVPMPC_VPCDC0_3DLUT_FL_CONFIG 0x12775 +#define mmVPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE 0x12776 +#define mmVPMPC_CFG_TEST_DEBUG_INDEX 0x12778 +#define mmVPMPC_CFG_TEST_DEBUG_DATA 0x12779 + + +// Registers from VPMPC_OCSC block + +#define mmVPMPC_OUT0_MUX 0x12789 +#define mmVPMPC_OUT0_FLOAT_CONTROL 0x1278A +#define mmVPMPC_OUT0_DENORM_CONTROL 0x1278B +#define mmVPMPC_OUT0_DENORM_CLAMP_G_Y 0x1278C +#define mmVPMPC_OUT0_DENORM_CLAMP_B_CB 0x1278D +#define mmVPMPC_OUT1_MUX 0x1278E +#define mmVPMPC_OUT1_FLOAT_CONTROL 0x1278F +#define mmVPMPC_OUT1_DENORM_CONTROL 0x12790 +#define mmVPMPC_OUT1_DENORM_CLAMP_G_Y 0x12791 +#define mmVPMPC_OUT1_DENORM_CLAMP_B_CB 0x12792 +#define mmVPMPC_OUT_CSC_COEF_FORMAT 0x1279D +#define mmVPMPC_OUT0_CSC_MODE 0x1279E +#define mmVPMPC_OUT0_CSC_C11_C12_A 0x1279F +#define mmVPMPC_OUT0_CSC_C13_C14_A 0x127A0 +#define mmVPMPC_OUT0_CSC_C21_C22_A 0x127A1 +#define mmVPMPC_OUT0_CSC_C23_C24_A 0x127A2 +#define mmVPMPC_OUT0_CSC_C31_C32_A 0x127A3 +#define mmVPMPC_OUT0_CSC_C33_C34_A 0x127A4 +#define mmVPMPC_OUT1_CSC_MODE 0x127A5 +#define mmVPMPC_OUT1_CSC_C11_C12_A 0x127A6 +#define mmVPMPC_OUT1_CSC_C13_C14_A 0x127A7 +#define mmVPMPC_OUT1_CSC_C21_C22_A 0x127A8 +#define mmVPMPC_OUT1_CSC_C23_C24_A 0x127A9 +#define mmVPMPC_OUT1_CSC_C31_C32_A 0x127AA +#define mmVPMPC_OUT1_CSC_C33_C34_A 0x127AB +#define mmVPMPC_OCSC_TEST_DEBUG_INDEX 0x127BB +#define mmVPMPC_OCSC_TEST_DEBUG_DATA 0x127BC + + +// Registers from VPMPCC block + +#define mmVPMPCC_TOP_SEL 0x125C0 +#define mmVPMPCC0_VPMPCC_TOP_SEL 0x125C0 +#define mmVPMPCC1_VPMPCC_TOP_SEL 0x125D5 +#define mmVPMPCC_BOT_SEL 0x125C1 +#define mmVPMPCC0_VPMPCC_BOT_SEL 0x125C1 +#define mmVPMPCC1_VPMPCC_BOT_SEL 0x125D6 +#define mmVPMPCC_VPOPP_ID 0x125C2 +#define mmVPMPCC0_VPMPCC_VPOPP_ID 0x125C2 +#define mmVPMPCC1_VPMPCC_VPOPP_ID 0x125D7 +#define mmVPMPCC_CONTROL 0x125C3 +#define mmVPMPCC0_VPMPCC_CONTROL 0x125C3 +#define mmVPMPCC1_VPMPCC_CONTROL 0x125D8 +#define mmVPMPCC_CONTROL2 0x125C4 +#define mmVPMPCC0_VPMPCC_CONTROL2 0x125C4 +#define mmVPMPCC1_VPMPCC_CONTROL2 0x125D9 +#define mmVPMPCC_TOP_GAIN 0x125C5 +#define mmVPMPCC0_VPMPCC_TOP_GAIN 0x125C5 +#define mmVPMPCC1_VPMPCC_TOP_GAIN 0x125DA +#define mmVPMPCC_BOT_GAIN_INSIDE 0x125C6 +#define mmVPMPCC0_VPMPCC_BOT_GAIN_INSIDE 0x125C6 +#define mmVPMPCC1_VPMPCC_BOT_GAIN_INSIDE 0x125DB +#define mmVPMPCC_BOT_GAIN_OUTSIDE 0x125C7 +#define mmVPMPCC0_VPMPCC_BOT_GAIN_OUTSIDE 0x125C7 +#define mmVPMPCC1_VPMPCC_BOT_GAIN_OUTSIDE 0x125DC +#define mmVPMPCC_MOVABLE_CM_LOCATION_CONTROL 0x125C8 +#define mmVPMPCC0_VPMPCC_MOVABLE_CM_LOCATION_CONTROL 0x125C8 +#define mmVPMPCC1_VPMPCC_MOVABLE_CM_LOCATION_CONTROL 0x125DD +#define mmVPMPCC_BG_R_CR 0x125C9 +#define mmVPMPCC0_VPMPCC_BG_R_CR 0x125C9 +#define mmVPMPCC1_VPMPCC_BG_R_CR 0x125DE +#define mmVPMPCC_BG_G_Y 0x125CA +#define mmVPMPCC0_VPMPCC_BG_G_Y 0x125CA +#define mmVPMPCC1_VPMPCC_BG_G_Y 0x125DF +#define mmVPMPCC_BG_B_CB 0x125CB +#define mmVPMPCC0_VPMPCC_BG_B_CB 0x125CB +#define mmVPMPCC1_VPMPCC_BG_B_CB 0x125E0 +#define mmVPMPCC_MEM_PWR_CTRL 0x125CC +#define mmVPMPCC0_VPMPCC_MEM_PWR_CTRL 0x125CC +#define mmVPMPCC1_VPMPCC_MEM_PWR_CTRL 0x125E1 +#define mmVPMPCC_STATUS 0x125CD +#define mmVPMPCC0_VPMPCC_STATUS 0x125CD +#define mmVPMPCC1_VPMPCC_STATUS 0x125E2 +#define mmVPMPCC_TEST_DEBUG_INDEX 0x125CF +#define mmVPMPCC0_VPMPCC_TEST_DEBUG_INDEX 0x125CF +#define mmVPMPCC1_VPMPCC_TEST_DEBUG_INDEX 0x125E4 +#define mmVPMPCC_TEST_DEBUG_DATA 0x125D0 +#define mmVPMPCC0_VPMPCC_TEST_DEBUG_DATA 0x125D0 +#define mmVPMPCC1_VPMPCC_TEST_DEBUG_DATA 0x125E5 + + +// Registers from VPMPCC_OGAM block + +#define mmVPMPCC_OGAM_CONTROL 0x12614 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_CONTROL 0x12614 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_CONTROL 0x1264B +#define mmVPMPCC_OGAM_LUT_INDEX 0x12615 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_LUT_INDEX 0x12615 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_LUT_INDEX 0x1264C +#define mmVPMPCC_OGAM_LUT_DATA 0x12616 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_LUT_DATA 0x12616 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_LUT_DATA 0x1264D +#define mmVPMPCC_OGAM_LUT_CONTROL 0x12617 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_LUT_CONTROL 0x12617 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_LUT_CONTROL 0x1264E +#define mmVPMPCC_OGAM_RAMA_START_CNTL_B 0x12618 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_CNTL_B 0x12618 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_CNTL_B 0x1264F +#define mmVPMPCC_OGAM_RAMA_START_CNTL_G 0x12619 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_CNTL_G 0x12619 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_CNTL_G 0x12650 +#define mmVPMPCC_OGAM_RAMA_START_CNTL_R 0x1261A +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_CNTL_R 0x1261A +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_CNTL_R 0x12651 +#define mmVPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x1261B +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x1261B +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x12652 +#define mmVPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x1261C +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x1261C +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x12653 +#define mmVPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x1261D +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x1261D +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x12654 +#define mmVPMPCC_OGAM_RAMA_START_BASE_CNTL_B 0x1261E +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_BASE_CNTL_B 0x1261E +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_BASE_CNTL_B 0x12655 +#define mmVPMPCC_OGAM_RAMA_START_BASE_CNTL_G 0x1261F +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_BASE_CNTL_G 0x1261F +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_BASE_CNTL_G 0x12656 +#define mmVPMPCC_OGAM_RAMA_START_BASE_CNTL_R 0x12620 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_BASE_CNTL_R 0x12620 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_BASE_CNTL_R 0x12657 +#define mmVPMPCC_OGAM_RAMA_END_CNTL1_B 0x12621 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL1_B 0x12621 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL1_B 0x12658 +#define mmVPMPCC_OGAM_RAMA_END_CNTL2_B 0x12622 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL2_B 0x12622 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL2_B 0x12659 +#define mmVPMPCC_OGAM_RAMA_END_CNTL1_G 0x12623 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL1_G 0x12623 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL1_G 0x1265A +#define mmVPMPCC_OGAM_RAMA_END_CNTL2_G 0x12624 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL2_G 0x12624 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL2_G 0x1265B +#define mmVPMPCC_OGAM_RAMA_END_CNTL1_R 0x12625 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL1_R 0x12625 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL1_R 0x1265C +#define mmVPMPCC_OGAM_RAMA_END_CNTL2_R 0x12626 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL2_R 0x12626 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL2_R 0x1265D +#define mmVPMPCC_OGAM_RAMA_OFFSET_B 0x12627 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_OFFSET_B 0x12627 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_OFFSET_B 0x1265E +#define mmVPMPCC_OGAM_RAMA_OFFSET_G 0x12628 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_OFFSET_G 0x12628 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_OFFSET_G 0x1265F +#define mmVPMPCC_OGAM_RAMA_OFFSET_R 0x12629 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_OFFSET_R 0x12629 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_OFFSET_R 0x12660 +#define mmVPMPCC_OGAM_RAMA_REGION_0_1 0x1262A +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_0_1 0x1262A +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_0_1 0x12661 +#define mmVPMPCC_OGAM_RAMA_REGION_2_3 0x1262B +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_2_3 0x1262B +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_2_3 0x12662 +#define mmVPMPCC_OGAM_RAMA_REGION_4_5 0x1262C +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_4_5 0x1262C +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_4_5 0x12663 +#define mmVPMPCC_OGAM_RAMA_REGION_6_7 0x1262D +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_6_7 0x1262D +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_6_7 0x12664 +#define mmVPMPCC_OGAM_RAMA_REGION_8_9 0x1262E +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_8_9 0x1262E +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_8_9 0x12665 +#define mmVPMPCC_OGAM_RAMA_REGION_10_11 0x1262F +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_10_11 0x1262F +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_10_11 0x12666 +#define mmVPMPCC_OGAM_RAMA_REGION_12_13 0x12630 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_12_13 0x12630 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_12_13 0x12667 +#define mmVPMPCC_OGAM_RAMA_REGION_14_15 0x12631 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_14_15 0x12631 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_14_15 0x12668 +#define mmVPMPCC_OGAM_RAMA_REGION_16_17 0x12632 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_16_17 0x12632 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_16_17 0x12669 +#define mmVPMPCC_OGAM_RAMA_REGION_18_19 0x12633 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_18_19 0x12633 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_18_19 0x1266A +#define mmVPMPCC_OGAM_RAMA_REGION_20_21 0x12634 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_20_21 0x12634 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_20_21 0x1266B +#define mmVPMPCC_OGAM_RAMA_REGION_22_23 0x12635 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_22_23 0x12635 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_22_23 0x1266C +#define mmVPMPCC_OGAM_RAMA_REGION_24_25 0x12636 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_24_25 0x12636 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_24_25 0x1266D +#define mmVPMPCC_OGAM_RAMA_REGION_26_27 0x12637 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_26_27 0x12637 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_26_27 0x1266E +#define mmVPMPCC_OGAM_RAMA_REGION_28_29 0x12638 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_28_29 0x12638 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_28_29 0x1266F +#define mmVPMPCC_OGAM_RAMA_REGION_30_31 0x12639 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_30_31 0x12639 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_30_31 0x12670 +#define mmVPMPCC_OGAM_RAMA_REGION_32_33 0x1263A +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_32_33 0x1263A +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_32_33 0x12671 +#define mmVPMPCC_GAMUT_REMAP_COEF_FORMAT 0x1263B +#define mmVPMPCC_OGAM0_VPMPCC_GAMUT_REMAP_COEF_FORMAT 0x1263B +#define mmVPMPCC_OGAM1_VPMPCC_GAMUT_REMAP_COEF_FORMAT 0x12672 +#define mmVPMPCC_GAMUT_REMAP_MODE 0x1263C +#define mmVPMPCC_OGAM0_VPMPCC_GAMUT_REMAP_MODE 0x1263C +#define mmVPMPCC_OGAM1_VPMPCC_GAMUT_REMAP_MODE 0x12673 +#define mmVPMPC_GAMUT_REMAP_C11_C12_A 0x1263D +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C11_C12_A 0x1263D +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C11_C12_A 0x12674 +#define mmVPMPC_GAMUT_REMAP_C13_C14_A 0x1263E +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C13_C14_A 0x1263E +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C13_C14_A 0x12675 +#define mmVPMPC_GAMUT_REMAP_C21_C22_A 0x1263F +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C21_C22_A 0x1263F +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C21_C22_A 0x12676 +#define mmVPMPC_GAMUT_REMAP_C23_C24_A 0x12640 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C23_C24_A 0x12640 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C23_C24_A 0x12677 +#define mmVPMPC_GAMUT_REMAP_C31_C32_A 0x12641 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C31_C32_A 0x12641 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C31_C32_A 0x12678 +#define mmVPMPC_GAMUT_REMAP_C33_C34_A 0x12642 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C33_C34_A 0x12642 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C33_C34_A 0x12679 +#define mmVPMPCC_OGAM_TEST_DEBUG_INDEX 0x12644 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_TEST_DEBUG_INDEX 0x12644 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_TEST_DEBUG_INDEX 0x1267B +#define mmVPMPCC_OGAM_TEST_DEBUG_DATA 0x12645 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_TEST_DEBUG_DATA 0x12645 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_TEST_DEBUG_DATA 0x1267C + + +// Registers from VPMPCC_MCM block + +#define mmVPMPCC_MCM_1DLUT_CONTROL 0x12882 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_CONTROL 0x12882 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_CONTROL 0x12912 +#define mmVPMPCC_MCM_1DLUT_LUT_INDEX 0x12883 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_LUT_INDEX 0x12883 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_LUT_INDEX 0x12913 +#define mmVPMPCC_MCM_1DLUT_LUT_DATA 0x12884 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_LUT_DATA 0x12884 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_LUT_DATA 0x12914 +#define mmVPMPCC_MCM_1DLUT_LUT_CONTROL 0x12885 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_LUT_CONTROL 0x12885 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_LUT_CONTROL 0x12915 +#define mmVPMPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x12886 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x12886 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x12916 +#define mmVPMPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x12887 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x12887 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x12917 +#define mmVPMPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x12888 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x12888 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x12918 +#define mmVPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x12889 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x12889 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x12919 +#define mmVPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x1288A +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x1288A +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x1291A +#define mmVPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x1288B +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x1288B +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x1291B +#define mmVPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x1288C +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x1288C +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x1291C +#define mmVPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x1288D +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x1288D +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x1291D +#define mmVPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x1288E +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x1288E +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x1291E +#define mmVPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x1288F +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x1288F +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x1291F +#define mmVPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x12890 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x12890 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x12920 +#define mmVPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x12891 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x12891 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x12921 +#define mmVPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x12892 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x12892 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x12922 +#define mmVPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x12893 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x12893 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x12923 +#define mmVPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x12894 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x12894 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x12924 +#define mmVPMPCC_MCM_1DLUT_RAMA_OFFSET_B 0x12895 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_OFFSET_B 0x12895 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_OFFSET_B 0x12925 +#define mmVPMPCC_MCM_1DLUT_RAMA_OFFSET_G 0x12896 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_OFFSET_G 0x12896 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_OFFSET_G 0x12926 +#define mmVPMPCC_MCM_1DLUT_RAMA_OFFSET_R 0x12897 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_OFFSET_R 0x12897 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_OFFSET_R 0x12927 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_0_1 0x12898 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_0_1 0x12898 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_0_1 0x12928 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_2_3 0x12899 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_2_3 0x12899 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_2_3 0x12929 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_4_5 0x1289A +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_4_5 0x1289A +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_4_5 0x1292A +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_6_7 0x1289B +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_6_7 0x1289B +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_6_7 0x1292B +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_8_9 0x1289C +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_8_9 0x1289C +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_8_9 0x1292C +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_10_11 0x1289D +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_10_11 0x1289D +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_10_11 0x1292D +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_12_13 0x1289E +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_12_13 0x1289E +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_12_13 0x1292E +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_14_15 0x1289F +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_14_15 0x1289F +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_14_15 0x1292F +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_16_17 0x128A0 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_16_17 0x128A0 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_16_17 0x12930 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_18_19 0x128A1 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_18_19 0x128A1 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_18_19 0x12931 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_20_21 0x128A2 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_20_21 0x128A2 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_20_21 0x12932 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_22_23 0x128A3 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_22_23 0x128A3 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_22_23 0x12933 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_24_25 0x128A4 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_24_25 0x128A4 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_24_25 0x12934 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_26_27 0x128A5 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_26_27 0x128A5 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_26_27 0x12935 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_28_29 0x128A6 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_28_29 0x128A6 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_28_29 0x12936 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_30_31 0x128A7 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_30_31 0x128A7 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_30_31 0x12937 +#define mmVPMPCC_MCM_1DLUT_RAMA_REGION_32_33 0x128A8 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_32_33 0x128A8 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_32_33 0x12938 +#define mmVPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT 0x128A9 +#define mmVPMPCC_MCM0_VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT 0x128A9 +#define mmVPMPCC_MCM1_VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT 0x12939 +#define mmVPMPCC_MCM_FIRST_GAMUT_REMAP_MODE 0x128AA +#define mmVPMPCC_MCM0_VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE 0x128AA +#define mmVPMPCC_MCM1_VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE 0x1293A +#define mmVPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA 0x128AB +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA 0x128AB +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA 0x1293B +#define mmVPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA 0x128AC +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA 0x128AC +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA 0x1293C +#define mmVPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA 0x128AD +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA 0x128AD +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA 0x1293D +#define mmVPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA 0x128AE +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA 0x128AE +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA 0x1293E +#define mmVPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA 0x128AF +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA 0x128AF +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA 0x1293F +#define mmVPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA 0x128B0 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA 0x128B0 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA 0x12940 +#define mmVPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT 0x128B1 +#define mmVPMPCC_MCM0_VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT 0x128B1 +#define mmVPMPCC_MCM1_VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT 0x12941 +#define mmVPMPCC_MCM_SECOND_GAMUT_REMAP_MODE 0x128B2 +#define mmVPMPCC_MCM0_VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE 0x128B2 +#define mmVPMPCC_MCM1_VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE 0x12942 +#define mmVPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA 0x128B3 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA 0x128B3 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA 0x12943 +#define mmVPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA 0x128B4 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA 0x128B4 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA 0x12944 +#define mmVPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA 0x128B5 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA 0x128B5 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA 0x12945 +#define mmVPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA 0x128B6 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA 0x128B6 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA 0x12946 +#define mmVPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA 0x128B7 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA 0x128B7 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA 0x12947 +#define mmVPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA 0x128B8 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA 0x128B8 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA 0x12948 +#define mmVPMPCC_MCM_MEM_PWR_CTRL 0x128B9 +#define mmVPMPCC_MCM0_VPMPCC_MCM_MEM_PWR_CTRL 0x128B9 +#define mmVPMPCC_MCM1_VPMPCC_MCM_MEM_PWR_CTRL 0x12949 +#define mmVPMPCC_MCM_TEST_DEBUG_INDEX 0x128BC +#define mmVPMPCC_MCM0_VPMPCC_MCM_TEST_DEBUG_INDEX 0x128BC +#define mmVPMPCC_MCM1_VPMPCC_MCM_TEST_DEBUG_INDEX 0x1294C +#define mmVPMPCC_MCM_TEST_DEBUG_DATA 0x128BD +#define mmVPMPCC_MCM0_VPMPCC_MCM_TEST_DEBUG_DATA 0x128BD +#define mmVPMPCC_MCM1_VPMPCC_MCM_TEST_DEBUG_DATA 0x1294D + + +// Registers from VPMPC_RMCM block + +#define mmVPMPC_RMCM_SHAPER_CONTROL 0x126F0 +#define mmVPMPC_RMCM_SHAPER_OFFSET_R 0x126F1 +#define mmVPMPC_RMCM_SHAPER_OFFSET_G 0x126F2 +#define mmVPMPC_RMCM_SHAPER_OFFSET_B 0x126F3 +#define mmVPMPC_RMCM_SHAPER_SCALE_R 0x126F4 +#define mmVPMPC_RMCM_SHAPER_SCALE_G_B 0x126F5 +#define mmVPMPC_RMCM_SHAPER_LUT_INDEX 0x126F6 +#define mmVPMPC_RMCM_SHAPER_LUT_DATA 0x126F7 +#define mmVPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK 0x126F8 +#define mmVPMPC_RMCM_SHAPER_RAMA_START_CNTL_B 0x126F9 +#define mmVPMPC_RMCM_SHAPER_RAMA_START_CNTL_G 0x126FA +#define mmVPMPC_RMCM_SHAPER_RAMA_START_CNTL_R 0x126FB +#define mmVPMPC_RMCM_SHAPER_RAMA_END_CNTL_B 0x126FC +#define mmVPMPC_RMCM_SHAPER_RAMA_END_CNTL_G 0x126FD +#define mmVPMPC_RMCM_SHAPER_RAMA_END_CNTL_R 0x126FE +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_0_1 0x126FF +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_2_3 0x12700 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_4_5 0x12701 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_6_7 0x12702 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_8_9 0x12703 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_10_11 0x12704 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_12_13 0x12705 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_14_15 0x12706 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_16_17 0x12707 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_18_19 0x12708 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_20_21 0x12709 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_22_23 0x1270A +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_24_25 0x1270B +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_26_27 0x1270C +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_28_29 0x1270D +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_30_31 0x1270E +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_32_33 0x1270F +#define mmVPMPC_RMCM_3DLUT_MODE 0x12710 +#define mmVPMPC_RMCM_3DLUT_INDEX 0x12711 +#define mmVPMPC_RMCM_3DLUT_DATA 0x12712 +#define mmVPMPC_RMCM_3DLUT_DATA_30BIT 0x12713 +#define mmVPMPC_RMCM_3DLUT_READ_WRITE_CONTROL 0x12714 +#define mmVPMPC_RMCM_3DLUT_OUT_NORM_FACTOR 0x12715 +#define mmVPMPC_RMCM_3DLUT_OUT_OFFSET_R 0x12716 +#define mmVPMPC_RMCM_3DLUT_OUT_OFFSET_G 0x12717 +#define mmVPMPC_RMCM_3DLUT_OUT_OFFSET_B 0x12718 +#define mmVPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT 0x12719 +#define mmVPMPC_RMCM_GAMUT_REMAP_MODE 0x1271A +#define mmVPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA 0x1271B +#define mmVPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA 0x1271C +#define mmVPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA 0x1271D +#define mmVPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA 0x1271E +#define mmVPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA 0x1271F +#define mmVPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA 0x12720 +#define mmVPMPC_RMCM_MEM_PWR_CTRL 0x12721 +#define mmVPMPC_RMCM_3DLUT_FAST_LOAD_SELECT 0x12722 +#define mmVPMPC_RMCM_3DLUT_FAST_LOAD_STATUS 0x12723 +#define mmVPMPC_RMCM_CNTL 0x12724 +#define mmVPMPC_RMCM_TEST_DEBUG_INDEX 0x12726 +#define mmVPMPC_RMCM_TEST_DEBUG_DATA 0x12727 + + +// Registers from VPFMT block + +#define mmVPFMT_CLAMP_COMPONENT_R 0x12AB0 +#define mmVPFMT0_VPFMT_CLAMP_COMPONENT_R 0x12AB0 +#define mmVPFMT1_VPFMT_CLAMP_COMPONENT_R 0x12AF3 +#define mmVPFMT_CLAMP_COMPONENT_G 0x12AB1 +#define mmVPFMT0_VPFMT_CLAMP_COMPONENT_G 0x12AB1 +#define mmVPFMT1_VPFMT_CLAMP_COMPONENT_G 0x12AF4 +#define mmVPFMT_CLAMP_COMPONENT_B 0x12AB2 +#define mmVPFMT0_VPFMT_CLAMP_COMPONENT_B 0x12AB2 +#define mmVPFMT1_VPFMT_CLAMP_COMPONENT_B 0x12AF5 +#define mmVPFMT_DYNAMIC_EXP_CNTL 0x12AB3 +#define mmVPFMT0_VPFMT_DYNAMIC_EXP_CNTL 0x12AB3 +#define mmVPFMT1_VPFMT_DYNAMIC_EXP_CNTL 0x12AF6 +#define mmVPFMT_CONTROL 0x12AB4 +#define mmVPFMT0_VPFMT_CONTROL 0x12AB4 +#define mmVPFMT1_VPFMT_CONTROL 0x12AF7 +#define mmVPFMT_BIT_DEPTH_CONTROL 0x12AB5 +#define mmVPFMT0_VPFMT_BIT_DEPTH_CONTROL 0x12AB5 +#define mmVPFMT1_VPFMT_BIT_DEPTH_CONTROL 0x12AF8 +#define mmVPFMT_DITHER_RAND_R_SEED 0x12AB6 +#define mmVPFMT0_VPFMT_DITHER_RAND_R_SEED 0x12AB6 +#define mmVPFMT1_VPFMT_DITHER_RAND_R_SEED 0x12AF9 +#define mmVPFMT_DITHER_RAND_G_SEED 0x12AB7 +#define mmVPFMT0_VPFMT_DITHER_RAND_G_SEED 0x12AB7 +#define mmVPFMT1_VPFMT_DITHER_RAND_G_SEED 0x12AFA +#define mmVPFMT_DITHER_RAND_B_SEED 0x12AB8 +#define mmVPFMT0_VPFMT_DITHER_RAND_B_SEED 0x12AB8 +#define mmVPFMT1_VPFMT_DITHER_RAND_B_SEED 0x12AFB +#define mmVPFMT_CLAMP_CNTL 0x12AB9 +#define mmVPFMT0_VPFMT_CLAMP_CNTL 0x12AB9 +#define mmVPFMT1_VPFMT_CLAMP_CNTL 0x12AFC +#define mmVPFMT_SUBSAMPLER_MEMORY_CONTROL 0x12ABA +#define mmVPFMT0_VPFMT_SUBSAMPLER_MEMORY_CONTROL 0x12ABA +#define mmVPFMT1_VPFMT_SUBSAMPLER_MEMORY_CONTROL 0x12AFD +#define mmVPFMT_DEBUG_CNTL 0x12ABB +#define mmVPFMT0_VPFMT_DEBUG_CNTL 0x12ABB +#define mmVPFMT1_VPFMT_DEBUG_CNTL 0x12AFE +#define mmVPFMT_TEST_DEBUG_INDEX 0x12ABC +#define mmVPFMT0_VPFMT_TEST_DEBUG_INDEX 0x12ABC +#define mmVPFMT1_VPFMT_TEST_DEBUG_INDEX 0x12AFF +#define mmVPFMT_TEST_DEBUG_DATA 0x12ABD +#define mmVPFMT0_VPFMT_TEST_DEBUG_DATA 0x12ABD +#define mmVPFMT1_VPFMT_TEST_DEBUG_DATA 0x12B00 + + +// Registers from VPOPP_PIPE block + +#define mmVPOPP_PIPE_CONTROL 0x12AD8 +#define mmVPOPP_PIPE0_VPOPP_PIPE_CONTROL 0x12AD8 +#define mmVPOPP_PIPE1_VPOPP_PIPE_CONTROL 0x12B1B +#define mmVPOPP_PIPE_OUTBG_EXT1 0x12AD9 +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_EXT1 0x12AD9 +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_EXT1 0x12B1C +#define mmVPOPP_PIPE_OUTBG_EXT2 0x12ADA +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_EXT2 0x12ADA +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_EXT2 0x12B1D +#define mmVPOPP_PIPE_OUTBG_COL1 0x12ADB +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_COL1 0x12ADB +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_COL1 0x12B1E +#define mmVPOPP_PIPE_OUTBG_COL2 0x12ADC +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_COL2 0x12ADC +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_COL2 0x12B1F +#define mmVPOPP_PIPE_SPARE_DEBUG 0x12ADD +#define mmVPOPP_PIPE0_VPOPP_PIPE_SPARE_DEBUG 0x12ADD +#define mmVPOPP_PIPE1_VPOPP_PIPE_SPARE_DEBUG 0x12B20 +#define mmVPOPP_PIPE_TEST_DEBUG_INDEX 0x12ADE +#define mmVPOPP_PIPE0_VPOPP_PIPE_TEST_DEBUG_INDEX 0x12ADE +#define mmVPOPP_PIPE1_VPOPP_PIPE_TEST_DEBUG_INDEX 0x12B21 +#define mmVPOPP_PIPE_TEST_DEBUG_DATA 0x12ADF +#define mmVPOPP_PIPE0_VPOPP_PIPE_TEST_DEBUG_DATA 0x12ADF +#define mmVPOPP_PIPE1_VPOPP_PIPE_TEST_DEBUG_DATA 0x12B22 + + +// Registers from VPOPP_TOP block + +#define mmVPOPP_TOP_CLK_CONTROL 0x12BC2 +#define mmVPOPP_DEBUG_CONTROL 0x12BC3 +#define mmVPOPP_CRC_CONTROL 0x12BC4 +#define mmVPOPP_CRC_RESULT_RG 0x12BC5 +#define mmVPOPP_CRC_RESULT_BC 0x12BC6 +#define mmVPOPP_FROD_CONTROL 0x12BC7 +#define mmVPOPP_FROD_MEM_PWR_CONTROL 0x12BC8 +#define mmVPOPP_TOP_SPARE_DEBUG 0x12BC9 +#define mmVPOPP_TOP_TEST_DEBUG_INDEX 0x12BCA +#define mmVPOPP_TOP_TEST_DEBUG_DATA 0x12BCB + +#endif diff --git a/src/amd/vpelib/src/chip/vpe20/inc/asic/chip_shift.h b/src/amd/vpelib/src/chip/vpe20/inc/asic/chip_shift.h new file mode 100644 index 00000000000..b43d8a71f2c --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/inc/asic/chip_shift.h @@ -0,0 +1,4705 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#if !defined (_vpe20_SHIFT_HEADER) +#define _vpe20_SHIFT_HEADER + +// reg: VPEC_DEC_START block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_DEC_START__START__SHIFT 0x00000000 + +// reg: VPEC_UCODE_ADDR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_UCODE_ADDR__VALUE__SHIFT 0x00000000 +#define VPEC_UCODE_ADDR__THID__SHIFT 0x0000000f + +// reg: VPEC_UCODE_DATA block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_UCODE_DATA__VALUE__SHIFT 0x00000000 + +// reg: VPEC_F32_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_F32_CNTL__HALT__SHIFT 0x00000000 +#define VPEC_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x00000002 +#define VPEC_F32_CNTL__TH0_CHECKSUM_CLR__SHIFT 0x00000008 +#define VPEC_F32_CNTL__TH0_RESET__SHIFT 0x00000009 +#define VPEC_F32_CNTL__TH0_ENABLE__SHIFT 0x0000000a +#define VPEC_F32_CNTL__TH1_CHECKSUM_CLR__SHIFT 0x0000000c +#define VPEC_F32_CNTL__TH1_RESET__SHIFT 0x0000000d +#define VPEC_F32_CNTL__TH1_ENABLE__SHIFT 0x0000000e +#define VPEC_F32_CNTL__TH0_PRIORITY__SHIFT 0x00000010 +#define VPEC_F32_CNTL__TH1_PRIORITY__SHIFT 0x00000018 + +// reg: VPEC_MMHUB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_MMHUB_CNTL__UNIT_ID__SHIFT 0x00000000 + +// reg: VPEC_MMHUB_TRUSTLVL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_MMHUB_TRUSTLVL__SECLVL0__SHIFT 0x00000000 +#define VPEC_MMHUB_TRUSTLVL__SECLVL1__SHIFT 0x00000004 +#define VPEC_MMHUB_TRUSTLVL__SECLVL2__SHIFT 0x00000008 +#define VPEC_MMHUB_TRUSTLVL__SECLVL3__SHIFT 0x0000000c +#define VPEC_MMHUB_TRUSTLVL__SECLVL4__SHIFT 0x00000010 +#define VPEC_MMHUB_TRUSTLVL__SECLVL5__SHIFT 0x00000014 +#define VPEC_MMHUB_TRUSTLVL__SECLVL6__SHIFT 0x00000018 +#define VPEC_MMHUB_TRUSTLVL__SECLVL7__SHIFT 0x0000001c + +// reg: VPEC_VPEP_CTRL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_VPEP_CTRL__VPEP_SOCCLK_EN__SHIFT 0x00000000 +#define VPEC_VPEP_CTRL__VPEP_SW_RESETB__SHIFT 0x00000001 +#define VPEC_VPEP_CTRL__RESERVED__SHIFT 0x00000002 +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P0__SHIFT 0x00000016 +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P1__SHIFT 0x00000017 +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P2__SHIFT 0x00000018 +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P0__SHIFT 0x00000019 +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P1__SHIFT 0x0000001a +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P2__SHIFT 0x0000001b +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_3DLUT__SHIFT 0x0000001c +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEC_VPEP_REG_FGCLKEN__SHIFT 0x0000001d +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEP_SOCCLK__SHIFT 0x0000001e +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPECLK__SHIFT 0x0000001f + +// reg: VPEC_CLK_CTRL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_CLK_CTRL__VPECLK_EN__SHIFT 0x00000001 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE0_CLK__SHIFT 0x00000008 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE1_CLK__SHIFT 0x00000009 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE2_CLK__SHIFT 0x0000000a +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE3_CLK__SHIFT 0x0000000b +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE4_CLK__SHIFT 0x0000000c +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE5_CLK__SHIFT 0x0000000d +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE0_CLK__SHIFT 0x00000010 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE1_CLK__SHIFT 0x00000011 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE2_CLK__SHIFT 0x00000012 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE3_CLK__SHIFT 0x00000013 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE4_CLK__SHIFT 0x00000014 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE5_CLK__SHIFT 0x00000015 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE6_CLK__SHIFT 0x00000016 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE7_CLK__SHIFT 0x00000017 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE8_CLK__SHIFT 0x00000018 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE9_CLK__SHIFT 0x00000019 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_PERF_CLK__SHIFT 0x0000001b +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_CE_CLK__SHIFT 0x0000001c +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_F32_CLK__SHIFT 0x0000001d +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_DYN_CLK__SHIFT 0x0000001e +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_REG_CLK__SHIFT 0x0000001f + +// reg: VPEC_COLLABORATE_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_COLLABORATE_CNTL__COLLABORATE_MODE_EN__SHIFT 0x00000000 + +// reg: VPEC_COLLABORATE_CFG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_COLLABORATE_CFG__MASTER_ID__SHIFT 0x00000000 +#define VPEC_COLLABORATE_CFG__MASTER_EN__SHIFT 0x00000003 +#define VPEC_COLLABORATE_CFG__SLAVE0_ID__SHIFT 0x00000004 +#define VPEC_COLLABORATE_CFG__SLAVE0_EN__SHIFT 0x00000007 + +// reg: VPEC_POWER_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_POWER_CNTL__LS_ENABLE__SHIFT 0x00000000 +#define VPEC_POWER_CNTL__UCODE_SRAM_DS_EN__SHIFT 0x00000001 +#define VPEC_POWER_CNTL__FISO__SHIFT 0x00000002 +#define VPEC_POWER_CNTL__UCODE_SRAM_POWER_UP_RECOVER_DELAY__SHIFT 0x00000008 +#define VPEC_POWER_CNTL__UCODE_SRAM_POWER_STATUS_CHANGE_WAKEUP_TIME__SHIFT 0x0000000f +#define VPEC_POWER_CNTL__UCODE_SRAM_POWER_STATUS_CHANGE_CLK_FORCE__SHIFT 0x00000012 +#define VPEC_POWER_CNTL__SRAM_POWER_LS_CHANGE_DELAY__SHIFT 0x00000014 +#define VPEC_POWER_CNTL__SRAM_POWER_LS_CHANGE_CLK_FORCE__SHIFT 0x00000017 +#define VPEC_POWER_CNTL__SRAM_POWER_LS_CHANGE_CLK_FORCE_DELAY__SHIFT 0x00000018 + +// reg: VPEC_ZPR_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_ZPR_CNTL__CLK_UNGATE_DELAY__SHIFT 0x00000000 +#define VPEC_ZPR_CNTL__RESERVED__SHIFT 0x00000008 + +// reg: VPEC_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_CNTL__TRAP_ENABLE__SHIFT 0x00000000 +#define VPEC_CNTL__RESERVED_2_2__SHIFT 0x00000002 +#define VPEC_CNTL__DATA_SWAP__SHIFT 0x00000003 +#define VPEC_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x00000005 +#define VPEC_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x00000006 +#define VPEC_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x00000009 +#define VPEC_CNTL__UMSCH_INT_ENABLE__SHIFT 0x0000000a +#define VPEC_CNTL__RESERVED_13_11__SHIFT 0x0000000b +#define VPEC_CNTL__NACK_GEN_ERR_INT_ENABLE__SHIFT 0x0000000e +#define VPEC_CNTL__NACK_PRT_INT_ENABLE__SHIFT 0x0000000f +#define VPEC_CNTL__RESERVED_16_16__SHIFT 0x00000010 +#define VPEC_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x00000011 +#define VPEC_CNTL__RESERVED_19_19__SHIFT 0x00000013 +#define VPEC_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x0000001c +#define VPEC_CNTL__FROZEN_INT_ENABLE__SHIFT 0x0000001d +#define VPEC_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x0000001e +#define VPEC_CNTL__RB_PREEMPT_INT_ENABLE__SHIFT 0x0000001f + +// reg: VPEC_CNTL_DCC block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_CNTL_DCC__WDCC_COMP_MODE__SHIFT 0x00000000 +#define VPEC_CNTL_DCC__RESERVED_3_2__SHIFT 0x00000002 +#define VPEC_CNTL_DCC__WDCC_MICRO_TILE_MODE__SHIFT 0x00000004 +#define VPEC_CNTL_DCC__RESERVED_7_6__SHIFT 0x00000006 +#define VPEC_CNTL_DCC__WDCC_DATA_FORMAT__SHIFT 0x00000008 +#define VPEC_CNTL_DCC__RESERVED_15_13__SHIFT 0x0000000d +#define VPEC_CNTL_DCC__WDCC_NUM_FORMAT_EN__SHIFT 0x00000010 +#define VPEC_CNTL_DCC__RESERVED_19_17__SHIFT 0x00000011 +#define VPEC_CNTL_DCC__WDCC_NUM_TYPE__SHIFT 0x00000014 +#define VPEC_CNTL_DCC__RESERVED_23_23__SHIFT 0x00000017 +#define VPEC_CNTL_DCC__WDCC_MAX_UNCOMP_SIZE__SHIFT 0x00000018 +#define VPEC_CNTL_DCC__WDCC_MAX_COMP_SIZE__SHIFT 0x00000019 +#define VPEC_CNTL_DCC__RESERVED_30_27__SHIFT 0x0000001b +#define VPEC_CNTL_DCC__RDCC_COMP_MODE__SHIFT 0x0000001f + +// reg: VPEC_CE_OP_MULTI_64B_BURST block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_CE_OP_MULTI_64B_BURST__EN__SHIFT 0x00000000 +#define VPEC_CE_OP_MULTI_64B_BURST__RESERVED_3_1__SHIFT 0x00000001 +#define VPEC_CE_OP_MULTI_64B_BURST__LAZY_TIMER_DLY__SHIFT 0x00000004 +#define VPEC_CE_OP_MULTI_64B_BURST__NUM_64B_BURST_ALLOWED__SHIFT 0x0000000a +#define VPEC_CE_OP_MULTI_64B_BURST__RESERVED_31_12__SHIFT 0x0000000c + +// reg: VPEC_CNTL1 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_CNTL1__RESERVED_3_1__SHIFT 0x00000001 +#define VPEC_CNTL1__SRBM_POLL_RETRYING__SHIFT 0x00000005 +#define VPEC_CNTL1__RESERVED_23_10__SHIFT 0x0000000a +#define VPEC_CNTL1__CG_STATUS_OUTPUT__SHIFT 0x00000018 +#define VPEC_CNTL1__SW_FREEZE_ENABLE__SHIFT 0x00000019 +#define VPEC_CNTL1__VPEP_CONFIG_INVALID_CHECK_ENABLE__SHIFT 0x0000001a +#define VPEC_CNTL1__RSMU_ACCESS_OFF_VPEP_RETURN_ERROR_ENABLE__SHIFT 0x0000001b +#define VPEC_CNTL1__RSMU_ACCESS_OFF_VPEP_REPORT_ERROR_ENABLE__SHIFT 0x0000001c +#define VPEC_CNTL1__RESERVED__SHIFT 0x0000001d + +// reg: VPEC_CNTL2 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_CNTL2__F32_CMD_PROC_DELAY__SHIFT 0x00000000 +#define VPEC_CNTL2__F32_SEND_POSTCODE_EN__SHIFT 0x00000004 +#define VPEC_CNTL2__UCODE_BUF_DS_EN__SHIFT 0x00000006 +#define VPEC_CNTL2__UCODE_SELFLOAD_THREAD_OVERLAP__SHIFT 0x00000007 +#define VPEC_CNTL2__LUTIB_FIFO_WATERMARK__SHIFT 0x00000008 +#define VPEC_CNTL2__CMDIB_FIFO_WATERMARK__SHIFT 0x0000000a +#define VPEC_CNTL2__RESERVED_14_12__SHIFT 0x0000000c +#define VPEC_CNTL2__IMPROVE_CE_IP_ARBITER__SHIFT 0x0000000f +#define VPEC_CNTL2__RB_FIFO_WATERMARK__SHIFT 0x00000010 +#define VPEC_CNTL2__IB_FIFO_WATERMARK__SHIFT 0x00000012 +#define VPEC_CNTL2__RESERVED_22_20__SHIFT 0x00000014 +#define VPEC_CNTL2__CH_RD_WATERMARK__SHIFT 0x00000017 +#define VPEC_CNTL2__CH_WR_WATERMARK__SHIFT 0x00000019 +#define VPEC_CNTL2__CH_WR_WATERMARK_LSB__SHIFT 0x0000001e + +// reg: VPEC_GB_ADDR_CONFIG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 +#define VPEC_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000003 +#define VPEC_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x00000006 +#define VPEC_GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x00000008 +#define VPEC_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x00000013 +#define VPEC_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x0000001a + +// reg: VPEC_GB_ADDR_CONFIG_READ block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x00000000 +#define VPEC_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000003 +#define VPEC_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x00000006 +#define VPEC_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT 0x00000008 +#define VPEC_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x00000013 +#define VPEC_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x0000001a + +// reg: VPEC_GB_ADDR_CONFIG_META block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_GB_ADDR_CONFIG_META__NUM_PIPES__SHIFT 0x00000000 +#define VPEC_GB_ADDR_CONFIG_META__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000003 +#define VPEC_GB_ADDR_CONFIG_META__MAX_COMPRESSED_FRAGS__SHIFT 0x00000006 +#define VPEC_GB_ADDR_CONFIG_META__NUM_PKRS__SHIFT 0x00000008 +#define VPEC_GB_ADDR_CONFIG_META__NUM_SHADER_ENGINES__SHIFT 0x00000013 +#define VPEC_GB_ADDR_CONFIG_META__NUM_RB_PER_SE__SHIFT 0x0000001a + +// reg: VPEC_PROCESS_QUANTUM0 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_PROCESS_QUANTUM0__PROCESS0_QUANTUM__SHIFT 0x00000000 +#define VPEC_PROCESS_QUANTUM0__PROCESS1_QUANTUM__SHIFT 0x00000008 +#define VPEC_PROCESS_QUANTUM0__PROCESS2_QUANTUM__SHIFT 0x00000010 +#define VPEC_PROCESS_QUANTUM0__PROCESS3_QUANTUM__SHIFT 0x00000018 + +// reg: VPEC_PROCESS_QUANTUM1 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_PROCESS_QUANTUM1__PROCESS4_QUANTUM__SHIFT 0x00000000 +#define VPEC_PROCESS_QUANTUM1__PROCESS5_QUANTUM__SHIFT 0x00000008 +#define VPEC_PROCESS_QUANTUM1__PROCESS6_QUANTUM__SHIFT 0x00000010 +#define VPEC_PROCESS_QUANTUM1__PROCESS7_QUANTUM__SHIFT 0x00000018 + +// reg: VPEC_CONTEXT_SWITCH_THRESHOLD block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_CONTEXT_SWITCH_THRESHOLD__REALTIME_THRESHOLD__SHIFT 0x00000000 +#define VPEC_CONTEXT_SWITCH_THRESHOLD__FOCUS_THRESHOLD__SHIFT 0x00000002 +#define VPEC_CONTEXT_SWITCH_THRESHOLD__NORMAL_THRESHOLD__SHIFT 0x00000004 +#define VPEC_CONTEXT_SWITCH_THRESHOLD__IDLE_THRESHOLD__SHIFT 0x00000006 + +// reg: VPEC_GLOBAL_QUANTUM block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM__SHIFT 0x00000000 +#define VPEC_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM__SHIFT 0x00000008 + +// reg: VPEC_HWE_MASK block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_HWE_MASK__HWE_MASK__SHIFT 0x00000000 + +// reg: VPEC_HWE_SRC_DST_TABLE0 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_HWE_SRC_DST_TABLE0__TABLE0__SHIFT 0x00000000 + +// reg: VPEC_HWE_SRC_DST_TABLE1 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_HWE_SRC_DST_TABLE1__TABLE1__SHIFT 0x00000000 + +// reg: VPEC_WATCHDOG_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_WATCHDOG_CNTL__QUEUE_HANG_COUNT__SHIFT 0x00000000 +#define VPEC_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT__SHIFT 0x00000008 + +// reg: VPEC_ATOMIC_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x00000000 +#define VPEC_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x0000001f + +// reg: VPEC_UCODE_VERSION block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_UCODE_VERSION__T0_UCODE_VERSION__SHIFT 0x00000000 +#define VPEC_UCODE_VERSION__T1_UCODE_VERSION__SHIFT 0x00000010 + +// reg: VPEC_MEMREQ_BURST_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_MEMREQ_BURST_CNTL__DATA_RD_BURST__SHIFT 0x00000000 +#define VPEC_MEMREQ_BURST_CNTL__DATA_WR_BURST__SHIFT 0x00000002 +#define VPEC_MEMREQ_BURST_CNTL__RB_RD_BURST__SHIFT 0x00000004 +#define VPEC_MEMREQ_BURST_CNTL__IB_RD_BURST__SHIFT 0x00000006 +#define VPEC_MEMREQ_BURST_CNTL__WR_BURST_WAIT_CYCLE__SHIFT 0x00000008 + +// reg: VPEC_TIMESTAMP_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_TIMESTAMP_CNTL__CAPTURE__SHIFT 0x00000000 + +// reg: VPEC_GLOBAL_TIMESTAMP_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_GLOBAL_TIMESTAMP_LO__DATA__SHIFT 0x00000000 + +// reg: VPEC_GLOBAL_TIMESTAMP_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_GLOBAL_TIMESTAMP_HI__DATA__SHIFT 0x00000000 + +// reg: VPEC_FREEZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_FREEZE__PREEMPT__SHIFT 0x00000000 +#define VPEC_FREEZE__FREEZE__SHIFT 0x00000004 +#define VPEC_FREEZE__FROZEN__SHIFT 0x00000005 +#define VPEC_FREEZE__F32_FREEZE__SHIFT 0x00000006 + +// reg: VPEC_CE_CTRL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x00000000 +#define VPEC_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x00000003 +#define VPEC_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x00000005 +#define VPEC_CE_CTRL__RESERVED__SHIFT 0x00000008 + +// reg: VPEC_RELAX_ORDERING_LUT block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x00000000 +#define VPEC_RELAX_ORDERING_LUT__VPE__SHIFT 0x00000001 +#define VPEC_RELAX_ORDERING_LUT__RESERVED_2_2__SHIFT 0x00000002 +#define VPEC_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x00000003 +#define VPEC_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x00000004 +#define VPEC_RELAX_ORDERING_LUT__FENCE__SHIFT 0x00000005 +#define VPEC_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x00000006 +#define VPEC_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x00000008 +#define VPEC_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x00000009 +#define VPEC_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0x0000000a +#define VPEC_RELAX_ORDERING_LUT__RESERVED_11_11__SHIFT 0x0000000b +#define VPEC_RELAX_ORDERING_LUT__RESERVED_12_12__SHIFT 0x0000000c +#define VPEC_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0x0000000d +#define VPEC_RELAX_ORDERING_LUT__NATIVE_FENCE__SHIFT 0x0000000e +#define VPEC_RELAX_ORDERING_LUT__RESERVED__SHIFT 0x0000000f +#define VPEC_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x0000001b +#define VPEC_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x0000001c +#define VPEC_RELAX_ORDERING_LUT__RESERVED_29_29__SHIFT 0x0000001d +#define VPEC_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x0000001e +#define VPEC_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x0000001f + +// reg: VPEC_CREDIT_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_CREDIT_CNTL__DRM_CREDIT__SHIFT 0x00000000 +#define VPEC_CREDIT_CNTL__MC_WRREQ_CREDIT__SHIFT 0x00000007 +#define VPEC_CREDIT_CNTL__MC_RDREQ_CREDIT__SHIFT 0x0000000d + +// reg: VPEC_SCRATCH_RAM_DATA block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_SCRATCH_RAM_DATA__DATA__SHIFT 0x00000000 + +// reg: VPEC_SCRATCH_RAM_ADDR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE_RESET_REQ block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE_RESET_REQ__QUEUE0_RESET__SHIFT 0x00000000 +#define VPEC_QUEUE_RESET_REQ__QUEUE1_RESET__SHIFT 0x00000001 +#define VPEC_QUEUE_RESET_REQ__QUEUE2_RESET__SHIFT 0x00000002 +#define VPEC_QUEUE_RESET_REQ__QUEUE3_RESET__SHIFT 0x00000003 +#define VPEC_QUEUE_RESET_REQ__QUEUE4_RESET__SHIFT 0x00000004 +#define VPEC_QUEUE_RESET_REQ__QUEUE5_RESET__SHIFT 0x00000005 +#define VPEC_QUEUE_RESET_REQ__QUEUE6_RESET__SHIFT 0x00000006 +#define VPEC_QUEUE_RESET_REQ__QUEUE7_RESET__SHIFT 0x00000007 +#define VPEC_QUEUE_RESET_REQ__RESERVED__SHIFT 0x00000008 + +// reg: VPEC_PERFCNT_PERFCOUNTER0_CFG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x00000000 +#define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x00000008 +#define VPEC_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x00000018 +#define VPEC_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x0000001c +#define VPEC_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x0000001d + +// reg: VPEC_PERFCNT_PERFCOUNTER1_CFG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x00000000 +#define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x00000008 +#define VPEC_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x00000018 +#define VPEC_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x0000001c +#define VPEC_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x0000001d + +// reg: VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x00000000 +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x00000008 +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x00000010 +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x00000018 +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x00000019 +#define VPEC_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x0000001a + +// reg: VPEC_PERFCNT_MISC_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x00000000 +#define VPEC_PERFCNT_MISC_CNTL__MMHUB_REQ_EVENT_SELECT__SHIFT 0x00000010 + +// reg: VPEC_PERFCNT_PERFCOUNTER_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x00000000 + +// reg: VPEC_PERFCNT_PERFCOUNTER_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x00000000 +#define VPEC_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x00000010 + +// reg: VPEC_DEBUG_INDEX block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_DEBUG_INDEX__INDEX__SHIFT 0x00000000 + +// reg: VPEC_DEBUG_DATA block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// reg: VPEC_CRC_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_CRC_CNTL__ENABLE__SHIFT 0x00000000 +#define VPEC_CRC_CNTL__CLEAR__SHIFT 0x00000001 + +// reg: VPEC_CRC_INDEX block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_CRC_INDEX__PIPE__SHIFT 0x00000000 +#define VPEC_CRC_INDEX__CRC_NODE__SHIFT 0x00000004 + +// reg: VPEC_CRC_DATA0 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_CRC_DATA0__DATA__SHIFT 0x00000000 + +// reg: VPEC_CRC_DATA1 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_CRC_DATA1__DATA__SHIFT 0x00000000 + +// reg: VPEC_CRC_DATA2 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_CRC_DATA2__DATA__SHIFT 0x00000000 + +// reg: VPEC_MAILBOX0 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_MAILBOX0__VALUE__SHIFT 0x00000000 + +// reg: VPEC_MAILBOX1 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_MAILBOX1__VALUE__SHIFT 0x00000000 + +// reg: VPEC_MAILBOX2 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_MAILBOX2__VALUE__SHIFT 0x00000000 + +// reg: VPEC_MAILBOX3 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_MAILBOX3__VALUE__SHIFT 0x00000000 + +// reg: VPEC_MAILBOX4 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_MAILBOX4__VALUE__SHIFT 0x00000000 + +// reg: VPEC_MAILBOX5 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_MAILBOX5__VALUE__SHIFT 0x00000000 + +// reg: VPEC_MAILBOX6 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_MAILBOX6__VALUE__SHIFT 0x00000000 + +// reg: VPEC_MAILBOX7 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_MAILBOX7__VALUE__SHIFT 0x00000000 + +// reg: VPEC_MAILBOX8 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_MAILBOX8__VALUE__SHIFT 0x00000000 + +// reg: VPEC_MAILBOX9 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_MAILBOX9__VALUE__SHIFT 0x00000000 + +// reg: VPEC_MAILBOX10 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_MAILBOX10__VALUE__SHIFT 0x00000000 + +// reg: VPEC_MAILBOX11 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_MAILBOX11__VALUE__SHIFT 0x00000000 + +// reg: VPEC_MAILBOX12 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_MAILBOX12__VALUE__SHIFT 0x00000000 + +// reg: VPEC_MAILBOX13 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_MAILBOX13__VALUE__SHIFT 0x00000000 + +// reg: VPEC_MAILBOX14 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_MAILBOX14__VALUE__SHIFT 0x00000000 + +// reg: VPEC_MAILBOX15 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_MAILBOX15__VALUE__SHIFT 0x00000000 + +// reg: VPEC_PUB_DUMMY0 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_PUB_DUMMY0__VALUE__SHIFT 0x00000000 + +// reg: VPEC_PUB_DUMMY1 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_PUB_DUMMY1__VALUE__SHIFT 0x00000000 + +// reg: VPEC_PUB_DUMMY2 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_PUB_DUMMY2__VALUE__SHIFT 0x00000000 + +// reg: VPEC_PUB_DUMMY3 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_PUB_DUMMY3__VALUE__SHIFT 0x00000000 + +// reg: VPEC_PUB_DUMMY4 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_PUB_DUMMY4__VALUE__SHIFT 0x00000000 + +// reg: VPEC_PUB_DUMMY5 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_PUB_DUMMY5__VALUE__SHIFT 0x00000000 + +// reg: VPEC_PUB_DUMMY6 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_PUB_DUMMY6__VALUE__SHIFT 0x00000000 + +// reg: VPEC_PUB_DUMMY7 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_PUB_DUMMY7__VALUE__SHIFT 0x00000000 + +// reg: VPEC_PUB_DUMMY8 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_PUB_DUMMY8__VALUE__SHIFT 0x00000000 + +// reg: VPEC_PUB_DUMMY9 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_PUB_DUMMY9__VALUE__SHIFT 0x00000000 + +// reg: VPEC_PUB_DUMMY10 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_PUB_DUMMY10__VALUE__SHIFT 0x00000000 + +// reg: VPEC_PUB_DUMMY11 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_PUB_DUMMY11__VALUE__SHIFT 0x00000000 + +// reg: VPEC_UCODE1_CHECKSUM block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_UCODE1_CHECKSUM__DATA__SHIFT 0x00000000 + +// reg: VPEC_VERSION block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_VERSION__MINVER__SHIFT 0x00000000 +#define VPEC_VERSION__MAJVER__SHIFT 0x00000008 +#define VPEC_VERSION__REV__SHIFT 0x00000010 + +// reg: VPEC_UCODE_CHECKSUM block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_UCODE_CHECKSUM__DATA__SHIFT 0x00000000 + +// reg: VPEC_RB_RPTR_FETCH block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_RB_RPTR_FETCH__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_RB_RPTR_FETCH_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_IB_OFFSET_FETCH block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_IB_OFFSET_FETCH__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_CMDIB_OFFSET_FETCH block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_CMDIB_OFFSET_FETCH__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_3DLUTIB_OFFSET_FETCH block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_3DLUTIB_OFFSET_FETCH__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_ATOMIC_PREOP_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_ATOMIC_PREOP_LO__DATA__SHIFT 0x00000000 + +// reg: VPEC_ATOMIC_PREOP_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_ATOMIC_PREOP_HI__DATA__SHIFT 0x00000000 + +// reg: VPEC_CE_BUSY block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_CE_BUSY__CE_IP_PIPE0_BUSY__SHIFT 0x00000000 +#define VPEC_CE_BUSY__CE_IP_PIPE1_BUSY__SHIFT 0x00000001 +#define VPEC_CE_BUSY__CE_IP_PIPE2_BUSY__SHIFT 0x00000002 +#define VPEC_CE_BUSY__CE_IP_PIPE3_BUSY__SHIFT 0x00000003 +#define VPEC_CE_BUSY__CE_IP_PIPE4_BUSY__SHIFT 0x00000004 +#define VPEC_CE_BUSY__CE_IP_PIPE5_BUSY__SHIFT 0x00000005 +#define VPEC_CE_BUSY__CE_OP_PIPE0_BUSY__SHIFT 0x00000010 +#define VPEC_CE_BUSY__CE_OP_PIPE1_BUSY__SHIFT 0x00000011 +#define VPEC_CE_BUSY__CE_OP_PIPE2_BUSY__SHIFT 0x00000012 +#define VPEC_CE_BUSY__CE_OP_PIPE3_BUSY__SHIFT 0x00000013 +#define VPEC_CE_BUSY__CE_OP_PIPE4_BUSY__SHIFT 0x00000014 +#define VPEC_CE_BUSY__CE_OP_PIPE5_BUSY__SHIFT 0x00000015 +#define VPEC_CE_BUSY__CE_OP_PIPE6_BUSY__SHIFT 0x00000016 +#define VPEC_CE_BUSY__CE_OP_PIPE7_BUSY__SHIFT 0x00000017 +#define VPEC_CE_BUSY__CE_OP_PIPE8_BUSY__SHIFT 0x00000018 +#define VPEC_CE_BUSY__CE_OP_PIPE9_BUSY__SHIFT 0x00000019 + +// reg: VPEC_F32_COUNTER block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_F32_COUNTER__VALUE__SHIFT 0x00000000 + +// reg: VPEC_HOLE_ADDR_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_HOLE_ADDR_LO__VALUE__SHIFT 0x00000000 + +// reg: VPEC_HOLE_ADDR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_HOLE_ADDR_HI__VALUE__SHIFT 0x00000000 + +// reg: VPEC_ERROR_LOG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_ERROR_LOG__OVERRIDE__SHIFT 0x00000000 +#define VPEC_ERROR_LOG__STATUS__SHIFT 0x00000010 + +// reg: VPEC_INT_STATUS block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_INT_STATUS__DATA__SHIFT 0x00000000 + +// reg: VPEC_STATUS block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_STATUS__IDLE__SHIFT 0x00000000 +#define VPEC_STATUS__REG_IDLE__SHIFT 0x00000001 +#define VPEC_STATUS__RB_EMPTY__SHIFT 0x00000002 +#define VPEC_STATUS__RB_FULL__SHIFT 0x00000003 +#define VPEC_STATUS__RB_CMD_IDLE__SHIFT 0x00000004 +#define VPEC_STATUS__RB_CMD_FULL__SHIFT 0x00000005 +#define VPEC_STATUS__IB_CMD_IDLE__SHIFT 0x00000006 +#define VPEC_STATUS__IB_CMD_FULL__SHIFT 0x00000007 +#define VPEC_STATUS__BLOCK_IDLE__SHIFT 0x00000008 +#define VPEC_STATUS__INSIDE_VPEP_CONFIG__SHIFT 0x00000009 +#define VPEC_STATUS__EX_IDLE__SHIFT 0x0000000a +#define VPEC_STATUS__INSIDE_VPEP_3DLUT_CONFIG__SHIFT 0x0000000b +#define VPEC_STATUS__PACKET_READY__SHIFT 0x0000000c +#define VPEC_STATUS__MC_WR_IDLE__SHIFT 0x0000000d +#define VPEC_STATUS__SRBM_IDLE__SHIFT 0x0000000e +#define VPEC_STATUS__CONTEXT_EMPTY__SHIFT 0x0000000f +#define VPEC_STATUS__INSIDE_IB__SHIFT 0x00000010 +#define VPEC_STATUS__RB_MC_RREQ_IDLE__SHIFT 0x00000011 +#define VPEC_STATUS__IB_MC_RREQ_IDLE__SHIFT 0x00000012 +#define VPEC_STATUS__MC_RD_IDLE__SHIFT 0x00000013 +#define VPEC_STATUS__DELTA_RPTR_EMPTY__SHIFT 0x00000014 +#define VPEC_STATUS__MC_RD_RET_STALL__SHIFT 0x00000015 +#define VPEC_STATUS__LUTIB_CMD_IDLE__SHIFT 0x00000016 +#define VPEC_STATUS__LUTIB_CMD_FULL__SHIFT 0x00000017 +#define VPEC_STATUS__CMDIB_MC_RREQ_IDLE__SHIFT 0x00000018 +#define VPEC_STATUS__PREV_CMD_IDLE__SHIFT 0x00000019 +#define VPEC_STATUS__CMDIB_CMD_IDLE__SHIFT 0x0000001a +#define VPEC_STATUS__CMDIB_CMD_FULL__SHIFT 0x0000001b +#define VPEC_STATUS__RESERVED_29_28__SHIFT 0x0000001c +#define VPEC_STATUS__INT_IDLE__SHIFT 0x0000001e +#define VPEC_STATUS__INT_REQ_STALL__SHIFT 0x0000001f + +// reg: VPEC_STATUS1 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_STATUS1__EX_START__SHIFT 0x00000000 +#define VPEC_STATUS1__VPEC_IDLE__SHIFT 0x00000001 +#define VPEC_STATUS1__RESERVED_31_2__SHIFT 0x00000002 + +// reg: VPEC_STATUS2 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_STATUS2__ID__SHIFT 0x00000000 +#define VPEC_STATUS2__TH0F32_INSTR_PTR__SHIFT 0x00000002 +#define VPEC_STATUS2__CMD_OP__SHIFT 0x00000010 + +// reg: VPEC_STATUS3 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_STATUS3__RESERVED_15_0__SHIFT 0x00000000 +#define VPEC_STATUS3__RESERVED_19_16__SHIFT 0x00000010 +#define VPEC_STATUS3__EXCEPTION_IDLE__SHIFT 0x00000014 +#define VPEC_STATUS3__RESERVED_21_21__SHIFT 0x00000015 +#define VPEC_STATUS3__RESERVED_22_22__SHIFT 0x00000016 +#define VPEC_STATUS3__RESERVED_23_23__SHIFT 0x00000017 +#define VPEC_STATUS3__RESERVED_24_24__SHIFT 0x00000018 +#define VPEC_STATUS3__RESERVED_25_25__SHIFT 0x00000019 +#define VPEC_STATUS3__INT_QUEUE_ID__SHIFT 0x0000001a +#define VPEC_STATUS3__RESERVED_31_30__SHIFT 0x0000001e + +// reg: VPEC_STATUS4 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_STATUS4__IDLE__SHIFT 0x00000000 +#define VPEC_STATUS4__IH_OUTSTANDING__SHIFT 0x00000002 +#define VPEC_STATUS4__RESERVED_3_3__SHIFT 0x00000003 +#define VPEC_STATUS4__CH_RD_OUTSTANDING__SHIFT 0x00000004 +#define VPEC_STATUS4__CH_WR_OUTSTANDING__SHIFT 0x00000005 +#define VPEC_STATUS4__RESERVED_6_6__SHIFT 0x00000006 +#define VPEC_STATUS4__RESERVED_7_7__SHIFT 0x00000007 +#define VPEC_STATUS4__RESERVED_8_8__SHIFT 0x00000008 +#define VPEC_STATUS4__RESERVED_9_9__SHIFT 0x00000009 +#define VPEC_STATUS4__REG_POLLING__SHIFT 0x0000000a +#define VPEC_STATUS4__MEM_POLLING__SHIFT 0x0000000b +#define VPEC_STATUS4__VPEP_REG_RD_OUTSTANDING__SHIFT 0x0000000c +#define VPEC_STATUS4__VPEP_REG_WR_OUTSTANDING__SHIFT 0x0000000d +#define VPEC_STATUS4__RESERVED_15_14__SHIFT 0x0000000e +#define VPEC_STATUS4__ACTIVE_QUEUE_ID__SHIFT 0x00000010 +#define VPEC_STATUS4__RESERVED_27_20__SHIFT 0x00000014 + +// reg: VPEC_STATUS5 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_STATUS5__QUEUE0_RB_ENABLE_STATUS__SHIFT 0x00000000 +#define VPEC_STATUS5__QUEUE1_RB_ENABLE_STATUS__SHIFT 0x00000001 +#define VPEC_STATUS5__QUEUE2_RB_ENABLE_STATUS__SHIFT 0x00000002 +#define VPEC_STATUS5__QUEUE3_RB_ENABLE_STATUS__SHIFT 0x00000003 +#define VPEC_STATUS5__QUEUE4_RB_ENABLE_STATUS__SHIFT 0x00000004 +#define VPEC_STATUS5__QUEUE5_RB_ENABLE_STATUS__SHIFT 0x00000005 +#define VPEC_STATUS5__QUEUE6_RB_ENABLE_STATUS__SHIFT 0x00000006 +#define VPEC_STATUS5__QUEUE7_RB_ENABLE_STATUS__SHIFT 0x00000007 +#define VPEC_STATUS5__RESERVED_27_16__SHIFT 0x00000010 + +// reg: VPEC_STATUS6 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_STATUS6__ID__SHIFT 0x00000000 +#define VPEC_STATUS6__TH1F32_INSTR_PTR__SHIFT 0x00000002 +#define VPEC_STATUS6__TH1_EXCEPTION__SHIFT 0x00000010 + +// reg: VPEC_STATUS7 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_STATUS7__TH0_DBG_STATUS__SHIFT 0x00000000 + +// reg: VPEC_STATUS8 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_STATUS8__CE_IP0_WREQ_IDLE__SHIFT 0x00000000 +#define VPEC_STATUS8__CE_IP0_WR_IDLE__SHIFT 0x00000001 +#define VPEC_STATUS8__CE_IP0_SPLIT_RD_IDLE__SHIFT 0x00000002 +#define VPEC_STATUS8__CE_IP0_SPLIT_WR_IDLE__SHIFT 0x00000003 +#define VPEC_STATUS8__CE_IP0_RREQ_IDLE__SHIFT 0x00000004 +#define VPEC_STATUS8__CE_IP0_OUT_IDLE__SHIFT 0x00000005 +#define VPEC_STATUS8__CE_IP0_IN_IDLE__SHIFT 0x00000006 +#define VPEC_STATUS8__CE_IP0_DST_IDLE__SHIFT 0x00000007 +#define VPEC_STATUS8__CE_IP0_CMD_IDLE__SHIFT 0x00000008 +#define VPEC_STATUS8__CE_IP1_WREQ_IDLE__SHIFT 0x00000009 +#define VPEC_STATUS8__CE_IP1_WR_IDLE__SHIFT 0x0000000a +#define VPEC_STATUS8__CE_IP1_SPLIT_RD_IDLE__SHIFT 0x0000000b +#define VPEC_STATUS8__CE_IP1_SPLIT_WR_IDLE__SHIFT 0x0000000c +#define VPEC_STATUS8__CE_IP1_RREQ_IDLE__SHIFT 0x0000000d +#define VPEC_STATUS8__CE_IP1_OUT_IDLE__SHIFT 0x0000000e +#define VPEC_STATUS8__CE_IP1_IN_IDLE__SHIFT 0x0000000f +#define VPEC_STATUS8__CE_IP1_DST_IDLE__SHIFT 0x00000010 +#define VPEC_STATUS8__CE_IP1_CMD_IDLE__SHIFT 0x00000011 +#define VPEC_STATUS8__CE_IP0_AFIFO_FULL__SHIFT 0x00000012 +#define VPEC_STATUS8__CE_IP0_CMD_INFO_FULL__SHIFT 0x00000013 +#define VPEC_STATUS8__CE_IP0_CMD_INFO1_FULL__SHIFT 0x00000014 +#define VPEC_STATUS8__CE_IP1_AFIFO_FULL__SHIFT 0x00000015 +#define VPEC_STATUS8__CE_IP1_CMD_INFO_FULL__SHIFT 0x00000016 +#define VPEC_STATUS8__CE_IP1_CMD_INFO1_FULL__SHIFT 0x00000017 +#define VPEC_STATUS8__CE_IP0_WR_STALL__SHIFT 0x00000018 +#define VPEC_STATUS8__CE_IP1_WR_STALL__SHIFT 0x00000019 +#define VPEC_STATUS8__CE_IP0_RD_STALL__SHIFT 0x0000001a +#define VPEC_STATUS8__CE_IP1_RD_STALL__SHIFT 0x0000001b +#define VPEC_STATUS8__RESERVED_31_28__SHIFT 0x0000001c + +// reg: VPEC_STATUS9 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_STATUS9__CE_IP2_WREQ_IDLE__SHIFT 0x00000000 +#define VPEC_STATUS9__CE_IP2_WR_IDLE__SHIFT 0x00000001 +#define VPEC_STATUS9__CE_IP2_SPLIT_RD_IDLE__SHIFT 0x00000002 +#define VPEC_STATUS9__CE_IP2_SPLIT_WR_IDLE__SHIFT 0x00000003 +#define VPEC_STATUS9__CE_IP2_RREQ_IDLE__SHIFT 0x00000004 +#define VPEC_STATUS9__CE_IP2_OUT_IDLE__SHIFT 0x00000005 +#define VPEC_STATUS9__CE_IP2_IN_IDLE__SHIFT 0x00000006 +#define VPEC_STATUS9__CE_IP2_DST_IDLE__SHIFT 0x00000007 +#define VPEC_STATUS9__CE_IP2_CMD_IDLE__SHIFT 0x00000008 +#define VPEC_STATUS9__CE_IP3_WREQ_IDLE__SHIFT 0x00000009 +#define VPEC_STATUS9__CE_IP3_WR_IDLE__SHIFT 0x0000000a +#define VPEC_STATUS9__CE_IP3_SPLIT_RD_IDLE__SHIFT 0x0000000b +#define VPEC_STATUS9__CE_IP3_SPLIT_WR_IDLE__SHIFT 0x0000000c +#define VPEC_STATUS9__CE_IP3_RREQ_IDLE__SHIFT 0x0000000d +#define VPEC_STATUS9__CE_IP3_OUT_IDLE__SHIFT 0x0000000e +#define VPEC_STATUS9__CE_IP3_IN_IDLE__SHIFT 0x0000000f +#define VPEC_STATUS9__CE_IP3_DST_IDLE__SHIFT 0x00000010 +#define VPEC_STATUS9__CE_IP3_CMD_IDLE__SHIFT 0x00000011 +#define VPEC_STATUS9__CE_IP2_AFIFO_FULL__SHIFT 0x00000012 +#define VPEC_STATUS9__CE_IP2_CMD_INFO_FULL__SHIFT 0x00000013 +#define VPEC_STATUS9__CE_IP2_CMD_INFO1_FULL__SHIFT 0x00000014 +#define VPEC_STATUS9__CE_IP3_AFIFO_FULL__SHIFT 0x00000015 +#define VPEC_STATUS9__CE_IP3_CMD_INFO_FULL__SHIFT 0x00000016 +#define VPEC_STATUS9__CE_IP3_CMD_INFO1_FULL__SHIFT 0x00000017 +#define VPEC_STATUS9__CE_IP2_WR_STALL__SHIFT 0x00000018 +#define VPEC_STATUS9__CE_IP3_WR_STALL__SHIFT 0x00000019 +#define VPEC_STATUS9__CE_IP2_RD_STALL__SHIFT 0x0000001a +#define VPEC_STATUS9__CE_IP3_RD_STALL__SHIFT 0x0000001b +#define VPEC_STATUS9__RESERVED_31_28__SHIFT 0x0000001c + +// reg: VPEC_STATUS10 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_STATUS10__CE_OP0_WR_IDLE__SHIFT 0x00000000 +#define VPEC_STATUS10__CE_OP0_CMD_IDLE__SHIFT 0x00000001 +#define VPEC_STATUS10__CE_OP1_WR_IDLE__SHIFT 0x00000002 +#define VPEC_STATUS10__CE_OP1_CMD_IDLE__SHIFT 0x00000003 +#define VPEC_STATUS10__CE_OP2_WR_IDLE__SHIFT 0x00000004 +#define VPEC_STATUS10__CE_OP2_CMD_IDLE__SHIFT 0x00000005 +#define VPEC_STATUS10__CE_OP3_WR_IDLE__SHIFT 0x00000006 +#define VPEC_STATUS10__CE_OP3_CMD_IDLE__SHIFT 0x00000007 +#define VPEC_STATUS10__CE_OP4_WR_IDLE__SHIFT 0x00000008 +#define VPEC_STATUS10__CE_OP4_CMD_IDLE__SHIFT 0x00000009 +#define VPEC_STATUS10__CE_OP5_WR_IDLE__SHIFT 0x0000000a +#define VPEC_STATUS10__CE_OP5_CMD_IDLE__SHIFT 0x0000000b +#define VPEC_STATUS10__CE_OP6_WR_IDLE__SHIFT 0x0000000c +#define VPEC_STATUS10__CE_OP6_CMD_IDLE__SHIFT 0x0000000d +#define VPEC_STATUS10__CE_OP7_WR_IDLE__SHIFT 0x0000000e +#define VPEC_STATUS10__CE_OP7_CMD_IDLE__SHIFT 0x0000000f +#define VPEC_STATUS10__CE_OP8_WR_IDLE__SHIFT 0x00000010 +#define VPEC_STATUS10__CE_OP8_CMD_IDLE__SHIFT 0x00000011 +#define VPEC_STATUS10__CE_OP9_WR_IDLE__SHIFT 0x00000012 +#define VPEC_STATUS10__CE_OP9_CMD_IDLE__SHIFT 0x00000013 +#define VPEC_STATUS10__RESERVED_31_28__SHIFT 0x0000001c + +// reg: VPEC_STATUS_DCC block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_STATUS_DCC__CE_IP0_MRQ_IDLE__SHIFT 0x00000000 +#define VPEC_STATUS_DCC__CE_IP0_DCCP_IDLE__SHIFT 0x00000001 +#define VPEC_STATUS_DCC__CE_IP0_DCC_RET_IDLE__SHIFT 0x00000002 +#define VPEC_STATUS_DCC__CE_IP1_MRQ_IDLE__SHIFT 0x00000003 +#define VPEC_STATUS_DCC__CE_IP1_DCCP_IDLE__SHIFT 0x00000004 +#define VPEC_STATUS_DCC__CE_IP1_DCC_RET_IDLE__SHIFT 0x00000005 +#define VPEC_STATUS_DCC__CE_IP2_MRQ_IDLE__SHIFT 0x00000006 +#define VPEC_STATUS_DCC__CE_IP2_DCCP_IDLE__SHIFT 0x00000007 +#define VPEC_STATUS_DCC__CE_IP2_DCC_RET_IDLE__SHIFT 0x00000008 +#define VPEC_STATUS_DCC__CE_IP3_MRQ_IDLE__SHIFT 0x00000009 +#define VPEC_STATUS_DCC__CE_IP3_DCCP_IDLE__SHIFT 0x0000000a +#define VPEC_STATUS_DCC__CE_IP3_DCC_RET_IDLE__SHIFT 0x0000000b +#define VPEC_STATUS_DCC__CE_IP4_MRQ_IDLE__SHIFT 0x0000000c +#define VPEC_STATUS_DCC__CE_IP4_DCCP_IDLE__SHIFT 0x0000000d +#define VPEC_STATUS_DCC__CE_IP4_DCC_RET_IDLE__SHIFT 0x0000000e +#define VPEC_STATUS_DCC__CE_IP5_MRQ_IDLE__SHIFT 0x0000000f +#define VPEC_STATUS_DCC__CE_IP5_DCCP_IDLE__SHIFT 0x00000010 +#define VPEC_STATUS_DCC__CE_IP5_DCC_RET_IDLE__SHIFT 0x00000011 +#define VPEC_STATUS_DCC__RESERVED_31_18__SHIFT 0x00000012 + +// reg: VPEC_STATUS11 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_STATUS11__CE_IP4_WREQ_IDLE__SHIFT 0x00000000 +#define VPEC_STATUS11__CE_IP4_WR_IDLE__SHIFT 0x00000001 +#define VPEC_STATUS11__CE_IP4_SPLIT_RD_IDLE__SHIFT 0x00000002 +#define VPEC_STATUS11__CE_IP4_SPLIT_WR_IDLE__SHIFT 0x00000003 +#define VPEC_STATUS11__CE_IP4_RREQ_IDLE__SHIFT 0x00000004 +#define VPEC_STATUS11__CE_IP4_OUT_IDLE__SHIFT 0x00000005 +#define VPEC_STATUS11__CE_IP4_IN_IDLE__SHIFT 0x00000006 +#define VPEC_STATUS11__CE_IP4_DST_IDLE__SHIFT 0x00000007 +#define VPEC_STATUS11__CE_IP4_CMD_IDLE__SHIFT 0x00000008 +#define VPEC_STATUS11__CE_IP5_WREQ_IDLE__SHIFT 0x00000009 +#define VPEC_STATUS11__CE_IP5_WR_IDLE__SHIFT 0x0000000a +#define VPEC_STATUS11__CE_IP5_SPLIT_RD_IDLE__SHIFT 0x0000000b +#define VPEC_STATUS11__CE_IP5_SPLIT_WR_IDLE__SHIFT 0x0000000c +#define VPEC_STATUS11__CE_IP5_RREQ_IDLE__SHIFT 0x0000000d +#define VPEC_STATUS11__CE_IP5_OUT_IDLE__SHIFT 0x0000000e +#define VPEC_STATUS11__CE_IP5_IN_IDLE__SHIFT 0x0000000f +#define VPEC_STATUS11__CE_IP5_DST_IDLE__SHIFT 0x00000010 +#define VPEC_STATUS11__CE_IP5_CMD_IDLE__SHIFT 0x00000011 +#define VPEC_STATUS11__CE_IP4_AFIFO_FULL__SHIFT 0x00000012 +#define VPEC_STATUS11__CE_IP4_CMD_INFO_FULL__SHIFT 0x00000013 +#define VPEC_STATUS11__CE_IP4_CMD_INFO1_FULL__SHIFT 0x00000014 +#define VPEC_STATUS11__CE_IP5_AFIFO_FULL__SHIFT 0x00000015 +#define VPEC_STATUS11__CE_IP5_CMD_INFO_FULL__SHIFT 0x00000016 +#define VPEC_STATUS11__CE_IP5_CMD_INFO1_FULL__SHIFT 0x00000017 +#define VPEC_STATUS11__CE_IP4_WR_STALL__SHIFT 0x00000018 +#define VPEC_STATUS11__CE_IP5_WR_STALL__SHIFT 0x00000019 +#define VPEC_STATUS11__CE_IP4_RD_STALL__SHIFT 0x0000001a +#define VPEC_STATUS11__CE_IP5_RD_STALL__SHIFT 0x0000001b +#define VPEC_STATUS11__RESERVED_31_28__SHIFT 0x0000001c + +// reg: VPEC_INST block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_INST__ID__SHIFT 0x00000000 +#define VPEC_INST__RESERVED__SHIFT 0x00000003 + +// reg: VPEC_QUEUE_STATUS0 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE_STATUS0__QUEUE0_STATUS__SHIFT 0x00000000 +#define VPEC_QUEUE_STATUS0__QUEUE1_STATUS__SHIFT 0x00000004 +#define VPEC_QUEUE_STATUS0__QUEUE2_STATUS__SHIFT 0x00000008 +#define VPEC_QUEUE_STATUS0__QUEUE3_STATUS__SHIFT 0x0000000c +#define VPEC_QUEUE_STATUS0__QUEUE4_STATUS__SHIFT 0x00000010 +#define VPEC_QUEUE_STATUS0__QUEUE5_STATUS__SHIFT 0x00000014 +#define VPEC_QUEUE_STATUS0__QUEUE6_STATUS__SHIFT 0x00000018 +#define VPEC_QUEUE_STATUS0__QUEUE7_STATUS__SHIFT 0x0000001c + +// reg: VPEC_QUEUE_HANG_STATUS block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE_HANG_STATUS__F30T0_HANG__SHIFT 0x00000000 +#define VPEC_QUEUE_HANG_STATUS__CE_HANG__SHIFT 0x00000001 +#define VPEC_QUEUE_HANG_STATUS__EOF_MISMATCH__SHIFT 0x00000002 +#define VPEC_QUEUE_HANG_STATUS__INVALID_PKT_FIELD__SHIFT 0x00000003 +#define VPEC_QUEUE_HANG_STATUS__INVALID_VPEP_CONFIG_ADDR__SHIFT 0x00000004 +#define VPEC_QUEUE_HANG_STATUS__F32_ACCESS_OFF_VPDPP1__SHIFT 0x00000005 +#define VPEC_QUEUE_HANG_STATUS__RSMU_ACCESS_OFF_VPDPP1__SHIFT 0x00000006 +#define VPEC_QUEUE_HANG_STATUS__EOH_MISMATCH__SHIFT 0x00000007 + +// reg: VPEC_DPM_IDLE_TIME block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_DPM_IDLE_TIME__VALUE__SHIFT 0x00000000 + +// reg: VPEC_DPM_BUSY_TIME block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_DPM_BUSY_TIME__VALUE__SHIFT 0x00000000 + +// reg: VPEC_DPM_IDLE_START_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_DPM_IDLE_START_LO__VALUE__SHIFT 0x00000000 + +// reg: VPEC_DPM_IDLE_START_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_DPM_IDLE_START_HI__VALUE__SHIFT 0x00000000 + +// reg: VPEC_DPM_BUSY_START_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_DPM_BUSY_START_LO__VALUE__SHIFT 0x00000000 + +// reg: VPEC_DPM_BUSY_START_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_DPM_BUSY_START_HI__VALUE__SHIFT 0x00000000 + +// reg: VPEC_DPM_LAST_REQ_TIMESTAMP block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_DPM_LAST_REQ_TIMESTAMP__VALUE__SHIFT 0x00000000 + +// reg: VPEC_DPM_NEW_JOB_DUMMY3 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_DPM_NEW_JOB_DUMMY3__VALUE__SHIFT 0x00000000 + +// reg: VPEC_DPM_STATE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_DPM_STATE__VALUE__SHIFT 0x00000000 + +// reg: VPEC_DPM0_FREQ block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_DPM0_FREQ__VALUE__SHIFT 0x00000000 + +// reg: VPEC_DPM1_FREQ block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_DPM1_FREQ__VALUE__SHIFT 0x00000000 + +// reg: VPEC_DPM2_FREQ block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_DPM2_FREQ__VALUE__SHIFT 0x00000000 + +// reg: VPEC_DPM3_FREQ block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_DPM3_FREQ__VALUE__SHIFT 0x00000000 + +// reg: VPEC_DPM_THRESHOLD_SKIP block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_DPM_THRESHOLD_SKIP__VALUE__SHIFT 0x00000000 + +// reg: VPEC_DPM_THRESHOLD_BUSY_OVERFLOW block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_DPM_THRESHOLD_BUSY_OVERFLOW__VALUE__SHIFT 0x00000000 + +// reg: VPEC_DPM_CALC_BUSY_IN_POSTPROCESS block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_DPM_CALC_BUSY_IN_POSTPROCESS__VALUE__SHIFT 0x00000000 + +// reg: VPEC_DPM_IN_CHECKIDLE_LOOP block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_DPM_IN_CHECKIDLE_LOOP__VALUE__SHIFT 0x00000000 + +// reg: VPEC_DPM_THRESHOLD_IDLE_OVERFLOW block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_DPM_THRESHOLD_IDLE_OVERFLOW__VALUE__SHIFT 0x00000000 + +// reg: VPEC_DPM_BUSY_CLAMP_COUNT block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_DPM_BUSY_CLAMP_COUNT__VALUE__SHIFT 0x00000000 + +// reg: VPEC_DPM_IDLE_CLAMP_COUNT block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_DPM_IDLE_CLAMP_COUNT__VALUE__SHIFT 0x00000000 + +// reg: VPEC_PG_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_PG_CNTL__PG_EN__SHIFT 0x00000000 +#define VPEC_PG_CNTL__PG_HYSTERESIS__SHIFT 0x00000001 +#define VPEC_PG_CNTL__PG1_EN__SHIFT 0x00000008 +#define VPEC_PG_CNTL__PG1_HYSTERESIS__SHIFT 0x00000009 +#define VPEC_PG_CNTL__ZSTATES_ENABLE__SHIFT 0x00000010 +#define VPEC_PG_CNTL__ZSTATES_HYSTERESIS__SHIFT 0x00000011 +#define VPEC_PG_CNTL__FENCE_HYSTERESIS__SHIFT 0x00000018 +#define VPEC_PG_CNTL__CHECK_RSMU_UPON_POWER_UP__SHIFT 0x0000001c + +// reg: VPEC_PG_STATUS block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_PG_STATUS__PG_STATUS__SHIFT 0x00000000 +#define VPEC_PG_STATUS__PG1_STATUS__SHIFT 0x00000002 + +// reg: VPEC_CLOCK_GATING_STATUS block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS__SHIFT 0x00000000 +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE0_CLK_GATE_STATUS__SHIFT 0x00000002 +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE1_CLK_GATE_STATUS__SHIFT 0x00000003 +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE2_CLK_GATE_STATUS__SHIFT 0x00000004 +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE3_CLK_GATE_STATUS__SHIFT 0x00000005 +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE0_CLK_GATE_STATUS__SHIFT 0x00000006 +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE1_CLK_GATE_STATUS__SHIFT 0x00000007 +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE2_CLK_GATE_STATUS__SHIFT 0x00000008 +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE3_CLK_GATE_STATUS__SHIFT 0x00000009 +#define VPEC_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS__SHIFT 0x0000000a +#define VPEC_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS__SHIFT 0x0000000b +#define VPEC_CLOCK_GATING_STATUS__USRAM_CLK_GATE_STATUS__SHIFT 0x0000000c +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE4_CLK_GATE_STATUS__SHIFT 0x0000000d +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE5_CLK_GATE_STATUS__SHIFT 0x0000000e +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE6_CLK_GATE_STATUS__SHIFT 0x0000000f +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE7_CLK_GATE_STATUS__SHIFT 0x00000010 +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE4_CLK_GATE_STATUS__SHIFT 0x00000011 +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE5_CLK_GATE_STATUS__SHIFT 0x00000012 +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE8_CLK_GATE_STATUS__SHIFT 0x00000013 +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE9_CLK_GATE_STATUS__SHIFT 0x00000014 + +// reg: VPEC_QUEUE0_RB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_RB_CNTL__RB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE0_RB_CNTL__RB_SIZE__SHIFT 0x00000001 +#define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x00000008 +#define VPEC_QUEUE0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x00000009 +#define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0x0000000a +#define VPEC_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0x0000000b +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0x0000000c +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0x0000000d +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x00000010 +#define VPEC_QUEUE0_RB_CNTL__RB_PRIV__SHIFT 0x00000017 +#define VPEC_QUEUE0_RB_CNTL__RB_VMID__SHIFT 0x00000018 + +// reg: VPEC_QUEUE0_SCHEDULE_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x00000000 +#define VPEC_QUEUE0_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x00000002 +#define VPEC_QUEUE0_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x00000006 +#define VPEC_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x00000008 + +// reg: VPEC_QUEUE0_RB_BASE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_RB_BASE__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_RB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_RB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_RB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_RB_RPTR__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_RB_RPTR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_RB_RPTR_HI__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_RB_WPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_RB_WPTR__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_RB_WPTR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_RB_WPTR_HI__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_RB_RPTR_ADDR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_RB_RPTR_ADDR_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x00000002 + +// reg: VPEC_QUEUE0_RB_AQL_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x00000001 +#define VPEC_QUEUE0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x00000008 +#define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x00000010 +#define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x00000011 +#define VPEC_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x00000012 + +// reg: VPEC_QUEUE0_MINOR_PTR_UPDATE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_CD_INFO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_CD_INFO__CD_INFO__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_RB_PREEMPT block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_SKIP_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_DOORBELL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_DOORBELL__ENABLE__SHIFT 0x0000001c +#define VPEC_QUEUE0_DOORBELL__CAPTURED__SHIFT 0x0000001e + +// reg: VPEC_QUEUE0_DOORBELL_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE0_DUMMY0 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_DUMMY0__DUMMY__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_DUMMY1 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_DUMMY1__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_DUMMY2 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_DUMMY2__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_DUMMY3 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_DUMMY3__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_DUMMY4 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_DUMMY4__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_IB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_IB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE0_IB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE0_IB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE0_IB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_IB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE0_IB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_IB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE0_IB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_IB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE0_IB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_IB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_IB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_IB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_CMDIB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_CMDIB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE0_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x00000004 +#define VPEC_QUEUE0_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE0_CMDIB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE0_CMDIB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE0_CMDIB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_CMDIB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE0_CMDIB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_CMDIB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE0_CMDIB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_CMDIB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE0_CMDIB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_CMDIB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_CMDIB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_CMDIB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_3DLUTIB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE0_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE0_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE0_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE0_3DLUTIB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_3DLUTIB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE0_3DLUTIB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_3DLUTIB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE0_3DLUTIB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_3DLUTIB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE0_3DLUTIB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_3DLUTIB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_3DLUTIB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_3DLUTIB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_CSA_ADDR_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_CSA_ADDR_LO__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_CSA_ADDR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_CSA_ADDR_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_CONTEXT_STATUS block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_CONTEXT_STATUS__SELECTED__SHIFT 0x00000000 +#define VPEC_QUEUE0_CONTEXT_STATUS__USE_IB__SHIFT 0x00000001 +#define VPEC_QUEUE0_CONTEXT_STATUS__IDLE__SHIFT 0x00000002 +#define VPEC_QUEUE0_CONTEXT_STATUS__EXPIRED__SHIFT 0x00000003 +#define VPEC_QUEUE0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x00000004 +#define VPEC_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x00000007 +#define VPEC_QUEUE0_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x00000008 +#define VPEC_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0x0000000a +#define VPEC_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0x0000000b +#define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x0000000c +#define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x00000010 + +// reg: VPEC_QUEUE0_DOORBELL_LOG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_DOORBELL_LOG__BE_ERROR__SHIFT 0x00000000 +#define VPEC_QUEUE0_DOORBELL_LOG__DATA__SHIFT 0x00000002 + +// reg: VPEC_QUEUE0_IB_SUB_REMAIN block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_IB_SUB_REMAIN__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_PREEMPT block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_PREEMPT__IB_PREEMPT__SHIFT 0x00000000 + +// reg: VPEC_QUEUE0_LOG0BUFFER_CFG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_LOG0BUFFER_CFG__ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE0_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x00000004 +#define VPEC_QUEUE0_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0x0000000c +#define VPEC_QUEUE0_LOG0BUFFER_CFG__RESERVED__SHIFT 0x00000014 + +// reg: VPEC_QUEUE0_LOG1BUFFER_CFG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE0_LOG1BUFFER_CFG__ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE0_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x00000001 +#define VPEC_QUEUE0_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x00000004 +#define VPEC_QUEUE0_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0x0000000c +#define VPEC_QUEUE0_LOG1BUFFER_CFG__RESERVED__SHIFT 0x00000014 + +// reg: VPEC_QUEUE1_RB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_RB_CNTL__RB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE1_RB_CNTL__RB_SIZE__SHIFT 0x00000001 +#define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x00000008 +#define VPEC_QUEUE1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x00000009 +#define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0x0000000a +#define VPEC_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0x0000000b +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0x0000000c +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0x0000000d +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x00000010 +#define VPEC_QUEUE1_RB_CNTL__RB_PRIV__SHIFT 0x00000017 +#define VPEC_QUEUE1_RB_CNTL__RB_VMID__SHIFT 0x00000018 + +// reg: VPEC_QUEUE1_SCHEDULE_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x00000000 +#define VPEC_QUEUE1_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x00000002 +#define VPEC_QUEUE1_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x00000006 +#define VPEC_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x00000008 + +// reg: VPEC_QUEUE1_RB_BASE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_RB_BASE__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_RB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_RB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_RB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_RB_RPTR__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_RB_RPTR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_RB_RPTR_HI__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_RB_WPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_RB_WPTR__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_RB_WPTR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_RB_WPTR_HI__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_RB_RPTR_ADDR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_RB_RPTR_ADDR_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x00000002 + +// reg: VPEC_QUEUE1_RB_AQL_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x00000001 +#define VPEC_QUEUE1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x00000008 +#define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x00000010 +#define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x00000011 +#define VPEC_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x00000012 + +// reg: VPEC_QUEUE1_MINOR_PTR_UPDATE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_CD_INFO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_CD_INFO__CD_INFO__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_RB_PREEMPT block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_SKIP_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_DOORBELL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_DOORBELL__ENABLE__SHIFT 0x0000001c +#define VPEC_QUEUE1_DOORBELL__CAPTURED__SHIFT 0x0000001e + +// reg: VPEC_QUEUE1_DOORBELL_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_DOORBELL_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE1_DUMMY0 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_DUMMY0__DUMMY__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_DUMMY1 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_DUMMY1__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_DUMMY2 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_DUMMY2__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_DUMMY3 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_DUMMY3__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_DUMMY4 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_DUMMY4__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_IB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_IB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE1_IB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE1_IB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE1_IB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_IB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE1_IB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_IB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE1_IB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_IB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE1_IB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_IB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_IB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_IB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_CMDIB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_CMDIB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE1_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x00000004 +#define VPEC_QUEUE1_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE1_CMDIB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE1_CMDIB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE1_CMDIB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_CMDIB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE1_CMDIB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_CMDIB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE1_CMDIB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_CMDIB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE1_CMDIB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_CMDIB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_CMDIB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_CMDIB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_3DLUTIB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE1_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE1_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE1_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE1_3DLUTIB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_3DLUTIB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE1_3DLUTIB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_3DLUTIB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE1_3DLUTIB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_3DLUTIB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE1_3DLUTIB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_3DLUTIB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_3DLUTIB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_3DLUTIB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_CSA_ADDR_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_CSA_ADDR_LO__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_CSA_ADDR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_CSA_ADDR_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_CONTEXT_STATUS block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_CONTEXT_STATUS__SELECTED__SHIFT 0x00000000 +#define VPEC_QUEUE1_CONTEXT_STATUS__USE_IB__SHIFT 0x00000001 +#define VPEC_QUEUE1_CONTEXT_STATUS__IDLE__SHIFT 0x00000002 +#define VPEC_QUEUE1_CONTEXT_STATUS__EXPIRED__SHIFT 0x00000003 +#define VPEC_QUEUE1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x00000004 +#define VPEC_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x00000007 +#define VPEC_QUEUE1_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x00000008 +#define VPEC_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0x0000000a +#define VPEC_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0x0000000b +#define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x0000000c +#define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x00000010 + +// reg: VPEC_QUEUE1_DOORBELL_LOG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_DOORBELL_LOG__BE_ERROR__SHIFT 0x00000000 +#define VPEC_QUEUE1_DOORBELL_LOG__DATA__SHIFT 0x00000002 + +// reg: VPEC_QUEUE1_IB_SUB_REMAIN block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_IB_SUB_REMAIN__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_PREEMPT block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_PREEMPT__IB_PREEMPT__SHIFT 0x00000000 + +// reg: VPEC_QUEUE1_LOG0BUFFER_CFG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_LOG0BUFFER_CFG__ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE1_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x00000004 +#define VPEC_QUEUE1_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0x0000000c +#define VPEC_QUEUE1_LOG0BUFFER_CFG__RESERVED__SHIFT 0x00000014 + +// reg: VPEC_QUEUE1_LOG1BUFFER_CFG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE1_LOG1BUFFER_CFG__ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE1_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x00000001 +#define VPEC_QUEUE1_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x00000004 +#define VPEC_QUEUE1_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0x0000000c +#define VPEC_QUEUE1_LOG1BUFFER_CFG__RESERVED__SHIFT 0x00000014 + +// reg: VPEC_QUEUE2_RB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_RB_CNTL__RB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE2_RB_CNTL__RB_SIZE__SHIFT 0x00000001 +#define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x00000008 +#define VPEC_QUEUE2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x00000009 +#define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0x0000000a +#define VPEC_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0x0000000b +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0x0000000c +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0x0000000d +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x00000010 +#define VPEC_QUEUE2_RB_CNTL__RB_PRIV__SHIFT 0x00000017 +#define VPEC_QUEUE2_RB_CNTL__RB_VMID__SHIFT 0x00000018 + +// reg: VPEC_QUEUE2_SCHEDULE_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x00000000 +#define VPEC_QUEUE2_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x00000002 +#define VPEC_QUEUE2_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x00000006 +#define VPEC_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x00000008 + +// reg: VPEC_QUEUE2_RB_BASE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_RB_BASE__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_RB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_RB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_RB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_RB_RPTR__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_RB_RPTR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_RB_RPTR_HI__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_RB_WPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_RB_WPTR__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_RB_WPTR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_RB_WPTR_HI__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_RB_RPTR_ADDR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_RB_RPTR_ADDR_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x00000002 + +// reg: VPEC_QUEUE2_RB_AQL_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x00000001 +#define VPEC_QUEUE2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x00000008 +#define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x00000010 +#define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x00000011 +#define VPEC_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x00000012 + +// reg: VPEC_QUEUE2_MINOR_PTR_UPDATE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_CD_INFO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_CD_INFO__CD_INFO__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_RB_PREEMPT block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_SKIP_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_DOORBELL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_DOORBELL__ENABLE__SHIFT 0x0000001c +#define VPEC_QUEUE2_DOORBELL__CAPTURED__SHIFT 0x0000001e + +// reg: VPEC_QUEUE2_DOORBELL_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_DOORBELL_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE2_DUMMY0 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_DUMMY0__DUMMY__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_DUMMY1 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_DUMMY1__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_DUMMY2 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_DUMMY2__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_DUMMY3 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_DUMMY3__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_DUMMY4 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_DUMMY4__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_IB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_IB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE2_IB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE2_IB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE2_IB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_IB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE2_IB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_IB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE2_IB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_IB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE2_IB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_IB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_IB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_IB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_CMDIB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_CMDIB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE2_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x00000004 +#define VPEC_QUEUE2_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE2_CMDIB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE2_CMDIB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE2_CMDIB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_CMDIB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE2_CMDIB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_CMDIB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE2_CMDIB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_CMDIB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE2_CMDIB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_CMDIB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_CMDIB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_CMDIB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_3DLUTIB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE2_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE2_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE2_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE2_3DLUTIB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_3DLUTIB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE2_3DLUTIB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_3DLUTIB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE2_3DLUTIB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_3DLUTIB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE2_3DLUTIB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_3DLUTIB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_3DLUTIB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_3DLUTIB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_CSA_ADDR_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_CSA_ADDR_LO__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_CSA_ADDR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_CSA_ADDR_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_CONTEXT_STATUS block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_CONTEXT_STATUS__SELECTED__SHIFT 0x00000000 +#define VPEC_QUEUE2_CONTEXT_STATUS__USE_IB__SHIFT 0x00000001 +#define VPEC_QUEUE2_CONTEXT_STATUS__IDLE__SHIFT 0x00000002 +#define VPEC_QUEUE2_CONTEXT_STATUS__EXPIRED__SHIFT 0x00000003 +#define VPEC_QUEUE2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x00000004 +#define VPEC_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x00000007 +#define VPEC_QUEUE2_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x00000008 +#define VPEC_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0x0000000a +#define VPEC_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0x0000000b +#define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x0000000c +#define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x00000010 + +// reg: VPEC_QUEUE2_DOORBELL_LOG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_DOORBELL_LOG__BE_ERROR__SHIFT 0x00000000 +#define VPEC_QUEUE2_DOORBELL_LOG__DATA__SHIFT 0x00000002 + +// reg: VPEC_QUEUE2_IB_SUB_REMAIN block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_IB_SUB_REMAIN__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_PREEMPT block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_PREEMPT__IB_PREEMPT__SHIFT 0x00000000 + +// reg: VPEC_QUEUE2_LOG0BUFFER_CFG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_LOG0BUFFER_CFG__ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE2_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x00000004 +#define VPEC_QUEUE2_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0x0000000c +#define VPEC_QUEUE2_LOG0BUFFER_CFG__RESERVED__SHIFT 0x00000014 + +// reg: VPEC_QUEUE2_LOG1BUFFER_CFG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE2_LOG1BUFFER_CFG__ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE2_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x00000001 +#define VPEC_QUEUE2_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x00000004 +#define VPEC_QUEUE2_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0x0000000c +#define VPEC_QUEUE2_LOG1BUFFER_CFG__RESERVED__SHIFT 0x00000014 + +// reg: VPEC_QUEUE3_RB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_RB_CNTL__RB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE3_RB_CNTL__RB_SIZE__SHIFT 0x00000001 +#define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x00000008 +#define VPEC_QUEUE3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x00000009 +#define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0x0000000a +#define VPEC_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0x0000000b +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0x0000000c +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0x0000000d +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x00000010 +#define VPEC_QUEUE3_RB_CNTL__RB_PRIV__SHIFT 0x00000017 +#define VPEC_QUEUE3_RB_CNTL__RB_VMID__SHIFT 0x00000018 + +// reg: VPEC_QUEUE3_SCHEDULE_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x00000000 +#define VPEC_QUEUE3_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x00000002 +#define VPEC_QUEUE3_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x00000006 +#define VPEC_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x00000008 + +// reg: VPEC_QUEUE3_RB_BASE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_RB_BASE__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_RB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_RB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_RB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_RB_RPTR__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_RB_RPTR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_RB_RPTR_HI__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_RB_WPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_RB_WPTR__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_RB_WPTR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_RB_WPTR_HI__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_RB_RPTR_ADDR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_RB_RPTR_ADDR_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x00000002 + +// reg: VPEC_QUEUE3_RB_AQL_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x00000001 +#define VPEC_QUEUE3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x00000008 +#define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x00000010 +#define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x00000011 +#define VPEC_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x00000012 + +// reg: VPEC_QUEUE3_MINOR_PTR_UPDATE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_CD_INFO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_CD_INFO__CD_INFO__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_RB_PREEMPT block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_SKIP_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_DOORBELL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_DOORBELL__ENABLE__SHIFT 0x0000001c +#define VPEC_QUEUE3_DOORBELL__CAPTURED__SHIFT 0x0000001e + +// reg: VPEC_QUEUE3_DOORBELL_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_DOORBELL_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE3_DUMMY0 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_DUMMY0__DUMMY__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_DUMMY1 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_DUMMY1__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_DUMMY2 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_DUMMY2__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_DUMMY3 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_DUMMY3__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_DUMMY4 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_DUMMY4__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_IB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_IB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE3_IB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE3_IB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE3_IB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_IB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE3_IB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_IB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE3_IB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_IB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE3_IB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_IB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_IB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_IB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_CMDIB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_CMDIB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE3_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x00000004 +#define VPEC_QUEUE3_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE3_CMDIB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE3_CMDIB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE3_CMDIB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_CMDIB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE3_CMDIB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_CMDIB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE3_CMDIB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_CMDIB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE3_CMDIB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_CMDIB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_CMDIB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_CMDIB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_3DLUTIB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE3_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE3_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE3_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE3_3DLUTIB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_3DLUTIB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE3_3DLUTIB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_3DLUTIB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE3_3DLUTIB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_3DLUTIB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE3_3DLUTIB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_3DLUTIB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_3DLUTIB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_3DLUTIB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_CSA_ADDR_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_CSA_ADDR_LO__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_CSA_ADDR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_CSA_ADDR_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_CONTEXT_STATUS block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_CONTEXT_STATUS__SELECTED__SHIFT 0x00000000 +#define VPEC_QUEUE3_CONTEXT_STATUS__USE_IB__SHIFT 0x00000001 +#define VPEC_QUEUE3_CONTEXT_STATUS__IDLE__SHIFT 0x00000002 +#define VPEC_QUEUE3_CONTEXT_STATUS__EXPIRED__SHIFT 0x00000003 +#define VPEC_QUEUE3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x00000004 +#define VPEC_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x00000007 +#define VPEC_QUEUE3_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x00000008 +#define VPEC_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0x0000000a +#define VPEC_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0x0000000b +#define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x0000000c +#define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x00000010 + +// reg: VPEC_QUEUE3_DOORBELL_LOG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_DOORBELL_LOG__BE_ERROR__SHIFT 0x00000000 +#define VPEC_QUEUE3_DOORBELL_LOG__DATA__SHIFT 0x00000002 + +// reg: VPEC_QUEUE3_IB_SUB_REMAIN block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_IB_SUB_REMAIN__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_PREEMPT block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_PREEMPT__IB_PREEMPT__SHIFT 0x00000000 + +// reg: VPEC_QUEUE3_LOG0BUFFER_CFG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_LOG0BUFFER_CFG__ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE3_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x00000004 +#define VPEC_QUEUE3_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0x0000000c +#define VPEC_QUEUE3_LOG0BUFFER_CFG__RESERVED__SHIFT 0x00000014 + +// reg: VPEC_QUEUE3_LOG1BUFFER_CFG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE3_LOG1BUFFER_CFG__ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE3_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x00000001 +#define VPEC_QUEUE3_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x00000004 +#define VPEC_QUEUE3_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0x0000000c +#define VPEC_QUEUE3_LOG1BUFFER_CFG__RESERVED__SHIFT 0x00000014 + +// reg: VPEC_QUEUE4_RB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_RB_CNTL__RB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE4_RB_CNTL__RB_SIZE__SHIFT 0x00000001 +#define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x00000008 +#define VPEC_QUEUE4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x00000009 +#define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0x0000000a +#define VPEC_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0x0000000b +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0x0000000c +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0x0000000d +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x00000010 +#define VPEC_QUEUE4_RB_CNTL__RB_PRIV__SHIFT 0x00000017 +#define VPEC_QUEUE4_RB_CNTL__RB_VMID__SHIFT 0x00000018 + +// reg: VPEC_QUEUE4_SCHEDULE_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x00000000 +#define VPEC_QUEUE4_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x00000002 +#define VPEC_QUEUE4_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x00000006 +#define VPEC_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x00000008 + +// reg: VPEC_QUEUE4_RB_BASE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_RB_BASE__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_RB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_RB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_RB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_RB_RPTR__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_RB_RPTR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_RB_RPTR_HI__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_RB_WPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_RB_WPTR__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_RB_WPTR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_RB_WPTR_HI__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_RB_RPTR_ADDR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_RB_RPTR_ADDR_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x00000002 + +// reg: VPEC_QUEUE4_RB_AQL_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x00000001 +#define VPEC_QUEUE4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x00000008 +#define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x00000010 +#define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x00000011 +#define VPEC_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x00000012 + +// reg: VPEC_QUEUE4_MINOR_PTR_UPDATE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_CD_INFO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_CD_INFO__CD_INFO__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_RB_PREEMPT block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_SKIP_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_DOORBELL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_DOORBELL__ENABLE__SHIFT 0x0000001c +#define VPEC_QUEUE4_DOORBELL__CAPTURED__SHIFT 0x0000001e + +// reg: VPEC_QUEUE4_DOORBELL_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_DOORBELL_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE4_DUMMY0 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_DUMMY0__DUMMY__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_DUMMY1 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_DUMMY1__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_DUMMY2 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_DUMMY2__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_DUMMY3 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_DUMMY3__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_DUMMY4 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_DUMMY4__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_IB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_IB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE4_IB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE4_IB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE4_IB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_IB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE4_IB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_IB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE4_IB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_IB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE4_IB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_IB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_IB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_IB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_CMDIB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_CMDIB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE4_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x00000004 +#define VPEC_QUEUE4_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE4_CMDIB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE4_CMDIB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE4_CMDIB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_CMDIB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE4_CMDIB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_CMDIB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE4_CMDIB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_CMDIB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE4_CMDIB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_CMDIB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_CMDIB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_CMDIB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_3DLUTIB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE4_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE4_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE4_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE4_3DLUTIB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_3DLUTIB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE4_3DLUTIB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_3DLUTIB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE4_3DLUTIB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_3DLUTIB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE4_3DLUTIB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_3DLUTIB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_3DLUTIB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_3DLUTIB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_CSA_ADDR_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_CSA_ADDR_LO__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_CSA_ADDR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_CSA_ADDR_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_CONTEXT_STATUS block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_CONTEXT_STATUS__SELECTED__SHIFT 0x00000000 +#define VPEC_QUEUE4_CONTEXT_STATUS__USE_IB__SHIFT 0x00000001 +#define VPEC_QUEUE4_CONTEXT_STATUS__IDLE__SHIFT 0x00000002 +#define VPEC_QUEUE4_CONTEXT_STATUS__EXPIRED__SHIFT 0x00000003 +#define VPEC_QUEUE4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x00000004 +#define VPEC_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x00000007 +#define VPEC_QUEUE4_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x00000008 +#define VPEC_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0x0000000a +#define VPEC_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0x0000000b +#define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x0000000c +#define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x00000010 + +// reg: VPEC_QUEUE4_DOORBELL_LOG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_DOORBELL_LOG__BE_ERROR__SHIFT 0x00000000 +#define VPEC_QUEUE4_DOORBELL_LOG__DATA__SHIFT 0x00000002 + +// reg: VPEC_QUEUE4_IB_SUB_REMAIN block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_IB_SUB_REMAIN__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_PREEMPT block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_PREEMPT__IB_PREEMPT__SHIFT 0x00000000 + +// reg: VPEC_QUEUE4_LOG0BUFFER_CFG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_LOG0BUFFER_CFG__ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE4_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x00000004 +#define VPEC_QUEUE4_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0x0000000c +#define VPEC_QUEUE4_LOG0BUFFER_CFG__RESERVED__SHIFT 0x00000014 + +// reg: VPEC_QUEUE4_LOG1BUFFER_CFG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE4_LOG1BUFFER_CFG__ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE4_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x00000001 +#define VPEC_QUEUE4_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x00000004 +#define VPEC_QUEUE4_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0x0000000c +#define VPEC_QUEUE4_LOG1BUFFER_CFG__RESERVED__SHIFT 0x00000014 + +// reg: VPEC_QUEUE5_RB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_RB_CNTL__RB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE5_RB_CNTL__RB_SIZE__SHIFT 0x00000001 +#define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x00000008 +#define VPEC_QUEUE5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x00000009 +#define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0x0000000a +#define VPEC_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0x0000000b +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0x0000000c +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0x0000000d +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x00000010 +#define VPEC_QUEUE5_RB_CNTL__RB_PRIV__SHIFT 0x00000017 +#define VPEC_QUEUE5_RB_CNTL__RB_VMID__SHIFT 0x00000018 + +// reg: VPEC_QUEUE5_SCHEDULE_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x00000000 +#define VPEC_QUEUE5_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x00000002 +#define VPEC_QUEUE5_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x00000006 +#define VPEC_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x00000008 + +// reg: VPEC_QUEUE5_RB_BASE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_RB_BASE__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_RB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_RB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_RB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_RB_RPTR__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_RB_RPTR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_RB_RPTR_HI__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_RB_WPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_RB_WPTR__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_RB_WPTR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_RB_WPTR_HI__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_RB_RPTR_ADDR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_RB_RPTR_ADDR_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x00000002 + +// reg: VPEC_QUEUE5_RB_AQL_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x00000001 +#define VPEC_QUEUE5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x00000008 +#define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x00000010 +#define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x00000011 +#define VPEC_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x00000012 + +// reg: VPEC_QUEUE5_MINOR_PTR_UPDATE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_CD_INFO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_CD_INFO__CD_INFO__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_RB_PREEMPT block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_SKIP_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_DOORBELL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_DOORBELL__ENABLE__SHIFT 0x0000001c +#define VPEC_QUEUE5_DOORBELL__CAPTURED__SHIFT 0x0000001e + +// reg: VPEC_QUEUE5_DOORBELL_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_DOORBELL_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE5_DUMMY0 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_DUMMY0__DUMMY__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_DUMMY1 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_DUMMY1__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_DUMMY2 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_DUMMY2__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_DUMMY3 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_DUMMY3__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_DUMMY4 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_DUMMY4__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_IB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_IB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE5_IB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE5_IB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE5_IB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_IB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE5_IB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_IB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE5_IB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_IB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE5_IB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_IB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_IB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_IB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_CMDIB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_CMDIB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE5_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x00000004 +#define VPEC_QUEUE5_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE5_CMDIB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE5_CMDIB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE5_CMDIB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_CMDIB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE5_CMDIB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_CMDIB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE5_CMDIB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_CMDIB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE5_CMDIB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_CMDIB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_CMDIB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_CMDIB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_3DLUTIB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE5_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE5_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE5_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE5_3DLUTIB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_3DLUTIB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE5_3DLUTIB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_3DLUTIB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE5_3DLUTIB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_3DLUTIB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE5_3DLUTIB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_3DLUTIB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_3DLUTIB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_3DLUTIB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_CSA_ADDR_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_CSA_ADDR_LO__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_CSA_ADDR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_CSA_ADDR_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_CONTEXT_STATUS block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_CONTEXT_STATUS__SELECTED__SHIFT 0x00000000 +#define VPEC_QUEUE5_CONTEXT_STATUS__USE_IB__SHIFT 0x00000001 +#define VPEC_QUEUE5_CONTEXT_STATUS__IDLE__SHIFT 0x00000002 +#define VPEC_QUEUE5_CONTEXT_STATUS__EXPIRED__SHIFT 0x00000003 +#define VPEC_QUEUE5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x00000004 +#define VPEC_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x00000007 +#define VPEC_QUEUE5_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x00000008 +#define VPEC_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0x0000000a +#define VPEC_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0x0000000b +#define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x0000000c +#define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x00000010 + +// reg: VPEC_QUEUE5_DOORBELL_LOG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_DOORBELL_LOG__BE_ERROR__SHIFT 0x00000000 +#define VPEC_QUEUE5_DOORBELL_LOG__DATA__SHIFT 0x00000002 + +// reg: VPEC_QUEUE5_IB_SUB_REMAIN block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_IB_SUB_REMAIN__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_PREEMPT block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_PREEMPT__IB_PREEMPT__SHIFT 0x00000000 + +// reg: VPEC_QUEUE5_LOG0BUFFER_CFG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_LOG0BUFFER_CFG__ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE5_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x00000004 +#define VPEC_QUEUE5_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0x0000000c +#define VPEC_QUEUE5_LOG0BUFFER_CFG__RESERVED__SHIFT 0x00000014 + +// reg: VPEC_QUEUE5_LOG1BUFFER_CFG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE5_LOG1BUFFER_CFG__ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE5_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x00000001 +#define VPEC_QUEUE5_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x00000004 +#define VPEC_QUEUE5_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0x0000000c +#define VPEC_QUEUE5_LOG1BUFFER_CFG__RESERVED__SHIFT 0x00000014 + +// reg: VPEC_QUEUE6_RB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_RB_CNTL__RB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE6_RB_CNTL__RB_SIZE__SHIFT 0x00000001 +#define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x00000008 +#define VPEC_QUEUE6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x00000009 +#define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0x0000000a +#define VPEC_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0x0000000b +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0x0000000c +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0x0000000d +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x00000010 +#define VPEC_QUEUE6_RB_CNTL__RB_PRIV__SHIFT 0x00000017 +#define VPEC_QUEUE6_RB_CNTL__RB_VMID__SHIFT 0x00000018 + +// reg: VPEC_QUEUE6_SCHEDULE_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x00000000 +#define VPEC_QUEUE6_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x00000002 +#define VPEC_QUEUE6_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x00000006 +#define VPEC_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x00000008 + +// reg: VPEC_QUEUE6_RB_BASE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_RB_BASE__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_RB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_RB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_RB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_RB_RPTR__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_RB_RPTR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_RB_RPTR_HI__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_RB_WPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_RB_WPTR__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_RB_WPTR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_RB_WPTR_HI__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_RB_RPTR_ADDR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_RB_RPTR_ADDR_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x00000002 + +// reg: VPEC_QUEUE6_RB_AQL_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x00000001 +#define VPEC_QUEUE6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x00000008 +#define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x00000010 +#define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x00000011 +#define VPEC_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x00000012 + +// reg: VPEC_QUEUE6_MINOR_PTR_UPDATE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_CD_INFO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_CD_INFO__CD_INFO__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_RB_PREEMPT block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_SKIP_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_DOORBELL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_DOORBELL__ENABLE__SHIFT 0x0000001c +#define VPEC_QUEUE6_DOORBELL__CAPTURED__SHIFT 0x0000001e + +// reg: VPEC_QUEUE6_DOORBELL_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_DOORBELL_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE6_DUMMY0 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_DUMMY0__DUMMY__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_DUMMY1 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_DUMMY1__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_DUMMY2 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_DUMMY2__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_DUMMY3 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_DUMMY3__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_DUMMY4 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_DUMMY4__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_IB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_IB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE6_IB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE6_IB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE6_IB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_IB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE6_IB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_IB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE6_IB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_IB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE6_IB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_IB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_IB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_IB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_CMDIB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_CMDIB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE6_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x00000004 +#define VPEC_QUEUE6_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE6_CMDIB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE6_CMDIB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE6_CMDIB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_CMDIB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE6_CMDIB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_CMDIB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE6_CMDIB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_CMDIB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE6_CMDIB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_CMDIB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_CMDIB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_CMDIB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_3DLUTIB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE6_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE6_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE6_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE6_3DLUTIB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_3DLUTIB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE6_3DLUTIB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_3DLUTIB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE6_3DLUTIB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_3DLUTIB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE6_3DLUTIB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_3DLUTIB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_3DLUTIB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_3DLUTIB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_CSA_ADDR_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_CSA_ADDR_LO__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_CSA_ADDR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_CSA_ADDR_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_CONTEXT_STATUS block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_CONTEXT_STATUS__SELECTED__SHIFT 0x00000000 +#define VPEC_QUEUE6_CONTEXT_STATUS__USE_IB__SHIFT 0x00000001 +#define VPEC_QUEUE6_CONTEXT_STATUS__IDLE__SHIFT 0x00000002 +#define VPEC_QUEUE6_CONTEXT_STATUS__EXPIRED__SHIFT 0x00000003 +#define VPEC_QUEUE6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x00000004 +#define VPEC_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x00000007 +#define VPEC_QUEUE6_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x00000008 +#define VPEC_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0x0000000a +#define VPEC_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0x0000000b +#define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x0000000c +#define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x00000010 + +// reg: VPEC_QUEUE6_DOORBELL_LOG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_DOORBELL_LOG__BE_ERROR__SHIFT 0x00000000 +#define VPEC_QUEUE6_DOORBELL_LOG__DATA__SHIFT 0x00000002 + +// reg: VPEC_QUEUE6_IB_SUB_REMAIN block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_IB_SUB_REMAIN__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_PREEMPT block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_PREEMPT__IB_PREEMPT__SHIFT 0x00000000 + +// reg: VPEC_QUEUE6_LOG0BUFFER_CFG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_LOG0BUFFER_CFG__ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE6_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x00000004 +#define VPEC_QUEUE6_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0x0000000c +#define VPEC_QUEUE6_LOG0BUFFER_CFG__RESERVED__SHIFT 0x00000014 + +// reg: VPEC_QUEUE6_LOG1BUFFER_CFG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE6_LOG1BUFFER_CFG__ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE6_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x00000001 +#define VPEC_QUEUE6_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x00000004 +#define VPEC_QUEUE6_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0x0000000c +#define VPEC_QUEUE6_LOG1BUFFER_CFG__RESERVED__SHIFT 0x00000014 + +// reg: VPEC_QUEUE7_RB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_RB_CNTL__RB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE7_RB_CNTL__RB_SIZE__SHIFT 0x00000001 +#define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x00000008 +#define VPEC_QUEUE7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x00000009 +#define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0x0000000a +#define VPEC_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0x0000000b +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0x0000000c +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0x0000000d +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x00000010 +#define VPEC_QUEUE7_RB_CNTL__RB_PRIV__SHIFT 0x00000017 +#define VPEC_QUEUE7_RB_CNTL__RB_VMID__SHIFT 0x00000018 + +// reg: VPEC_QUEUE7_SCHEDULE_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x00000000 +#define VPEC_QUEUE7_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x00000002 +#define VPEC_QUEUE7_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x00000006 +#define VPEC_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x00000008 + +// reg: VPEC_QUEUE7_RB_BASE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_RB_BASE__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_RB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_RB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_RB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_RB_RPTR__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_RB_RPTR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_RB_RPTR_HI__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_RB_WPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_RB_WPTR__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_RB_WPTR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_RB_WPTR_HI__OFFSET__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_RB_RPTR_ADDR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_RB_RPTR_ADDR_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x00000002 + +// reg: VPEC_QUEUE7_RB_AQL_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x00000001 +#define VPEC_QUEUE7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x00000008 +#define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x00000010 +#define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x00000011 +#define VPEC_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x00000012 + +// reg: VPEC_QUEUE7_MINOR_PTR_UPDATE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_CD_INFO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_CD_INFO__CD_INFO__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_RB_PREEMPT block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_SKIP_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_DOORBELL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_DOORBELL__ENABLE__SHIFT 0x0000001c +#define VPEC_QUEUE7_DOORBELL__CAPTURED__SHIFT 0x0000001e + +// reg: VPEC_QUEUE7_DOORBELL_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_DOORBELL_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE7_DUMMY0 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_DUMMY0__DUMMY__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_DUMMY1 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_DUMMY1__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_DUMMY2 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_DUMMY2__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_DUMMY3 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_DUMMY3__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_DUMMY4 block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_DUMMY4__VALUE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_IB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_IB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE7_IB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE7_IB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE7_IB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_IB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE7_IB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_IB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE7_IB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_IB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE7_IB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_IB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_IB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_IB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_CMDIB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_CMDIB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE7_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x00000004 +#define VPEC_QUEUE7_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE7_CMDIB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE7_CMDIB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE7_CMDIB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_CMDIB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE7_CMDIB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_CMDIB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE7_CMDIB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_CMDIB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE7_CMDIB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_CMDIB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_CMDIB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_CMDIB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_3DLUTIB_CNTL block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE7_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x00000008 +#define VPEC_QUEUE7_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x00000010 +#define VPEC_QUEUE7_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x0000001f + +// reg: VPEC_QUEUE7_3DLUTIB_RPTR block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_3DLUTIB_RPTR__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE7_3DLUTIB_OFFSET block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_3DLUTIB_OFFSET__OFFSET__SHIFT 0x00000002 + +// reg: VPEC_QUEUE7_3DLUTIB_BASE_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_3DLUTIB_BASE_LO__ADDR__SHIFT 0x00000005 + +// reg: VPEC_QUEUE7_3DLUTIB_BASE_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_3DLUTIB_BASE_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_3DLUTIB_SIZE block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_3DLUTIB_SIZE__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_CSA_ADDR_LO block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_CSA_ADDR_LO__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_CSA_ADDR_HI block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_CSA_ADDR_HI__ADDR__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_CONTEXT_STATUS block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_CONTEXT_STATUS__SELECTED__SHIFT 0x00000000 +#define VPEC_QUEUE7_CONTEXT_STATUS__USE_IB__SHIFT 0x00000001 +#define VPEC_QUEUE7_CONTEXT_STATUS__IDLE__SHIFT 0x00000002 +#define VPEC_QUEUE7_CONTEXT_STATUS__EXPIRED__SHIFT 0x00000003 +#define VPEC_QUEUE7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x00000004 +#define VPEC_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x00000007 +#define VPEC_QUEUE7_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x00000008 +#define VPEC_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0x0000000a +#define VPEC_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0x0000000b +#define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x0000000c +#define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x00000010 + +// reg: VPEC_QUEUE7_DOORBELL_LOG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_DOORBELL_LOG__BE_ERROR__SHIFT 0x00000000 +#define VPEC_QUEUE7_DOORBELL_LOG__DATA__SHIFT 0x00000002 + +// reg: VPEC_QUEUE7_IB_SUB_REMAIN block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_IB_SUB_REMAIN__SIZE__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_PREEMPT block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_PREEMPT__IB_PREEMPT__SHIFT 0x00000000 + +// reg: VPEC_QUEUE7_LOG0BUFFER_CFG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_LOG0BUFFER_CFG__ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE7_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x00000004 +#define VPEC_QUEUE7_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0x0000000c +#define VPEC_QUEUE7_LOG0BUFFER_CFG__RESERVED__SHIFT 0x00000014 + +// reg: VPEC_QUEUE7_LOG1BUFFER_CFG block: VPEC comp: amd.com/lib/vpec-vpe2sw/0 +#define VPEC_QUEUE7_LOG1BUFFER_CFG__ENABLE__SHIFT 0x00000000 +#define VPEC_QUEUE7_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x00000001 +#define VPEC_QUEUE7_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x00000004 +#define VPEC_QUEUE7_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0x0000000c +#define VPEC_QUEUE7_LOG1BUFFER_CFG__RESERVED__SHIFT 0x00000014 + +// reg: VPEP_MGCG_CNTL block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPEP_MGCG_CNTL__VPDPP0_CLK_GATE_DIS__SHIFT 0x00000000 +#define VPEP_MGCG_CNTL__VPDPP1_CLK_GATE_DIS__SHIFT 0x00000003 +#define VPEP_MGCG_CNTL__VPMPC_CLK_GATE_DIS__SHIFT 0x0000000c +#define VPEP_MGCG_CNTL__VPOPP_CLK_GATE_DIS__SHIFT 0x00000012 +#define VPEP_MGCG_CNTL__VPCDC_SOCCLK_G_GATE_DIS__SHIFT 0x00000014 +#define VPEP_MGCG_CNTL__VPCDC_SOCCLK_R_GATE_DIS__SHIFT 0x00000015 +#define VPEP_MGCG_CNTL__VPCDC_VPECLK_G_GATE_DIS__SHIFT 0x00000016 +#define VPEP_MGCG_CNTL__VPCDC_VPECLK_R_GATE_DIS__SHIFT 0x00000017 +#define VPEP_MGCG_CNTL__VPCDC_FE1_CLK_G_GATE_DIS__SHIFT 0x00000018 +#define VPEP_MGCG_CNTL__VPCDC_BE1_CLK_G_GATE_DIS__SHIFT 0x00000019 +#define VPEP_MGCG_CNTL__VPCDC_FGCG_REP_DIS__SHIFT 0x0000001e + +// reg: VPCDC_SOFT_RESET block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_SOFT_RESET__VPCDC_SOCCLK_SOFT_RESET__SHIFT 0x00000000 +#define VPCDC_SOFT_RESET__VPCDC_VPECLK_SOFT_RESET__SHIFT 0x00000001 + +// reg: VPCDC_FE0_SURFACE_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_FE0_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_FE0__SHIFT 0x00000000 +#define VPCDC_FE0_SURFACE_CONFIG__ROTATION_ANGLE_FE0__SHIFT 0x00000009 +#define VPCDC_FE0_SURFACE_CONFIG__H_MIRROR_EN_FE0__SHIFT 0x0000000c +#define VPCDC_FE0_SURFACE_CONFIG__PIX_SURFACE_LINEAR_FE0__SHIFT 0x0000000d + +// reg: VPCDC_FE0_CROSSBAR_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_ALPHA_FE0__SHIFT 0x00000000 +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_Y_G_FE0__SHIFT 0x00000002 +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CB_B_FE0__SHIFT 0x00000004 +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CR_R_FE0__SHIFT 0x00000006 + +// reg: VPCDC_FE0_VIEWPORT_START_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_X_START_FE0__SHIFT 0x00000000 +#define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_Y_START_FE0__SHIFT 0x00000010 + +// reg: VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_WIDTH_FE0__SHIFT 0x00000000 +#define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_HEIGHT_FE0__SHIFT 0x00000010 + +// reg: VPCDC_FE0_VIEWPORT_START_C_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_X_START_C_FE0__SHIFT 0x00000000 +#define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_Y_START_C_FE0__SHIFT 0x00000010 + +// reg: VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_WIDTH_C_FE0__SHIFT 0x00000000 +#define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_HEIGHT_C_FE0__SHIFT 0x00000010 + +// reg: VPCDC_FE1_SURFACE_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_FE1_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_FE1__SHIFT 0x00000000 +#define VPCDC_FE1_SURFACE_CONFIG__ROTATION_ANGLE_FE1__SHIFT 0x00000009 +#define VPCDC_FE1_SURFACE_CONFIG__H_MIRROR_EN_FE1__SHIFT 0x0000000c +#define VPCDC_FE1_SURFACE_CONFIG__PIX_SURFACE_LINEAR_FE1__SHIFT 0x0000000d + +// reg: VPCDC_FE1_CROSSBAR_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_FE1_CROSSBAR_CONFIG__CROSSBAR_SRC_ALPHA_FE1__SHIFT 0x00000000 +#define VPCDC_FE1_CROSSBAR_CONFIG__CROSSBAR_SRC_Y_G_FE1__SHIFT 0x00000002 +#define VPCDC_FE1_CROSSBAR_CONFIG__CROSSBAR_SRC_CB_B_FE1__SHIFT 0x00000004 +#define VPCDC_FE1_CROSSBAR_CONFIG__CROSSBAR_SRC_CR_R_FE1__SHIFT 0x00000006 + +// reg: VPCDC_FE1_VIEWPORT_START_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_FE1_VIEWPORT_START_CONFIG__VIEWPORT_X_START_FE1__SHIFT 0x00000000 +#define VPCDC_FE1_VIEWPORT_START_CONFIG__VIEWPORT_Y_START_FE1__SHIFT 0x00000010 + +// reg: VPCDC_FE1_VIEWPORT_DIMENSION_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_FE1_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_WIDTH_FE1__SHIFT 0x00000000 +#define VPCDC_FE1_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_HEIGHT_FE1__SHIFT 0x00000010 + +// reg: VPCDC_FE1_VIEWPORT_START_C_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_FE1_VIEWPORT_START_C_CONFIG__VIEWPORT_X_START_C_FE1__SHIFT 0x00000000 +#define VPCDC_FE1_VIEWPORT_START_C_CONFIG__VIEWPORT_Y_START_C_FE1__SHIFT 0x00000010 + +// reg: VPCDC_FE1_VIEWPORT_DIMENSION_C_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_FE1_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_WIDTH_C_FE1__SHIFT 0x00000000 +#define VPCDC_FE1_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_HEIGHT_C_FE1__SHIFT 0x00000010 + +// reg: VPCDC_BE0_P2B_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL0__SHIFT 0x00000000 +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL1__SHIFT 0x00000002 +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL2__SHIFT 0x00000004 +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL3__SHIFT 0x00000006 +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_FORMAT_SEL__SHIFT 0x00000008 +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_TILED__SHIFT 0x00000011 +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_X_START_PLANE0__SHIFT 0x00000012 +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_X_START_PLANE1__SHIFT 0x00000017 + +// reg: VPCDC_BE0_GLOBAL_SYNC_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_OFFSET__SHIFT 0x00000000 +#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_WIDTH__SHIFT 0x0000000a +#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VREADY_OFFSET__SHIFT 0x00000014 + +// reg: VPCDC_BE1_P2B_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_XBAR_SEL0__SHIFT 0x00000000 +#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_XBAR_SEL1__SHIFT 0x00000002 +#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_XBAR_SEL2__SHIFT 0x00000004 +#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_XBAR_SEL3__SHIFT 0x00000006 +#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_FORMAT_SEL__SHIFT 0x00000008 +#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_TILED__SHIFT 0x00000011 +#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_X_START_PLANE0__SHIFT 0x00000012 +#define VPCDC_BE1_P2B_CONFIG__VPCDC_BE1_P2B_X_START_PLANE1__SHIFT 0x00000017 + +// reg: VPCDC_BE1_GLOBAL_SYNC_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_BE1_GLOBAL_SYNC_CONFIG__BE1_VUPDATE_OFFSET__SHIFT 0x00000000 +#define VPCDC_BE1_GLOBAL_SYNC_CONFIG__BE1_VUPDATE_WIDTH__SHIFT 0x0000000a +#define VPCDC_BE1_GLOBAL_SYNC_CONFIG__BE1_VREADY_OFFSET__SHIFT 0x00000014 + +// reg: VPCDC_BE2_P2B_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_XBAR_SEL0__SHIFT 0x00000000 +#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_XBAR_SEL1__SHIFT 0x00000002 +#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_XBAR_SEL2__SHIFT 0x00000004 +#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_XBAR_SEL3__SHIFT 0x00000006 +#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_FORMAT_SEL__SHIFT 0x00000008 +#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_TILED__SHIFT 0x00000011 +#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_X_START_PLANE0__SHIFT 0x00000012 +#define VPCDC_BE2_P2B_CONFIG__VPCDC_BE2_P2B_X_START_PLANE1__SHIFT 0x00000017 + +// reg: VPCDC_BE2_GLOBAL_SYNC_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_BE2_GLOBAL_SYNC_CONFIG__BE2_VUPDATE_OFFSET__SHIFT 0x00000000 +#define VPCDC_BE2_GLOBAL_SYNC_CONFIG__BE2_VUPDATE_WIDTH__SHIFT 0x0000000a +#define VPCDC_BE2_GLOBAL_SYNC_CONFIG__BE2_VREADY_OFFSET__SHIFT 0x00000014 + +// reg: VPCDC_BE3_P2B_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_XBAR_SEL0__SHIFT 0x00000000 +#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_XBAR_SEL1__SHIFT 0x00000002 +#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_XBAR_SEL2__SHIFT 0x00000004 +#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_XBAR_SEL3__SHIFT 0x00000006 +#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_FORMAT_SEL__SHIFT 0x00000008 +#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_TILED__SHIFT 0x00000011 +#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_X_START_PLANE0__SHIFT 0x00000012 +#define VPCDC_BE3_P2B_CONFIG__VPCDC_BE3_P2B_X_START_PLANE1__SHIFT 0x00000017 + +// reg: VPCDC_BE3_GLOBAL_SYNC_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_BE3_GLOBAL_SYNC_CONFIG__BE3_VUPDATE_OFFSET__SHIFT 0x00000000 +#define VPCDC_BE3_GLOBAL_SYNC_CONFIG__BE3_VUPDATE_WIDTH__SHIFT 0x0000000a +#define VPCDC_BE3_GLOBAL_SYNC_CONFIG__BE3_VREADY_OFFSET__SHIFT 0x00000014 + +// reg: VPCDC_GLOBAL_SYNC_TRIGGER block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_GLOBAL_SYNC_TRIGGER__VPBE_GS_TRIG__SHIFT 0x00000000 + +// reg: VPCDC_VREADY_STATUS block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_VREADY_STATUS__VPFE_VR_STATUS__SHIFT 0x00000000 + +// reg: VPEP_MEM_GLOBAL_PWR_REQ_CNTL block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPEP_MEM_GLOBAL_PWR_REQ_CNTL__MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x00000000 + +// reg: VPFE0_MEM_PWR_CNTL block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_FORCE__SHIFT 0x00000000 +#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_MODE__SHIFT 0x00000002 +#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_STATE__SHIFT 0x00000004 +#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_DIS__SHIFT 0x00000006 + +// reg: VPFE1_MEM_PWR_CNTL block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPFE1_MEM_PWR_CNTL__VPFE1_MEM_PWR_FORCE__SHIFT 0x00000000 +#define VPFE1_MEM_PWR_CNTL__VPFE1_MEM_PWR_MODE__SHIFT 0x00000002 +#define VPFE1_MEM_PWR_CNTL__VPFE1_MEM_PWR_STATE__SHIFT 0x00000004 +#define VPFE1_MEM_PWR_CNTL__VPFE1_MEM_PWR_DIS__SHIFT 0x00000006 + +// reg: VPBE0_MEM_PWR_CNTL block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_FORCE__SHIFT 0x00000000 +#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_MODE__SHIFT 0x00000002 +#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_STATE__SHIFT 0x00000004 +#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_DIS__SHIFT 0x00000006 + +// reg: VPBE1_MEM_PWR_CNTL block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPBE1_MEM_PWR_CNTL__VPBE1_MEM_PWR_FORCE__SHIFT 0x00000000 +#define VPBE1_MEM_PWR_CNTL__VPBE1_MEM_PWR_MODE__SHIFT 0x00000002 +#define VPBE1_MEM_PWR_CNTL__VPBE1_MEM_PWR_STATE__SHIFT 0x00000004 +#define VPBE1_MEM_PWR_CNTL__VPBE1_MEM_PWR_DIS__SHIFT 0x00000006 + +// reg: VPBE2_MEM_PWR_CNTL block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPBE2_MEM_PWR_CNTL__VPBE2_MEM_PWR_FORCE__SHIFT 0x00000000 +#define VPBE2_MEM_PWR_CNTL__VPBE2_MEM_PWR_MODE__SHIFT 0x00000002 +#define VPBE2_MEM_PWR_CNTL__VPBE2_MEM_PWR_STATE__SHIFT 0x00000004 +#define VPBE2_MEM_PWR_CNTL__VPBE2_MEM_PWR_DIS__SHIFT 0x00000006 + +// reg: VPBE3_MEM_PWR_CNTL block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPBE3_MEM_PWR_CNTL__VPBE3_MEM_PWR_FORCE__SHIFT 0x00000000 +#define VPBE3_MEM_PWR_CNTL__VPBE3_MEM_PWR_MODE__SHIFT 0x00000002 +#define VPBE3_MEM_PWR_CNTL__VPBE3_MEM_PWR_STATE__SHIFT 0x00000004 +#define VPBE3_MEM_PWR_CNTL__VPBE3_MEM_PWR_DIS__SHIFT 0x00000006 + +// reg: VPEP_RBBMIF_TIMEOUT block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPEP_RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x00000000 +#define VPEP_RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_HOLD__SHIFT 0x00000014 + +// reg: VPEP_RBBMIF_STATUS block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x00000000 +#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x0000001c +#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x0000001d +#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x0000001e +#define VPEP_RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x0000001f + +// reg: VPEP_RBBMIF_TIMEOUT_DIS block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x00000000 +#define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x00000001 +#define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x00000002 +#define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x00000003 +#define VPEP_RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x00000004 + +// reg: VPCDC_DEBUG_CTRL0 block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_DEBUG_CTRL0__VPCDC_DBG_EN__SHIFT 0x00000000 +#define VPCDC_DEBUG_CTRL0__VPCDC_DBGMUX_OUT_0_SEL_SOCCLK__SHIFT 0x00000014 + +// reg: VPCDC_DEBUG_CTRL1 block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_0_SEL_VPECLK__SHIFT 0x00000000 +#define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_1_SEL_VPECLK__SHIFT 0x00000008 +#define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_2_SEL_VPECLK__SHIFT 0x00000010 +#define VPCDC_DEBUG_CTRL1__VPCDC_DBGMUX_OUT_3_SEL_VPECLK__SHIFT 0x00000018 + +// reg: VPCDC_TEST_DEBUG_INDEX block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_TEST_DEBUG_INDEX__VPCDC_TEST_DEBUG_INDEX__SHIFT 0x00000000 + +// reg: VPCDC_TEST_DEBUG_DATA block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_TEST_DEBUG_DATA__VPCDC_TEST_DEBUG_DATA__SHIFT 0x00000000 + +// reg: VPCDC_3DLUT_FL_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_MODE__SHIFT 0x00000000 +#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_CROSSBAR_SRC_G__SHIFT 0x00000002 +#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_CROSSBAR_SRC_B__SHIFT 0x00000004 +#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_CROSSBAR_SRC_R__SHIFT 0x00000006 +#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_SIZE__SHIFT 0x00000008 + +// reg: VPCDC_CONTROL block: CDC comp: amd.com/lib/vpcdc-vpep2sw/1.0 +#define VPCDC_CONTROL__VPCDC_HISTOGRAM0_EN__SHIFT 0x00000000 +#define VPCDC_CONTROL__VPCDC_HISTOGRAM1_EN__SHIFT 0x00000002 +#define VPCDC_CONTROL__VPCDC_FROD_EN__SHIFT 0x00000008 + +// reg: PERFCOUNTER_CNTL block: DC_PERFMON comp: amd.com/lib/dcperfmon/1.0 +#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x00000000 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x00000009 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0x0000000c +#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0x0000000f +#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x00000010 +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x00000016 +#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x00000017 +#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x00000018 +#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x00000019 +#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x0000001a +#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x0000001d + +// reg: PERFCOUNTER_CNTL2 block: DC_PERFMON comp: amd.com/lib/dcperfmon/1.0 +#define PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x00000000 +#define PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x00000002 +#define PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x00000003 +#define PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x00000008 +#define PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x0000001d + +// reg: PERFCOUNTER_STATE block: DC_PERFMON comp: amd.com/lib/dcperfmon/1.0 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x00000000 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x00000002 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x00000004 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x00000006 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x00000008 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0x0000000a +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0x0000000c +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0x0000000e +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x00000010 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x00000012 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x00000014 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x00000016 +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x00000018 +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x0000001a +#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x0000001c +#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x0000001e + +// reg: VPCNVC_SURFACE_PIXEL_FORMAT block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_SURFACE_PIXEL_FORMAT__VPCNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x00000000 + +// reg: VPCNVC_FORMAT_CONTROL block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x00000000 +#define VPCNVC_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x00000004 +#define VPCNVC_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x00000008 +#define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS__SHIFT 0x0000000c +#define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS_MSB_ALIGN__SHIFT 0x0000000d +#define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x00000010 +#define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x00000011 +#define VPCNVC_FORMAT_CONTROL__VPCNVC_UPDATE_PENDING__SHIFT 0x00000014 + +// reg: VPCNVC_FCNV_FP_BIAS_R block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x00000000 + +// reg: VPCNVC_FCNV_FP_BIAS_G block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x00000000 + +// reg: VPCNVC_FCNV_FP_BIAS_B block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x00000000 + +// reg: VPCNVC_FCNV_FP_SCALE_R block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x00000000 + +// reg: VPCNVC_FCNV_FP_SCALE_G block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x00000000 + +// reg: VPCNVC_FCNV_FP_SCALE_B block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x00000000 + +// reg: VPCNVC_COLOR_KEYER_CONTROL block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x00000000 +#define VPCNVC_COLOR_KEYER_CONTROL__LUMA_KEYER_EN__SHIFT 0x00000001 +#define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x00000004 + +// reg: VPCNVC_COLOR_KEYER_ALPHA block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x00000000 +#define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x00000010 + +// reg: VPCNVC_COLOR_KEYER_RED block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x00000000 +#define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x00000010 + +// reg: VPCNVC_COLOR_KEYER_GREEN block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x00000000 +#define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x00000010 + +// reg: VPCNVC_COLOR_KEYER_BLUE block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x00000000 +#define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x00000010 + +// reg: VPCNVC_ALPHA_2BIT_LUT01 block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT0__SHIFT 0x00000000 +#define VPCNVC_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT1__SHIFT 0x00000010 + +// reg: VPCNVC_ALPHA_2BIT_LUT23 block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT2__SHIFT 0x00000000 +#define VPCNVC_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT3__SHIFT 0x00000010 + +// reg: VPCNVC_PRE_DEALPHA block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x00000000 +#define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x00000004 + +// reg: VPCNVC_PRE_CSC_MODE block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x00000000 +#define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x00000002 + +// reg: VPCNVC_PRE_CSC_C11_C12 block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x00000000 +#define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x00000010 + +// reg: VPCNVC_PRE_CSC_C13_C14 block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x00000000 +#define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x00000010 + +// reg: VPCNVC_PRE_CSC_C21_C22 block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x00000000 +#define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x00000010 + +// reg: VPCNVC_PRE_CSC_C23_C24 block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x00000000 +#define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x00000010 + +// reg: VPCNVC_PRE_CSC_C31_C32 block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x00000000 +#define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x00000010 + +// reg: VPCNVC_PRE_CSC_C33_C34 block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x00000000 +#define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x00000010 + +// reg: VPCNVC_COEF_FORMAT block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x00000000 + +// reg: VPCNVC_PRE_DEGAM block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x00000000 +#define VPCNVC_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x00000004 + +// reg: VPCNVC_PRE_REALPHA block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x00000000 +#define VPCNVC_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x00000004 + +// reg: VPCNVC_CFG_TEST_DEBUG_INDEX block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_CFG_TEST_DEBUG_INDEX__VPCNVC_CFG_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define VPCNVC_CFG_TEST_DEBUG_INDEX__VPCNVC_CFG_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 + +// reg: VPCNVC_CFG_TEST_DEBUG_DATA block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCNVC_CFG_TEST_DEBUG_DATA__VPCNVC_CFG_TEST_DEBUG_DATA__SHIFT 0x00000000 + +// reg: VPDSCL_COEF_RAM_TAP_SELECT block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x00000000 +#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x00000008 +#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x00000010 + +// reg: VPDSCL_COEF_RAM_TAP_DATA block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x00000000 +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0x0000000f +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x00000010 +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x0000001f + +// reg: VPDSCL_MODE block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_MODE__VPDSCL_MODE__SHIFT 0x00000000 +#define VPDSCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0x0000000c +#define VPDSCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x00000010 +#define VPDSCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x00000014 +#define VPDSCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x00000018 + +// reg: VPDSCL_TAP_CONTROL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x00000000 +#define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x00000004 +#define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x00000008 +#define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0x0000000c + +// reg: VPDSCL_CONTROL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x00000000 + +// reg: VPDSCL_2TAP_CONTROL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x00000000 +#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x00000004 +#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x00000008 +#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x00000010 +#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x00000014 +#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x00000018 + +// reg: VPDSCL_MANUAL_REPLICATE_CONTROL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x00000000 +#define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x00000008 + +// reg: VPDSCL_HORZ_FILTER_SCALE_RATIO block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x00000000 + +// reg: VPDSCL_HORZ_FILTER_INIT block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x00000000 +#define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x00000018 + +// reg: VPDSCL_HORZ_FILTER_SCALE_RATIO_C block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x00000000 + +// reg: VPDSCL_HORZ_FILTER_INIT_C block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x00000000 +#define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x00000018 + +// reg: VPDSCL_VERT_FILTER_SCALE_RATIO block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x00000000 + +// reg: VPDSCL_VERT_FILTER_INIT block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x00000000 +#define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x00000018 + +// reg: VPDSCL_VERT_FILTER_INIT_BOT block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x00000000 +#define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x00000018 + +// reg: VPDSCL_VERT_FILTER_SCALE_RATIO_C block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x00000000 + +// reg: VPDSCL_VERT_FILTER_INIT_C block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x00000000 +#define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x00000018 + +// reg: VPDSCL_VERT_FILTER_INIT_BOT_C block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x00000000 +#define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x00000018 + +// reg: VPDSCL_BLACK_COLOR block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x00000000 +#define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x00000010 + +// reg: VPDSCL_UPDATE block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x00000000 + +// reg: VPDSCL_AUTOCAL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x00000000 + +// reg: VPDSCL_EXT_OVERSCAN_LEFT_RIGHT block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x00000000 +#define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x00000010 + +// reg: VPDSCL_EXT_OVERSCAN_TOP_BOTTOM block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x00000000 +#define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x00000010 + +// reg: VPOTG_H_BLANK block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPOTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x00000000 +#define VPOTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x00000010 + +// reg: VPOTG_V_BLANK block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPOTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x00000000 +#define VPOTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x00000010 + +// reg: VPDSCL_RECOUT_START block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_RECOUT_START__RECOUT_START_X__SHIFT 0x00000000 +#define VPDSCL_RECOUT_START__RECOUT_START_Y__SHIFT 0x00000010 + +// reg: VPDSCL_RECOUT_SIZE block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x00000000 +#define VPDSCL_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x00000010 + +// reg: VPMPC_SIZE block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPMPC_SIZE__VPMPC_WIDTH__SHIFT 0x00000000 +#define VPMPC_SIZE__VPMPC_HEIGHT__SHIFT 0x00000010 + +// reg: VPLB_DATA_FORMAT block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPLB_DATA_FORMAT__ALPHA_EN__SHIFT 0x00000004 + +// reg: VPLB_MEMORY_CTRL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPLB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x00000008 +#define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x00000010 +#define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x00000018 + +// reg: VPLB_V_COUNTER block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPLB_V_COUNTER__V_COUNTER__SHIFT 0x00000000 +#define VPLB_V_COUNTER__V_COUNTER_C__SHIFT 0x00000010 + +// reg: VPDSCL_MEM_PWR_CTRL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x00000000 +#define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x00000002 +#define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x00000004 +#define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x00000006 +#define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x00000008 +#define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0x0000000a +#define VPDSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x0000001c + +// reg: VPDSCL_MEM_PWR_STATUS block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x00000000 +#define VPDSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x00000002 +#define VPDSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x00000004 + +// reg: VPDSCL_EASF_H_MODE block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_H_MODE__SCL_EASF_H_EN__SHIFT 0x00000000 +#define VPDSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN__SHIFT 0x00000004 +#define VPDSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR__SHIFT 0x00000008 + +// reg: VPDSCL_EASF_V_MODE block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_V_MODE__SCL_EASF_V_EN__SHIFT 0x00000000 +#define VPDSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN__SHIFT 0x00000004 +#define VPDSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR__SHIFT 0x00000008 + +// reg: VPDSCL_SC_MODE block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_SC_MODE__SCL_SC_MATRIX_MODE__SHIFT 0x00000000 +#define VPDSCL_SC_MODE__SCL_SC_LTONL_EN__SHIFT 0x00000008 + +// reg: VPDSCL_SC_MATRIX_C0C1 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0__SHIFT 0x00000000 +#define VPDSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1__SHIFT 0x00000010 + +// reg: VPDSCL_SC_MATRIX_C2C3 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2__SHIFT 0x00000000 +#define VPDSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3__SHIFT 0x00000010 + +// reg: VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1__SHIFT 0x00000000 +#define VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2__SHIFT 0x00000010 + +// reg: VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1__SHIFT 0x00000000 +#define VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2__SHIFT 0x00000010 + +// reg: VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1__SHIFT 0x00000000 +#define VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2__SHIFT 0x00000010 + +// reg: VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1__SHIFT 0x00000000 +#define VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2__SHIFT 0x00000010 + +// reg: VPDSCL_EASF_V_RINGEST_3TAP_CNTL1 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT__SHIFT 0x00000000 +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL__SHIFT 0x00000010 + +// reg: VPDSCL_EASF_V_RINGEST_3TAP_CNTL2 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE__SHIFT 0x00000000 +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE__SHIFT 0x00000010 + +// reg: VPDSCL_EASF_V_RINGEST_3TAP_CNTL3 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE__SHIFT 0x00000000 +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET__SHIFT 0x00000010 + +// reg: VPDSCL_EASF_RINGEST_FORCE block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE__SHIFT 0x00000000 +#define VPDSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE__SHIFT 0x00000010 + +// reg: VPDSCL_EASF_H_BF_CNTL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE__SHIFT 0x00000008 +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE__SHIFT 0x00000010 +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN__SHIFT 0x00000014 +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN__SHIFT 0x00000018 +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN__SHIFT 0x0000001c + +// reg: VPDSCL_EASF_H_BF_FINAL_MAX_MIN block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB__SHIFT 0x00000008 +#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA__SHIFT 0x00000010 +#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB__SHIFT 0x00000018 + +// reg: VPDSCL_EASF_V_BF_CNTL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE__SHIFT 0x00000008 +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE__SHIFT 0x00000010 +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN__SHIFT 0x00000014 +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN__SHIFT 0x00000018 +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN__SHIFT 0x0000001c + +// reg: VPDSCL_EASF_V_BF_FINAL_MAX_MIN block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB__SHIFT 0x00000008 +#define VPDSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA__SHIFT 0x00000010 +#define VPDSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB__SHIFT 0x00000018 + +// reg: VPDSCL_EASF_H_BF1_PWL_SEG0 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_H_BF1_PWL_SEG1 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_H_BF1_PWL_SEG2 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_H_BF1_PWL_SEG3 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_H_BF1_PWL_SEG4 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_H_BF1_PWL_SEG5 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_H_BF1_PWL_SEG6 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_H_BF1_PWL_SEG7 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7__SHIFT 0x0000000c + +// reg: VPDSCL_EASF_V_BF1_PWL_SEG0 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_V_BF1_PWL_SEG1 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_V_BF1_PWL_SEG2 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_V_BF1_PWL_SEG3 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_V_BF1_PWL_SEG4 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_V_BF1_PWL_SEG5 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_V_BF1_PWL_SEG6 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_V_BF1_PWL_SEG7 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7__SHIFT 0x0000000c + +// reg: VPDSCL_EASF_H_BF3_PWL_SEG0 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0__SHIFT 0x00000013 + +// reg: VPDSCL_EASF_H_BF3_PWL_SEG1 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1__SHIFT 0x00000013 + +// reg: VPDSCL_EASF_H_BF3_PWL_SEG2 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2__SHIFT 0x00000013 + +// reg: VPDSCL_EASF_H_BF3_PWL_SEG3 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3__SHIFT 0x00000013 + +// reg: VPDSCL_EASF_H_BF3_PWL_SEG4 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4__SHIFT 0x00000013 + +// reg: VPDSCL_EASF_H_BF3_PWL_SEG5 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5__SHIFT 0x0000000c + +// reg: VPDSCL_EASF_V_BF3_PWL_SEG0 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0__SHIFT 0x00000013 + +// reg: VPDSCL_EASF_V_BF3_PWL_SEG1 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1__SHIFT 0x00000013 + +// reg: VPDSCL_EASF_V_BF3_PWL_SEG2 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2__SHIFT 0x00000013 + +// reg: VPDSCL_EASF_V_BF3_PWL_SEG3 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3__SHIFT 0x00000013 + +// reg: VPDSCL_EASF_V_BF3_PWL_SEG4 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4__SHIFT 0x00000013 + +// reg: VPDSCL_EASF_V_BF3_PWL_SEG5 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5__SHIFT 0x0000000c + +// reg: VPISHARP_MODE block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPISHARP_MODE__ISHARP_EN__SHIFT 0x00000000 +#define VPISHARP_MODE__ISHARP_NOISEDET_EN__SHIFT 0x00000004 +#define VPISHARP_MODE__ISHARP_NOISEDET_MODE__SHIFT 0x00000005 +#define VPISHARP_MODE__ISHARP_LBA_MODE__SHIFT 0x00000009 +#define VPISHARP_MODE__ISHARP_FMT_MODE__SHIFT 0x0000000b +#define VPISHARP_MODE__ISHARP_FMT_NORM__SHIFT 0x0000000c +#define VPISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT__SHIFT 0x0000001c + +// reg: VPISHARP_DELTA_CTRL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT__SHIFT 0x00000000 + +// reg: VPISHARP_DELTA_INDEX block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX__SHIFT 0x00000000 + +// reg: VPISHARP_DELTA_DATA block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPISHARP_DELTA_DATA__ISHARP_DELTA_DATA__SHIFT 0x00000000 + +// reg: VPISHARP_NLDELTA_SOFT_CLIP block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P__SHIFT 0x00000000 +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P__SHIFT 0x00000001 +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P__SHIFT 0x00000008 +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N__SHIFT 0x00000010 +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N__SHIFT 0x00000011 +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N__SHIFT 0x00000018 + +// reg: VPISHARP_NOISEDET_THRESHOLD block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE__SHIFT 0x00000000 +#define VPISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE__SHIFT 0x00000010 + +// reg: VPISHARP_NOISE_GAIN_PWL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN__SHIFT 0x00000000 +#define VPISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN__SHIFT 0x00000008 +#define VPISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE__SHIFT 0x00000010 + +// reg: VPISHARP_LBA_PWL_SEG0 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0__SHIFT 0x00000000 +#define VPISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0__SHIFT 0x0000000c +#define VPISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0__SHIFT 0x00000014 + +// reg: VPISHARP_LBA_PWL_SEG1 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1__SHIFT 0x00000000 +#define VPISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1__SHIFT 0x0000000c +#define VPISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1__SHIFT 0x00000014 + +// reg: VPISHARP_LBA_PWL_SEG2 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2__SHIFT 0x00000000 +#define VPISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2__SHIFT 0x0000000c +#define VPISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2__SHIFT 0x00000014 + +// reg: VPISHARP_LBA_PWL_SEG3 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3__SHIFT 0x00000000 +#define VPISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3__SHIFT 0x0000000c +#define VPISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3__SHIFT 0x00000014 + +// reg: VPISHARP_LBA_PWL_SEG4 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4__SHIFT 0x00000000 +#define VPISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4__SHIFT 0x0000000c +#define VPISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4__SHIFT 0x00000014 + +// reg: VPISHARP_LBA_PWL_SEG5 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5__SHIFT 0x00000000 +#define VPISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5__SHIFT 0x0000000c + +// reg: VPISHARP_DELTA_LUT_MEM_PWR_CTRL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE__SHIFT 0x00000000 +#define VPISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS__SHIFT 0x00000002 +#define VPISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE__SHIFT 0x00000004 + +// reg: VPDSCL_DEBUG block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_DEBUG__SCL_DEBUG__SHIFT 0x00000000 + +// reg: VPDSCL_TEST_DEBUG_INDEX block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define VPDSCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 + +// reg: VPDSCL_TEST_DEBUG_DATA block: VPDSCL comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDSCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x00000000 + +// reg: VPCM_CONTROL block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_CONTROL__VPCM_BYPASS__SHIFT 0x00000000 +#define VPCM_CONTROL__VPCM_UPDATE_PENDING__SHIFT 0x00000008 + +// reg: VPCM_POST_CSC_CONTROL block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE__SHIFT 0x00000000 +#define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE_CURRENT__SHIFT 0x00000002 + +// reg: VPCM_POST_CSC_C11_C12 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C11__SHIFT 0x00000000 +#define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C12__SHIFT 0x00000010 + +// reg: VPCM_POST_CSC_C13_C14 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C13__SHIFT 0x00000000 +#define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C14__SHIFT 0x00000010 + +// reg: VPCM_POST_CSC_C21_C22 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C21__SHIFT 0x00000000 +#define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C22__SHIFT 0x00000010 + +// reg: VPCM_POST_CSC_C23_C24 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C23__SHIFT 0x00000000 +#define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C24__SHIFT 0x00000010 + +// reg: VPCM_POST_CSC_C31_C32 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C31__SHIFT 0x00000000 +#define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C32__SHIFT 0x00000010 + +// reg: VPCM_POST_CSC_C33_C34 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C33__SHIFT 0x00000000 +#define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C34__SHIFT 0x00000010 + +// reg: VPCM_BIAS_CR_R block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_BIAS_CR_R__VPCM_BIAS_CR_R__SHIFT 0x00000000 + +// reg: VPCM_BIAS_Y_G_CB_B block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_Y_G__SHIFT 0x00000000 +#define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_CB_B__SHIFT 0x00000010 + +// reg: VPCM_GAMCOR_CONTROL block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE__SHIFT 0x00000000 +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_PWL_DISABLE__SHIFT 0x00000003 +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE_CURRENT__SHIFT 0x00000004 +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_SELECT_CURRENT__SHIFT 0x00000006 + +// reg: VPCM_GAMCOR_LUT_INDEX block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_LUT_INDEX__VPCM_GAMCOR_LUT_INDEX__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_LUT_DATA block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_LUT_DATA__VPCM_GAMCOR_LUT_DATA__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_LUT_CONTROL block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x00000000 +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x00000003 +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_DBG__SHIFT 0x00000005 +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_HOST_SEL__SHIFT 0x00000006 +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x00000007 + +// reg: VPCM_GAMCOR_RAMA_START_CNTL_B block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x00000014 + +// reg: VPCM_GAMCOR_RAMA_START_CNTL_G block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x00000014 + +// reg: VPCM_GAMCOR_RAMA_START_CNTL_R block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x00000014 + +// reg: VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_START_BASE_CNTL_B block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_START_BASE_CNTL_G block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_START_BASE_CNTL_R block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_END_CNTL1_B block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_END_CNTL1_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_END_CNTL2_B block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x00000010 + +// reg: VPCM_GAMCOR_RAMA_END_CNTL1_G block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_END_CNTL1_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_END_CNTL2_G block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x00000010 + +// reg: VPCM_GAMCOR_RAMA_END_CNTL1_R block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_END_CNTL1_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_END_CNTL2_R block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x00000010 + +// reg: VPCM_GAMCOR_RAMA_OFFSET_B block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_OFFSET_B__VPCM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_OFFSET_G block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_OFFSET_G__VPCM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_OFFSET_R block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_OFFSET_R__VPCM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_REGION_0_1 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_2_3 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_4_5 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_6_7 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_8_9 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_10_11 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_12_13 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_14_15 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_16_17 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_18_19 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_20_21 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_22_23 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_24_25 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_26_27 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_28_29 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_30_31 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_32_33 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_HDR_MULT_COEF block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_HDR_MULT_COEF__VPCM_HDR_MULT_COEF__SHIFT 0x00000000 + +// reg: VPCM_MEM_PWR_CTRL block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x00000000 +#define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x00000002 +#define VPCM_MEM_PWR_CTRL__HIST_MEM_PWR_FORCE__SHIFT 0x00000008 +#define VPCM_MEM_PWR_CTRL__HIST_MEM_PWR_DIS__SHIFT 0x00000009 + +// reg: VPCM_MEM_PWR_STATUS block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x00000000 +#define VPCM_MEM_PWR_STATUS__HIST_MEM_PWR_STATE__SHIFT 0x00000008 + +// reg: VPCM_DEALPHA block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_DEALPHA__VPCM_DEALPHA_EN__SHIFT 0x00000000 +#define VPCM_DEALPHA__VPCM_DEALPHA_ABLND__SHIFT 0x00000001 + +// reg: VPCM_COEF_FORMAT block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_COEF_FORMAT__VPCM_BIAS_FORMAT__SHIFT 0x00000000 +#define VPCM_COEF_FORMAT__VPCM_POST_CSC_COEF_FORMAT__SHIFT 0x00000004 + +// reg: VPCM_TEST_DEBUG_INDEX block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_TEST_DEBUG_INDEX__VPCM_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define VPCM_TEST_DEBUG_INDEX__VPCM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 + +// reg: VPCM_TEST_DEBUG_DATA block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_TEST_DEBUG_DATA__VPCM_TEST_DEBUG_DATA__SHIFT 0x00000000 + +// reg: VPCM_HIST_CNTL block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_HIST_CNTL__VPCM_HIST_SEL__SHIFT 0x00000000 +#define VPCM_HIST_CNTL__VPCM_HIST_CH_EN__SHIFT 0x00000002 +#define VPCM_HIST_CNTL__VPCM_HIST_SRC1_SEL__SHIFT 0x00000004 +#define VPCM_HIST_CNTL__VPCM_HIST_SRC2_SEL__SHIFT 0x00000005 +#define VPCM_HIST_CNTL__VPCM_HIST_SRC3_SEL__SHIFT 0x00000006 +#define VPCM_HIST_CNTL__VPCM_HIST_CH1_XBAR__SHIFT 0x00000007 +#define VPCM_HIST_CNTL__VPCM_HIST_CH2_XBAR__SHIFT 0x00000009 +#define VPCM_HIST_CNTL__VPCM_HIST_CH3_XBAR__SHIFT 0x0000000b +#define VPCM_HIST_CNTL__VPCM_HIST_FORMAT__SHIFT 0x0000000d +#define VPCM_HIST_CNTL__VPCM_HIST_READ_CHANNEL_MASK__SHIFT 0x0000000f + +// reg: VPCM_HIST_SCALE_SRC1 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_HIST_SCALE_SRC1__VPCM_HIST_SCALE_SRC1__SHIFT 0x00000000 + +// reg: VPCM_HIST_COEFA_SRC2 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_HIST_COEFA_SRC2__VPCM_HIST_COEFA_SRC2__SHIFT 0x00000000 + +// reg: VPCM_HIST_COEFB_SRC2 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_HIST_COEFB_SRC2__VPCM_HIST_COEFB_SRC2__SHIFT 0x00000000 + +// reg: VPCM_HIST_COEFC_SRC2 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_HIST_COEFC_SRC2__VPCM_HIST_COEFC_SRC2__SHIFT 0x00000000 + +// reg: VPCM_HIST_SCALE_SRC3 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_HIST_SCALE_SRC3__VPCM_HIST_SCALE_SRC3__SHIFT 0x00000000 + +// reg: VPCM_HIST_BIAS_SRC1 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_HIST_BIAS_SRC1__VPCM_HIST_BIAS_SRC1__SHIFT 0x00000000 + +// reg: VPCM_HIST_BIAS_SRC2 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_HIST_BIAS_SRC2__VPCM_HIST_BIAS_SRC2__SHIFT 0x00000000 + +// reg: VPCM_HIST_BIAS_SRC3 block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_HIST_BIAS_SRC3__VPCM_HIST_BIAS_SRC3__SHIFT 0x00000000 + +// reg: VPCM_HIST_LOCK block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_HIST_LOCK__VPCM_HIST_LOCK__SHIFT 0x00000000 + +// reg: VPCM_HIST_INDEX block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_HIST_INDEX__VPCM_HIST_INDEX__SHIFT 0x00000000 + +// reg: VPCM_HIST_DATA block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_HIST_DATA__VPCM_HIST_DATA__SHIFT 0x00000000 + +// reg: VPCM_HIST_STATUS block: VPCM comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPCM_HIST_STATUS__VPCM_HIST_RDY_STATUS__SHIFT 0x00000000 +#define VPCM_HIST_STATUS__VPCM_HIST_FRAME_COLLECT_SKIPPED__SHIFT 0x00000004 +#define VPCM_HIST_STATUS__VPCM_HIST_FRAME_COLLECT_SKIPPED_CURRENT__SHIFT 0x00000005 +#define VPCM_HIST_STATUS__VPCM_HIST_FRAME_COLLECT_SKIPPED_CNT__SHIFT 0x00000006 +#define VPCM_HIST_STATUS__VPCM_HIST_TX_NOT_COMPLETED__SHIFT 0x00000010 +#define VPCM_HIST_STATUS__VPCM_HIST_TX_NOT_COMPLETED_CURRENT__SHIFT 0x00000011 +#define VPCM_HIST_STATUS__VPCM_HIST_TX_STATUS__SHIFT 0x00000012 +#define VPCM_HIST_STATUS__VPCM_HIST_COUNT_OVERFLOW__SHIFT 0x00000018 +#define VPCM_HIST_STATUS__VPCM_HIST_COUNT_OVERFLOW_CURRENT__SHIFT 0x00000019 +#define VPCM_HIST_STATUS__VPCM_HIST_COLLECT_INCOMPLETE__SHIFT 0x0000001a +#define VPCM_HIST_STATUS__VPCM_HIST_COLLECT_INCOMPLETE_CURRENT__SHIFT 0x0000001b + +// reg: VPDPP_CONTROL block: VPDPP_TOP comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDPP_CONTROL__VPECLK_G_GATE_DISABLE__SHIFT 0x00000008 +#define VPDPP_CONTROL__VPECLK_G_VPDSCL_GATE_DISABLE__SHIFT 0x0000000c +#define VPDPP_CONTROL__VPECLK_R_GATE_DISABLE__SHIFT 0x0000000e +#define VPDPP_CONTROL__VPDPP_FGCG_REP_DIS__SHIFT 0x00000018 + +// reg: VPDPP_SOFT_RESET block: VPDPP_TOP comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDPP_SOFT_RESET__VPCNVC_SOFT_RESET__SHIFT 0x00000000 +#define VPDPP_SOFT_RESET__VPDSCL_SOFT_RESET__SHIFT 0x00000004 +#define VPDPP_SOFT_RESET__VPCM_SOFT_RESET__SHIFT 0x00000008 +#define VPDPP_SOFT_RESET__VPOBUF_SOFT_RESET__SHIFT 0x0000000c +#define VPDPP_SOFT_RESET__VPHIST_SOFT_RESET__SHIFT 0x00000010 + +// reg: VPDPP_CRC_VAL_R_G block: VPDPP_TOP comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDPP_CRC_VAL_R_G__VPDPP_CRC_R_CR__SHIFT 0x00000000 +#define VPDPP_CRC_VAL_R_G__VPDPP_CRC_G_Y__SHIFT 0x00000010 + +// reg: VPDPP_CRC_VAL_B_A block: VPDPP_TOP comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDPP_CRC_VAL_B_A__VPDPP_CRC_B_CB__SHIFT 0x00000000 +#define VPDPP_CRC_VAL_B_A__VPDPP_CRC_ALPHA__SHIFT 0x00000010 + +// reg: VPDPP_CRC_CTRL block: VPDPP_TOP comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDPP_CRC_CTRL__VPDPP_CRC_EN__SHIFT 0x00000000 +#define VPDPP_CRC_CTRL__VPDPP_CRC_CONT_EN__SHIFT 0x00000001 +#define VPDPP_CRC_CTRL__VPDPP_CRC_ONE_SHOT_PENDING__SHIFT 0x00000002 +#define VPDPP_CRC_CTRL__VPDPP_CRC_420_COMP_SEL__SHIFT 0x00000003 +#define VPDPP_CRC_CTRL__VPDPP_CRC_SRC_SEL__SHIFT 0x00000004 +#define VPDPP_CRC_CTRL__VPDPP_CRC_PIX_FORMAT_SEL__SHIFT 0x0000000b +#define VPDPP_CRC_CTRL__VPDPP_CRC_MASK__SHIFT 0x00000010 + +// reg: VPHOST_READ_CONTROL block: VPDPP_TOP comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPHOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x00000000 + +// reg: VPDPP_DEBUG_SEL block: VPDPP_TOP comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDPP_DEBUG_SEL__VPDPP_VPECLK_DEBUG_BUS_SEL__SHIFT 0x00000000 +#define VPDPP_DEBUG_SEL__VPDPP_DBG_EN__SHIFT 0x0000001f + +// reg: VPDPP_DEBUG_SPARE block: VPDPP_TOP comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDPP_DEBUG_SPARE__VPDPP_DEBUG_SPARE__SHIFT 0x00000000 + +// reg: VPDPP_TEST_DEBUG_INDEX block: VPDPP_TOP comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDPP_TEST_DEBUG_INDEX__VPDPP_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define VPDPP_TEST_DEBUG_INDEX__VPDPP_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 + +// reg: VPDPP_TEST_DEBUG_DATA block: VPDPP_TOP comp: amd.com/lib/vpdpp-vpep2sw/1.0 +#define VPDPP_TEST_DEBUG_DATA__VPDPP_TEST_DEBUG_DATA__SHIFT 0x00000000 + +// reg: VPMPC_CLOCK_CONTROL block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_CLOCK_CONTROL__VPECLK_G_GATE_DISABLE__SHIFT 0x00000000 +#define VPMPC_CLOCK_CONTROL__VPECLK_R_GATE_DISABLE__SHIFT 0x00000001 + +// reg: VPMPC_SOFT_RESET block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_SOFT_RESET__VPMPCC0_SOFT_RESET__SHIFT 0x00000000 +#define VPMPC_SOFT_RESET__VPMPCC1_SOFT_RESET__SHIFT 0x00000001 +#define VPMPC_SOFT_RESET__VPMPC_SFR0_SOFT_RESET__SHIFT 0x0000000a +#define VPMPC_SOFT_RESET__VPMPC_SFR1_SOFT_RESET__SHIFT 0x0000000b +#define VPMPC_SOFT_RESET__VPMPC_SFT0_SOFT_RESET__SHIFT 0x00000014 +#define VPMPC_SOFT_RESET__VPMPC_SFT1_SOFT_RESET__SHIFT 0x00000015 +#define VPMPC_SOFT_RESET__VPMPC_SOFT_RESET__SHIFT 0x0000001f + +// reg: VPMPC_CRC_CTRL block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_CRC_CTRL__VPMPC_CRC_EN__SHIFT 0x00000000 +#define VPMPC_CRC_CTRL__VPMPC_CRC_CONT_EN__SHIFT 0x00000004 +#define VPMPC_CRC_CTRL__VPMPC_CRC_SRC_SEL__SHIFT 0x00000018 +#define VPMPC_CRC_CTRL__VPMPC_CRC_ONE_SHOT_PENDING__SHIFT 0x0000001c +#define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_ENABLED__SHIFT 0x0000001e +#define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_LOCK__SHIFT 0x0000001f + +// reg: VPMPC_CRC_SEL_CONTROL block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPDPP_SEL__SHIFT 0x00000000 +#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPOPP_SEL__SHIFT 0x00000004 +#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_MASK__SHIFT 0x00000010 + +// reg: VPMPC_CRC_RESULT_AR block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_A__SHIFT 0x00000000 +#define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_R__SHIFT 0x00000010 + +// reg: VPMPC_CRC_RESULT_GB block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_G__SHIFT 0x00000000 +#define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_B__SHIFT 0x00000010 + +// reg: VPMPC_CRC_RESULT_C block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_CRC_RESULT_C__VPMPC_CRC_RESULT_C__SHIFT 0x00000000 + +// reg: VPMPC_DEBUG_CONTROL block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_EN__SHIFT 0x00000000 +#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_TOP_DATA_SELECT__SHIFT 0x00000001 +#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_DIRECT_OUT_SELECT__SHIFT 0x00000004 +#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_DIRECT_OUT_SFR_SELECT__SHIFT 0x00000008 +#define VPMPC_DEBUG_CONTROL__VPMPC_DEBUG_DATA_DIRECT_OUT_SFT_SELECT__SHIFT 0x0000000c +#define VPMPC_DEBUG_CONTROL__VPMPC_RMCM_DEBUG_DATA_SELECT__SHIFT 0x00000010 + +// reg: VPMPCC_DEBUG_DATA_SELECT block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT0__SHIFT 0x00000000 +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT0__SHIFT 0x00000004 +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT0__SHIFT 0x00000006 +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT1__SHIFT 0x00000008 +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT1__SHIFT 0x0000000c +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT1__SHIFT 0x0000000e +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT2__SHIFT 0x00000010 +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT2__SHIFT 0x00000014 +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT2__SHIFT 0x00000016 +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_SELECT3__SHIFT 0x00000018 +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_BYTE_SELECT3__SHIFT 0x0000001c +#define VPMPCC_DEBUG_DATA_SELECT__VPMPCC_DEBUG_DATA_VPMPCC_OGAM_SELECT3__SHIFT 0x0000001e + +// reg: VPMPC_BYPASS_BG_AR block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_ALPHA__SHIFT 0x00000000 +#define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_R_CR__SHIFT 0x00000010 + +// reg: VPMPC_BYPASS_BG_GB block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_G_Y__SHIFT 0x00000000 +#define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_B_CB__SHIFT 0x00000010 + +// reg: VPMPC_HOST_READ_CONTROL block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x00000000 + +// reg: VPMPC_PENDING_STATUS_MISC block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_PENDING_STATUS_MISC__VPMPCC0_CONFIG_UPDATE_PENDING__SHIFT 0x00000008 +#define VPMPC_PENDING_STATUS_MISC__VPMPCC1_CONFIG_UPDATE_PENDING__SHIFT 0x00000009 + +// reg: VPMPC_VPCDC0_3DLUT_FL_CONFIG block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_VPCDC0_3DLUT_FL_CONFIG__VPCDC0_3DLUT_FL_MODE__SHIFT 0x00000000 +#define VPMPC_VPCDC0_3DLUT_FL_CONFIG__VPCDC0_3DLUT_FL_FORMAT__SHIFT 0x00000004 + +// reg: VPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE__VPCDC0_3DLUT_FL_BIAS__SHIFT 0x00000000 +#define VPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE__VPCDC0_3DLUT_FL_SCALE__SHIFT 0x00000010 + +// reg: VPMPC_CFG_TEST_DEBUG_INDEX block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_CFG_TEST_DEBUG_INDEX__VPMPC_CFG_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define VPMPC_CFG_TEST_DEBUG_INDEX__VPMPC_CFG_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 + +// reg: VPMPC_CFG_TEST_DEBUG_DATA block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_CFG_TEST_DEBUG_DATA__VPMPC_CFG_TEST_DEBUG_DATA__SHIFT 0x00000000 + +// reg: VPMPC_OUT0_MUX block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT0_MUX__VPMPC_OUT_MUX__SHIFT 0x00000000 + +// reg: VPMPC_OUT0_FLOAT_CONTROL block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT0_FLOAT_CONTROL__VPMPC_OUT_FLOAT_EN__SHIFT 0x00000000 + +// reg: VPMPC_OUT0_DENORM_CONTROL block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x00000000 +#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0x0000000c +#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_MODE__SHIFT 0x00000018 + +// reg: VPMPC_OUT0_DENORM_CLAMP_G_Y block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x00000000 +#define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0x0000000c + +// reg: VPMPC_OUT0_DENORM_CLAMP_B_CB block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x00000000 +#define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0x0000000c + +// reg: VPMPC_OUT1_MUX block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT1_MUX__VPMPC_OUT_MUX__SHIFT 0x00000000 + +// reg: VPMPC_OUT1_FLOAT_CONTROL block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT1_FLOAT_CONTROL__VPMPC_OUT_FLOAT_EN__SHIFT 0x00000000 + +// reg: VPMPC_OUT1_DENORM_CONTROL block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT1_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x00000000 +#define VPMPC_OUT1_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0x0000000c +#define VPMPC_OUT1_DENORM_CONTROL__VPMPC_OUT_DENORM_MODE__SHIFT 0x00000018 + +// reg: VPMPC_OUT1_DENORM_CLAMP_G_Y block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT1_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x00000000 +#define VPMPC_OUT1_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0x0000000c + +// reg: VPMPC_OUT1_DENORM_CLAMP_B_CB block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT1_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x00000000 +#define VPMPC_OUT1_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0x0000000c + +// reg: VPMPC_OUT_CSC_COEF_FORMAT block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT_CSC_COEF_FORMAT__VPMPC_OCSC0_COEF_FORMAT__SHIFT 0x00000000 +#define VPMPC_OUT_CSC_COEF_FORMAT__VPMPC_OCSC1_COEF_FORMAT__SHIFT 0x00000001 + +// reg: VPMPC_OUT0_CSC_MODE block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE__SHIFT 0x00000000 +#define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE_CURRENT__SHIFT 0x00000007 + +// reg: VPMPC_OUT0_CSC_C11_C12_A block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C11_A__SHIFT 0x00000000 +#define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C12_A__SHIFT 0x00000010 + +// reg: VPMPC_OUT0_CSC_C13_C14_A block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C13_A__SHIFT 0x00000000 +#define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C14_A__SHIFT 0x00000010 + +// reg: VPMPC_OUT0_CSC_C21_C22_A block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C21_A__SHIFT 0x00000000 +#define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C22_A__SHIFT 0x00000010 + +// reg: VPMPC_OUT0_CSC_C23_C24_A block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C23_A__SHIFT 0x00000000 +#define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C24_A__SHIFT 0x00000010 + +// reg: VPMPC_OUT0_CSC_C31_C32_A block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C31_A__SHIFT 0x00000000 +#define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C32_A__SHIFT 0x00000010 + +// reg: VPMPC_OUT0_CSC_C33_C34_A block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C33_A__SHIFT 0x00000000 +#define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C34_A__SHIFT 0x00000010 + +// reg: VPMPC_OUT1_CSC_MODE block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT1_CSC_MODE__VPMPC_OCSC_MODE__SHIFT 0x00000000 +#define VPMPC_OUT1_CSC_MODE__VPMPC_OCSC_MODE_CURRENT__SHIFT 0x00000007 + +// reg: VPMPC_OUT1_CSC_C11_C12_A block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT1_CSC_C11_C12_A__VPMPC_OCSC_C11_A__SHIFT 0x00000000 +#define VPMPC_OUT1_CSC_C11_C12_A__VPMPC_OCSC_C12_A__SHIFT 0x00000010 + +// reg: VPMPC_OUT1_CSC_C13_C14_A block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT1_CSC_C13_C14_A__VPMPC_OCSC_C13_A__SHIFT 0x00000000 +#define VPMPC_OUT1_CSC_C13_C14_A__VPMPC_OCSC_C14_A__SHIFT 0x00000010 + +// reg: VPMPC_OUT1_CSC_C21_C22_A block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT1_CSC_C21_C22_A__VPMPC_OCSC_C21_A__SHIFT 0x00000000 +#define VPMPC_OUT1_CSC_C21_C22_A__VPMPC_OCSC_C22_A__SHIFT 0x00000010 + +// reg: VPMPC_OUT1_CSC_C23_C24_A block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT1_CSC_C23_C24_A__VPMPC_OCSC_C23_A__SHIFT 0x00000000 +#define VPMPC_OUT1_CSC_C23_C24_A__VPMPC_OCSC_C24_A__SHIFT 0x00000010 + +// reg: VPMPC_OUT1_CSC_C31_C32_A block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT1_CSC_C31_C32_A__VPMPC_OCSC_C31_A__SHIFT 0x00000000 +#define VPMPC_OUT1_CSC_C31_C32_A__VPMPC_OCSC_C32_A__SHIFT 0x00000010 + +// reg: VPMPC_OUT1_CSC_C33_C34_A block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OUT1_CSC_C33_C34_A__VPMPC_OCSC_C33_A__SHIFT 0x00000000 +#define VPMPC_OUT1_CSC_C33_C34_A__VPMPC_OCSC_C34_A__SHIFT 0x00000010 + +// reg: VPMPC_OCSC_TEST_DEBUG_INDEX block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OCSC_TEST_DEBUG_INDEX__VPMPC_OCSC_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define VPMPC_OCSC_TEST_DEBUG_INDEX__VPMPC_OCSC_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 + +// reg: VPMPC_OCSC_TEST_DEBUG_DATA block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_OCSC_TEST_DEBUG_DATA__VPMPC_OCSC_TEST_DEBUG_DATA__SHIFT 0x00000000 + +// reg: VPMPCC_TOP_SEL block: VPMPCC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_TOP_SEL__VPMPCC_TOP_SEL__SHIFT 0x00000000 + +// reg: VPMPCC_BOT_SEL block: VPMPCC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_BOT_SEL__VPMPCC_BOT_SEL__SHIFT 0x00000000 + +// reg: VPMPCC_VPOPP_ID block: VPMPCC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_VPOPP_ID__VPMPCC_VPOPP_ID__SHIFT 0x00000000 + +// reg: VPMPCC_CONTROL block: VPMPCC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_CONTROL__VPMPCC_MODE__SHIFT 0x00000000 +#define VPMPCC_CONTROL__VPMPCC_ALPHA_BLND_MODE__SHIFT 0x00000004 +#define VPMPCC_CONTROL__VPMPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x00000006 +#define VPMPCC_CONTROL__VPMPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x00000007 +#define VPMPCC_CONTROL__VPMPCC_BOT_GAIN_MODE__SHIFT 0x0000000b + +// reg: VPMPCC_CONTROL2 block: VPMPCC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_CONTROL2__VPMPCC_GLOBAL_ALPHA__SHIFT 0x00000000 +#define VPMPCC_CONTROL2__VPMPCC_GLOBAL_GAIN__SHIFT 0x00000010 + +// reg: VPMPCC_TOP_GAIN block: VPMPCC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_TOP_GAIN__VPMPCC_TOP_GAIN__SHIFT 0x00000000 + +// reg: VPMPCC_BOT_GAIN_INSIDE block: VPMPCC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_BOT_GAIN_INSIDE__VPMPCC_BOT_GAIN_INSIDE__SHIFT 0x00000000 + +// reg: VPMPCC_BOT_GAIN_OUTSIDE block: VPMPCC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_BOT_GAIN_OUTSIDE__VPMPCC_BOT_GAIN_OUTSIDE__SHIFT 0x00000000 + +// reg: VPMPCC_MOVABLE_CM_LOCATION_CONTROL block: VPMPCC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT 0x00000000 +#define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT 0x00000004 + +// reg: VPMPCC_BG_R_CR block: VPMPCC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_BG_R_CR__VPMPCC_BG_R_CR__SHIFT 0x00000000 + +// reg: VPMPCC_BG_G_Y block: VPMPCC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_BG_G_Y__VPMPCC_BG_G_Y__SHIFT 0x00000000 + +// reg: VPMPCC_BG_B_CB block: VPMPCC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_BG_B_CB__VPMPCC_BG_B_CB__SHIFT 0x00000000 + +// reg: VPMPCC_MEM_PWR_CTRL block: VPMPCC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x00000000 +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_DIS__SHIFT 0x00000002 +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x00000004 +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_STATE__SHIFT 0x00000008 + +// reg: VPMPCC_STATUS block: VPMPCC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_STATUS__VPMPCC_IDLE__SHIFT 0x00000000 +#define VPMPCC_STATUS__VPMPCC_BUSY__SHIFT 0x00000001 +#define VPMPCC_STATUS__VPMPCC_DISABLED__SHIFT 0x00000002 + +// reg: VPMPCC_TEST_DEBUG_INDEX block: VPMPCC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_TEST_DEBUG_INDEX__VPMPCC_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define VPMPCC_TEST_DEBUG_INDEX__VPMPCC_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 + +// reg: VPMPCC_TEST_DEBUG_DATA block: VPMPCC comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_TEST_DEBUG_DATA__VPMPCC_TEST_DEBUG_DATA__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_CONTROL block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE__SHIFT 0x00000000 +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_PWL_DISABLE__SHIFT 0x00000003 +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE_CURRENT__SHIFT 0x00000007 +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_SELECT_CURRENT__SHIFT 0x00000009 + +// reg: VPMPCC_OGAM_LUT_INDEX block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_LUT_INDEX__VPMPCC_OGAM_LUT_INDEX__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_LUT_DATA block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_LUT_DATA__VPMPCC_OGAM_LUT_DATA__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_LUT_CONTROL block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x00000000 +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x00000003 +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_DBG__SHIFT 0x00000005 +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_HOST_SEL__SHIFT 0x00000006 +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x00000007 + +// reg: VPMPCC_OGAM_RAMA_START_CNTL_B block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x00000014 + +// reg: VPMPCC_OGAM_RAMA_START_CNTL_G block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x00000014 + +// reg: VPMPCC_OGAM_RAMA_START_CNTL_R block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x00000014 + +// reg: VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_START_BASE_CNTL_B block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_START_BASE_CNTL_G block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_START_BASE_CNTL_R block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_END_CNTL1_B block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_END_CNTL1_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_END_CNTL2_B block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x00000010 + +// reg: VPMPCC_OGAM_RAMA_END_CNTL1_G block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_END_CNTL1_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_END_CNTL2_G block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x00000010 + +// reg: VPMPCC_OGAM_RAMA_END_CNTL1_R block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_END_CNTL1_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_END_CNTL2_R block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x00000010 + +// reg: VPMPCC_OGAM_RAMA_OFFSET_B block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_OFFSET_B__VPMPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_OFFSET_G block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_OFFSET_G__VPMPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_OFFSET_R block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_OFFSET_R__VPMPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_REGION_0_1 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_2_3 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_4_5 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_6_7 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_8_9 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_10_11 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_12_13 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_14_15 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_16_17 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_18_19 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_20_21 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_22_23 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_24_25 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_26_27 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_28_29 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_30_31 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_32_33 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_GAMUT_REMAP_COEF_FORMAT block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_GAMUT_REMAP_COEF_FORMAT__VPMPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x00000000 + +// reg: VPMPCC_GAMUT_REMAP_MODE block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE__SHIFT 0x00000000 +#define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x00000007 + +// reg: VPMPC_GAMUT_REMAP_C11_C12_A block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C11_A__SHIFT 0x00000000 +#define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C12_A__SHIFT 0x00000010 + +// reg: VPMPC_GAMUT_REMAP_C13_C14_A block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C13_A__SHIFT 0x00000000 +#define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C14_A__SHIFT 0x00000010 + +// reg: VPMPC_GAMUT_REMAP_C21_C22_A block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C21_A__SHIFT 0x00000000 +#define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C22_A__SHIFT 0x00000010 + +// reg: VPMPC_GAMUT_REMAP_C23_C24_A block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C23_A__SHIFT 0x00000000 +#define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C24_A__SHIFT 0x00000010 + +// reg: VPMPC_GAMUT_REMAP_C31_C32_A block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C31_A__SHIFT 0x00000000 +#define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C32_A__SHIFT 0x00000010 + +// reg: VPMPC_GAMUT_REMAP_C33_C34_A block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C33_A__SHIFT 0x00000000 +#define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C34_A__SHIFT 0x00000010 + +// reg: VPMPCC_OGAM_TEST_DEBUG_INDEX block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_TEST_DEBUG_INDEX__VPMPCC_OGAM_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define VPMPCC_OGAM_TEST_DEBUG_INDEX__VPMPCC_OGAM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 + +// reg: VPMPCC_OGAM_TEST_DEBUG_DATA block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_OGAM_TEST_DEBUG_DATA__VPMPCC_OGAM_TEST_DEBUG_DATA__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_CONTROL block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_PWL_DISABLE__SHIFT 0x00000003 +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE_CURRENT__SHIFT 0x00000004 +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT 0x00000006 + +// reg: VPMPCC_MCM_1DLUT_LUT_INDEX block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_LUT_INDEX__VPMPCC_MCM_1DLUT_LUT_INDEX__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_LUT_DATA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_LUT_DATA__VPMPCC_MCM_1DLUT_LUT_DATA__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_LUT_CONTROL block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT 0x00000003 +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT 0x00000005 +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT 0x00000006 +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT 0x00000007 + +// reg: VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x00000014 + +// reg: VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x00000014 + +// reg: VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x00000014 + +// reg: VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x00000010 + +// reg: VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x00000010 + +// reg: VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x00000010 + +// reg: VPMPCC_MCM_1DLUT_RAMA_OFFSET_B block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_B__VPMPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_OFFSET_G block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_G__VPMPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_OFFSET_R block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_R__VPMPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_0_1 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_2_3 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_4_5 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_6_7 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_8_9 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_10_11 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_12_13 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_14_15 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_16_17 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_18_19 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_20_21 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_22_23 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_24_25 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_26_27 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_28_29 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_30_31 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_32_33 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE__VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE__SHIFT 0x00000000 +#define VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE__VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x00000007 + +// reg: VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C11_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C12_SETA__SHIFT 0x00000010 + +// reg: VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C13_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C14_SETA__SHIFT 0x00000010 + +// reg: VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C21_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C22_SETA__SHIFT 0x00000010 + +// reg: VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C23_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C24_SETA__SHIFT 0x00000010 + +// reg: VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C31_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C32_SETA__SHIFT 0x00000010 + +// reg: VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C33_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C34_SETA__SHIFT 0x00000010 + +// reg: VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE__VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE__SHIFT 0x00000000 +#define VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE__VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x00000007 + +// reg: VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C11_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C12_SETA__SHIFT 0x00000010 + +// reg: VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C13_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C14_SETA__SHIFT 0x00000010 + +// reg: VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C21_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C22_SETA__SHIFT 0x00000010 + +// reg: VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C23_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C24_SETA__SHIFT 0x00000010 + +// reg: VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C31_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C32_SETA__SHIFT 0x00000010 + +// reg: VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C33_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C34_SETA__SHIFT 0x00000010 + +// reg: VPMPCC_MCM_MEM_PWR_CTRL block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT 0x00000010 +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT 0x00000012 +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT 0x00000014 +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_TEST_DEBUG_INDEX block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_TEST_DEBUG_INDEX__VPMPCC_MCM_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define VPMPCC_MCM_TEST_DEBUG_INDEX__VPMPCC_MCM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 + +// reg: VPMPCC_MCM_TEST_DEBUG_DATA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPCC_MCM_TEST_DEBUG_DATA__VPMPCC_MCM_TEST_DEBUG_DATA__SHIFT 0x00000000 + +// reg: VPMPC_RMCM_SHAPER_CONTROL block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_CONTROL__VPMPC_RMCM_SHAPER_LUT_MODE__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_CONTROL__VPMPC_RMCM_SHAPER_MODE_CURRENT__SHIFT 0x00000002 +#define VPMPC_RMCM_SHAPER_CONTROL__VPMPC_RMCM_SHAPER_SELECT_CURRENT__SHIFT 0x00000004 + +// reg: VPMPC_RMCM_SHAPER_OFFSET_R block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_OFFSET_R__VPMPC_RMCM_SHAPER_OFFSET_R__SHIFT 0x00000000 + +// reg: VPMPC_RMCM_SHAPER_OFFSET_G block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_OFFSET_G__VPMPC_RMCM_SHAPER_OFFSET_G__SHIFT 0x00000000 + +// reg: VPMPC_RMCM_SHAPER_OFFSET_B block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_OFFSET_B__VPMPC_RMCM_SHAPER_OFFSET_B__SHIFT 0x00000000 + +// reg: VPMPC_RMCM_SHAPER_SCALE_R block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_SCALE_R__VPMPC_RMCM_SHAPER_SCALE_R__SHIFT 0x00000000 + +// reg: VPMPC_RMCM_SHAPER_SCALE_G_B block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_SCALE_G_B__VPMPC_RMCM_SHAPER_SCALE_G__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_SCALE_G_B__VPMPC_RMCM_SHAPER_SCALE_B__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_SHAPER_LUT_INDEX block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_LUT_INDEX__VPMPC_RMCM_SHAPER_LUT_INDEX__SHIFT 0x00000000 + +// reg: VPMPC_RMCM_SHAPER_LUT_DATA block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_LUT_DATA__VPMPC_RMCM_SHAPER_LUT_DATA__SHIFT 0x00000000 + +// reg: VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__VPMPC_RMCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x00000004 + +// reg: VPMPC_RMCM_SHAPER_RAMA_START_CNTL_B block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x00000014 + +// reg: VPMPC_RMCM_SHAPER_RAMA_START_CNTL_G block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x00000014 + +// reg: VPMPC_RMCM_SHAPER_RAMA_START_CNTL_R block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x00000014 + +// reg: VPMPC_RMCM_SHAPER_RAMA_END_CNTL_B block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_SHAPER_RAMA_END_CNTL_G block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_SHAPER_RAMA_END_CNTL_R block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_0_1 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_2_3 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_4_5 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_6_7 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_8_9 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_10_11 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_12_13 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_14_15 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_16_17 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_18_19 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_20_21 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_22_23 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_24_25 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_26_27 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_28_29 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_30_31 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_32_33 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_3DLUT_MODE block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_MODE__SHIFT 0x00000000 +#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_SIZE__SHIFT 0x00000004 +#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_MODE_CURRENT__SHIFT 0x00000008 +#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_SELECT_CURRENT__SHIFT 0x0000000a + +// reg: VPMPC_RMCM_3DLUT_INDEX block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_3DLUT_INDEX__VPMPC_RMCM_3DLUT_INDEX__SHIFT 0x00000000 + +// reg: VPMPC_RMCM_3DLUT_DATA block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_3DLUT_DATA__VPMPC_RMCM_3DLUT_DATA0__SHIFT 0x00000000 +#define VPMPC_RMCM_3DLUT_DATA__VPMPC_RMCM_3DLUT_DATA1__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_3DLUT_DATA_30BIT block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_3DLUT_DATA_30BIT__VPMPC_RMCM_3DLUT_DATA_30BIT__SHIFT 0x00000002 + +// reg: VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_WRITE_EN_MASK__SHIFT 0x00000000 +#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_RAM_SEL__SHIFT 0x00000004 +#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_30BIT_EN__SHIFT 0x00000008 +#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_READ_SEL__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_3DLUT_OUT_NORM_FACTOR block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_3DLUT_OUT_NORM_FACTOR__VPMPC_RMCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x00000000 + +// reg: VPMPC_RMCM_3DLUT_OUT_OFFSET_R block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_R__VPMPC_RMCM_3DLUT_OUT_OFFSET_R__SHIFT 0x00000000 +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_R__VPMPC_RMCM_3DLUT_OUT_SCALE_R__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_3DLUT_OUT_OFFSET_G block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_G__VPMPC_RMCM_3DLUT_OUT_OFFSET_G__SHIFT 0x00000000 +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_G__VPMPC_RMCM_3DLUT_OUT_SCALE_G__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_3DLUT_OUT_OFFSET_B block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_B__VPMPC_RMCM_3DLUT_OUT_OFFSET_B__SHIFT 0x00000000 +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_B__VPMPC_RMCM_3DLUT_OUT_SCALE_B__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT__VPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x00000000 + +// reg: VPMPC_RMCM_GAMUT_REMAP_MODE block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_GAMUT_REMAP_MODE__VPMPC_RMCM_GAMUT_REMAP_MODE__SHIFT 0x00000000 +#define VPMPC_RMCM_GAMUT_REMAP_MODE__VPMPC_RMCM_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x00000007 + +// reg: VPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA__VPMPC_RMCM_GAMUT_REMAP_C11_SETA__SHIFT 0x00000000 +#define VPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA__VPMPC_RMCM_GAMUT_REMAP_C12_SETA__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA__VPMPC_RMCM_GAMUT_REMAP_C13_SETA__SHIFT 0x00000000 +#define VPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA__VPMPC_RMCM_GAMUT_REMAP_C14_SETA__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA__VPMPC_RMCM_GAMUT_REMAP_C21_SETA__SHIFT 0x00000000 +#define VPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA__VPMPC_RMCM_GAMUT_REMAP_C22_SETA__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA__VPMPC_RMCM_GAMUT_REMAP_C23_SETA__SHIFT 0x00000000 +#define VPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA__VPMPC_RMCM_GAMUT_REMAP_C24_SETA__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA__VPMPC_RMCM_GAMUT_REMAP_C31_SETA__SHIFT 0x00000000 +#define VPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA__VPMPC_RMCM_GAMUT_REMAP_C32_SETA__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA__VPMPC_RMCM_GAMUT_REMAP_C33_SETA__SHIFT 0x00000000 +#define VPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA__VPMPC_RMCM_GAMUT_REMAP_C34_SETA__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_MEM_PWR_CTRL block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x00000000 +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_PWR_DIS__SHIFT 0x00000002 +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x00000004 +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x00000008 +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_PWR_DIS__SHIFT 0x0000000a +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0x0000000c +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_PWR_STATE__SHIFT 0x00000018 +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_PWR_STATE__SHIFT 0x0000001a + +// reg: VPMPC_RMCM_3DLUT_FAST_LOAD_SELECT block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_3DLUT_FAST_LOAD_SELECT__VPMPC_RMCM_3DLUT_FL_SEL__SHIFT 0x00000000 + +// reg: VPMPC_RMCM_3DLUT_FAST_LOAD_STATUS block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_3DLUT_FAST_LOAD_STATUS__VPMPC_RMCM_3DLUT_FL_DONE__SHIFT 0x00000000 + +// reg: VPMPC_RMCM_CNTL block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_CNTL__VPMPC_RMCM_CNTL__SHIFT 0x00000000 + +// reg: VPMPC_RMCM_TEST_DEBUG_INDEX block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_TEST_DEBUG_INDEX__VPMPC_RMCM_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define VPMPC_RMCM_TEST_DEBUG_INDEX__VPMPC_RMCM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 + +// reg: VPMPC_RMCM_TEST_DEBUG_DATA block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2sw/1.0 +#define VPMPC_RMCM_TEST_DEBUG_DATA__VPMPC_RMCM_TEST_DEBUG_DATA__SHIFT 0x00000000 + +// reg: VPFMT_CLAMP_COMPONENT_R block: VPFMT comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_LOWER_R__SHIFT 0x00000000 +#define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_UPPER_R__SHIFT 0x00000010 + +// reg: VPFMT_CLAMP_COMPONENT_G block: VPFMT comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_LOWER_G__SHIFT 0x00000000 +#define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_UPPER_G__SHIFT 0x00000010 + +// reg: VPFMT_CLAMP_COMPONENT_B block: VPFMT comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_LOWER_B__SHIFT 0x00000000 +#define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_UPPER_B__SHIFT 0x00000010 + +// reg: VPFMT_DYNAMIC_EXP_CNTL block: VPFMT comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_EN__SHIFT 0x00000000 +#define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_MODE__SHIFT 0x00000004 + +// reg: VPFMT_CONTROL block: VPFMT comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPFMT_CONTROL__VPFMT_PIXEL_ENCODING__SHIFT 0x00000000 +#define VPFMT_CONTROL__VPFMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x00000004 +#define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x00000008 +#define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0x0000000c +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_HTAPS__SHIFT 0x00000010 +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_LEFT_EDGE__SHIFT 0x00000012 +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_RIGHT_EDGE__SHIFT 0x00000013 +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_VTAPS__SHIFT 0x00000014 +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_TOP_EDGE__SHIFT 0x00000016 +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_BOTTOM_EDGE__SHIFT 0x00000017 +#define VPFMT_CONTROL__VPFMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x00000018 + +// reg: VPFMT_BIT_DEPTH_CONTROL block: VPFMT comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_EN__SHIFT 0x00000000 +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_MODE__SHIFT 0x00000001 +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_DEPTH__SHIFT 0x00000004 +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_EN__SHIFT 0x00000008 +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_MODE__SHIFT 0x00000009 +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_DEPTH__SHIFT 0x0000000b +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_FRAME_RANDOM_ENABLE__SHIFT 0x0000000d +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_RGB_RANDOM_ENABLE__SHIFT 0x0000000e +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0x0000000f + +// reg: VPFMT_DITHER_RAND_R_SEED block: VPFMT comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPFMT_DITHER_RAND_R_SEED__VPFMT_RAND_R_SEED__SHIFT 0x00000000 +#define VPFMT_DITHER_RAND_R_SEED__VPFMT_OFFSET_R_CR__SHIFT 0x00000010 + +// reg: VPFMT_DITHER_RAND_G_SEED block: VPFMT comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPFMT_DITHER_RAND_G_SEED__VPFMT_RAND_G_SEED__SHIFT 0x00000000 +#define VPFMT_DITHER_RAND_G_SEED__VPFMT_OFFSET_G_Y__SHIFT 0x00000010 + +// reg: VPFMT_DITHER_RAND_B_SEED block: VPFMT comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPFMT_DITHER_RAND_B_SEED__VPFMT_RAND_B_SEED__SHIFT 0x00000000 +#define VPFMT_DITHER_RAND_B_SEED__VPFMT_OFFSET_B_CB__SHIFT 0x00000010 + +// reg: VPFMT_CLAMP_CNTL block: VPFMT comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_DATA_EN__SHIFT 0x00000000 +#define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_COLOR_FORMAT__SHIFT 0x00000010 + +// reg: VPFMT_SUBSAMPLER_MEMORY_CONTROL block: VPFMT comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_SUBSAMPLER_MEM_PWR_FORCE__SHIFT 0x00000000 +#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_SUBSAMPLER_MEM_PWR_DIS__SHIFT 0x00000004 +#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_SUBSAMPLER_MEM_PWR_STATE__SHIFT 0x00000008 +#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0000000c + +// reg: VPFMT_DEBUG_CNTL block: VPFMT comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPFMT_DEBUG_CNTL__VPFMT_DEBUG_COLOR_SELECT__SHIFT 0x00000000 + +// reg: VPFMT_TEST_DEBUG_INDEX block: VPFMT comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPFMT_TEST_DEBUG_INDEX__VPFMT_TEST_DEBUG_INDEX__SHIFT 0x00000000 +#define VPFMT_TEST_DEBUG_INDEX__VPFMT_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 + +// reg: VPFMT_TEST_DEBUG_DATA block: VPFMT comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPFMT_TEST_DEBUG_DATA__VPFMT_TEST_DEBUG_DATA__SHIFT 0x00000000 + +// reg: VPOPP_PIPE_CONTROL block: VPOPP_PIPE comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_CLOCK_ON__SHIFT 0x00000001 +#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x00000004 +#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_ALPHA_SEL__SHIFT 0x00000005 +#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_ALPHA__SHIFT 0x00000010 + +// reg: VPOPP_PIPE_OUTBG_EXT1 block: VPOPP_PIPE comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPOPP_PIPE_OUTBG_EXT1__OUTBG_EXT_TOP__SHIFT 0x00000000 +#define VPOPP_PIPE_OUTBG_EXT1__OUTBG_EXT_BOT__SHIFT 0x0000000e + +// reg: VPOPP_PIPE_OUTBG_EXT2 block: VPOPP_PIPE comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPOPP_PIPE_OUTBG_EXT2__OUTBG_EXT_LEFT__SHIFT 0x00000000 +#define VPOPP_PIPE_OUTBG_EXT2__OUTBG_EXT_RIGHT__SHIFT 0x0000000b + +// reg: VPOPP_PIPE_OUTBG_COL1 block: VPOPP_PIPE comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPOPP_PIPE_OUTBG_COL1__OUTBG_R_CR__SHIFT 0x00000000 +#define VPOPP_PIPE_OUTBG_COL1__OUTBG_B_CB__SHIFT 0x00000010 + +// reg: VPOPP_PIPE_OUTBG_COL2 block: VPOPP_PIPE comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPOPP_PIPE_OUTBG_COL2__OUTBG_Y__SHIFT 0x00000000 + +// reg: VPOPP_PIPE_SPARE_DEBUG block: VPOPP_PIPE comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPOPP_PIPE_SPARE_DEBUG__VPOPP_PIPE_SPARE_DEBUG__SHIFT 0x00000000 + +// reg: VPOPP_PIPE_TEST_DEBUG_INDEX block: VPOPP_PIPE comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPOPP_PIPE_TEST_DEBUG_INDEX__VPOPP_PIPE_TEST_DEBUG_INDEX__SHIFT 0x00000000 + +// reg: VPOPP_PIPE_TEST_DEBUG_DATA block: VPOPP_PIPE comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPOPP_PIPE_TEST_DEBUG_DATA__VPOPP_PIPE_TEST_DEBUG_DATA__SHIFT 0x00000000 + +// reg: VPOPP_TOP_CLK_CONTROL block: VPOPP_TOP comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_R_GATE_DIS__SHIFT 0x00000000 +#define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_G_GATE_DIS__SHIFT 0x00000001 + +// reg: VPOPP_DEBUG_CONTROL block: VPOPP_TOP comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPOPP_DEBUG_CONTROL__VPOPP_DBG_EN__SHIFT 0x00000000 +#define VPOPP_DEBUG_CONTROL__VPOPP_VPFMT_DEBUG_BUS_SELECT__SHIFT 0x00000004 +#define VPOPP_DEBUG_CONTROL__VPOPP_VPOPP_PIPE_DEBUG_BUS_SELECT__SHIFT 0x00000010 + +// reg: VPOPP_CRC_CONTROL block: VPOPP_TOP comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPOPP_CRC_CONTROL__VPOPP_CRC_EN__SHIFT 0x00000000 +#define VPOPP_CRC_CONTROL__VPOPP_CRC_CONT_EN__SHIFT 0x00000001 +#define VPOPP_CRC_CONTROL__VPOPP_CRC_PIXEL_SELECT__SHIFT 0x00000002 +#define VPOPP_CRC_CONTROL__VPOPP_CRC_SOURCE_SELECT__SHIFT 0x00000004 +#define VPOPP_CRC_CONTROL__VPOPP_CRC_PIPE_SELECT__SHIFT 0x00000006 +#define VPOPP_CRC_CONTROL__VPOPP_CRC_MASK__SHIFT 0x00000008 +#define VPOPP_CRC_CONTROL__VPOPP_CRC_ONE_SHOT_PENDING__SHIFT 0x0000001f + +// reg: VPOPP_CRC_RESULT_RG block: VPOPP_TOP comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPOPP_CRC_RESULT_RG__VPOPP_CRC_RESULT_R__SHIFT 0x00000000 +#define VPOPP_CRC_RESULT_RG__VPOPP_CRC_RESULT_G__SHIFT 0x00000010 + +// reg: VPOPP_CRC_RESULT_BC block: VPOPP_TOP comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPOPP_CRC_RESULT_BC__VPOPP_CRC_RESULT_B__SHIFT 0x00000000 +#define VPOPP_CRC_RESULT_BC__VPOPP_CRC_RESULT_C__SHIFT 0x00000010 + +// reg: VPOPP_FROD_CONTROL block: VPOPP_TOP comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPOPP_FROD_CONTROL__FROD_EN__SHIFT 0x00000000 + +// reg: VPOPP_FROD_MEM_PWR_CONTROL block: VPOPP_TOP comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_PWR_FORCE__SHIFT 0x00000000 +#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_PWR_DIS__SHIFT 0x00000004 +#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_PWR_STATE__SHIFT 0x00000008 +#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_DEFAULT_LOW_PWR_STATE__SHIFT 0x0000000c + +// reg: VPOPP_TOP_SPARE_DEBUG block: VPOPP_TOP comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPOPP_TOP_SPARE_DEBUG__VPOPP_TOP_SPARE_DEBUG__SHIFT 0x00000000 + +// reg: VPOPP_TOP_TEST_DEBUG_INDEX block: VPOPP_TOP comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPOPP_TOP_TEST_DEBUG_INDEX__VPOPP_TOP_TEST_DEBUG_INDEX__SHIFT 0x00000000 + +// reg: VPOPP_TOP_TEST_DEBUG_DATA block: VPOPP_TOP comp: amd.com/lib/vpopp-vpep2sw/1.0 +#define VPOPP_TOP_TEST_DEBUG_DATA__VPOPP_TOP_TEST_DEBUG_DATA__SHIFT 0x00000000 + + +#endif diff --git a/src/amd/vpelib/src/chip/vpe20/inc/vpe20_cdc_be.h b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_cdc_be.h new file mode 100644 index 00000000000..f08a3ef51a0 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_cdc_be.h @@ -0,0 +1,116 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#pragma once + +#include "cdc.h" +#include "reg_helper.h" +#include "vpe10_cdc_be.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define VPE20_CDC_VUPDATE_OFFSET_DEFAULT (20) +#define VPE20_CDC_VUPDATE_WIDTH_DEFAULT (60) +#define VPE20_CDC_VREADY_OFFSET_DEFAULT (150) + +/* Some HW registers have been renamed, and even though there are only few exceptions, all have + * to be copied and set individually. The order is the same as in VPE10 so it's easy to compare, + * but the only thing that matters is that they both have the same set of vars/registers. + */ +#define CDC_BE_REG_LIST_VPE20(id) \ + SRIDFVL_CDC(P2B_CONFIG, VPCDC_BE, id), \ + SRIDFVL_CDC(GLOBAL_SYNC_CONFIG, VPCDC_BE, id), \ + SRIDFVL1(VPCDC_CONTROL) + +#define CDC_BE_FIELD_LIST_VPE20(post_fix) \ + SFRB(VPCDC_BE0_P2B_XBAR_SEL0, VPCDC_BE0_P2B_CONFIG, post_fix), \ + SFRB(VPCDC_BE0_P2B_XBAR_SEL1, VPCDC_BE0_P2B_CONFIG, post_fix), \ + SFRB(VPCDC_BE0_P2B_XBAR_SEL2, VPCDC_BE0_P2B_CONFIG, post_fix), \ + SFRB(VPCDC_BE0_P2B_XBAR_SEL3, VPCDC_BE0_P2B_CONFIG, post_fix), \ + SFRB(VPCDC_BE0_P2B_FORMAT_SEL, VPCDC_BE0_P2B_CONFIG, post_fix), \ + SFRB(VPCDC_BE0_P2B_TILED, VPCDC_BE0_P2B_CONFIG, post_fix), \ + SFRB(VPCDC_BE0_P2B_X_START_PLANE0, VPCDC_BE0_P2B_CONFIG, post_fix), \ + SFRB(VPCDC_BE0_P2B_X_START_PLANE1, VPCDC_BE0_P2B_CONFIG, post_fix), \ + SFRB(BE0_VUPDATE_OFFSET, VPCDC_BE0_GLOBAL_SYNC_CONFIG, post_fix), \ + SFRB(BE0_VUPDATE_WIDTH, VPCDC_BE0_GLOBAL_SYNC_CONFIG, post_fix), \ + SFRB(BE0_VREADY_OFFSET, VPCDC_BE0_GLOBAL_SYNC_CONFIG, post_fix), \ + SFRB(VPCDC_FROD_EN, VPCDC_CONTROL, post_fix), \ + SFRB(VPCDC_HISTOGRAM0_EN, VPCDC_CONTROL, post_fix), \ + SFRB(VPCDC_HISTOGRAM1_EN, VPCDC_CONTROL, post_fix) + + +#define CDC_BE_REG_VARIABLE_LIST_VPE20 \ + CDC_BE_REG_VARIABLE_LIST_VPE10 \ + reg_id_val VPCDC_CONTROL; + + +#define CDC_BE_FIELD_VARIABLE_LIST_VPE20(type) \ + CDC_BE_FIELD_VARIABLE_LIST_VPE10(type) \ + type VPCDC_BE0_P2B_TILED; \ + type VPCDC_BE0_P2B_X_START_PLANE0; \ + type VPCDC_BE0_P2B_X_START_PLANE1; \ + type VPCDC_FROD_EN; \ + type VPCDC_HISTOGRAM0_EN; \ + type VPCDC_HISTOGRAM1_EN; + + +/* Variable list is the same as the one for VPE10 at the moment as it's the same set of registers. + * Note that adding VPE2 specific variables must be done at the bottom so that casting can work. + * See PROGRAM_ENTRY(),the order here matters, VPE1 subset must be in the same order in VPE2 list. + */ +struct vpe20_cdc_be_registers { + CDC_BE_REG_VARIABLE_LIST_VPE20 +}; + +struct vpe20_cdc_be_shift { + CDC_BE_FIELD_VARIABLE_LIST_VPE20(uint8_t) +}; + +struct vpe20_cdc_be_mask { + CDC_BE_FIELD_VARIABLE_LIST_VPE20(uint32_t) +}; + +struct vpe20_cdc_be { + struct cdc_be base; // base class, must be the first field + struct vpe20_cdc_be_registers *regs; + const struct vpe20_cdc_be_shift *shift; + const struct vpe20_cdc_be_mask *mask; +}; + +void vpe20_construct_cdc_be(struct vpe_priv *vpe_priv, struct cdc_be *cdc_be); + +void vpe20_cdc_program_global_sync( + struct cdc_be *cdc_be, uint32_t vupdate_offset, uint32_t vupdate_width, uint32_t vready_offset); + +void vpe20_cdc_program_p2b_config(struct cdc_be *cdc_be, enum vpe_surface_pixel_format format, + enum vpe_swizzle_mode_values swizzle, const struct vpe_rect *viewport, + const struct vpe_rect *viewport_c); + +void vpe20_cdc_program_control(struct cdc_be *cdc_be, uint8_t enable_frod, uint32_t hist_dsets[]); + +void vpe20_cdc_program_histo(struct cdc_be *cdc_be); +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe20/inc/vpe20_cdc_fe.h b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_cdc_fe.h new file mode 100644 index 00000000000..c5497e507f1 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_cdc_fe.h @@ -0,0 +1,150 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#pragma once + +#include "cdc.h" +#include "reg_helper.h" +#include "vpe10_cdc_fe.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Some HW registers have been renamed, and even though there are only few exceptions, all have + * to be copied and set individually. The order is the same as in VPE10 so it's easy to compare, + * but the only thing that matters is that they both have the same set of vars/registers. + */ +#define CDC_FE_REG_LIST_VPE20(id) \ + SRIDFVL1(VPEP_MGCG_CNTL), SRIDFVL1(VPCDC_SOFT_RESET), \ + SRIDFVL_CDC(SURFACE_CONFIG, VPCDC_FE, id), SRIDFVL_CDC(CROSSBAR_CONFIG, VPCDC_FE, id), \ + SRIDFVL_CDC(VIEWPORT_START_CONFIG, VPCDC_FE, id), \ + SRIDFVL_CDC(VIEWPORT_DIMENSION_CONFIG, VPCDC_FE, id), \ + SRIDFVL_CDC(VIEWPORT_START_C_CONFIG, VPCDC_FE, id), \ + SRIDFVL_CDC(VIEWPORT_DIMENSION_C_CONFIG, VPCDC_FE, id), \ + SRIDFVL1(VPCDC_GLOBAL_SYNC_TRIGGER), SRIDFVL1(VPEP_MEM_GLOBAL_PWR_REQ_CNTL), \ + SRIDFVL2(MEM_PWR_CNTL, VPFE, id), SRIDFVL2(MEM_PWR_CNTL, VPBE, id), \ + SRIDFVL1(VPCDC_3DLUT_FL_CONFIG) + +#define CDC_FE_FIELD_LIST_VPE20_COMMON(post_fix) \ + SFRB(VPDPP0_CLK_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \ + SFRB(VPMPC_CLK_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \ + SFRB(VPOPP_CLK_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \ + SFRB(VPCDC_SOCCLK_G_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \ + SFRB(VPCDC_SOCCLK_R_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \ + SFRB(VPCDC_VPECLK_G_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \ + SFRB(VPCDC_VPECLK_R_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \ + SFRB(VPCDC_SOCCLK_SOFT_RESET, VPCDC_SOFT_RESET, post_fix), \ + SFRB(VPCDC_VPECLK_SOFT_RESET, VPCDC_SOFT_RESET, post_fix), \ + SFRB(SURFACE_PIXEL_FORMAT_FE0, VPCDC_FE0_SURFACE_CONFIG, post_fix), \ + SFRB(ROTATION_ANGLE_FE0, VPCDC_FE0_SURFACE_CONFIG, post_fix), \ + SFRB(H_MIRROR_EN_FE0, VPCDC_FE0_SURFACE_CONFIG, post_fix), \ + SFRB(PIX_SURFACE_LINEAR_FE0, VPCDC_FE0_SURFACE_CONFIG, post_fix), \ + SFRB(CROSSBAR_SRC_ALPHA_FE0, VPCDC_FE0_CROSSBAR_CONFIG, post_fix), \ + SFRB(CROSSBAR_SRC_Y_G_FE0, VPCDC_FE0_CROSSBAR_CONFIG, post_fix), \ + SFRB(CROSSBAR_SRC_CB_B_FE0, VPCDC_FE0_CROSSBAR_CONFIG, post_fix), \ + SFRB(CROSSBAR_SRC_CR_R_FE0, VPCDC_FE0_CROSSBAR_CONFIG, post_fix), \ + SFRB(VIEWPORT_X_START_FE0, VPCDC_FE0_VIEWPORT_START_CONFIG, post_fix), \ + SFRB(VIEWPORT_Y_START_FE0, VPCDC_FE0_VIEWPORT_START_CONFIG, post_fix), \ + SFRB(VIEWPORT_WIDTH_FE0, VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG, post_fix), \ + SFRB(VIEWPORT_HEIGHT_FE0, VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG, post_fix), \ + SFRB(VIEWPORT_X_START_C_FE0, VPCDC_FE0_VIEWPORT_START_C_CONFIG, post_fix), \ + SFRB(VIEWPORT_Y_START_C_FE0, VPCDC_FE0_VIEWPORT_START_C_CONFIG, post_fix), \ + SFRB(VIEWPORT_WIDTH_C_FE0, VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG, post_fix), \ + SFRB(VIEWPORT_HEIGHT_C_FE0, VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG, post_fix), \ + SFRB(VPBE_GS_TRIG, VPCDC_GLOBAL_SYNC_TRIGGER, post_fix), \ + SFRB(VPFE_VR_STATUS, VPCDC_VREADY_STATUS, post_fix), \ + SFRB(MEM_GLOBAL_PWR_REQ_DIS, VPEP_MEM_GLOBAL_PWR_REQ_CNTL, post_fix), \ + SFRB(VPFE0_MEM_PWR_FORCE, VPFE0_MEM_PWR_CNTL, post_fix), \ + SFRB(VPFE0_MEM_PWR_MODE, VPFE0_MEM_PWR_CNTL, post_fix), \ + SFRB(VPFE0_MEM_PWR_STATE, VPFE0_MEM_PWR_CNTL, post_fix), \ + SFRB(VPFE0_MEM_PWR_DIS, VPFE0_MEM_PWR_CNTL, post_fix), \ + SFRB(VPBE0_MEM_PWR_FORCE, VPBE0_MEM_PWR_CNTL, post_fix), \ + SFRB(VPBE0_MEM_PWR_MODE, VPBE0_MEM_PWR_CNTL, post_fix), \ + SFRB(VPBE0_MEM_PWR_STATE, VPBE0_MEM_PWR_CNTL, post_fix), \ + SFRB(VPBE0_MEM_PWR_DIS, VPBE0_MEM_PWR_CNTL, post_fix), \ + SFRB(VPCDC_3DLUT_FL_CROSSBAR_SRC_G, VPCDC_3DLUT_FL_CONFIG, post_fix), \ + SFRB(VPCDC_3DLUT_FL_CROSSBAR_SRC_B, VPCDC_3DLUT_FL_CONFIG, post_fix), \ + SFRB(VPCDC_3DLUT_FL_CROSSBAR_SRC_R, VPCDC_3DLUT_FL_CONFIG, post_fix) + +#define CDC_FE_FIELD_LIST_VPE20(post_fix) \ + CDC_FE_FIELD_LIST_VPE20_COMMON(post_fix), \ + SFRB(VPCDC_3DLUT_FL_MODE, VPCDC_3DLUT_FL_CONFIG, post_fix), \ + SFRB(VPCDC_3DLUT_FL_SIZE, VPCDC_3DLUT_FL_CONFIG, post_fix) + +#define CDC_FE_REG_VARIABLE_LIST_VPE20_COMMON \ + CDC_FE_REG_VARIABLE_LIST_VPE10 \ + reg_id_val VPCDC_3DLUT_FL_CONFIG; + +#define CDC_FE_REG_VARIABLE_LIST_VPE20 CDC_FE_REG_VARIABLE_LIST_VPE20_COMMON + +#define CDC_FE_FIELD_VARIABLE_LIST_VPE20_COMMON(type) \ + CDC_FE_FIELD_VARIABLE_LIST_VPE10(type) \ + type VPCDC_3DLUT_FL_CROSSBAR_SRC_G; \ + type VPCDC_3DLUT_FL_CROSSBAR_SRC_B; \ + type VPCDC_3DLUT_FL_CROSSBAR_SRC_R; + +#define CDC_FE_FIELD_VARIABLE_LIST_VPE20(type) \ + CDC_FE_FIELD_VARIABLE_LIST_VPE20_COMMON(type) \ + type VPCDC_3DLUT_FL_MODE; \ + type VPCDC_3DLUT_FL_SIZE; + +/* Variable list is the same as the one for VPE10 at the moment as it's the same set of registers. + * Note that adding VPE2 specific variables must be done at the bottom so that casting can work. + * See PROGRAM_ENTRY(),the order here matters, VPE1 subset must be in the same order in VPE2 list. + */ +struct vpe20_cdc_fe_registers { + CDC_FE_REG_VARIABLE_LIST_VPE20 +}; + +struct vpe20_cdc_fe_shift { + CDC_FE_FIELD_VARIABLE_LIST_VPE20(uint8_t) +}; + +struct vpe20_cdc_fe_mask { + CDC_FE_FIELD_VARIABLE_LIST_VPE20(uint32_t) +}; + +struct vpe20_cdc_fe { + struct cdc_fe base; // base class, must be the first field + struct vpe20_cdc_fe_registers *regs; + const struct vpe20_cdc_fe_shift *shift; + const struct vpe20_cdc_fe_mask *mask; +}; + +void vpe20_construct_cdc_fe(struct vpe_priv *vpe_priv, struct cdc_fe *cdc_fe); + +void vpe20_cdc_program_surface_config(struct cdc_fe *cdc_fe, enum vpe_surface_pixel_format format, + enum vpe_rotation_angle rotation, bool horizontal_mirror, enum vpe_swizzle_mode_values swizzle); + +void vpe20_cdc_program_crossbar_config(struct cdc_fe *cdc_fe, enum vpe_surface_pixel_format format); + +void vpe20_cdc_program_viewport( + struct cdc_fe *cdc_fe, const struct vpe_rect *viewport, const struct vpe_rect *viewport_c); + +void vpe20_program_3dlut_fl_config( + struct cdc_fe *cdc_fe, enum lut_dimension lut_dimension, struct vpe_3dlut *lut_3d); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe20/inc/vpe20_cm_common.h b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_cm_common.h new file mode 100644 index 00000000000..70dff51014e --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_cm_common.h @@ -0,0 +1,38 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#pragma once + +#include "color.h" +#include "hw_shared.h" +#include "vpe10/inc/vpe10_cm_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void vpe20_dpp_program_input_transfer_func(struct dpp *dpp, struct transfer_func *input_tf); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe20/inc/vpe20_cmd_builder.h b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_cmd_builder.h new file mode 100644 index 00000000000..fa3cfc43fcd --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_cmd_builder.h @@ -0,0 +1,42 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#pragma once + +#include "cmd_builder.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void vpe20_construct_cmd_builder(struct vpe_priv *vpe_priv, struct cmd_builder *cmd_builder); + +enum vpe_status vpe20_build_plane_descriptor( + struct vpe_priv *vpe_priv, struct vpe_buf *buf, uint32_t cmd_idx); + +enum vpe_status vpe20_build_vpe_cmd( + struct vpe_priv *vpe_priv, struct vpe_build_bufs *cur_bufs, uint32_t cmd_idx); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe20/inc/vpe20_command.h b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_command.h new file mode 100644 index 00000000000..5c010ed4d60 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_command.h @@ -0,0 +1,189 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** Generic Command Header + * Generic Commands include: + * Noop, Fence, Trap, + * RegisterWrite, PollRegisterWriteMemory, + * SetLocalTimestamp, GetLocalTimestamp + * GetGlobalGPUTimestamp */ +#define VPE_HEADER_SUB_OPCODE__SHIFT 8 +#define VPE_HEADER_SUB_OPCODE_MASK 0x0000FF00 +#define VPE_HEADER_OPCODE__SHIFT 0 +#define VPE_HEADER_OPCODE_MASK 0x000000FF + +#define VPE_CMD_HEADER(op, subop) \ + (((subop << VPE_HEADER_SUB_OPCODE__SHIFT) & VPE_HEADER_SUB_OPCODE_MASK) | \ + ((op << VPE_HEADER_OPCODE__SHIFT) & VPE_HEADER_OPCODE_MASK)) + +/*************************** + * VPE Descriptor + ***************************/ +#define VPE_DESC_CD__SHIFT 16 +#define VPE_DESC_CD_MASK 0x00FF0000 + +#define VPE_DESC_ADDR__SHIFT 32 +#define VPE_DESC_HIGH_ADDR_MASK 0xFFFFFFFF00000000 +/* The lowest bits are reuse and tmz as bit 1 and bit 0. + Smibs will substract the address with emb gpuva to + get offset and then reuse bit will be preserved + So as long as the embedded buffer is allocated + at correct alignment (currently low addr is [31:2] + which means we need a 4 byte(2 bit) alignment), + the offset generated will still cover the + reuse bit as part of it. + Ex : Address : 0x200036 GPU Virtual Address : 0x200000 + offset is 0x36 which keeps the reuse bit */ +#define VPE_DESC_LOW_ADDR_MASK 0x00000000FFFFFFFF +#define VPE_DESC_REUSE_TMZ_MASK 0x000000000000003F + +#define VPE_DESC_NUM_CONFIG_DESCRIPTOR__SHIFT 0 +#define VPE_DESC_NUM_CONFIG_DESCRIPTOR_MASK 0x000000FF + +#define VPE_DESC_REUSE__MASK 0x00000010 + +#define VPE_DESC_CMD_HEADER(cd) \ + (VPE_CMD_HEADER(VPE_CMD_OPCODE_VPE_DESC, 0) | (((cd) << VPE_DESC_CD__SHIFT) & VPE_DESC_CD_MASK)) + +/*************************** + * VPE Plane Config + ***************************/ +enum VPE_PLANE_CFG_SUBOP { + VPE_PLANE_CFG_SUBOP_1_TO_1 = 0x0, + VPE_PLANE_CFG_SUBOP_2_TO_1 = 0x1, + VPE_PLANE_CFG_SUBOP_2_TO_2 = 0x2 +}; + +#define VPE_PLANE_ADDR_ALIGNMENT_MASK 0x3F + +#define VPE_PLANE_CFG_ONE_PLANE 0 +#define VPE_PLANE_CFG_TWO_PLANES 1 +#define VPE_PLANE_CFG_THREE_PLANES 2 + +#define VPE_PLANE_CFG_NPS0__SHIFT 16 +#define VPE_PLANE_CFG_NPS0_MASK 0x00030000 + +#define VPE_PLANE_CFG_NPD0__SHIFT 18 +#define VPE_PLANE_CFG_NPD0_MASK 0x000C0000 + +#define VPE_PLANE_CFG_NPS1__SHIFT 20 +#define VPE_PLANE_CFG_NPS1_MASK 0x00300000 + +#define VPE_PLANE_CFG_NPD1__SHIFT 22 +#define VPE_PLANE_CFG_NPD1_MASK 0x00C00000 + +#define VPE_PLANE_CFG_DCOMP0__SHIFT 24 +#define VPE_PLANE_CFG_DCOMP0_MASK 0x01000000 +#define VPE_PLANE_CFG_DCOMP1__SHIFT 25 +#define VPE_PLANE_CFG_DCOMP1_MASK 0x02000000 +#define VPE_PLANE_CFG_FROD__SHIFT 27 +#define VPE_PLANE_CFG_FROD_MASK 0x08000000 +#define VPE_PLANE_CFG_HIST0_DSETS__SHIFT 28 +#define VPE_PLANE_CFG_HIST0_DSETS_MASK 0x30000000 +#define VPE_PLANE_CFG_HIST1_DSETS__SHIFT 30 +#define VPE_PLANE_CFG_HIST1_DSETS_MASK 0xC0000000 +#define VPE_PLANE_CFG_SCAN_PATTERN__SHIFT 0 +#define VPE_PLANE_CFG_SCAN_PATTERN_MASK 0x00000007 +#define VPE_PLANE_CFG_SWIZZLE_MODE__SHIFT 3 +#define VPE_PLANE_CFG_SWIZZLE_MODE_MASK 0x000000F8 +#define VPE_PLANE_CFG_TMZ__SHIFT 16 +#define VPE_PLANE_CFG_TMZ_MASK 0x000F0000 +#define VPE_PLANE_CFG_SRC_COMP_MODE__SHIFT 0 +#define VPE_PLANE_CFG_SRC_COMP_MODE_MASK 0x00000001 +#define VPE_META_ADDR__SHIFT 32 +#define VPE_META_HIGH_ADDR_MASK 0xFFFFFFFF00000000 +#define VPE_META_LOW_ADDR_MASK 0x00000000FFFFFFFF +#define VPE_PLANE_CFG_META_TMZ__SHIFT 0 +#define VPE_PLANE_CFG_META_TMZ_MASK 0x0000000F +#define VPE_PLANE_CFG_META_PITCH__SHIFT 0 +#define VPE_PLANE_CFG_META_PITCH_MASK 0x00003FFF +#define VPE_PLANE_CFG_PIXEL_FORMAT__SHIFT 16 +#define VPE_PLANE_CFG_PIXEL_FORMAT_MASK 0x007F0000 +#define VPE_PLANE_CFG_INDEPENDENT_BLOCKS__SHIFT 23 +#define VPE_PLANE_CFG_INDEPENDENT_BLOCKS_MASK 0x01800000 +#define VPE_PLANE_CFG_PA__SHIFT 31 +#define VPE_PLANE_CFG_PA_MASK 0x80000000 +#define VPE_PLANE_CFG_DST_COMP_MODE__SHIFT 0 +#define VPE_PLANE_CFG_DST_COMP_MODE_MASK 0x00000003 +#define VPE_PLANE_CFG_UTILE_MODE__SHIFT 4 +#define VPE_PLANE_CFG_UTILE_MODE_MASK 0x00000030 +#define VPE_PLANE_CFG_DATA_FORMAT__SHIFT 8 +#define VPE_PLANE_CFG_DATA_FORMAT_MASK 0x00001F00 +#define VPE_PLANE_CFG_VID_NUM_ENABLE__SHIFT 16 +#define VPE_PLANE_CFG_VID_NUM_ENABLE_MASK 0x00010000 +#define VPE_PLANE_CFG_NUM_TYPE__SHIFT 20 +#define VPE_PLANE_CFG_NUM_TYPE_MASK 0x00700000 +#define VPE_PLANE_CFG_MAX_COMP_BLOCK_SIZE__SHIFT 24 +#define VPE_PLANE_CFG_MAX_COMP_BLOCK_SIZE_MASK 0x01000000 +#define VPE_PLANE_CFG_MAX_UNCOMP_BLOCK_SIZE__SHIFT 25 +#define VPE_PLANE_CFG_MAX_UNCOMP_BLOCK_SIZE_MASK 0x06000000 +#define VPE_PLANE_CFG_DSET_SIZE__SHIFT 0 +#define VPE_PLANE_CFG_DSET_SIZE_MASK 0x00000003 +#define VPE_PLANE_ADDR__SHIFT 32 +#define VPE_PLANE_HIGH_ADDR_MASK 0xFFFFFFFF00000000 +#define VPE_PLANE_LOW_ADDR_MASK 0x00000000FFFFFF00 +#define VPE_PLANE_CFG_PITCH__SHIFT 0 +#define VPE_PLANE_CFG_PITCH_MASK 0x0000FFFF +#define VPE_PLANE_CFG_VIEWPORT_Y__SHIFT 16 +#define VPE_PLANE_CFG_VIEWPORT_Y_MASK 0xFFFF0000 +#define VPE_PLANE_CFG_VIEWPORT_X__SHIFT 0 +#define VPE_PLANE_CFG_VIEWPORT_X_MASK 0x0000FFFF +#define VPE_PLANE_CFG_VIEWPORT_HEIGHT__SHIFT 16 +#define VPE_PLANE_CFG_VIEWPORT_HEIGHT_MASK 0x3FFF0000 +#define VPE_PLANE_CFG_VIEWPORT_WIDTH__SHIFT 0 +#define VPE_PLANE_CFG_VIEWPORT_WIDTH_MASK 0x00003FFF +#define VPE_PLANE_CFG_VIEWPORT_ELEMENT_SIZE__SHIFT 29 +#define VPE_PLANE_CFG_VIEWPORT_ELEMENT_SIZE_MASK 0xE0000000 +#define VPE_HIST_ADDR__SHIFT 32 +#define VPE_HIST_HIGH_ADDR_MASK 0xFFFFFFFF00000000 +#define VPE_HIST_LOW_ADDR_MASK 0x00000000FFFFFFFF + +enum VPE_PLANE_CFG_ELEMENT_SIZE { + VPE_PLANE_CFG_ELEMENT_SIZE_8BPE = 0, + VPE_PLANE_CFG_ELEMENT_SIZE_16BPE = 1, + VPE_PLANE_CFG_ELEMENT_SIZE_32BPE = 2, + VPE_PLANE_CFG_ELEMENT_SIZE_64BPE = 3 +}; + +#define VPE_PLANE_CFG_CMD_HEADER( \ + subop, nps0, npd0, nps1, npd1, dcomp0, dcomp1, frod, hist0_dsets, hist1_dsets) \ + (VPE_CMD_HEADER(VPE_CMD_OPCODE_PLANE_CFG, subop) | \ + (((nps0) << VPE_PLANE_CFG_NPS0__SHIFT) & VPE_PLANE_CFG_NPS0_MASK) | \ + (((npd0) << VPE_PLANE_CFG_NPD0__SHIFT) & VPE_PLANE_CFG_NPD0_MASK) | \ + (((nps1) << VPE_PLANE_CFG_NPS1__SHIFT) & VPE_PLANE_CFG_NPS1_MASK) | \ + (((npd1) << VPE_PLANE_CFG_NPD1__SHIFT) & VPE_PLANE_CFG_NPD1_MASK) | \ + (((dcomp0) << VPE_PLANE_CFG_DCOMP0__SHIFT) & VPE_PLANE_CFG_DCOMP0_MASK) | \ + (((dcomp1) << VPE_PLANE_CFG_DCOMP1__SHIFT) & VPE_PLANE_CFG_DCOMP1_MASK) | \ + (((frod) << VPE_PLANE_CFG_FROD__SHIFT) & VPE_PLANE_CFG_FROD_MASK) | \ + (((hist0_dsets) << VPE_PLANE_CFG_HIST0_DSETS__SHIFT) & VPE_PLANE_CFG_HIST0_DSETS_MASK) | \ + (((hist1_dsets) << VPE_PLANE_CFG_HIST1_DSETS__SHIFT) & VPE_PLANE_CFG_HIST1_DSETS_MASK)) + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe20/inc/vpe20_config_writer.h b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_config_writer.h new file mode 100644 index 00000000000..3ad243e4e20 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_config_writer.h @@ -0,0 +1,26 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include "config_writer.h" + +void vpe20_config_writer_init(struct config_writer *writer); diff --git a/src/amd/vpelib/src/chip/vpe20/inc/vpe20_dpp.h b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_dpp.h new file mode 100644 index 00000000000..f245f06835a --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_dpp.h @@ -0,0 +1,634 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#pragma once + +#include "dpp.h" +#include "vpe10_dpp.h" +#include "transform.h" +#include "reg_helper.h" +#include "vpe_types.h" +#include "color_table.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Used to resolve corner case +#define DPP_SFRB(field_name, reg_name, post_fix) .field_name = reg_name##_##field_name##post_fix + +#define DPP_REG_LIST_VPE20_COMMON(id) \ + DPP_REG_LIST_VPE10_COMMON(id), SRIDFVL(VPCNVC_ALPHA_2BIT_LUT01, VPCNVC_CFG, id), \ + SRIDFVL(VPCNVC_ALPHA_2BIT_LUT23, VPCNVC_CFG, id), SRIDFVL(VPDSCL_SC_MODE, VPDSCL, id), \ + SRIDFVL(VPDSCL_SC_MATRIX_C0C1, VPDSCL, id), SRIDFVL(VPDSCL_SC_MATRIX_C2C3, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_H_MODE, VPDSCL, id), SRIDFVL(VPDSCL_EASF_V_MODE, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_H_BF_CNTL, VPDSCL, id), SRIDFVL(VPDSCL_EASF_V_BF_CNTL, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_H_BF_FINAL_MAX_MIN, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_V_BF_FINAL_MAX_MIN, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_H_BF1_PWL_SEG0, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_H_BF1_PWL_SEG1, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_H_BF1_PWL_SEG2, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_H_BF1_PWL_SEG3, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_H_BF1_PWL_SEG4, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_H_BF1_PWL_SEG5, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_H_BF1_PWL_SEG6, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_H_BF1_PWL_SEG7, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_H_BF3_PWL_SEG0, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_H_BF3_PWL_SEG1, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_H_BF3_PWL_SEG2, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_H_BF3_PWL_SEG3, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_H_BF3_PWL_SEG4, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_H_BF3_PWL_SEG5, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_V_BF1_PWL_SEG0, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_V_BF1_PWL_SEG1, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_V_BF1_PWL_SEG2, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_V_BF1_PWL_SEG3, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_V_BF1_PWL_SEG4, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_V_BF1_PWL_SEG5, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_V_BF1_PWL_SEG6, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_V_BF1_PWL_SEG7, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_V_BF3_PWL_SEG0, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_V_BF3_PWL_SEG1, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_V_BF3_PWL_SEG2, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_V_BF3_PWL_SEG3, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_V_BF3_PWL_SEG4, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_V_BF3_PWL_SEG5, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_RINGEST_FORCE, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_V_RINGEST_3TAP_CNTL1, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_V_RINGEST_3TAP_CNTL2, VPDSCL, id), \ + SRIDFVL(VPDSCL_EASF_V_RINGEST_3TAP_CNTL3, VPDSCL, id), SRIDFVL(VPISHARP_MODE, VPDSCL, id), \ + SRIDFVL(VPISHARP_DELTA_CTRL, VPDSCL, id), SRIDFVL(VPISHARP_DELTA_INDEX, VPDSCL, id), \ + SRIDFVL(VPISHARP_DELTA_DATA, VPDSCL, id), SRIDFVL(VPISHARP_LBA_PWL_SEG0, VPDSCL, id), \ + SRIDFVL(VPISHARP_LBA_PWL_SEG1, VPDSCL, id), SRIDFVL(VPISHARP_LBA_PWL_SEG2, VPDSCL, id), \ + SRIDFVL(VPISHARP_LBA_PWL_SEG3, VPDSCL, id), SRIDFVL(VPISHARP_LBA_PWL_SEG4, VPDSCL, id), \ + SRIDFVL(VPISHARP_LBA_PWL_SEG5, VPDSCL, id), \ + SRIDFVL(VPISHARP_DELTA_LUT_MEM_PWR_CTRL, VPDSCL, id), \ + SRIDFVL(VPISHARP_NLDELTA_SOFT_CLIP, VPDSCL, id), \ + SRIDFVL(VPISHARP_NOISEDET_THRESHOLD, VPDSCL, id), \ + SRIDFVL(VPISHARP_NOISE_GAIN_PWL, VPDSCL, id), SRIDFVL(VPCM_HIST_CNTL, VPCM, id), \ + SRIDFVL(VPCM_HIST_SCALE_SRC1, VPCM, id), SRIDFVL(VPCM_HIST_SCALE_SRC3, VPCM, id), \ + SRIDFVL(VPCM_HIST_BIAS_SRC1, VPCM, id), SRIDFVL(VPCM_HIST_BIAS_SRC2, VPCM, id), \ + SRIDFVL(VPCM_HIST_BIAS_SRC3, VPCM, id), SRIDFVL(VPCM_HIST_COEFA_SRC2, VPCM, id), \ + SRIDFVL(VPCM_HIST_COEFB_SRC2, VPCM, id), SRIDFVL(VPCM_HIST_COEFC_SRC2, VPCM, id) + +#define DPP_REG_LIST_VPE20(id) \ + DPP_REG_LIST_VPE20_COMMON(id), SRIDFVL(VPDSCL_VERT_FILTER_INIT_BOT, VPDSCL, id), \ + SRIDFVL(VPDSCL_VERT_FILTER_INIT_BOT_C, VPDSCL, id), \ + SRIDFVL(VPCNVC_PRE_DEGAM, VPCNVC_CFG, id) + +#define DPP_FIELD_LIST_VPE20_COMMON(post_fix) \ + DPP_FIELD_LIST_VPE10_COMMON(post_fix), \ + SFRB(ALPHA_2BIT_LUT0, VPCNVC_ALPHA_2BIT_LUT01, post_fix), \ + SFRB(ALPHA_2BIT_LUT1, VPCNVC_ALPHA_2BIT_LUT01, post_fix), \ + SFRB(ALPHA_2BIT_LUT2, VPCNVC_ALPHA_2BIT_LUT23, post_fix), \ + SFRB(ALPHA_2BIT_LUT3, VPCNVC_ALPHA_2BIT_LUT23, post_fix), \ + SFRB(SCL_SC_MATRIX_MODE, VPDSCL_SC_MODE, post_fix), \ + SFRB(SCL_SC_MATRIX_C0, VPDSCL_SC_MATRIX_C0C1, post_fix), \ + SFRB(SCL_SC_MATRIX_C1, VPDSCL_SC_MATRIX_C0C1, post_fix), \ + SFRB(SCL_SC_MATRIX_C2, VPDSCL_SC_MATRIX_C2C3, post_fix), \ + SFRB(SCL_SC_MATRIX_C3, VPDSCL_SC_MATRIX_C2C3, post_fix), \ + SFRB(SCL_SC_LTONL_EN, VPDSCL_SC_MODE, post_fix), \ + SFRB(SCL_EASF_H_EN, VPDSCL_EASF_H_MODE, post_fix), \ + SFRB(SCL_EASF_H_RINGEST_FORCE_EN, VPDSCL_EASF_H_MODE, post_fix), \ + SFRB(SCL_EASF_H_2TAP_SHARP_FACTOR, VPDSCL_EASF_H_MODE, post_fix), \ + SFRB(SCL_EASF_V_EN, VPDSCL_EASF_V_MODE, post_fix), \ + SFRB(SCL_EASF_V_RINGEST_FORCE_EN, VPDSCL_EASF_V_MODE, post_fix), \ + SFRB(SCL_EASF_V_2TAP_SHARP_FACTOR, VPDSCL_EASF_V_MODE, post_fix), \ + SFRB(SCL_EASF_H_BF1_EN, VPDSCL_EASF_H_BF_CNTL, post_fix), \ + SFRB(SCL_EASF_H_BF2_MODE, VPDSCL_EASF_H_BF_CNTL, post_fix), \ + SFRB(SCL_EASF_H_BF3_MODE, VPDSCL_EASF_H_BF_CNTL, post_fix), \ + SFRB(SCL_EASF_H_BF2_FLAT1_GAIN, VPDSCL_EASF_H_BF_CNTL, post_fix), \ + SFRB(SCL_EASF_H_BF2_FLAT2_GAIN, VPDSCL_EASF_H_BF_CNTL, post_fix), \ + SFRB(SCL_EASF_H_BF2_ROC_GAIN, VPDSCL_EASF_H_BF_CNTL, post_fix), \ + SFRB(SCL_EASF_V_BF1_EN, VPDSCL_EASF_V_BF_CNTL, post_fix), \ + SFRB(SCL_EASF_V_BF2_MODE, VPDSCL_EASF_V_BF_CNTL, post_fix), \ + SFRB(SCL_EASF_V_BF3_MODE, VPDSCL_EASF_V_BF_CNTL, post_fix), \ + SFRB(SCL_EASF_V_BF2_FLAT1_GAIN, VPDSCL_EASF_V_BF_CNTL, post_fix), \ + SFRB(SCL_EASF_V_BF2_FLAT2_GAIN, VPDSCL_EASF_V_BF_CNTL, post_fix), \ + SFRB(SCL_EASF_V_BF2_ROC_GAIN, VPDSCL_EASF_V_BF_CNTL, post_fix), \ + SFRB(SCL_EASF_H_RINGEST_EVENTAP_GAIN1, VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN, post_fix), \ + SFRB(SCL_EASF_H_RINGEST_EVENTAP_GAIN2, VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN, post_fix), \ + SFRB(SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1, VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE, post_fix), \ + SFRB(SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2, VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE, post_fix), \ + SFRB(SCL_EASF_V_RINGEST_EVENTAP_GAIN1, VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN, post_fix), \ + SFRB(SCL_EASF_V_RINGEST_EVENTAP_GAIN2, VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN, post_fix), \ + SFRB(SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1, VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE, post_fix), \ + SFRB(SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2, VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE, post_fix), \ + SFRB(SCL_EASF_H_BF_MAXA, VPDSCL_EASF_H_BF_FINAL_MAX_MIN, post_fix), \ + SFRB(SCL_EASF_H_BF_MAXB, VPDSCL_EASF_H_BF_FINAL_MAX_MIN, post_fix), \ + SFRB(SCL_EASF_H_BF_MINA, VPDSCL_EASF_H_BF_FINAL_MAX_MIN, post_fix), \ + SFRB(SCL_EASF_H_BF_MINB, VPDSCL_EASF_H_BF_FINAL_MAX_MIN, post_fix), \ + SFRB(SCL_EASF_H_BF1_PWL_IN_SEG0, VPDSCL_EASF_H_BF1_PWL_SEG0, post_fix), \ + SFRB(SCL_EASF_H_BF1_PWL_BASE_SEG0, VPDSCL_EASF_H_BF1_PWL_SEG0, post_fix), \ + SFRB(SCL_EASF_H_BF1_PWL_SLOPE_SEG0, VPDSCL_EASF_H_BF1_PWL_SEG0, post_fix), \ + SFRB(SCL_EASF_H_BF1_PWL_IN_SEG1, VPDSCL_EASF_H_BF1_PWL_SEG1, post_fix), \ + SFRB(SCL_EASF_H_BF1_PWL_BASE_SEG1, VPDSCL_EASF_H_BF1_PWL_SEG1, post_fix), \ + SFRB(SCL_EASF_H_BF1_PWL_SLOPE_SEG1, VPDSCL_EASF_H_BF1_PWL_SEG1, post_fix), \ + SFRB(SCL_EASF_H_BF1_PWL_IN_SEG2, VPDSCL_EASF_H_BF1_PWL_SEG2, post_fix), \ + SFRB(SCL_EASF_H_BF1_PWL_BASE_SEG2, VPDSCL_EASF_H_BF1_PWL_SEG2, post_fix), \ + SFRB(SCL_EASF_H_BF1_PWL_SLOPE_SEG2, VPDSCL_EASF_H_BF1_PWL_SEG2, post_fix), \ + SFRB(SCL_EASF_H_BF1_PWL_IN_SEG3, VPDSCL_EASF_H_BF1_PWL_SEG3, post_fix), \ + SFRB(SCL_EASF_H_BF1_PWL_BASE_SEG3, VPDSCL_EASF_H_BF1_PWL_SEG3, post_fix), \ + SFRB(SCL_EASF_H_BF1_PWL_SLOPE_SEG3, VPDSCL_EASF_H_BF1_PWL_SEG3, post_fix), \ + SFRB(SCL_EASF_H_BF1_PWL_IN_SEG4, VPDSCL_EASF_H_BF1_PWL_SEG4, post_fix), \ + SFRB(SCL_EASF_H_BF1_PWL_BASE_SEG4, VPDSCL_EASF_H_BF1_PWL_SEG4, post_fix), \ + SFRB(SCL_EASF_H_BF1_PWL_SLOPE_SEG4, VPDSCL_EASF_H_BF1_PWL_SEG4, post_fix), \ + SFRB(SCL_EASF_H_BF1_PWL_IN_SEG5, VPDSCL_EASF_H_BF1_PWL_SEG5, post_fix), \ + SFRB(SCL_EASF_H_BF1_PWL_BASE_SEG5, VPDSCL_EASF_H_BF1_PWL_SEG5, post_fix), \ + SFRB(SCL_EASF_H_BF1_PWL_SLOPE_SEG5, VPDSCL_EASF_H_BF1_PWL_SEG5, post_fix), \ + SFRB(SCL_EASF_H_BF1_PWL_IN_SEG6, VPDSCL_EASF_H_BF1_PWL_SEG6, post_fix), \ + SFRB(SCL_EASF_H_BF1_PWL_BASE_SEG6, VPDSCL_EASF_H_BF1_PWL_SEG6, post_fix), \ + SFRB(SCL_EASF_H_BF1_PWL_SLOPE_SEG6, VPDSCL_EASF_H_BF1_PWL_SEG6, post_fix), \ + SFRB(SCL_EASF_H_BF1_PWL_IN_SEG7, VPDSCL_EASF_H_BF1_PWL_SEG7, post_fix), \ + SFRB(SCL_EASF_H_BF1_PWL_BASE_SEG7, VPDSCL_EASF_H_BF1_PWL_SEG7, post_fix), \ + SFRB(SCL_EASF_H_BF3_PWL_IN_SEG0, VPDSCL_EASF_H_BF3_PWL_SEG0, post_fix), \ + SFRB(SCL_EASF_H_BF3_PWL_BASE_SEG0, VPDSCL_EASF_H_BF3_PWL_SEG0, post_fix), \ + SFRB(SCL_EASF_H_BF3_PWL_SLOPE_SEG0, VPDSCL_EASF_H_BF3_PWL_SEG0, post_fix), \ + SFRB(SCL_EASF_H_BF3_PWL_IN_SEG1, VPDSCL_EASF_H_BF3_PWL_SEG1, post_fix), \ + SFRB(SCL_EASF_H_BF3_PWL_BASE_SEG1, VPDSCL_EASF_H_BF3_PWL_SEG1, post_fix), \ + SFRB(SCL_EASF_H_BF3_PWL_SLOPE_SEG1, VPDSCL_EASF_H_BF3_PWL_SEG1, post_fix), \ + SFRB(SCL_EASF_H_BF3_PWL_IN_SEG2, VPDSCL_EASF_H_BF3_PWL_SEG2, post_fix), \ + SFRB(SCL_EASF_H_BF3_PWL_BASE_SEG2, VPDSCL_EASF_H_BF3_PWL_SEG2, post_fix), \ + SFRB(SCL_EASF_H_BF3_PWL_SLOPE_SEG2, VPDSCL_EASF_H_BF3_PWL_SEG2, post_fix), \ + SFRB(SCL_EASF_H_BF3_PWL_IN_SEG3, VPDSCL_EASF_H_BF3_PWL_SEG3, post_fix), \ + SFRB(SCL_EASF_H_BF3_PWL_BASE_SEG3, VPDSCL_EASF_H_BF3_PWL_SEG3, post_fix), \ + SFRB(SCL_EASF_H_BF3_PWL_SLOPE_SEG3, VPDSCL_EASF_H_BF3_PWL_SEG3, post_fix), \ + SFRB(SCL_EASF_H_BF3_PWL_IN_SEG4, VPDSCL_EASF_H_BF3_PWL_SEG4, post_fix), \ + SFRB(SCL_EASF_H_BF3_PWL_BASE_SEG4, VPDSCL_EASF_H_BF3_PWL_SEG4, post_fix), \ + SFRB(SCL_EASF_H_BF3_PWL_SLOPE_SEG4, VPDSCL_EASF_H_BF3_PWL_SEG4, post_fix), \ + SFRB(SCL_EASF_H_BF3_PWL_IN_SEG5, VPDSCL_EASF_H_BF3_PWL_SEG5, post_fix), \ + SFRB(SCL_EASF_H_BF3_PWL_BASE_SEG5, VPDSCL_EASF_H_BF3_PWL_SEG5, post_fix), \ + SFRB(SCL_EASF_V_BF1_PWL_IN_SEG0, VPDSCL_EASF_V_BF1_PWL_SEG0, post_fix), \ + SFRB(SCL_EASF_V_BF1_PWL_BASE_SEG0, VPDSCL_EASF_V_BF1_PWL_SEG0, post_fix), \ + SFRB(SCL_EASF_V_BF1_PWL_SLOPE_SEG0, VPDSCL_EASF_V_BF1_PWL_SEG0, post_fix), \ + SFRB(SCL_EASF_V_BF1_PWL_IN_SEG1, VPDSCL_EASF_V_BF1_PWL_SEG1, post_fix), \ + SFRB(SCL_EASF_V_BF1_PWL_BASE_SEG1, VPDSCL_EASF_V_BF1_PWL_SEG1, post_fix), \ + SFRB(SCL_EASF_V_BF1_PWL_SLOPE_SEG1, VPDSCL_EASF_V_BF1_PWL_SEG1, post_fix), \ + SFRB(SCL_EASF_V_BF1_PWL_IN_SEG2, VPDSCL_EASF_V_BF1_PWL_SEG2, post_fix), \ + SFRB(SCL_EASF_V_BF1_PWL_BASE_SEG2, VPDSCL_EASF_V_BF1_PWL_SEG2, post_fix), \ + SFRB(SCL_EASF_V_BF1_PWL_SLOPE_SEG2, VPDSCL_EASF_V_BF1_PWL_SEG2, post_fix), \ + SFRB(SCL_EASF_V_BF1_PWL_IN_SEG3, VPDSCL_EASF_V_BF1_PWL_SEG3, post_fix), \ + SFRB(SCL_EASF_V_BF1_PWL_BASE_SEG3, VPDSCL_EASF_V_BF1_PWL_SEG3, post_fix), \ + SFRB(SCL_EASF_V_BF1_PWL_SLOPE_SEG3, VPDSCL_EASF_V_BF1_PWL_SEG3, post_fix), \ + SFRB(SCL_EASF_V_BF1_PWL_IN_SEG4, VPDSCL_EASF_V_BF1_PWL_SEG4, post_fix), \ + SFRB(SCL_EASF_V_BF1_PWL_BASE_SEG4, VPDSCL_EASF_V_BF1_PWL_SEG4, post_fix), \ + SFRB(SCL_EASF_V_BF1_PWL_SLOPE_SEG4, VPDSCL_EASF_V_BF1_PWL_SEG4, post_fix), \ + SFRB(SCL_EASF_V_BF1_PWL_IN_SEG5, VPDSCL_EASF_V_BF1_PWL_SEG5, post_fix), \ + SFRB(SCL_EASF_V_BF1_PWL_BASE_SEG5, VPDSCL_EASF_V_BF1_PWL_SEG5, post_fix), \ + SFRB(SCL_EASF_V_BF1_PWL_SLOPE_SEG5, VPDSCL_EASF_V_BF1_PWL_SEG5, post_fix), \ + SFRB(SCL_EASF_V_BF1_PWL_IN_SEG6, VPDSCL_EASF_V_BF1_PWL_SEG6, post_fix), \ + SFRB(SCL_EASF_V_BF1_PWL_BASE_SEG6, VPDSCL_EASF_V_BF1_PWL_SEG6, post_fix), \ + SFRB(SCL_EASF_V_BF1_PWL_SLOPE_SEG6, VPDSCL_EASF_V_BF1_PWL_SEG6, post_fix), \ + SFRB(SCL_EASF_V_BF1_PWL_IN_SEG7, VPDSCL_EASF_V_BF1_PWL_SEG7, post_fix), \ + SFRB(SCL_EASF_V_BF1_PWL_BASE_SEG7, VPDSCL_EASF_V_BF1_PWL_SEG7, post_fix), \ + SFRB(SCL_EASF_V_BF3_PWL_IN_SEG0, VPDSCL_EASF_V_BF3_PWL_SEG0, post_fix), \ + SFRB(SCL_EASF_V_BF3_PWL_BASE_SEG0, VPDSCL_EASF_V_BF3_PWL_SEG0, post_fix), \ + SFRB(SCL_EASF_V_BF3_PWL_SLOPE_SEG0, VPDSCL_EASF_V_BF3_PWL_SEG0, post_fix), \ + SFRB(SCL_EASF_V_BF3_PWL_IN_SEG1, VPDSCL_EASF_V_BF3_PWL_SEG1, post_fix), \ + SFRB(SCL_EASF_V_BF3_PWL_BASE_SEG1, VPDSCL_EASF_V_BF3_PWL_SEG1, post_fix), \ + SFRB(SCL_EASF_V_BF3_PWL_SLOPE_SEG1, VPDSCL_EASF_V_BF3_PWL_SEG1, post_fix), \ + SFRB(SCL_EASF_V_BF3_PWL_IN_SEG2, VPDSCL_EASF_V_BF3_PWL_SEG2, post_fix), \ + SFRB(SCL_EASF_V_BF3_PWL_BASE_SEG2, VPDSCL_EASF_V_BF3_PWL_SEG2, post_fix), \ + SFRB(SCL_EASF_V_BF3_PWL_SLOPE_SEG2, VPDSCL_EASF_V_BF3_PWL_SEG2, post_fix), \ + SFRB(SCL_EASF_V_BF3_PWL_IN_SEG3, VPDSCL_EASF_V_BF3_PWL_SEG3, post_fix), \ + SFRB(SCL_EASF_V_BF3_PWL_BASE_SEG3, VPDSCL_EASF_V_BF3_PWL_SEG3, post_fix), \ + SFRB(SCL_EASF_V_BF3_PWL_SLOPE_SEG3, VPDSCL_EASF_V_BF3_PWL_SEG3, post_fix), \ + SFRB(SCL_EASF_V_BF3_PWL_IN_SEG4, VPDSCL_EASF_V_BF3_PWL_SEG4, post_fix), \ + SFRB(SCL_EASF_V_BF3_PWL_BASE_SEG4, VPDSCL_EASF_V_BF3_PWL_SEG4, post_fix), \ + SFRB(SCL_EASF_V_BF3_PWL_SLOPE_SEG4, VPDSCL_EASF_V_BF3_PWL_SEG4, post_fix), \ + SFRB(SCL_EASF_V_BF3_PWL_IN_SEG5, VPDSCL_EASF_V_BF3_PWL_SEG5, post_fix), \ + SFRB(SCL_EASF_V_BF3_PWL_BASE_SEG5, VPDSCL_EASF_V_BF3_PWL_SEG5, post_fix), \ + SFRB(SCL_EASF_H_RINGEST_FORCE, VPDSCL_EASF_RINGEST_FORCE, post_fix), \ + SFRB(SCL_EASF_V_RINGEST_FORCE, VPDSCL_EASF_RINGEST_FORCE, post_fix), \ + SFRB(SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT, VPDSCL_EASF_V_RINGEST_3TAP_CNTL1, post_fix), \ + SFRB(SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL, VPDSCL_EASF_V_RINGEST_3TAP_CNTL1, post_fix), \ + SFRB(SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE, VPDSCL_EASF_V_RINGEST_3TAP_CNTL2, post_fix), \ + SFRB(SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE, VPDSCL_EASF_V_RINGEST_3TAP_CNTL2, post_fix), \ + SFRB(SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE, VPDSCL_EASF_V_RINGEST_3TAP_CNTL3, post_fix), \ + SFRB(SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET, VPDSCL_EASF_V_RINGEST_3TAP_CNTL3, post_fix), \ + SFRB(ISHARP_EN, VPISHARP_MODE, post_fix), \ + SFRB(ISHARP_NOISEDET_EN, VPISHARP_MODE, post_fix), \ + SFRB(ISHARP_NOISEDET_MODE, VPISHARP_MODE, post_fix), \ + SFRB(ISHARP_LBA_MODE, VPISHARP_MODE, post_fix), \ + SFRB(ISHARP_DELTA_LUT_SELECT_CURRENT, VPISHARP_MODE, post_fix), \ + SFRB(ISHARP_FMT_MODE, VPISHARP_MODE, post_fix), \ + SFRB(ISHARP_FMT_NORM, VPISHARP_MODE, post_fix), \ + SFRB(ISHARP_DELTA_LUT_HOST_SELECT, VPISHARP_DELTA_CTRL, post_fix), \ + SFRB(ISHARP_DELTA_INDEX, VPISHARP_DELTA_INDEX, post_fix), \ + SFRB(ISHARP_DELTA_DATA, VPISHARP_DELTA_DATA, post_fix), \ + SFRB(ISHARP_LBA_PWL_IN_SEG0, VPISHARP_LBA_PWL_SEG0, post_fix), \ + SFRB(ISHARP_LBA_PWL_BASE_SEG0, VPISHARP_LBA_PWL_SEG0, post_fix), \ + SFRB(ISHARP_LBA_PWL_SLOPE_SEG0, VPISHARP_LBA_PWL_SEG0, post_fix), \ + SFRB(ISHARP_LBA_PWL_IN_SEG1, VPISHARP_LBA_PWL_SEG1, post_fix), \ + SFRB(ISHARP_LBA_PWL_BASE_SEG1, VPISHARP_LBA_PWL_SEG1, post_fix), \ + SFRB(ISHARP_LBA_PWL_SLOPE_SEG1, VPISHARP_LBA_PWL_SEG1, post_fix), \ + SFRB(ISHARP_LBA_PWL_IN_SEG2, VPISHARP_LBA_PWL_SEG2, post_fix), \ + SFRB(ISHARP_LBA_PWL_BASE_SEG2, VPISHARP_LBA_PWL_SEG2, post_fix), \ + SFRB(ISHARP_LBA_PWL_SLOPE_SEG2, VPISHARP_LBA_PWL_SEG2, post_fix), \ + SFRB(ISHARP_LBA_PWL_IN_SEG3, VPISHARP_LBA_PWL_SEG3, post_fix), \ + SFRB(ISHARP_LBA_PWL_BASE_SEG3, VPISHARP_LBA_PWL_SEG3, post_fix), \ + SFRB(ISHARP_LBA_PWL_SLOPE_SEG3, VPISHARP_LBA_PWL_SEG3, post_fix), \ + SFRB(ISHARP_LBA_PWL_IN_SEG4, VPISHARP_LBA_PWL_SEG4, post_fix), \ + SFRB(ISHARP_LBA_PWL_BASE_SEG4, VPISHARP_LBA_PWL_SEG4, post_fix), \ + SFRB(ISHARP_LBA_PWL_SLOPE_SEG4, VPISHARP_LBA_PWL_SEG4, post_fix), \ + SFRB(ISHARP_LBA_PWL_IN_SEG5, VPISHARP_LBA_PWL_SEG5, post_fix), \ + SFRB(ISHARP_LBA_PWL_BASE_SEG5, VPISHARP_LBA_PWL_SEG5, post_fix), \ + SFRB(ISHARP_DELTA_LUT_MEM_PWR_FORCE, VPISHARP_DELTA_LUT_MEM_PWR_CTRL, post_fix), \ + SFRB(ISHARP_DELTA_LUT_MEM_PWR_DIS, VPISHARP_DELTA_LUT_MEM_PWR_CTRL, post_fix), \ + SFRB(ISHARP_DELTA_LUT_MEM_PWR_STATE, VPISHARP_DELTA_LUT_MEM_PWR_CTRL, post_fix), \ + SFRB(ISHARP_NLDELTA_SCLIP_EN_P, VPISHARP_NLDELTA_SOFT_CLIP, post_fix), \ + SFRB(ISHARP_NLDELTA_SCLIP_PIVOT_P, VPISHARP_NLDELTA_SOFT_CLIP, post_fix), \ + SFRB(ISHARP_NLDELTA_SCLIP_SLOPE_P, VPISHARP_NLDELTA_SOFT_CLIP, post_fix), \ + SFRB(ISHARP_NLDELTA_SCLIP_EN_N, VPISHARP_NLDELTA_SOFT_CLIP, post_fix), \ + SFRB(ISHARP_NLDELTA_SCLIP_PIVOT_N, VPISHARP_NLDELTA_SOFT_CLIP, post_fix), \ + SFRB(ISHARP_NLDELTA_SCLIP_SLOPE_N, VPISHARP_NLDELTA_SOFT_CLIP, post_fix), \ + SFRB(ISHARP_NOISEDET_UTHRE, VPISHARP_NOISEDET_THRESHOLD, post_fix), \ + SFRB(ISHARP_NOISEDET_DTHRE, VPISHARP_NOISEDET_THRESHOLD, post_fix), \ + SFRB(ISHARP_NOISEDET_PWL_START_IN, VPISHARP_NOISE_GAIN_PWL, post_fix), \ + SFRB(ISHARP_NOISEDET_PWL_END_IN, VPISHARP_NOISE_GAIN_PWL, post_fix), \ + SFRB(ISHARP_NOISEDET_PWL_SLOPE, VPISHARP_NOISE_GAIN_PWL, post_fix), \ + SFRB(LUMA_KEYER_EN, VPCNVC_COLOR_KEYER_CONTROL, post_fix), \ + SFRB(VPCM_HIST_CH_EN, VPCM_HIST_CNTL, post_fix), \ + SFRB(VPCM_HIST_SRC1_SEL, VPCM_HIST_CNTL, post_fix), \ + SFRB(VPCM_HIST_SRC2_SEL, VPCM_HIST_CNTL, post_fix), \ + SFRB(VPCM_HIST_SRC3_SEL, VPCM_HIST_CNTL, post_fix), \ + SFRB(VPCM_HIST_SEL, VPCM_HIST_CNTL, post_fix), \ + SFRB(VPCM_HIST_CH1_XBAR, VPCM_HIST_CNTL, post_fix), \ + SFRB(VPCM_HIST_CH2_XBAR, VPCM_HIST_CNTL, post_fix), \ + SFRB(VPCM_HIST_CH3_XBAR, VPCM_HIST_CNTL, post_fix), \ + SFRB(VPCM_HIST_FORMAT, VPCM_HIST_CNTL, post_fix), \ + SFRB(VPCM_HIST_READ_CHANNEL_MASK, VPCM_HIST_CNTL, post_fix), \ + SFRB(VPCM_HIST_SCALE_SRC1, VPCM_HIST_SCALE_SRC1, post_fix), \ + SFRB(VPCM_HIST_SCALE_SRC3, VPCM_HIST_SCALE_SRC3, post_fix), \ + SFRB(VPCM_HIST_BIAS_SRC1, VPCM_HIST_BIAS_SRC1, post_fix), \ + SFRB(VPCM_HIST_BIAS_SRC2, VPCM_HIST_BIAS_SRC2, post_fix), \ + SFRB(VPCM_HIST_BIAS_SRC3, VPCM_HIST_BIAS_SRC3, post_fix), \ + SFRB(VPCM_HIST_COEFA_SRC2, VPCM_HIST_COEFA_SRC2, post_fix), \ + SFRB(VPCM_HIST_COEFB_SRC2, VPCM_HIST_COEFB_SRC2, post_fix), \ + SFRB(VPCM_HIST_COEFC_SRC2, VPCM_HIST_COEFC_SRC2, post_fix) +#define DPP_FIELD_LIST_VPE20(post_fix) \ + DPP_FIELD_LIST_VPE20_COMMON(post_fix), \ + SFRB(VPCM_GAMCOR_LUT_CONFIG_MODE, VPCM_GAMCOR_LUT_CONTROL, post_fix), \ + SFRB(SCL_V_INIT_FRAC_BOT, VPDSCL_VERT_FILTER_INIT_BOT, post_fix), \ + SFRB(SCL_V_INIT_INT_BOT, VPDSCL_VERT_FILTER_INIT_BOT, post_fix), \ + SFRB(SCL_V_INIT_FRAC_BOT_C, VPDSCL_VERT_FILTER_INIT_BOT_C, post_fix), \ + SFRB(SCL_V_INIT_INT_BOT_C, VPDSCL_VERT_FILTER_INIT_BOT_C, post_fix), \ + SFRB(PRE_DEGAM_MODE, VPCNVC_PRE_DEGAM, post_fix), \ + SFRB(PRE_DEGAM_SELECT, VPCNVC_PRE_DEGAM, post_fix) + +#define DPP_REG_VARIABLE_LIST_VPE20_COMMON \ + DPP_REG_VARIABLE_LIST_VPE10_COMMON \ + reg_id_val VPCNVC_ALPHA_2BIT_LUT01; \ + reg_id_val VPCNVC_ALPHA_2BIT_LUT23; \ + reg_id_val VPDSCL_SC_MODE; \ + reg_id_val VPDSCL_SC_MATRIX_C0C1; \ + reg_id_val VPDSCL_SC_MATRIX_C2C3; \ + reg_id_val VPDSCL_EASF_H_MODE; \ + reg_id_val VPDSCL_EASF_V_MODE; \ + reg_id_val VPDSCL_EASF_H_BF_CNTL; \ + reg_id_val VPDSCL_EASF_V_BF_CNTL; \ + reg_id_val VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN; \ + reg_id_val VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE; \ + reg_id_val VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN; \ + reg_id_val VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE; \ + reg_id_val VPDSCL_EASF_H_BF_FINAL_MAX_MIN; \ + reg_id_val VPDSCL_EASF_V_BF_FINAL_MAX_MIN; \ + reg_id_val VPDSCL_EASF_H_BF1_PWL_SEG0; \ + reg_id_val VPDSCL_EASF_H_BF1_PWL_SEG1; \ + reg_id_val VPDSCL_EASF_H_BF1_PWL_SEG2; \ + reg_id_val VPDSCL_EASF_H_BF1_PWL_SEG3; \ + reg_id_val VPDSCL_EASF_H_BF1_PWL_SEG4; \ + reg_id_val VPDSCL_EASF_H_BF1_PWL_SEG5; \ + reg_id_val VPDSCL_EASF_H_BF1_PWL_SEG6; \ + reg_id_val VPDSCL_EASF_H_BF1_PWL_SEG7; \ + reg_id_val VPDSCL_EASF_H_BF3_PWL_SEG0; \ + reg_id_val VPDSCL_EASF_H_BF3_PWL_SEG1; \ + reg_id_val VPDSCL_EASF_H_BF3_PWL_SEG2; \ + reg_id_val VPDSCL_EASF_H_BF3_PWL_SEG3; \ + reg_id_val VPDSCL_EASF_H_BF3_PWL_SEG4; \ + reg_id_val VPDSCL_EASF_H_BF3_PWL_SEG5; \ + reg_id_val VPDSCL_EASF_V_BF1_PWL_SEG0; \ + reg_id_val VPDSCL_EASF_V_BF1_PWL_SEG1; \ + reg_id_val VPDSCL_EASF_V_BF1_PWL_SEG2; \ + reg_id_val VPDSCL_EASF_V_BF1_PWL_SEG3; \ + reg_id_val VPDSCL_EASF_V_BF1_PWL_SEG4; \ + reg_id_val VPDSCL_EASF_V_BF1_PWL_SEG5; \ + reg_id_val VPDSCL_EASF_V_BF1_PWL_SEG6; \ + reg_id_val VPDSCL_EASF_V_BF1_PWL_SEG7; \ + reg_id_val VPDSCL_EASF_V_BF3_PWL_SEG0; \ + reg_id_val VPDSCL_EASF_V_BF3_PWL_SEG1; \ + reg_id_val VPDSCL_EASF_V_BF3_PWL_SEG2; \ + reg_id_val VPDSCL_EASF_V_BF3_PWL_SEG3; \ + reg_id_val VPDSCL_EASF_V_BF3_PWL_SEG4; \ + reg_id_val VPDSCL_EASF_V_BF3_PWL_SEG5; \ + reg_id_val VPDSCL_EASF_RINGEST_FORCE; \ + reg_id_val VPDSCL_EASF_V_RINGEST_3TAP_CNTL1; \ + reg_id_val VPDSCL_EASF_V_RINGEST_3TAP_CNTL2; \ + reg_id_val VPDSCL_EASF_V_RINGEST_3TAP_CNTL3; \ + reg_id_val VPISHARP_MODE; \ + reg_id_val VPISHARP_DELTA_CTRL; \ + reg_id_val VPISHARP_DELTA_INDEX; \ + reg_id_val VPISHARP_DELTA_DATA; \ + reg_id_val VPISHARP_LBA_PWL_SEG0; \ + reg_id_val VPISHARP_LBA_PWL_SEG1; \ + reg_id_val VPISHARP_LBA_PWL_SEG2; \ + reg_id_val VPISHARP_LBA_PWL_SEG3; \ + reg_id_val VPISHARP_LBA_PWL_SEG4; \ + reg_id_val VPISHARP_LBA_PWL_SEG5; \ + reg_id_val VPISHARP_DELTA_LUT_MEM_PWR_CTRL; \ + reg_id_val VPISHARP_NLDELTA_SOFT_CLIP; \ + reg_id_val VPISHARP_NOISEDET_THRESHOLD; \ + reg_id_val VPISHARP_NOISE_GAIN_PWL; \ + reg_id_val VPCM_HIST_CNTL; \ + reg_id_val VPCM_HIST_SCALE_SRC1; \ + reg_id_val VPCM_HIST_SCALE_SRC3; \ + reg_id_val VPCM_HIST_BIAS_SRC1; \ + reg_id_val VPCM_HIST_BIAS_SRC2; \ + reg_id_val VPCM_HIST_BIAS_SRC3; \ + reg_id_val VPCM_HIST_COEFA_SRC2; \ + reg_id_val VPCM_HIST_COEFB_SRC2; \ + reg_id_val VPCM_HIST_COEFC_SRC2; + +#define DPP_REG_VARIABLE_LIST_VPE20 \ + DPP_REG_VARIABLE_LIST_VPE20_COMMON \ + reg_id_val VPDSCL_VERT_FILTER_INIT_BOT; \ + reg_id_val VPDSCL_VERT_FILTER_INIT_BOT_C; \ + reg_id_val VPCNVC_PRE_DEGAM; + +#define DPP_FIELD_VARIABLE_LIST_VPE20_COMMON(type) \ + DPP_FIELD_VARIABLE_LIST_VPE10_COMMON(type) \ + type SCL_SC_MATRIX_MODE; \ + type SCL_SC_LTONL_EN; \ + type SCL_SC_MATRIX_C0; \ + type SCL_SC_MATRIX_C1; \ + type SCL_SC_MATRIX_C2; \ + type SCL_SC_MATRIX_C3; \ + type SCL_EASF_H_EN; \ + type SCL_EASF_H_RINGEST_FORCE_EN; \ + type SCL_EASF_H_2TAP_SHARP_FACTOR; \ + type SCL_EASF_V_EN; \ + type SCL_EASF_V_RINGEST_FORCE_EN; \ + type SCL_EASF_V_2TAP_SHARP_FACTOR; \ + type SCL_EASF_H_BF1_EN; \ + type SCL_EASF_H_BF2_MODE; \ + type SCL_EASF_H_BF3_MODE; \ + type SCL_EASF_H_BF2_FLAT1_GAIN; \ + type SCL_EASF_H_BF2_FLAT2_GAIN; \ + type SCL_EASF_H_BF2_ROC_GAIN; \ + type SCL_EASF_V_BF1_EN; \ + type SCL_EASF_V_BF2_MODE; \ + type SCL_EASF_V_BF3_MODE; \ + type SCL_EASF_V_BF2_FLAT1_GAIN; \ + type SCL_EASF_V_BF2_FLAT2_GAIN; \ + type SCL_EASF_V_BF2_ROC_GAIN; \ + type SCL_EASF_H_RINGEST_EVENTAP_GAIN1; \ + type SCL_EASF_H_RINGEST_EVENTAP_GAIN2; \ + type SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1; \ + type SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2; \ + type SCL_EASF_V_RINGEST_EVENTAP_GAIN1; \ + type SCL_EASF_V_RINGEST_EVENTAP_GAIN2; \ + type SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1; \ + type SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2; \ + type SCL_EASF_H_BF_MAXA; \ + type SCL_EASF_H_BF_MAXB; \ + type SCL_EASF_H_BF_MINA; \ + type SCL_EASF_H_BF_MINB; \ + type SCL_EASF_V_BF_MAXA; \ + type SCL_EASF_V_BF_MAXB; \ + type SCL_EASF_V_BF_MINA; \ + type SCL_EASF_V_BF_MINB; \ + type SCL_EASF_H_BF1_PWL_IN_SEG0; \ + type SCL_EASF_H_BF1_PWL_BASE_SEG0; \ + type SCL_EASF_H_BF1_PWL_SLOPE_SEG0; \ + type SCL_EASF_H_BF1_PWL_IN_SEG1; \ + type SCL_EASF_H_BF1_PWL_BASE_SEG1; \ + type SCL_EASF_H_BF1_PWL_SLOPE_SEG1; \ + type SCL_EASF_H_BF1_PWL_IN_SEG2; \ + type SCL_EASF_H_BF1_PWL_BASE_SEG2; \ + type SCL_EASF_H_BF1_PWL_SLOPE_SEG2; \ + type SCL_EASF_H_BF1_PWL_IN_SEG3; \ + type SCL_EASF_H_BF1_PWL_BASE_SEG3; \ + type SCL_EASF_H_BF1_PWL_SLOPE_SEG3; \ + type SCL_EASF_H_BF1_PWL_IN_SEG4; \ + type SCL_EASF_H_BF1_PWL_BASE_SEG4; \ + type SCL_EASF_H_BF1_PWL_SLOPE_SEG4; \ + type SCL_EASF_H_BF1_PWL_IN_SEG5; \ + type SCL_EASF_H_BF1_PWL_BASE_SEG5; \ + type SCL_EASF_H_BF1_PWL_SLOPE_SEG5; \ + type SCL_EASF_H_BF1_PWL_IN_SEG6; \ + type SCL_EASF_H_BF1_PWL_BASE_SEG6; \ + type SCL_EASF_H_BF1_PWL_SLOPE_SEG6; \ + type SCL_EASF_H_BF1_PWL_IN_SEG7; \ + type SCL_EASF_H_BF1_PWL_BASE_SEG7; \ + type SCL_EASF_H_BF3_PWL_IN_SEG0; \ + type SCL_EASF_H_BF3_PWL_BASE_SEG0; \ + type SCL_EASF_H_BF3_PWL_SLOPE_SEG0; \ + type SCL_EASF_H_BF3_PWL_IN_SEG1; \ + type SCL_EASF_H_BF3_PWL_BASE_SEG1; \ + type SCL_EASF_H_BF3_PWL_SLOPE_SEG1; \ + type SCL_EASF_H_BF3_PWL_IN_SEG2; \ + type SCL_EASF_H_BF3_PWL_BASE_SEG2; \ + type SCL_EASF_H_BF3_PWL_SLOPE_SEG2; \ + type SCL_EASF_H_BF3_PWL_IN_SEG3; \ + type SCL_EASF_H_BF3_PWL_BASE_SEG3; \ + type SCL_EASF_H_BF3_PWL_SLOPE_SEG3; \ + type SCL_EASF_H_BF3_PWL_IN_SEG4; \ + type SCL_EASF_H_BF3_PWL_BASE_SEG4; \ + type SCL_EASF_H_BF3_PWL_SLOPE_SEG4; \ + type SCL_EASF_H_BF3_PWL_IN_SEG5; \ + type SCL_EASF_H_BF3_PWL_BASE_SEG5; \ + type SCL_EASF_V_BF1_PWL_IN_SEG0; \ + type SCL_EASF_V_BF1_PWL_BASE_SEG0; \ + type SCL_EASF_V_BF1_PWL_SLOPE_SEG0; \ + type SCL_EASF_V_BF1_PWL_IN_SEG1; \ + type SCL_EASF_V_BF1_PWL_BASE_SEG1; \ + type SCL_EASF_V_BF1_PWL_SLOPE_SEG1; \ + type SCL_EASF_V_BF1_PWL_IN_SEG2; \ + type SCL_EASF_V_BF1_PWL_BASE_SEG2; \ + type SCL_EASF_V_BF1_PWL_SLOPE_SEG2; \ + type SCL_EASF_V_BF1_PWL_IN_SEG3; \ + type SCL_EASF_V_BF1_PWL_BASE_SEG3; \ + type SCL_EASF_V_BF1_PWL_SLOPE_SEG3; \ + type SCL_EASF_V_BF1_PWL_IN_SEG4; \ + type SCL_EASF_V_BF1_PWL_BASE_SEG4; \ + type SCL_EASF_V_BF1_PWL_SLOPE_SEG4; \ + type SCL_EASF_V_BF1_PWL_IN_SEG5; \ + type SCL_EASF_V_BF1_PWL_BASE_SEG5; \ + type SCL_EASF_V_BF1_PWL_SLOPE_SEG5; \ + type SCL_EASF_V_BF1_PWL_IN_SEG6; \ + type SCL_EASF_V_BF1_PWL_BASE_SEG6; \ + type SCL_EASF_V_BF1_PWL_SLOPE_SEG6; \ + type SCL_EASF_V_BF1_PWL_IN_SEG7; \ + type SCL_EASF_V_BF1_PWL_BASE_SEG7; \ + type SCL_EASF_V_BF3_PWL_IN_SEG0; \ + type SCL_EASF_V_BF3_PWL_BASE_SEG0; \ + type SCL_EASF_V_BF3_PWL_SLOPE_SEG0; \ + type SCL_EASF_V_BF3_PWL_IN_SEG1; \ + type SCL_EASF_V_BF3_PWL_BASE_SEG1; \ + type SCL_EASF_V_BF3_PWL_SLOPE_SEG1; \ + type SCL_EASF_V_BF3_PWL_IN_SEG2; \ + type SCL_EASF_V_BF3_PWL_BASE_SEG2; \ + type SCL_EASF_V_BF3_PWL_SLOPE_SEG2; \ + type SCL_EASF_V_BF3_PWL_IN_SEG3; \ + type SCL_EASF_V_BF3_PWL_BASE_SEG3; \ + type SCL_EASF_V_BF3_PWL_SLOPE_SEG3; \ + type SCL_EASF_V_BF3_PWL_IN_SEG4; \ + type SCL_EASF_V_BF3_PWL_BASE_SEG4; \ + type SCL_EASF_V_BF3_PWL_SLOPE_SEG4; \ + type SCL_EASF_V_BF3_PWL_IN_SEG5; \ + type SCL_EASF_V_BF3_PWL_BASE_SEG5; \ + type SCL_EASF_H_RINGEST_FORCE; \ + type SCL_EASF_V_RINGEST_FORCE; \ + type SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT; \ + type SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL; \ + type SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE; \ + type SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE; \ + type SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE; \ + type SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET; \ + type ISHARP_EN; \ + type ISHARP_NOISEDET_EN; \ + type ISHARP_NOISEDET_MODE; \ + type ISHARP_LBA_MODE; \ + type ISHARP_DELTA_LUT_SELECT; \ + type ISHARP_FMT_MODE; \ + type ISHARP_FMT_NORM; \ + type ISHARP_DELTA_LUT_SELECT_CURRENT; \ + type ISHARP_DELTA_LUT_HOST_SELECT; \ + type ISHARP_DELTA_INDEX; \ + type ISHARP_DELTA_DATA; \ + type ISHARP_LBA_PWL_IN_SEG0; \ + type ISHARP_LBA_PWL_BASE_SEG0; \ + type ISHARP_LBA_PWL_SLOPE_SEG0; \ + type ISHARP_LBA_PWL_IN_SEG1; \ + type ISHARP_LBA_PWL_BASE_SEG1; \ + type ISHARP_LBA_PWL_SLOPE_SEG1; \ + type ISHARP_LBA_PWL_IN_SEG2; \ + type ISHARP_LBA_PWL_BASE_SEG2; \ + type ISHARP_LBA_PWL_SLOPE_SEG2; \ + type ISHARP_LBA_PWL_IN_SEG3; \ + type ISHARP_LBA_PWL_BASE_SEG3; \ + type ISHARP_LBA_PWL_SLOPE_SEG3; \ + type ISHARP_LBA_PWL_IN_SEG4; \ + type ISHARP_LBA_PWL_BASE_SEG4; \ + type ISHARP_LBA_PWL_SLOPE_SEG4; \ + type ISHARP_LBA_PWL_IN_SEG5; \ + type ISHARP_LBA_PWL_BASE_SEG5; \ + type ISHARP_DELTA_LUT_MEM_PWR_FORCE; \ + type ISHARP_DELTA_LUT_MEM_PWR_DIS; \ + type ISHARP_DELTA_LUT_MEM_PWR_STATE; \ + type ISHARP_NLDELTA_SCLIP_EN_P; \ + type ISHARP_NLDELTA_SCLIP_PIVOT_P; \ + type ISHARP_NLDELTA_SCLIP_SLOPE_P; \ + type ISHARP_NLDELTA_SCLIP_EN_N; \ + type ISHARP_NLDELTA_SCLIP_PIVOT_N; \ + type ISHARP_NLDELTA_SCLIP_SLOPE_N; \ + type ISHARP_NOISEDET_UTHRE; \ + type ISHARP_NOISEDET_DTHRE; \ + type ISHARP_NOISEDET_PWL_START_IN; \ + type ISHARP_NOISEDET_PWL_END_IN; \ + type ISHARP_NOISEDET_PWL_SLOPE; \ + type LUMA_KEYER_EN; \ + type VPCM_HIST_SEL; \ + type VPCM_HIST_CH_EN; \ + type VPCM_HIST_SRC1_SEL; \ + type VPCM_HIST_SRC2_SEL; \ + type VPCM_HIST_SRC3_SEL; \ + type VPCM_HIST_CH1_XBAR; \ + type VPCM_HIST_CH2_XBAR; \ + type VPCM_HIST_CH3_XBAR; \ + type VPCM_HIST_FORMAT; \ + type VPCM_HIST_READ_CHANNEL_MASK; \ + type VPCM_HIST_SCALE_SRC1; \ + type VPCM_HIST_SCALE_SRC3; \ + type VPCM_HIST_BIAS_SRC1; \ + type VPCM_HIST_BIAS_SRC2; \ + type VPCM_HIST_BIAS_SRC3; \ + type VPCM_HIST_COEFA_SRC2; \ + type VPCM_HIST_COEFB_SRC2; \ + type VPCM_HIST_COEFC_SRC2; \ + type VPCNVC_FORMAT_CROSSBAR_R; \ + type VPCNVC_FORMAT_CROSSBAR_G; \ + type VPCNVC_FORMAT_CROSSBAR_B; + +#define DPP_FIELD_VARIABLE_LIST_VPE20(type) \ + DPP_FIELD_VARIABLE_LIST_VPE20_COMMON(type) \ + type VPCM_GAMCOR_LUT_CONFIG_MODE; \ + type SCL_V_INIT_FRAC_BOT; \ + type SCL_V_INIT_INT_BOT; \ + type SCL_V_INIT_FRAC_BOT_C; \ + type SCL_V_INIT_INT_BOT_C; \ + type PRE_DEGAM_MODE; \ + type PRE_DEGAM_SELECT; + +struct vpe20_dpp_registers { + DPP_REG_VARIABLE_LIST_VPE20 +}; + +struct vpe20_dpp_shift { + DPP_FIELD_VARIABLE_LIST_VPE20(uint8_t) +}; + +struct vpe20_dpp_mask { + DPP_FIELD_VARIABLE_LIST_VPE20(uint32_t) +}; + +struct vpe20_dpp { + struct dpp base; // base class, must be the 1st field + struct vpe20_dpp_registers *regs; + const struct vpe20_dpp_shift *shift; + const struct vpe20_dpp_mask *mask; +}; + +enum vpe10_dscl_mode_sel vpe20_dpp_dscl_get_dscl_mode(const struct scaler_data *data); + +void vpe20_construct_dpp(struct vpe_priv *vpe_priv, struct dpp *dpp); + +void vpe20_dpp_set_segment_scaler(struct dpp *dpp, const struct scaler_data *scl_data); + +void vpe20_dpp_dscl_set_scaler_position(struct dpp *dpp, const struct scaler_data *scl_data); + +void vpe20_dpp_set_frame_scaler(struct dpp *dpp, const struct scaler_data *scl_data); + +void vpe20_dpp_program_input_transfer_func(struct dpp *dpp, struct transfer_func *input_tf); + +void vpe20_dscl_program_easf(struct dpp *dpp_base, const struct scaler_data *scl_data); + +void vpe20_dscl_disable_easf(struct dpp *dpp, const struct scaler_data *scl_data); + +void vpe20_dscl_program_isharp(struct dpp *dpp, const struct scaler_data *scl_data); + +void vpe20_dpp_enable_clocks(struct dpp *dpp, bool enable); + +void vpe20_dpp_cnv_program_alpha_keyer( + struct dpp *dpp, const struct cnv_keyer_params *keyer_params); +void vpe20_dpp_program_cnv( + struct dpp *dpp, enum vpe_surface_pixel_format format, enum vpe_expansion_mode mode); + +void vpe20_dpp_program_histo(struct dpp* dpp, struct vpe_histogram_param* hist_para, enum color_space csm); +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe20/inc/vpe20_mpc.h b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_mpc.h new file mode 100644 index 00000000000..be6749de154 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_mpc.h @@ -0,0 +1,709 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#pragma once + +#include "mpc.h" +#include "reg_helper.h" +#include "vpe10_mpc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define RMCM_MPCC_DISCONNECTED 0xf + +#define MPC_REG_LIST_VPE20_COMMON(id) \ + MPC_REG_LIST_VPE10_COMMON(id), \ + SRIDFVL(VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE, VPMPCC_MCM, id), \ + SRIDFVL(VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA, VPMPCC_MCM, id), \ + SRIDFVL(VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA, VPMPCC_MCM, id), \ + SRIDFVL(VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA, VPMPCC_MCM, id), \ + SRIDFVL(VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA, VPMPCC_MCM, id), \ + SRIDFVL(VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA, VPMPCC_MCM, id), \ + SRIDFVL(VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE, VPMPCC_MCM, id), \ + SRIDFVL(VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA, VPMPCC_MCM, id), \ + SRIDFVL(VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA, VPMPCC_MCM, id), \ + SRIDFVL(VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA, VPMPCC_MCM, id), \ + SRIDFVL(VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA, VPMPCC_MCM, id), \ + SRIDFVL(VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA, VPMPCC_MCM, id), \ + SRIDFVL(VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA, VPMPCC_MCM, id), \ + SRIDFVL(VPMPCC_CONTROL2, VPMPCC, id) + +#define MPC_REG_LIST_VPE20(id) \ + MPC_REG_LIST_VPE20_COMMON(id), SRIDFVL3(SHAPER_CONTROL, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_OFFSET_R, VPMPC_RMCM, id), SRIDFVL3(SHAPER_OFFSET_G, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_OFFSET_B, VPMPC_RMCM, id), SRIDFVL3(SHAPER_SCALE_R, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_SCALE_G_B, VPMPC_RMCM, id), SRIDFVL3(SHAPER_LUT_INDEX, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_LUT_DATA, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_LUT_WRITE_EN_MASK, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_RAMA_START_CNTL_B, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_RAMA_START_CNTL_G, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_RAMA_START_CNTL_R, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_RAMA_END_CNTL_B, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_RAMA_END_CNTL_G, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_RAMA_END_CNTL_R, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_RAMA_REGION_0_1, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_RAMA_REGION_2_3, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_RAMA_REGION_4_5, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_RAMA_REGION_6_7, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_RAMA_REGION_8_9, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_RAMA_REGION_10_11, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_RAMA_REGION_12_13, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_RAMA_REGION_14_15, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_RAMA_REGION_16_17, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_RAMA_REGION_18_19, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_RAMA_REGION_20_21, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_RAMA_REGION_22_23, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_RAMA_REGION_24_25, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_RAMA_REGION_26_27, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_RAMA_REGION_28_29, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_RAMA_REGION_30_31, VPMPC_RMCM, id), \ + SRIDFVL3(SHAPER_RAMA_REGION_32_33, VPMPC_RMCM, id), SRIDFVL3(3DLUT_MODE, VPMPC_RMCM, id), \ + SRIDFVL3(3DLUT_INDEX, VPMPC_RMCM, id), SRIDFVL3(3DLUT_DATA, VPMPC_RMCM, id), \ + SRIDFVL3(3DLUT_DATA_30BIT, VPMPC_RMCM, id), \ + SRIDFVL3(3DLUT_READ_WRITE_CONTROL, VPMPC_RMCM, id), \ + SRIDFVL3(3DLUT_OUT_NORM_FACTOR, VPMPC_RMCM, id), \ + SRIDFVL3(3DLUT_OUT_OFFSET_R, VPMPC_RMCM, id), \ + SRIDFVL3(3DLUT_OUT_OFFSET_G, VPMPC_RMCM, id), \ + SRIDFVL3(3DLUT_OUT_OFFSET_B, VPMPC_RMCM, id), \ + SRIDFVL3(GAMUT_REMAP_COEF_FORMAT, VPMPC_RMCM, id), \ + SRIDFVL3(GAMUT_REMAP_MODE, VPMPC_RMCM, id), \ + SRIDFVL3(GAMUT_REMAP_C11_C12_SETA, VPMPC_RMCM, id), \ + SRIDFVL3(GAMUT_REMAP_C13_C14_SETA, VPMPC_RMCM, id), \ + SRIDFVL3(GAMUT_REMAP_C21_C22_SETA, VPMPC_RMCM, id), \ + SRIDFVL3(GAMUT_REMAP_C23_C24_SETA, VPMPC_RMCM, id), \ + SRIDFVL3(GAMUT_REMAP_C31_C32_SETA, VPMPC_RMCM, id), \ + SRIDFVL3(GAMUT_REMAP_C33_C34_SETA, VPMPC_RMCM, id), \ + SRIDFVL3(MEM_PWR_CTRL, VPMPC_RMCM, id), SRIDFVL3(3DLUT_FAST_LOAD_SELECT, VPMPC_RMCM, id), \ + SRIDFVL3(CNTL, VPMPC_RMCM, id), SRIDFVL1(VPMPC_VPCDC0_3DLUT_FL_CONFIG), \ + SRIDFVL1(VPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE) + +#define MPC_FIELD_LIST_VPE20_COMMON(post_fix) \ + MPC_FIELD_LIST_VPE10_COMMON(post_fix), SFRB(VPMPC_RMCM_CNTL, VPMPC_RMCM_CNTL, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_LUT_MODE, VPMPC_RMCM_SHAPER_CONTROL, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_MODE_CURRENT, VPMPC_RMCM_SHAPER_CONTROL, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_SELECT_CURRENT, VPMPC_RMCM_SHAPER_CONTROL, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_OFFSET_R, VPMPC_RMCM_SHAPER_OFFSET_R, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_OFFSET_G, VPMPC_RMCM_SHAPER_OFFSET_G, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_OFFSET_B, VPMPC_RMCM_SHAPER_OFFSET_B, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_SCALE_R, VPMPC_RMCM_SHAPER_SCALE_R, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_LUT_INDEX, VPMPC_RMCM_SHAPER_LUT_INDEX, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_LUT_DATA, VPMPC_RMCM_SHAPER_LUT_DATA, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_LUT_WRITE_SEL, VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B, VPMPC_RMCM_SHAPER_RAMA_START_CNTL_B, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, \ + VPMPC_RMCM_SHAPER_RAMA_START_CNTL_B, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_G, VPMPC_RMCM_SHAPER_RAMA_START_CNTL_G, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, \ + VPMPC_RMCM_SHAPER_RAMA_START_CNTL_G, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_R, VPMPC_RMCM_SHAPER_RAMA_START_CNTL_R, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, \ + VPMPC_RMCM_SHAPER_RAMA_START_CNTL_R, post_fix), \ + SFRB( \ + VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B, VPMPC_RMCM_SHAPER_RAMA_END_CNTL_B, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, VPMPC_RMCM_SHAPER_RAMA_END_CNTL_B, \ + post_fix), \ + SFRB( \ + VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_G, VPMPC_RMCM_SHAPER_RAMA_END_CNTL_G, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_G, VPMPC_RMCM_SHAPER_RAMA_END_CNTL_G, \ + post_fix), \ + SFRB( \ + VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_R, VPMPC_RMCM_SHAPER_RAMA_END_CNTL_R, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_R, VPMPC_RMCM_SHAPER_RAMA_END_CNTL_R, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_0_1, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, VPMPC_RMCM_SHAPER_RAMA_REGION_0_1, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_0_1, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, VPMPC_RMCM_SHAPER_RAMA_REGION_0_1, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_2_3, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, VPMPC_RMCM_SHAPER_RAMA_REGION_2_3, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_2_3, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, VPMPC_RMCM_SHAPER_RAMA_REGION_2_3, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_4_5, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, VPMPC_RMCM_SHAPER_RAMA_REGION_4_5, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_4_5, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, VPMPC_RMCM_SHAPER_RAMA_REGION_4_5, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_6_7, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, VPMPC_RMCM_SHAPER_RAMA_REGION_6_7, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_6_7, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, VPMPC_RMCM_SHAPER_RAMA_REGION_6_7, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_8_9, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, VPMPC_RMCM_SHAPER_RAMA_REGION_8_9, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_8_9, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, VPMPC_RMCM_SHAPER_RAMA_REGION_8_9, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_10_11, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_10_11, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_10_11, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_10_11, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_12_13, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_12_13, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_12_13, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_12_13, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_14_15, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_14_15, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_14_15, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_14_15, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_16_17, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_16_17, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_16_17, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_16_17, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_18_19, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_18_19, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_18_19, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_18_19, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_20_21, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_20_21, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_20_21, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_20_21, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_22_23, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_22_23, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_22_23, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_22_23, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_24_25, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_24_25, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_24_25, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_24_25, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_26_27, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_26_27, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_26_27, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_26_27, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_28_29, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_28_29, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_28_29, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_28_29, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_30_31, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_30_31, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_30_31, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_30_31, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_32_33, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_32_33, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, VPMPC_RMCM_SHAPER_RAMA_REGION_32_33, \ + post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, \ + VPMPC_RMCM_SHAPER_RAMA_REGION_32_33, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_MODE, VPMPC_RMCM_3DLUT_MODE, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_SIZE, VPMPC_RMCM_3DLUT_MODE, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_MODE_CURRENT, VPMPC_RMCM_3DLUT_MODE, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_SELECT_CURRENT, VPMPC_RMCM_3DLUT_MODE, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_INDEX, VPMPC_RMCM_3DLUT_INDEX, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_DATA0, VPMPC_RMCM_3DLUT_DATA, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_DATA1, VPMPC_RMCM_3DLUT_DATA, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_DATA_30BIT, VPMPC_RMCM_3DLUT_DATA_30BIT, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_WRITE_EN_MASK, VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_RAM_SEL, VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_30BIT_EN, VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_READ_SEL, VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_OUT_NORM_FACTOR, VPMPC_RMCM_3DLUT_OUT_NORM_FACTOR, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_OUT_OFFSET_R, VPMPC_RMCM_3DLUT_OUT_OFFSET_R, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_OUT_SCALE_R, VPMPC_RMCM_3DLUT_OUT_OFFSET_R, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_OUT_OFFSET_G, VPMPC_RMCM_3DLUT_OUT_OFFSET_G, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_OUT_SCALE_G, VPMPC_RMCM_3DLUT_OUT_OFFSET_G, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_OUT_OFFSET_B, VPMPC_RMCM_3DLUT_OUT_OFFSET_B, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_OUT_SCALE_B, VPMPC_RMCM_3DLUT_OUT_OFFSET_B, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_MEM_PWR_FORCE, VPMPC_RMCM_MEM_PWR_CTRL, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_MEM_PWR_DIS, VPMPC_RMCM_MEM_PWR_CTRL, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_MEM_LOW_PWR_MODE, VPMPC_RMCM_MEM_PWR_CTRL, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_MEM_PWR_FORCE, VPMPC_RMCM_MEM_PWR_CTRL, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_MEM_PWR_DIS, VPMPC_RMCM_MEM_PWR_CTRL, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_MEM_LOW_PWR_MODE, VPMPC_RMCM_MEM_PWR_CTRL, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_MEM_PWR_STATE, VPMPC_RMCM_MEM_PWR_CTRL, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_MEM_PWR_STATE, VPMPC_RMCM_MEM_PWR_CTRL, post_fix), \ + SFRB(VPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT, VPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT, post_fix), \ + SFRB(VPMPC_RMCM_GAMUT_REMAP_MODE, VPMPC_RMCM_GAMUT_REMAP_MODE, post_fix), \ + SFRB(VPMPC_RMCM_GAMUT_REMAP_MODE_CURRENT, VPMPC_RMCM_GAMUT_REMAP_MODE, post_fix), \ + SFRB(VPMPC_RMCM_GAMUT_REMAP_C11_SETA, VPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA, post_fix), \ + SFRB(VPMPC_RMCM_GAMUT_REMAP_C12_SETA, VPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA, post_fix), \ + SFRB(VPMPC_RMCM_GAMUT_REMAP_C13_SETA, VPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA, post_fix), \ + SFRB(VPMPC_RMCM_GAMUT_REMAP_C14_SETA, VPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA, post_fix), \ + SFRB(VPMPC_RMCM_GAMUT_REMAP_C21_SETA, VPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA, post_fix), \ + SFRB(VPMPC_RMCM_GAMUT_REMAP_C22_SETA, VPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA, post_fix), \ + SFRB(VPMPC_RMCM_GAMUT_REMAP_C23_SETA, VPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA, post_fix), \ + SFRB(VPMPC_RMCM_GAMUT_REMAP_C24_SETA, VPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA, post_fix), \ + SFRB(VPMPC_RMCM_GAMUT_REMAP_C31_SETA, VPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA, post_fix), \ + SFRB(VPMPC_RMCM_GAMUT_REMAP_C32_SETA, VPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA, post_fix), \ + SFRB(VPMPC_RMCM_GAMUT_REMAP_C33_SETA, VPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA, post_fix), \ + SFRB(VPMPC_RMCM_GAMUT_REMAP_C34_SETA, VPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA, post_fix), \ + SFRB(VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, \ + post_fix), \ + SFRB(VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE, VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE, post_fix), \ + SFRB(VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT, VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE, \ + post_fix), \ + SFRB(VPMPCC_MCM_FIRST_GAMUT_REMAP_C11_SETA, VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA, \ + post_fix), \ + SFRB(VPMPCC_MCM_FIRST_GAMUT_REMAP_C12_SETA, VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA, \ + post_fix), \ + SFRB(VPMPCC_MCM_FIRST_GAMUT_REMAP_C13_SETA, VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA, \ + post_fix), \ + SFRB(VPMPCC_MCM_FIRST_GAMUT_REMAP_C14_SETA, VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA, \ + post_fix), \ + SFRB(VPMPCC_MCM_FIRST_GAMUT_REMAP_C21_SETA, VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA, \ + post_fix), \ + SFRB(VPMPCC_MCM_FIRST_GAMUT_REMAP_C22_SETA, VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA, \ + post_fix), \ + SFRB(VPMPCC_MCM_FIRST_GAMUT_REMAP_C23_SETA, VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA, \ + post_fix), \ + SFRB(VPMPCC_MCM_FIRST_GAMUT_REMAP_C24_SETA, VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA, \ + post_fix), \ + SFRB(VPMPCC_MCM_FIRST_GAMUT_REMAP_C31_SETA, VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA, \ + post_fix), \ + SFRB(VPMPCC_MCM_FIRST_GAMUT_REMAP_C32_SETA, VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA, \ + post_fix), \ + SFRB(VPMPCC_MCM_FIRST_GAMUT_REMAP_C33_SETA, VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA, \ + post_fix), \ + SFRB(VPMPCC_MCM_FIRST_GAMUT_REMAP_C34_SETA, VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA, \ + post_fix), \ + SFRB(VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT, VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT, \ + post_fix), \ + SFRB(VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE, VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE, post_fix), \ + SFRB(VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT, VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE, \ + post_fix), \ + SFRB(VPMPCC_MCM_SECOND_GAMUT_REMAP_C11_SETA, VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA, \ + post_fix), \ + SFRB(VPMPCC_MCM_SECOND_GAMUT_REMAP_C12_SETA, VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA, \ + post_fix), \ + SFRB(VPMPCC_MCM_SECOND_GAMUT_REMAP_C13_SETA, VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA, \ + post_fix), \ + SFRB(VPMPCC_MCM_SECOND_GAMUT_REMAP_C14_SETA, VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA, \ + post_fix), \ + SFRB(VPMPCC_MCM_SECOND_GAMUT_REMAP_C21_SETA, VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA, \ + post_fix), \ + SFRB(VPMPCC_MCM_SECOND_GAMUT_REMAP_C22_SETA, VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA, \ + post_fix), \ + SFRB(VPMPCC_MCM_SECOND_GAMUT_REMAP_C23_SETA, VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA, \ + post_fix), \ + SFRB(VPMPCC_MCM_SECOND_GAMUT_REMAP_C24_SETA, VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA, \ + post_fix), \ + SFRB(VPMPCC_MCM_SECOND_GAMUT_REMAP_C31_SETA, VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA, \ + post_fix), \ + SFRB(VPMPCC_MCM_SECOND_GAMUT_REMAP_C32_SETA, VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA, \ + post_fix), \ + SFRB(VPMPCC_MCM_SECOND_GAMUT_REMAP_C33_SETA, VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA, \ + post_fix), \ + SFRB(VPMPCC_MCM_SECOND_GAMUT_REMAP_C34_SETA, VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA, \ + post_fix), \ + SFRB(VPMPCC_GLOBAL_ALPHA, VPMPCC_CONTROL2, post_fix), \ + SFRB(VPMPCC_GLOBAL_GAIN, VPMPCC_CONTROL2, post_fix) + +#define MPC_FIELD_LIST_VPE20(post_fix) \ + MPC_FIELD_LIST_VPE20_COMMON(post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_SCALE_G, VPMPC_RMCM_SHAPER_SCALE_G_B, post_fix), \ + SFRB(VPMPC_RMCM_SHAPER_SCALE_B, VPMPC_RMCM_SHAPER_SCALE_G_B, post_fix), \ + SFRB(VPMPC_RMCM_3DLUT_FL_SEL, VPMPC_RMCM_3DLUT_FAST_LOAD_SELECT, post_fix), \ + SFRB(VPCDC0_3DLUT_FL_MODE, VPMPC_VPCDC0_3DLUT_FL_CONFIG, post_fix), \ + SFRB(VPCDC0_3DLUT_FL_FORMAT, VPMPC_VPCDC0_3DLUT_FL_CONFIG, post_fix), \ + SFRB(VPCDC0_3DLUT_FL_BIAS, VPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE, post_fix), \ + SFRB(VPCDC0_3DLUT_FL_SCALE, VPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE, post_fix) + +#define MPC_REG_VARIABLE_LIST_VPE20_COMMON \ + MPC_REG_VARIABLE_LIST_VPE10_COMMON \ + reg_id_val VPMPC_RMCM_CNTL; \ + reg_id_val VPMPC_RMCM_SHAPER_CONTROL; \ + reg_id_val VPMPC_RMCM_SHAPER_OFFSET_R; \ + reg_id_val VPMPC_RMCM_SHAPER_OFFSET_G; \ + reg_id_val VPMPC_RMCM_SHAPER_OFFSET_B; \ + reg_id_val VPMPC_RMCM_SHAPER_SCALE_R; \ + reg_id_val VPMPC_RMCM_SHAPER_LUT_INDEX; \ + reg_id_val VPMPC_RMCM_SHAPER_LUT_DATA; \ + reg_id_val VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK; \ + reg_id_val VPMPC_RMCM_SHAPER_RAMA_START_CNTL_B; \ + reg_id_val VPMPC_RMCM_SHAPER_RAMA_START_CNTL_G; \ + reg_id_val VPMPC_RMCM_SHAPER_RAMA_START_CNTL_R; \ + reg_id_val VPMPC_RMCM_SHAPER_RAMA_END_CNTL_B; \ + reg_id_val VPMPC_RMCM_SHAPER_RAMA_END_CNTL_G; \ + reg_id_val VPMPC_RMCM_SHAPER_RAMA_END_CNTL_R; \ + reg_id_val VPMPC_RMCM_SHAPER_RAMA_REGION_0_1; \ + reg_id_val VPMPC_RMCM_SHAPER_RAMA_REGION_2_3; \ + reg_id_val VPMPC_RMCM_SHAPER_RAMA_REGION_4_5; \ + reg_id_val VPMPC_RMCM_SHAPER_RAMA_REGION_6_7; \ + reg_id_val VPMPC_RMCM_SHAPER_RAMA_REGION_8_9; \ + reg_id_val VPMPC_RMCM_SHAPER_RAMA_REGION_10_11; \ + reg_id_val VPMPC_RMCM_SHAPER_RAMA_REGION_12_13; \ + reg_id_val VPMPC_RMCM_SHAPER_RAMA_REGION_14_15; \ + reg_id_val VPMPC_RMCM_SHAPER_RAMA_REGION_16_17; \ + reg_id_val VPMPC_RMCM_SHAPER_RAMA_REGION_18_19; \ + reg_id_val VPMPC_RMCM_SHAPER_RAMA_REGION_20_21; \ + reg_id_val VPMPC_RMCM_SHAPER_RAMA_REGION_22_23; \ + reg_id_val VPMPC_RMCM_SHAPER_RAMA_REGION_24_25; \ + reg_id_val VPMPC_RMCM_SHAPER_RAMA_REGION_26_27; \ + reg_id_val VPMPC_RMCM_SHAPER_RAMA_REGION_28_29; \ + reg_id_val VPMPC_RMCM_SHAPER_RAMA_REGION_30_31; \ + reg_id_val VPMPC_RMCM_SHAPER_RAMA_REGION_32_33; \ + reg_id_val VPMPC_RMCM_3DLUT_MODE; \ + reg_id_val VPMPC_RMCM_3DLUT_INDEX; \ + reg_id_val VPMPC_RMCM_3DLUT_DATA; \ + reg_id_val VPMPC_RMCM_3DLUT_DATA_30BIT; \ + reg_id_val VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL; \ + reg_id_val VPMPC_RMCM_3DLUT_OUT_NORM_FACTOR; \ + reg_id_val VPMPC_RMCM_3DLUT_OUT_OFFSET_R; \ + reg_id_val VPMPC_RMCM_3DLUT_OUT_OFFSET_G; \ + reg_id_val VPMPC_RMCM_3DLUT_OUT_OFFSET_B; \ + reg_id_val VPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT; \ + reg_id_val VPMPC_RMCM_GAMUT_REMAP_MODE; \ + reg_id_val VPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA; \ + reg_id_val VPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA; \ + reg_id_val VPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA; \ + reg_id_val VPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA; \ + reg_id_val VPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA; \ + reg_id_val VPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA; \ + reg_id_val VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT; \ + reg_id_val VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE; \ + reg_id_val VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA; \ + reg_id_val VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA; \ + reg_id_val VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA; \ + reg_id_val VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA; \ + reg_id_val VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA; \ + reg_id_val VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA; \ + reg_id_val VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT; \ + reg_id_val VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE; \ + reg_id_val VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA; \ + reg_id_val VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA; \ + reg_id_val VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA; \ + reg_id_val VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA; \ + reg_id_val VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA; \ + reg_id_val VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA; \ + reg_id_val VPMPC_RMCM_MEM_PWR_CTRL; \ + reg_id_val VPMPCC_CONTROL2; \ + reg_id_val VPCM_HIST_INDEX; + +#define MPC_REG_VARIABLE_LIST_VPE20 \ + MPC_REG_VARIABLE_LIST_VPE20_COMMON \ + reg_id_val VPMPC_RMCM_SHAPER_SCALE_G_B; \ + reg_id_val VPMPC_RMCM_3DLUT_FAST_LOAD_SELECT; \ + reg_id_val VPMPC_VPCDC0_3DLUT_FL_CONFIG; \ + reg_id_val VPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE; + +#define MPC_FIELD_VARIABLE_LIST_VPE20_COMMON(type) \ + MPC_FIELD_VARIABLE_LIST_VPE10_COMMON(type) \ + type VPMPC_RMCM_CNTL; \ + type VPMPC_RMCM_SHAPER_LUT_MODE; \ + type VPMPC_RMCM_SHAPER_MODE_CURRENT; \ + type VPMPC_RMCM_SHAPER_SELECT_CURRENT; \ + type VPMPC_RMCM_SHAPER_OFFSET_R; \ + type VPMPC_RMCM_SHAPER_OFFSET_G; \ + type VPMPC_RMCM_SHAPER_OFFSET_B; \ + type VPMPC_RMCM_SHAPER_SCALE_R; \ + type VPMPC_RMCM_SHAPER_LUT_INDEX; \ + type VPMPC_RMCM_SHAPER_LUT_DATA; \ + type VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK; \ + type VPMPC_RMCM_SHAPER_LUT_WRITE_SEL; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_G; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_R; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_G; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_G; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_R; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_R; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET; \ + type VPMPC_RMCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS; \ + type VPMPC_RMCM_3DLUT_MODE; \ + type VPMPC_RMCM_3DLUT_SIZE; \ + type VPMPC_RMCM_3DLUT_MODE_CURRENT; \ + type VPMPC_RMCM_3DLUT_SELECT_CURRENT; \ + type VPMPC_RMCM_3DLUT_INDEX; \ + type VPMPC_RMCM_3DLUT_DATA0; \ + type VPMPC_RMCM_3DLUT_DATA1; \ + type VPMPC_RMCM_3DLUT_DATA_30BIT; \ + type VPMPC_RMCM_3DLUT_WRITE_EN_MASK; \ + type VPMPC_RMCM_3DLUT_RAM_SEL; \ + type VPMPC_RMCM_3DLUT_30BIT_EN; \ + type VPMPC_RMCM_3DLUT_READ_SEL; \ + type VPMPC_RMCM_3DLUT_OUT_NORM_FACTOR; \ + type VPMPC_RMCM_3DLUT_OUT_OFFSET_R; \ + type VPMPC_RMCM_3DLUT_OUT_SCALE_R; \ + type VPMPC_RMCM_3DLUT_OUT_OFFSET_G; \ + type VPMPC_RMCM_3DLUT_OUT_SCALE_G; \ + type VPMPC_RMCM_3DLUT_OUT_OFFSET_B; \ + type VPMPC_RMCM_3DLUT_OUT_SCALE_B; \ + type VPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT; \ + type VPMPC_RMCM_GAMUT_REMAP_MODE; \ + type VPMPC_RMCM_GAMUT_REMAP_MODE_CURRENT; \ + type VPMPC_RMCM_GAMUT_REMAP_C11_SETA; \ + type VPMPC_RMCM_GAMUT_REMAP_C12_SETA; \ + type VPMPC_RMCM_GAMUT_REMAP_C13_SETA; \ + type VPMPC_RMCM_GAMUT_REMAP_C14_SETA; \ + type VPMPC_RMCM_GAMUT_REMAP_C21_SETA; \ + type VPMPC_RMCM_GAMUT_REMAP_C22_SETA; \ + type VPMPC_RMCM_GAMUT_REMAP_C23_SETA; \ + type VPMPC_RMCM_GAMUT_REMAP_C24_SETA; \ + type VPMPC_RMCM_GAMUT_REMAP_C31_SETA; \ + type VPMPC_RMCM_GAMUT_REMAP_C32_SETA; \ + type VPMPC_RMCM_GAMUT_REMAP_C33_SETA; \ + type VPMPC_RMCM_GAMUT_REMAP_C34_SETA; \ + type VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT; \ + type VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE; \ + type VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT; \ + type VPMPCC_MCM_FIRST_GAMUT_REMAP_C11_SETA; \ + type VPMPCC_MCM_FIRST_GAMUT_REMAP_C12_SETA; \ + type VPMPCC_MCM_FIRST_GAMUT_REMAP_C13_SETA; \ + type VPMPCC_MCM_FIRST_GAMUT_REMAP_C14_SETA; \ + type VPMPCC_MCM_FIRST_GAMUT_REMAP_C21_SETA; \ + type VPMPCC_MCM_FIRST_GAMUT_REMAP_C22_SETA; \ + type VPMPCC_MCM_FIRST_GAMUT_REMAP_C23_SETA; \ + type VPMPCC_MCM_FIRST_GAMUT_REMAP_C24_SETA; \ + type VPMPCC_MCM_FIRST_GAMUT_REMAP_C31_SETA; \ + type VPMPCC_MCM_FIRST_GAMUT_REMAP_C32_SETA; \ + type VPMPCC_MCM_FIRST_GAMUT_REMAP_C33_SETA; \ + type VPMPCC_MCM_FIRST_GAMUT_REMAP_C34_SETA; \ + type VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT; \ + type VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE; \ + type VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT; \ + type VPMPCC_MCM_SECOND_GAMUT_REMAP_C11_SETA; \ + type VPMPCC_MCM_SECOND_GAMUT_REMAP_C12_SETA; \ + type VPMPCC_MCM_SECOND_GAMUT_REMAP_C13_SETA; \ + type VPMPCC_MCM_SECOND_GAMUT_REMAP_C14_SETA; \ + type VPMPCC_MCM_SECOND_GAMUT_REMAP_C21_SETA; \ + type VPMPCC_MCM_SECOND_GAMUT_REMAP_C22_SETA; \ + type VPMPCC_MCM_SECOND_GAMUT_REMAP_C23_SETA; \ + type VPMPCC_MCM_SECOND_GAMUT_REMAP_C24_SETA; \ + type VPMPCC_MCM_SECOND_GAMUT_REMAP_C31_SETA; \ + type VPMPCC_MCM_SECOND_GAMUT_REMAP_C32_SETA; \ + type VPMPCC_MCM_SECOND_GAMUT_REMAP_C33_SETA; \ + type VPMPCC_MCM_SECOND_GAMUT_REMAP_C34_SETA; \ + type VPMPC_RMCM_SHAPER_MEM_PWR_STATE; \ + type VPMPC_RMCM_3DLUT_MEM_PWR_STATE; \ + type VPMPC_RMCM_SHAPER_MEM_PWR_FORCE; \ + type VPMPC_RMCM_SHAPER_MEM_PWR_DIS; \ + type VPMPC_RMCM_SHAPER_MEM_LOW_PWR_MODE; \ + type VPMPC_RMCM_3DLUT_MEM_PWR_FORCE; \ + type VPMPC_RMCM_3DLUT_MEM_PWR_DIS; \ + type VPMPC_RMCM_3DLUT_MEM_LOW_PWR_MODE; + +#define MPC_FIELD_VARIABLE_LIST_VPE20(type) \ + MPC_FIELD_VARIABLE_LIST_VPE20_COMMON(type) \ + type VPMPC_RMCM_SHAPER_SCALE_G; \ + type VPMPC_RMCM_SHAPER_SCALE_B; \ + type VPMPC_RMCM_3DLUT_FL_SEL; \ + type VPCDC0_3DLUT_FL_MODE; \ + type VPCDC0_3DLUT_FL_FORMAT; \ + type VPCDC0_3DLUT_FL_BIAS; \ + type VPCDC0_3DLUT_FL_SCALE; + +struct vpe20_mpc_registers { + MPC_REG_VARIABLE_LIST_VPE20 +}; + +struct vpe20_mpc_shift { + MPC_FIELD_VARIABLE_LIST_VPE20(uint8_t) +}; + +struct vpe20_mpc_mask { + MPC_FIELD_VARIABLE_LIST_VPE20(uint32_t) +}; + +struct vpe20_mpc { + struct mpc base; + struct vpe20_mpc_registers *regs; + const struct vpe20_mpc_shift *shift; + const struct vpe20_mpc_mask *mask; +}; + +void vpe20_construct_mpc(struct vpe_priv *vpe_priv, struct mpc *mpc); + +void vpe20_mpc_program_mpcc_mux(struct mpc *mpc, enum mpc_mpccid mpcc_idx, + enum mpc_mux_topsel topsel, enum mpc_mux_botsel botsel, enum mpc_mux_outmux outmux, + enum mpc_mux_oppid oppid); + +void vpe20_mpc_program_mpcc_blending( + struct mpc *mpc, enum mpc_mpccid mpcc_idx, struct mpcc_blnd_cfg *blnd_cfg); + +void vpe20_mpc_power_on_1dlut_shaper_3dlut(struct mpc *mpc, bool power_on); + +void vpe20_mpc_shaper_bypass(struct mpc *mpc, bool bypass); + +bool vpe20_mpc_program_shaper(struct mpc *mpc, const struct pwl_params *params); + +// using direct config to program the 3dlut specified in params +void vpe20_mpc_program_3dlut(struct mpc *mpc, const struct tetrahedral_params *params); + +void vpe20_mpc_set_mpc_shaper_3dlut( + struct mpc *mpc, struct transfer_func *func_shaper, struct vpe_3dlut *lut3d_func); + +// using indirect config to configure the 3DLut +// note that we still need direct config to switch the mask between lut0 - lut3 +bool vpe20_mpc_program_3dlut_indirect(struct mpc *mpc, + struct vpe_buf *lut0_3_buf, // 3d lut buf which contains the data for lut0-lut3 + bool use_tetrahedral_17, bool use_12bits); + +void vpe20_attach_3dlut_to_mpc_inst(struct mpc *mpc, enum mpc_mpccid mpcc_idx); + +bool vpe20_mpc_program_movable_cm(struct mpc *mpc, struct transfer_func *func_shaper, + struct vpe_3dlut *lut3d_func, struct transfer_func *blend_tf, bool afterblend); + +void vpe20_mpc_set_gamut_remap2(struct mpc *mpc, struct colorspace_transform *gamut_remap, + enum mpcc_gamut_remap_id mpcc_gamut_remap_block_id); + +void vpe20_update_3dlut_fl_bias_scale(struct mpc *mpc, uint16_t bias, uint16_t scale); + +void vpe20_mpc_program_3dlut_fl_config(struct mpc *mpc, enum vpe_3dlut_mem_layout layout, + enum vpe_3dlut_mem_format format, bool enable); + +void vpe20_mpc_program_3dlut_fl(struct mpc *mpc, enum lut_dimension lut_dimension, bool use_12bit); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe20/inc/vpe20_opp.h b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_opp.h new file mode 100644 index 00000000000..1de1edb9663 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_opp.h @@ -0,0 +1,222 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#pragma once + +#include "opp.h" +#include "reg_helper.h" +#include "vpe10_opp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Some HW registers have been renamed, and even though there are only few exceptions, all have + * to be copied and set individually. The order is the same as in VPE10 so it's easy to compare, + * but the only thing that matters is that they both have the same set of vars/registers. + */ + +#define OPP_REG_LIST_VPE20(id) \ + OPP_REG_LIST_VPE10_COMMON(id), \ + SRIDFVL1(VPOPP_TOP_CLK_CONTROL), \ + SRIDFVL(VPFMT_SUBSAMPLER_MEMORY_CONTROL, VPFMT, id), \ + SRIDFVL(VPOPP_PIPE_OUTBG_EXT1, VPOPP_PIPE, id), \ + SRIDFVL(VPOPP_PIPE_OUTBG_EXT2, VPOPP_PIPE, id), \ + SRIDFVL(VPOPP_PIPE_OUTBG_COL1, VPOPP_PIPE, id), \ + SRIDFVL(VPOPP_PIPE_OUTBG_COL2, VPOPP_PIPE, id), \ + SRIDFVL1(VPOPP_CRC_CONTROL), \ + SRIDFVL1(VPOPP_CRC_RESULT_RG), \ + SRIDFVL1(VPOPP_CRC_RESULT_BC), \ + SRIDFVL1(VPOPP_FROD_CONTROL), \ + SRIDFVL1(VPOPP_FROD_MEM_PWR_CONTROL) + + +#define OPP_FIELD_LIST_VPE20_COMMON(post_fix) \ + OPP_FIELD_LIST_VPE10_COMMON(post_fix), \ + SFRB(VPFMT_PIXEL_ENCODING, VPFMT_CONTROL, post_fix), \ + SFRB(VPFMT_SUBSAMPLE_HTAPS, VPFMT_CONTROL, post_fix), \ + SFRB(VPFMT_SUBSAMPLE_LEFT_EDGE, VPFMT_CONTROL, post_fix), \ + SFRB(VPFMT_SUBSAMPLE_RIGHT_EDGE, VPFMT_CONTROL, post_fix), \ + SFRB(VPFMT_SUBSAMPLE_VTAPS, VPFMT_CONTROL, post_fix), \ + SFRB(VPFMT_SUBSAMPLE_TOP_EDGE, VPFMT_CONTROL, post_fix), \ + SFRB(VPFMT_SUBSAMPLE_BOTTOM_EDGE, VPFMT_CONTROL, post_fix), \ + SFRB(VPFMT_SUBSAMPLER_MEM_PWR_FORCE, VPFMT_SUBSAMPLER_MEMORY_CONTROL, post_fix), \ + SFRB(VPFMT_SUBSAMPLER_MEM_PWR_DIS, VPFMT_SUBSAMPLER_MEMORY_CONTROL, post_fix), \ + SFRB(VPFMT_SUBSAMPLER_MEM_PWR_STATE, VPFMT_SUBSAMPLER_MEMORY_CONTROL, post_fix), \ + SFRB(VPFMT_DEFAULT_MEM_LOW_POWER_STATE, VPFMT_SUBSAMPLER_MEMORY_CONTROL, post_fix), \ + SFRB(OUTBG_EXT_TOP, VPOPP_PIPE_OUTBG_EXT1, post_fix), \ + SFRB(OUTBG_EXT_BOT, VPOPP_PIPE_OUTBG_EXT1, post_fix), \ + SFRB(OUTBG_EXT_LEFT, VPOPP_PIPE_OUTBG_EXT2, post_fix), \ + SFRB(OUTBG_EXT_RIGHT, VPOPP_PIPE_OUTBG_EXT2, post_fix), \ + SFRB(OUTBG_R_CR, VPOPP_PIPE_OUTBG_COL1, post_fix), \ + SFRB(OUTBG_B_CB, VPOPP_PIPE_OUTBG_COL1, post_fix), \ + SFRB(OUTBG_Y, VPOPP_PIPE_OUTBG_COL2, post_fix), \ + SFRB(VPOPP_CRC_EN, VPOPP_CRC_CONTROL, post_fix), \ + SFRB(VPOPP_CRC_CONT_EN, VPOPP_CRC_CONTROL, post_fix), \ + SFRB(VPOPP_CRC_PIXEL_SELECT, VPOPP_CRC_CONTROL, post_fix), \ + SFRB(VPOPP_CRC_SOURCE_SELECT, VPOPP_CRC_CONTROL, post_fix), \ + SFRB(VPOPP_CRC_PIPE_SELECT, VPOPP_CRC_CONTROL, post_fix), \ + SFRB(VPOPP_CRC_MASK, VPOPP_CRC_CONTROL, post_fix), \ + SFRB(VPOPP_CRC_ONE_SHOT_PENDING, VPOPP_CRC_CONTROL, post_fix), \ + SFRB(VPOPP_CRC_RESULT_R, VPOPP_CRC_RESULT_RG, post_fix), \ + SFRB(VPOPP_CRC_RESULT_G, VPOPP_CRC_RESULT_RG, post_fix), \ + SFRB(VPOPP_CRC_RESULT_B, VPOPP_CRC_RESULT_BC, post_fix), \ + SFRB(VPOPP_CRC_RESULT_C, VPOPP_CRC_RESULT_BC, post_fix), \ + SFRB(FROD_EN, VPOPP_FROD_CONTROL, post_fix), \ + SFRB(FROD_MEM_PWR_FORCE, VPOPP_FROD_MEM_PWR_CONTROL, post_fix), \ + SFRB(FROD_MEM_PWR_DIS, VPOPP_FROD_MEM_PWR_CONTROL, post_fix), \ + SFRB(FROD_MEM_PWR_STATE, VPOPP_FROD_MEM_PWR_CONTROL, post_fix), \ + SFRB(FROD_MEM_DEFAULT_LOW_PWR_STATE, VPOPP_FROD_MEM_PWR_CONTROL, post_fix) + +#define OPP_FIELD_LIST_VPE20(post_fix) \ + OPP_FIELD_LIST_VPE20_COMMON(post_fix), \ + SFRB(VPFMT_SPATIAL_DITHER_EN, VPFMT_BIT_DEPTH_CONTROL, post_fix), \ + SFRB(VPFMT_SPATIAL_DITHER_MODE, VPFMT_BIT_DEPTH_CONTROL, post_fix), \ + SFRB(VPFMT_SPATIAL_DITHER_DEPTH, VPFMT_BIT_DEPTH_CONTROL, post_fix), \ + SFRB(VPFMT_FRAME_RANDOM_ENABLE, VPFMT_BIT_DEPTH_CONTROL, post_fix), \ + SFRB(VPFMT_RGB_RANDOM_ENABLE, VPFMT_BIT_DEPTH_CONTROL, post_fix), \ + SFRB(VPFMT_HIGHPASS_RANDOM_ENABLE, VPFMT_BIT_DEPTH_CONTROL, post_fix), \ + SFRB(VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, VPFMT_CONTROL, post_fix), \ + SFRB(VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, VPFMT_CONTROL, post_fix), \ + SFRB(VPFMT_RAND_R_SEED, VPFMT_DITHER_RAND_R_SEED, post_fix), \ + SFRB(VPFMT_RAND_G_SEED, VPFMT_DITHER_RAND_G_SEED, post_fix), \ + SFRB(VPFMT_RAND_B_SEED, VPFMT_DITHER_RAND_B_SEED, post_fix), \ + SFRB(VPOPP_PIPE_ALPHA_SEL, VPOPP_PIPE_CONTROL, post_fix), \ + SFRB(VPOPP_PIPE_ALPHA, VPOPP_PIPE_CONTROL, post_fix) + +#define OPP_REG_VARIABLE_LIST_VPE20 \ + OPP_REG_VARIABLE_LIST_VPE10_COMMON \ + reg_id_val VPFMT_SUBSAMPLER_MEMORY_CONTROL; \ + reg_id_val VPOPP_PIPE_OUTBG_EXT1; \ + reg_id_val VPOPP_PIPE_OUTBG_EXT2; \ + reg_id_val VPOPP_PIPE_OUTBG_COL1; \ + reg_id_val VPOPP_PIPE_OUTBG_COL2; \ + reg_id_val VPOPP_CRC_CONTROL; \ + reg_id_val VPOPP_CRC_RESULT_RG; \ + reg_id_val VPOPP_CRC_RESULT_BC; \ + reg_id_val VPOPP_FROD_CONTROL; \ + reg_id_val VPOPP_FROD_MEM_PWR_CONTROL; + +#define OPP_FIELD_VARIABLE_LIST_VPE20_COMMON(type) \ + OPP_FIELD_VARIABLE_LIST_VPE10_COMMON(type) \ + type VPFMT_PIXEL_ENCODING; \ + type VPFMT_SUBSAMPLE_HTAPS; \ + type VPFMT_SUBSAMPLE_LEFT_EDGE; \ + type VPFMT_SUBSAMPLE_RIGHT_EDGE; \ + type VPFMT_SUBSAMPLE_VTAPS; \ + type VPFMT_SUBSAMPLE_TOP_EDGE; \ + type VPFMT_SUBSAMPLE_BOTTOM_EDGE; \ + type VPFMT_SUBSAMPLER_MEM_PWR_FORCE; \ + type VPFMT_SUBSAMPLER_MEM_PWR_DIS; \ + type VPFMT_SUBSAMPLER_MEM_PWR_STATE; \ + type VPFMT_DEFAULT_MEM_LOW_POWER_STATE; \ + type OUTBG_EXT_TOP; \ + type OUTBG_EXT_BOT; \ + type OUTBG_EXT_LEFT; \ + type OUTBG_EXT_RIGHT; \ + type OUTBG_R_CR; \ + type OUTBG_B_CB; \ + type OUTBG_Y; \ + type VPOPP_CRC_EN; \ + type VPOPP_CRC_CONT_EN; \ + type VPOPP_CRC_PIXEL_SELECT; \ + type VPOPP_CRC_SOURCE_SELECT; \ + type VPOPP_CRC_PIPE_SELECT; \ + type VPOPP_CRC_MASK; \ + type VPOPP_CRC_ONE_SHOT_PENDING; \ + type VPOPP_CRC_RESULT_R; \ + type VPOPP_CRC_RESULT_G; \ + type VPOPP_CRC_RESULT_B; \ + type VPOPP_CRC_RESULT_C; \ + type FROD_EN; \ + type FROD_MEM_PWR_FORCE; \ + type FROD_MEM_PWR_DIS; \ + type FROD_MEM_PWR_STATE; \ + type FROD_MEM_DEFAULT_LOW_PWR_STATE; + +#define OPP_FIELD_VARIABLE_LIST_VPE20(type) \ + OPP_FIELD_VARIABLE_LIST_VPE20_COMMON(type) \ + type VPFMT_SPATIAL_DITHER_EN; \ + type VPFMT_SPATIAL_DITHER_MODE; \ + type VPFMT_SPATIAL_DITHER_DEPTH; \ + type VPFMT_FRAME_RANDOM_ENABLE; \ + type VPFMT_RGB_RANDOM_ENABLE; \ + type VPFMT_HIGHPASS_RANDOM_ENABLE; \ + type VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX; \ + type VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP; \ + type VPFMT_RAND_R_SEED; \ + type VPFMT_RAND_G_SEED; \ + type VPFMT_RAND_B_SEED; \ + type VPOPP_PIPE_ALPHA; \ + type VPOPP_PIPE_ALPHA_SEL; + +/* Variable list is the same as the one for VPE10 at the moment as it's the same set of registers. + * Note that adding VPE2 specific variables must be done at the bottom so that casting can work. + * See PROGRAM_ENTRY(),the order here matters, VPE1 subset must be in the same order in VPE2 list. + */ +struct vpe20_opp_registers { + OPP_REG_VARIABLE_LIST_VPE20 +}; + +struct vpe20_opp_shift { + OPP_FIELD_VARIABLE_LIST_VPE20(uint8_t) +}; + +struct vpe20_opp_mask { + OPP_FIELD_VARIABLE_LIST_VPE20(uint32_t) +}; + +struct vpe20_opp { + struct opp base; // base class, must be the first field + struct vpe20_opp_registers *regs; + const struct vpe20_opp_shift *shift; + const struct vpe20_opp_mask *mask; +}; + +void vpe20_construct_opp(struct vpe_priv *vpe_priv, struct opp *opp); + +void vpe20_opp_build_fmt_subsample_params(struct opp *opp, enum vpe_surface_pixel_format format, + enum subsampling_quality subsample_quality, enum chroma_cositing cositing, + struct fmt_boundary_mode boundary_mode, struct fmt_subsampling_params *subsample_params); + +void vpe20_opp_program_fmt_control(struct opp *opp, struct fmt_control_params *fmt_ctrl); + +void vpe20_opp_program_bit_depth_reduction( + struct opp *opp, const struct bit_depth_reduction_params *params); + +void vpe20_opp_set_bg(struct opp* opp, struct vpe_rect target_rect, struct vpe_rect dst_rect, + enum vpe_surface_pixel_format format, struct vpe_color bgcolor); + +void vpe20_opp_program_pipe_crc(struct opp *opp, bool enable); + +void vpe20_opp_program_frod(struct opp *opp, struct opp_frod_param *frod_param); + +void vpe20_opp_get_fmt_extra_pixel(enum vpe_surface_pixel_format format, + enum subsampling_quality subsample_quality, enum chroma_cositing cositing, + struct fmt_extra_pixel_info *extra_pixel); + +void vpe20_opp_program_pipe_control(struct opp *opp, const struct opp_pipe_control_params *params); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe20/inc/vpe20_plane_desc_writer.h b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_plane_desc_writer.h new file mode 100644 index 00000000000..0b42bb4e2eb --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_plane_desc_writer.h @@ -0,0 +1,110 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "vpe_types.h" +#include "plane_desc_writer.h" +#include "vpe_priv.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct vpe20_plane_desc_header { + int32_t nps0; + int32_t npd0; + int32_t nps1; + int32_t npd1; + int32_t subop; + int32_t dcomp0; + int32_t dcomp1; + uint8_t hist0_dsets; + uint8_t hist1_dsets; + int32_t frod; +}; + +struct vpe20_plane_desc_src { + uint8_t tmz; + enum vpe_swizzle_mode_values swizzle; + uint32_t base_addr_lo; + uint32_t base_addr_hi; + uint16_t pitch; + uint16_t viewport_x; + uint16_t viewport_y; + uint16_t viewport_w; + uint16_t viewport_h; + uint8_t elem_size; + enum vpe_scan_direction scan; + bool comp_mode; + uint32_t meta_base_addr_lo; + uint32_t meta_base_addr_hi; + uint16_t meta_pitch; + uint8_t dcc_ind_blk; + uint32_t format; +}; + +struct vpe20_plane_desc_dst { + uint8_t tmz; + enum vpe_swizzle_mode_values swizzle; + uint32_t base_addr_lo; + uint32_t base_addr_hi; + uint16_t pitch; + uint16_t viewport_x; + uint16_t viewport_y; + uint16_t viewport_w; + uint16_t viewport_h; + uint8_t elem_size; + bool comp_mode; +}; + +void vpe20_construct_plane_desc_writer(struct plane_desc_writer *writer); +/** initialize the plane descriptor writer. + * Calls right before building any plane descriptor + * + * /param writer writer instance + * /param buf points to the current buf, + * /param plane_desc_header header + */ + +void vpe20_plane_desc_writer_init( + struct plane_desc_writer *writer, struct vpe_buf *buf, void *p_header); + +/** fill the value to the embedded buffer. */ +void vpe20_plane_desc_writer_add_source( + struct plane_desc_writer *writer, void *p_source, bool is_plane0); + +/** fill the value to the embedded buffer. */ +void vpe20_plane_desc_writer_add_destination( + struct plane_desc_writer *writer, void *p_destination, bool is_plane0); + +void vpe20_plane_desc_writer_add_meta(struct plane_desc_writer *writer, void *p_source); + +/** fill the value to the embedded buffer for histogram collection. */ +void vpe20_plane_desc_writer_add_hist_destination(struct plane_desc_writer *writer, + void *p_destination, uint32_t hist_idx, uint8_t hist_dsets_array[]); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe20/inc/vpe20_resource.h b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_resource.h new file mode 100644 index 00000000000..1449f047ce2 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_resource.h @@ -0,0 +1,160 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#pragma once + +#include "resource.h" + +#ifdef __cplusplus +extern "C" { +#endif + +enum vpe_status vpe20_construct_resource(struct vpe_priv *vpe_priv, struct resource *res); + +void vpe20_update_recout_dst_viewport(struct scaler_data *data, + enum vpe_surface_pixel_format format, struct spl_opp_adjust *opp_adjust, + bool opp_background_gen); + +void vpe20_update_src_viewport(struct scaler_data *data, enum vpe_surface_pixel_format format); + +void vpe20_calculate_dst_viewport_and_active( + struct segment_ctx* segment_ctx, uint32_t max_seg_width); + +bool vpe20_check_h_mirror_support(bool* input_mirror, bool* output_mirror); + +void vpe20_destroy_resource(struct vpe_priv *vpe_priv, struct resource *res); + +bool vpe20_check_input_format(enum vpe_surface_pixel_format format); + +bool vpe20_check_output_format(enum vpe_surface_pixel_format format); + +bool vpe20_check_output_color_space( + enum vpe_surface_pixel_format format, const struct vpe_color_space *vcs); + +void vpe20_set_lls_pref(struct vpe_priv *vpe_priv, struct spl_in *spl_input, + enum color_transfer_func tf, enum vpe_surface_pixel_format pixel_format); + +enum vpe_status vpe20_check_bg_color_support(struct vpe_priv* vpe_priv, struct vpe_color* bg_color); + +void vpe20_bg_color_convert(enum color_space output_cs, struct transfer_func *output_tf, + enum vpe_surface_pixel_format pixel_format, struct vpe_color *mpc_bg_color, + struct vpe_color *opp_bg_color, bool enable_3dlut); + +int32_t vpe20_program_backend(struct vpe_priv* vpe_priv, uint32_t pipe_idx, uint32_t cmd_idx, bool seg_only); + +uint16_t vpe20_get_bg_stream_idx(struct vpe_priv *vpe_priv); + +uint32_t vpe20_get_hw_surface_format(enum vpe_surface_pixel_format format); + +enum vpe_status vpe20_calculate_segments( + struct vpe_priv *vpe_priv, const struct vpe_build_param *params); + +int32_t vpe20_program_frontend(struct vpe_priv* vpe_priv, uint32_t pipe_idx, uint32_t cmd_idx, + uint32_t cmd_input_idx, bool seg_only); + +bool vpe20_get_dcc_compression_output_cap( + const struct vpe_dcc_surface_param *params, struct vpe_surface_dcc_cap *cap); + +bool vpe20_get_dcc_compression_input_cap( + const struct vpe_dcc_surface_param *params, struct vpe_surface_dcc_cap *cap); + +void vpe20_create_stream_ops_config(struct vpe_priv *vpe_priv, uint32_t pipe_idx, + uint32_t cmd_input_idx, struct stream_ctx *stream_ctx, struct vpe_cmd_info *cmd_info); + +enum vpe_status vpe20_populate_cmd_info(struct vpe_priv *vpe_priv); + +enum vpe_status vpe20_set_num_segments(struct vpe_priv *vpe_priv, struct stream_ctx *stream_ctx, + struct scaler_data *scl_data, struct vpe_rect *src_rect, struct vpe_rect *dst_rect, + uint32_t *max_seg_width, uint32_t recout_width_alignment); + +void vpe20_get_bufs_req(struct vpe_priv *vpe_priv, struct vpe_bufs_req *req); + +enum vpe_status vpe20_check_mirror_rotation_support(const struct vpe_stream *stream); + +enum vpe_status vpe20_update_blnd_gamma(struct vpe_priv *vpe_priv, + const struct vpe_build_param *param, const struct vpe_stream *stream, + struct transfer_func *blnd_tf); + +enum vpe_status vpe20_update_output_gamma(struct vpe_priv *vpe_priv, + const struct vpe_build_param *param, struct transfer_func *output_tf, bool geometric_scaling); + +struct cdc_fe *vpe20_cdc_fe_create(struct vpe_priv *vpe_priv, int inst); +struct cdc_be *vpe20_cdc_be_create(struct vpe_priv *vpe_priv, int inst); +struct dpp *vpe20_dpp_create(struct vpe_priv *vpe_priv, int inst); +struct opp *vpe20_opp_create(struct vpe_priv *vpe_priv, int inst); +struct mpc *vpe20_mpc_create(struct vpe_priv *vpe_priv, int inst); + +void vpe20_fill_bg_cmd_scaler_data( + struct stream_ctx *stream_ctx, struct vpe_rect *dst_viewport, struct scaler_data *scaler_data); + +void vpe20_create_bg_segments( + struct vpe_priv *vpe_priv, struct vpe_rect *gaps, uint16_t gaps_cnt, enum vpe_cmd_ops ops); + +uint32_t vpe20_get_max_seg_width(struct output_ctx *output_ctx, + enum vpe_surface_pixel_format format, enum vpe_scan_direction scan); + +enum vpe_status vpe20_fill_alpha_through_luma_cmd_info( + struct vpe_priv *vpe_priv, uint16_t alpha_stream_idx); + +enum vpe_status vpe20_fill_non_performance_mode_cmd_info( + struct vpe_priv *vpe_priv, uint16_t stream_idx); + +enum vpe_status vpe20_fill_performance_mode_cmd_info( + struct vpe_priv *vpe_priv, uint16_t stream_idx, uint16_t avail_pipe_count); + +enum vpe_status vpe20_fill_blending_cmd_info( + struct vpe_priv *vpe_priv, uint16_t top_stream_idx, uint16_t bot_stream_idx); + +uint32_t vpe20_get_num_pipes_available(struct vpe_priv *vpe_priv, struct stream_ctx *stream_ctx); + +void vpe20_set_frod_output_viewport(struct vpe_cmd_output *dst_output, + struct vpe_cmd_output *src_output, uint32_t viewport_divider, + enum vpe_surface_pixel_format format); + +void vpe20_reset_pipes(struct vpe_priv *vpe_priv); + +enum vpe_status vpe20_populate_frod_param( + struct vpe_priv *vpe_priv, const struct vpe_build_param *param); + +void vpe20_update_opp_adjust_and_boundary(struct stream_ctx *stream_ctx, uint16_t seg_idx, + bool dst_subsampled, const struct vpe_rect *src_rect, const struct vpe_rect *dst_rect, + struct output_ctx *output_ctx, struct spl_opp_adjust *opp_recout_adjust); + +bool vpe20_set_dst_cmd_info_scaler(struct stream_ctx *dst_stream_ctx, + struct scaler_data *dst_scaler_data, struct vpe_rect recout, struct vpe_rect dst_viewport, + struct fmt_boundary_mode *boundary_mode, struct spl_opp_adjust *opp_adjust); + +bool vpe20_validate_cached_param(struct vpe_priv *vpe_priv, const struct vpe_build_param *param); + +void vpe20_program_3dlut_fl(struct vpe_priv *vpe_priv, uint32_t cmd_idx); + +const struct vpe_caps *vpe20_get_capability(void); + +void vpe20_setup_check_funcs(struct vpe_check_support_funcs *funcs); + +enum vpe_status vpe20_check_lut3d_compound( + const struct vpe_stream *stream, const struct vpe_build_param *param); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe20/inc/vpe20_vpe_desc_writer.h b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_vpe_desc_writer.h new file mode 100644 index 00000000000..3845a167441 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/inc/vpe20_vpe_desc_writer.h @@ -0,0 +1,46 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "vpe_desc_writer.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void vpe20_construct_vpe_desc_writer(struct vpe_desc_writer *writer); + +enum vpe_status vpe20_vpe_desc_writer_init( + struct vpe_desc_writer *writer, struct vpe_buf *buf, int cd); + +void vpe20_vpe_desc_writer_add_plane_desc( + struct vpe_desc_writer *writer, uint64_t plane_desc_addr, uint8_t tmz); + +void vpe20_vpe_desc_writer_add_config_desc( + struct vpe_desc_writer *writer, uint64_t config_desc_addr, bool reuse, uint8_t tmz); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe20/vpe20_cdc_be.c b/src/amd/vpelib/src/chip/vpe20/vpe20_cdc_be.c new file mode 100644 index 00000000000..9da8bdf875e --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/vpe20_cdc_be.c @@ -0,0 +1,407 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "common.h" +#include "vpe_priv.h" +#include "vpe20_cdc_be.h" + +#define CTX_BASE cdc_be +#define CTX vpe20_cdc_be + +enum mux_sel { + MUX_SEL_ALPHA = 0, + MUX_SEL_Y_G = 1, + MUX_SEL_CB_B = 2, + MUX_SEL_CR_R = 3 +}; + +static struct cdc_be_funcs cdc_func = { + .program_cdc_control = vpe20_cdc_program_control, + .program_global_sync = vpe20_cdc_program_global_sync, + .program_p2b_config = vpe20_cdc_program_p2b_config, +}; + +void vpe20_cdc_program_control(struct cdc_be *cdc_be, uint8_t enable_frod, uint32_t hist_dsets[]) +{ + PROGRAM_ENTRY(); + REG_SET_3(VPCDC_CONTROL, 0, VPCDC_FROD_EN, enable_frod, VPCDC_HISTOGRAM0_EN, hist_dsets[0], + VPCDC_HISTOGRAM1_EN, hist_dsets[1]); +} + +void vpe20_cdc_program_global_sync( + struct cdc_be *cdc_be, uint32_t vupdate_offset, uint32_t vupdate_width, uint32_t vready_offset) +{ + PROGRAM_ENTRY(); + + REG_SET_3(VPCDC_BE0_GLOBAL_SYNC_CONFIG, 0, BE0_VUPDATE_OFFSET, vupdate_offset, + BE0_VUPDATE_WIDTH, vupdate_width, BE0_VREADY_OFFSET, vready_offset); +} +void vpe20_cdc_program_p2b_config(struct cdc_be *cdc_be, enum vpe_surface_pixel_format format, + enum vpe_swizzle_mode_values swizzle, const struct vpe_rect *viewport, + const struct vpe_rect *viewport_c) +{ + uint32_t bar_sel0 = (uint32_t)MUX_SEL_CB_B; + uint32_t bar_sel1 = (uint32_t)MUX_SEL_Y_G; + uint32_t bar_sel2 = (uint32_t)MUX_SEL_CR_R; + uint32_t bar_sel3 = (uint32_t)MUX_SEL_ALPHA; + uint32_t p2b_format_sel = 0; + uint32_t tile_mode = swizzle == VPE_SW_LINEAR ? 0 : 1; + uint32_t x_start_plane0 = 0; + uint32_t x_start_plane1 = 0; + + PROGRAM_ENTRY(); + + if (viewport != NULL) { + x_start_plane0 = viewport->x; + } + + if (viewport_c != NULL) { + x_start_plane1 = viewport_c->x; + } + + // Conversion to the element coordinate of x_start_plane0 is only required for packed 422 + // formats as only these formats' pixel sizes and element sizes differ among supported formats + if (vpe_is_yuv422(format) && vpe_is_yuv_packed(format)) { + x_start_plane0 = x_start_plane0 / 2; + } + + switch (tile_mode) { + case VPE_SW_LINEAR: + tile_mode = 0; + x_start_plane0 = x_start_plane0 % (32 / (uint32_t)vpe_get_element_size_in_bytes(format, 0)); + x_start_plane1 = x_start_plane1 % (32 / (uint32_t)vpe_get_element_size_in_bytes(format, 1)); + // Pre-divided by 2 + break; + default: + tile_mode = 1; + x_start_plane0 = x_start_plane0 % 4; + x_start_plane1 = x_start_plane1 % 4; + } + + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XRGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrCbYA8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_YCrCbA8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888: + p2b_format_sel = 8; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: + p2b_format_sel = 10; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102: + p2b_format_sel = 11; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + p2b_format_sel = 20; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616: + p2b_format_sel = 21; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616_UNORM: + p2b_format_sel = 26; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_UNORM: + p2b_format_sel = 27; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_SNORM: + p2b_format_sel = 28; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616_SNORM: + p2b_format_sel = 29; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA12121212: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb12121212: + p2b_format_sel = 24; + break; + // Planar YUV formats + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrCb: + p2b_format_sel = 0x40; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbCr: + p2b_format_sel = 0x41; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrCb: + p2b_format_sel = 0x42; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbCr: + p2b_format_sel = 0x43; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrCb: + p2b_format_sel = 0x44; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbCr: + p2b_format_sel = 0x45; + break; + // Packed YUV formats + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrYCb: + p2b_format_sel = 0x48; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbYCr: + p2b_format_sel = 0x49; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CrYCbY: + p2b_format_sel = 0x4a; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CbYCrY: + p2b_format_sel = 0x4b; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrYCb: + p2b_format_sel = 0x4c; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbYCr: + p2b_format_sel = 0x4d; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CrYCbY: + p2b_format_sel = 0x4e; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CbYCrY: + p2b_format_sel = 0x4f; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrYCb: + p2b_format_sel = 0x50; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbYCr: + p2b_format_sel = 0x51; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CrYCbY: + p2b_format_sel = 0x52; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CbYCrY: + p2b_format_sel = 0x53; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: + p2b_format_sel = 0x70; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: + p2b_format_sel = 0x71; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: + p2b_format_sel = 0x76; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: + p2b_format_sel = 0x77; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_R8: + p2b_format_sel = 0x78; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_R16: + p2b_format_sel = 0x7D; + break; + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_RGB: + p2b_format_sel = 0x109; + break; + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_YCbCr: + p2b_format_sel = 0x10D; + break; + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB: + p2b_format_sel = 0x115; + break; + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB_FLOAT: + p2b_format_sel = 0x118; + break; + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_YCbCr: + p2b_format_sel = 0x12A; + break; + default: + VPE_ASSERT(0); + break; + } + + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_RGB: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB_FLOAT: + bar_sel3 = (uint32_t)MUX_SEL_CR_R; + bar_sel2 = (uint32_t)MUX_SEL_CB_B; + bar_sel1 = (uint32_t)MUX_SEL_Y_G; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrCb: + bar_sel3 = (uint32_t)MUX_SEL_CR_R; + bar_sel2 = (uint32_t)MUX_SEL_CB_B; + bar_sel1 = (uint32_t)MUX_SEL_Y_G; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbCr: + bar_sel3 = (uint32_t)MUX_SEL_CB_B; + bar_sel2 = (uint32_t)MUX_SEL_CR_R; + bar_sel1 = (uint32_t)MUX_SEL_Y_G; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CrYCbY: + bar_sel3 = (uint32_t)MUX_SEL_CR_R; + bar_sel2 = (uint32_t)MUX_SEL_CB_B; + bar_sel1 = (uint32_t)MUX_SEL_Y_G; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CbYCrY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CbYCrY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CbYCrY: + bar_sel3 = (uint32_t)MUX_SEL_CB_B; + bar_sel2 = (uint32_t)MUX_SEL_CR_R; + bar_sel1 = (uint32_t)MUX_SEL_Y_G; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA12121212: + bar_sel3 = (uint32_t)MUX_SEL_CR_R; + bar_sel2 = (uint32_t)MUX_SEL_Y_G; + bar_sel1 = (uint32_t)MUX_SEL_CB_B; + bar_sel0 = (uint32_t)MUX_SEL_ALPHA; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616_UNORM: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616_SNORM: + bar_sel3 = (uint32_t)MUX_SEL_ALPHA; + bar_sel2 = (uint32_t)MUX_SEL_CB_B; + bar_sel1 = (uint32_t)MUX_SEL_Y_G; + bar_sel0 = (uint32_t)MUX_SEL_CR_R; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_UNORM: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_SNORM: + bar_sel3 = (uint32_t)MUX_SEL_CB_B; + bar_sel2 = (uint32_t)MUX_SEL_Y_G; + bar_sel1 = (uint32_t)MUX_SEL_CR_R; + bar_sel0 = (uint32_t)MUX_SEL_ALPHA; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + bar_sel3 = (uint32_t)MUX_SEL_ALPHA; + bar_sel2 = (uint32_t)MUX_SEL_CR_R; + bar_sel1 = (uint32_t)MUX_SEL_Y_G; + bar_sel0 = (uint32_t)MUX_SEL_CB_B; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: + bar_sel3 = (uint32_t)MUX_SEL_ALPHA; + bar_sel2 = (uint32_t)MUX_SEL_CB_B; + bar_sel1 = (uint32_t)MUX_SEL_Y_G; + bar_sel0 = (uint32_t)MUX_SEL_CR_R; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA8888: + bar_sel3 = (uint32_t)MUX_SEL_CR_R; + bar_sel2 = (uint32_t)MUX_SEL_Y_G; + bar_sel1 = (uint32_t)MUX_SEL_CB_B; + bar_sel0 = (uint32_t)MUX_SEL_ALPHA; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrCbYA8888: + bar_sel3 = (uint32_t)MUX_SEL_CR_R; + bar_sel2 = (uint32_t)MUX_SEL_CB_B; + bar_sel1 = (uint32_t)MUX_SEL_Y_G; + bar_sel0 = (uint32_t)MUX_SEL_ALPHA; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: + bar_sel2 = (uint32_t)MUX_SEL_Y_G; + bar_sel1 = (uint32_t)MUX_SEL_CR_R; + bar_sel0 = (uint32_t)MUX_SEL_CB_B; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_YCrCbA8888: + bar_sel3 = (uint32_t)MUX_SEL_Y_G; + bar_sel2 = (uint32_t)MUX_SEL_CR_R; + bar_sel1 = (uint32_t)MUX_SEL_CB_B; + bar_sel0 = (uint32_t)MUX_SEL_ALPHA; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb8888: + bar_sel2 = (uint32_t)MUX_SEL_CR_R; + bar_sel1 = (uint32_t)MUX_SEL_Y_G; + bar_sel0 = (uint32_t)MUX_SEL_CB_B; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888: + bar_sel2 = (uint32_t)MUX_SEL_Y_G; + bar_sel1 = (uint32_t)MUX_SEL_CB_B; + bar_sel0 = (uint32_t)MUX_SEL_CR_R; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_R8: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_R16: + bar_sel3 = (uint32_t)MUX_SEL_Y_G; + bar_sel2 = (uint32_t)MUX_SEL_CB_B; + bar_sel1 = (uint32_t)MUX_SEL_CR_R; + bar_sel0 = (uint32_t)MUX_SEL_ALPHA; + break; + default: + break; + } + + REG_SET_8(VPCDC_BE0_P2B_CONFIG, 0, VPCDC_BE0_P2B_XBAR_SEL0, bar_sel0, VPCDC_BE0_P2B_XBAR_SEL1, + bar_sel1, VPCDC_BE0_P2B_XBAR_SEL2, bar_sel2, VPCDC_BE0_P2B_XBAR_SEL3, bar_sel3, + VPCDC_BE0_P2B_FORMAT_SEL, p2b_format_sel, VPCDC_BE0_P2B_TILED, tile_mode, + VPCDC_BE0_P2B_X_START_PLANE0, x_start_plane0, VPCDC_BE0_P2B_X_START_PLANE1, x_start_plane1); +} + +void vpe20_construct_cdc_be(struct vpe_priv *vpe_priv, struct cdc_be *cdc_be) +{ + cdc_be->vpe_priv = vpe_priv; + cdc_be->funcs = &cdc_func; +} + diff --git a/src/amd/vpelib/src/chip/vpe20/vpe20_cdc_fe.c b/src/amd/vpelib/src/chip/vpe20/vpe20_cdc_fe.c new file mode 100644 index 00000000000..56b468f1beb --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/vpe20_cdc_fe.c @@ -0,0 +1,154 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "common.h" +#include "vpe_priv.h" +#include "vpe20_cdc_fe.h" +#include "vpe20_resource.h" + +#define CTX_BASE cdc_fe +#define CTX vpe20_cdc_fe + +enum mux_sel { + MUX_SEL_ALPHA = 0, + MUX_SEL_Y_G = 1, + MUX_SEL_CB_B = 2, + MUX_SEL_CR_R = 3 +}; + +static struct cdc_fe_funcs cdc_fe_func = { + .program_surface_config = vpe20_cdc_program_surface_config, + .program_crossbar_config = vpe20_cdc_program_crossbar_config, + .program_3dlut_fl_config = vpe20_program_3dlut_fl_config, + .program_viewport = vpe20_cdc_program_viewport, +}; + +void vpe20_construct_cdc_fe(struct vpe_priv *vpe_priv, struct cdc_fe *cdc_fe) +{ + cdc_fe->vpe_priv = vpe_priv; + cdc_fe->funcs = &cdc_fe_func; +} + +void vpe20_cdc_program_surface_config(struct cdc_fe *cdc_fe, enum vpe_surface_pixel_format format, + enum vpe_rotation_angle rotation, bool horizontal_mirror, enum vpe_swizzle_mode_values swizzle) +{ + uint32_t surface_linear = 0; + uint32_t rotation_angle = 0; + uint32_t surf_format = 8; + + PROGRAM_ENTRY(); + + /* Program rotation angle and horz mirror - no mirror */ + if (rotation == VPE_ROTATION_ANGLE_0) + rotation_angle = 0; + else if (rotation == VPE_ROTATION_ANGLE_90) + rotation_angle = 1; + else if (rotation == VPE_ROTATION_ANGLE_180) + rotation_angle = 2; + else if (rotation == VPE_ROTATION_ANGLE_270) + rotation_angle = 3; + + if (swizzle == VPE_SW_LINEAR) + surface_linear = 1; + else + surface_linear = 0; + + surf_format = vpe20_get_hw_surface_format(format); + + REG_SET_4(VPCDC_FE0_SURFACE_CONFIG, 0, SURFACE_PIXEL_FORMAT_FE0, surf_format, + ROTATION_ANGLE_FE0, rotation_angle, H_MIRROR_EN_FE0, (unsigned)horizontal_mirror, + PIX_SURFACE_LINEAR_FE0, surface_linear); +} + +void vpe20_cdc_program_crossbar_config(struct cdc_fe *cdc_fe, enum vpe_surface_pixel_format format) +{ + uint32_t alpha_bar = (uint32_t)MUX_SEL_ALPHA; + uint32_t green_bar = (uint32_t)MUX_SEL_Y_G; + uint32_t red_bar = (uint32_t)MUX_SEL_CR_R; + uint32_t blue_bar = (uint32_t)MUX_SEL_CB_B; + + PROGRAM_ENTRY(); + + if (format == VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 || + format == VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888 || + format == VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 || + format == VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F || + format == VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888 || + format == VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888 || + format == VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102 || + format == VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F || + format == VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbYCr || + format == VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CbYCrY || + format == VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbYCr || + format == VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CbYCrY || + format == VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbYCr || + format == VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CbYCrY || + format == VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 || + format == VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_UNORM || + format == VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_SNORM || + format == VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888) { + red_bar = MUX_SEL_CB_B; + blue_bar = MUX_SEL_CR_R; + } + + if (format == VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrCbYA8888) { + blue_bar = MUX_SEL_Y_G; + green_bar = MUX_SEL_CB_B; + } + REG_SET_4(VPCDC_FE0_CROSSBAR_CONFIG, 0, CROSSBAR_SRC_ALPHA_FE0, alpha_bar, + CROSSBAR_SRC_CR_R_FE0, red_bar, CROSSBAR_SRC_Y_G_FE0, green_bar, CROSSBAR_SRC_CB_B_FE0, + blue_bar); +} + +void vpe20_cdc_program_viewport( + struct cdc_fe *cdc_fe, const struct vpe_rect *viewport, const struct vpe_rect *viewport_c) +{ + + PROGRAM_ENTRY(); + + REG_SET_2(VPCDC_FE0_VIEWPORT_START_CONFIG, 0, VIEWPORT_X_START_FE0, viewport->x, + VIEWPORT_Y_START_FE0, viewport->y); + + REG_SET_2(VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG, 0, VIEWPORT_WIDTH_FE0, viewport->width, + VIEWPORT_HEIGHT_FE0, viewport->height); + + REG_SET_2(VPCDC_FE0_VIEWPORT_START_C_CONFIG, 0, VIEWPORT_X_START_C_FE0, viewport_c->x, + VIEWPORT_Y_START_C_FE0, viewport_c->y); + + REG_SET_2(VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG, 0, VIEWPORT_WIDTH_C_FE0, viewport_c->width, + VIEWPORT_HEIGHT_C_FE0, viewport_c->height); +} + +void vpe20_program_3dlut_fl_config( + struct cdc_fe *cdc_fe, enum lut_dimension lut_dimension, struct vpe_3dlut *lut_3d) +{ + PROGRAM_ENTRY(); + + REG_SET_5(VPCDC_3DLUT_FL_CONFIG, 0, + VPCDC_3DLUT_FL_CROSSBAR_SRC_G, lut_3d->dma_params.crossbar_g, + VPCDC_3DLUT_FL_CROSSBAR_SRC_B, lut_3d->dma_params.crossbar_b, + VPCDC_3DLUT_FL_CROSSBAR_SRC_R, lut_3d->dma_params.crossbar_r, + VPCDC_3DLUT_FL_MODE, lut_3d->dma_params.layout, + VPCDC_3DLUT_FL_SIZE, lut_dimension == LUT_DIM_33 ? 1 : 0); +} diff --git a/src/amd/vpelib/src/chip/vpe20/vpe20_cmd_builder.c b/src/amd/vpelib/src/chip/vpe20/vpe20_cmd_builder.c new file mode 100644 index 00000000000..d86b538f661 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/vpe20_cmd_builder.c @@ -0,0 +1,742 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include "vpe_assert.h" +#include "common.h" +#include "vpe_priv.h" +#include "vpe20_command.h" +#include "vpe20_plane_desc_writer.h" +#include "vpe10_cmd_builder.h" +#include "vpe20_cmd_builder.h" +#include "vpe20_resource.h" + +#define LOG_INPUT_PLANE 1 +#define LOG_OUTPUT_PLANE 0 + +static void get_np_and_subop(struct vpe_priv *vpe_priv, struct vpe_cmd_info *cmd_info, + struct vpe20_plane_desc_header *header); + +static enum VPE_PLANE_CFG_ELEMENT_SIZE vpe_get_element_size( + enum vpe_surface_pixel_format format, int plane_idx); + +static void log_plane_desc_event(struct vpe_priv *vpe_priv, struct vpe_cmd_info *cmd_info, + struct vpe20_plane_desc_header *header, struct vpe20_plane_desc_src *src, + struct vpe20_plane_desc_dst *dst, uint32_t cmd_idx, uint32_t io_idx, uint32_t plane_idx, + bool input_flag); + +void vpe20_construct_cmd_builder(struct vpe_priv *vpe_priv, struct cmd_builder *builder) +{ + builder->build_noops = vpe10_build_noops; + builder->build_vpe_cmd = vpe20_build_vpe_cmd; + builder->build_plane_descriptor = vpe20_build_plane_descriptor; +} + +enum vpe_status vpe20_build_vpe_cmd( + struct vpe_priv *vpe_priv, struct vpe_build_bufs *cur_bufs, uint32_t cmd_idx) +{ + struct cmd_builder *builder = &vpe_priv->resource.cmd_builder; + struct vpe_desc_writer *vpe_desc_writer = &vpe_priv->vpe_desc_writer; + struct vpe_buf *emb_buf = &cur_bufs->emb_buf; + struct output_ctx *output_ctx; + struct pipe_ctx *pipe_ctx = NULL; + uint32_t pipe_idx, config_idx; + struct vpe_vector *config_vector; + struct config_record *config; + struct vpe_cmd_info *cmd_info = vpe_vector_get(vpe_priv->vpe_cmd_vector, cmd_idx); + enum vpe_status status = VPE_STATUS_OK; + + VPE_ASSERT(cmd_info); + if (!cmd_info) + return VPE_STATUS_ERROR; + + vpe_desc_writer->init(vpe_desc_writer, &cur_bufs->cmd_buf, cmd_info->cd); + + // plane descriptor + builder->build_plane_descriptor(vpe_priv, emb_buf, cmd_idx); + + vpe_desc_writer->add_plane_desc( + vpe_desc_writer, vpe_priv->plane_desc_writer.base_gpu_va, (uint8_t)emb_buf->tmz); + + // reclaim any pipe if the owner no longer presents + vpe_pipe_reclaim(vpe_priv, cmd_info); + + config_writer_init(&vpe_priv->config_writer, emb_buf); + + vpe_priv->resource.reset_pipes(vpe_priv); + + /* 3D LUT FL programming */ + vpe_priv->resource.program_fastload(vpe_priv, cmd_idx); + + // frontend programming + for (pipe_idx = 0; pipe_idx < cmd_info->num_inputs; pipe_idx++) { + bool reuse; + struct stream_ctx *stream_ctx; + uint16_t stream_idx; + enum vpe_cmd_type cmd_type = VPE_CMD_TYPE_COUNT; + + // keep using the same pipe whenever possible + // this would allow reuse of the previous register configs + stream_idx = cmd_info->inputs[pipe_idx].stream_idx; + pipe_ctx = &vpe_priv->pipe_ctx[pipe_idx]; + + reuse = (pipe_ctx->owner == stream_idx); + VPE_ASSERT(pipe_ctx->owner == PIPE_CTX_NO_OWNER || pipe_ctx->owner == stream_idx); + pipe_ctx->owner = stream_idx; + stream_ctx = &vpe_priv->stream_ctx[cmd_info->inputs[pipe_idx].stream_idx]; + + if (!reuse) { + vpe_priv->resource.program_frontend( + vpe_priv, pipe_ctx->pipe_idx, cmd_idx, pipe_idx, false); + } else { + if (vpe_priv->init.debug.disable_reuse_bit) + reuse = false; + + // frame specific for same type of command + switch (cmd_info->ops) { + case VPE_CMD_OPS_BG: + cmd_type = VPE_CMD_TYPE_BG; + break; + case VPE_CMD_OPS_COMPOSITING: + cmd_type = VPE_CMD_TYPE_COMPOSITING; + break; + case VPE_CMD_OPS_BLENDING: + cmd_type = VPE_CMD_TYPE_BLENDING; + break; + case VPE_CMD_OPS_BG_VSCF_INPUT: + cmd_type = VPE_CMD_TYPE_BG_VSCF_INPUT; + break; + case VPE_CMD_OPS_BG_VSCF_OUTPUT: + cmd_type = VPE_CMD_TYPE_BG_VSCF_OUTPUT; + break; + case VPE_CMD_OPS_BG_VSCF_PIPE0: + cmd_type = VPE_CMD_TYPE_BG_VSCF_PIPE0; + break; + case VPE_CMD_OPS_BG_VSCF_PIPE1: + cmd_type = VPE_CMD_TYPE_BG_VSCF_PIPE1; + break; + case VPE_CMD_OPS_ALPHA_THROUGH_LUMA: + cmd_type = VPE_CMD_TYPE_ALPHA_THROUGH_LUMA; + break; + default: + VPE_ASSERT(0); + status = VPE_STATUS_ERROR; + break; + } + + // follow the same order of config generation in "non-reuse" case + // stream sharing + config_vector = stream_ctx->configs[pipe_idx]; + VPE_ASSERT(config_vector->num_elements); + for (config_idx = 0; config_idx < config_vector->num_elements; config_idx++) { + config = (struct config_record *)vpe_vector_get(config_vector, config_idx); + if (!config) { + status = VPE_STATUS_ERROR; + break; + } + + vpe_desc_writer->add_config_desc( + vpe_desc_writer, config->config_base_addr, reuse, (uint8_t)emb_buf->tmz); + } + + if (status != VPE_STATUS_OK) + break; + + // stream-op sharing + config_vector = stream_ctx->stream_op_configs[pipe_idx][cmd_type]; + for (config_idx = 0; config_idx < config_vector->num_elements; config_idx++) { + config = (struct config_record *)vpe_vector_get(config_vector, config_idx); + if (!config) { + status = VPE_STATUS_ERROR; + break; + } + + vpe_desc_writer->add_config_desc( + vpe_desc_writer, config->config_base_addr, false, (uint8_t)emb_buf->tmz); + } + + if (status != VPE_STATUS_OK) + break; + + // command specific + vpe_priv->resource.program_frontend( + vpe_priv, pipe_ctx->pipe_idx, cmd_idx, pipe_idx, true); + } + } + + // If config writer has been crashed due to buffer overflow + if ((status == VPE_STATUS_OK) && (vpe_priv->config_writer.status != VPE_STATUS_OK)) { + status = vpe_priv->config_writer.status; + } + + // Back End Programming + if (status == VPE_STATUS_OK) { + // backend programming + output_ctx = &vpe_priv->output_ctx; + + for (pipe_idx = 0; pipe_idx < cmd_info->num_outputs; pipe_idx++) { + config_vector = output_ctx->configs[pipe_idx]; + bool seg_only; + + if (!config_vector->num_elements) { + seg_only = false; + } else { + seg_only = true; + bool reuse = !vpe_priv->init.debug.disable_reuse_bit; + + // re-use output register configs + for (config_idx = 0; config_idx < config_vector->num_elements; config_idx++) { + config = (struct config_record *)vpe_vector_get( + output_ctx->configs[pipe_idx], config_idx); + if (!config) { + status = VPE_STATUS_ERROR; + break; + } + + vpe_desc_writer->add_config_desc( + vpe_desc_writer, config->config_base_addr, reuse, (uint8_t)emb_buf->tmz); + } + if (status != VPE_STATUS_OK) + break; + } + vpe_priv->resource.program_backend(vpe_priv, pipe_idx, cmd_idx, seg_only); + } + } + + // If config writer has been crashed due to buffer overflow + if ((status == VPE_STATUS_OK) && (vpe_priv->config_writer.status != VPE_STATUS_OK)) { + status = vpe_priv->config_writer.status; + } + + /* If writer crashed due to buffer overflow */ + if ((status == VPE_STATUS_OK) && (vpe_desc_writer->status != VPE_STATUS_OK)) { + status = vpe_desc_writer->status; + } + + if (status == VPE_STATUS_OK) { + vpe_desc_writer->complete(vpe_desc_writer); + } + + return status; +} + +enum vpe_status vpe20_build_plane_descriptor( + struct vpe_priv *vpe_priv, struct vpe_buf *buf, uint32_t cmd_idx) +{ + struct stream_ctx *stream_ctx; + struct vpe_surface_info *surface_info; + int32_t stream_idx; + struct vpe_cmd_info *cmd_info; + PHYSICAL_ADDRESS_LOC *addrloc; + PHYSICAL_ADDRESS_LOC addrhist; + struct vpe20_plane_desc_src src; + struct vpe20_plane_desc_dst dst; + + struct vpe20_plane_desc_header header = {0}; + struct cmd_builder *builder = &vpe_priv->resource.cmd_builder; + struct plane_desc_writer *plane_desc_writer = &vpe_priv->plane_desc_writer; + uint32_t viewport_divider = FROD_DOWNSAMPLING_RATIO; + const uint32_t hist_size = 1024; // 256 bins, each 4 bytes + uint32_t hist_dsets = 0; + uint32_t line_offset; + uint32_t num_pipes = 1; + uint32_t performance_mode_offset; + cmd_info = vpe_vector_get(vpe_priv->vpe_cmd_vector, cmd_idx); + VPE_ASSERT(plane_desc_writer); + VPE_ASSERT(cmd_info); + if (!cmd_info) + return VPE_STATUS_ERROR; + + VPE_ASSERT(cmd_info->num_inputs <= 2); + + // obtains number of planes for each source/destination stream + for (int i = 0; i < cmd_info->num_inputs; i++) { + stream_idx = cmd_info->inputs[i].stream_idx; + stream_ctx = &vpe_priv->stream_ctx[stream_idx]; + src.scan = stream_ctx->scan; + surface_info = &stream_ctx->stream.surface_info; + if (i == 0) + header.dcomp0 = surface_info->dcc.enable ? 1 : 0; + else if (i == 1) + header.dcomp1 = surface_info->dcc.enable ? 1 : 0; + } + + get_np_and_subop(vpe_priv, cmd_info, &header); + + if (cmd_info->frod_param.enable_frod) { + header.frod = 1; + } + + for (int i = 0; i < cmd_info->num_inputs; i++) { + stream_idx = cmd_info->inputs[i].stream_idx; + stream_ctx = &vpe_priv->stream_ctx[stream_idx]; + cmd_info->histo_dsets[i] = stream_ctx->stream.hist_params.hist_dsets; + if ((cmd_info->histo_dsets[i] > 0) && (cmd_info->histo_dsets[i] <= MAX_HISTO_SETS)) { + if (i == 0) { + header.hist0_dsets = (uint8_t)stream_ctx->stream.hist_params.hist_dsets; + } + else { + header.hist1_dsets = (uint8_t)stream_ctx->stream.hist_params.hist_dsets; + } + } + } + plane_desc_writer->init(&vpe_priv->plane_desc_writer, buf, &header); + + for (int i = 0; i < cmd_info->num_inputs && i < MAX_INPUT_PIPE; i++) { + struct dscl_prog_data* dscl_data = &cmd_info->inputs[i].scaler_data.dscl_prog_data; + + stream_idx = cmd_info->inputs[i].stream_idx; + stream_ctx = &vpe_priv->stream_ctx[stream_idx]; + surface_info = &stream_ctx->stream.surface_info; + + src.tmz = surface_info->address.tmz_surface; + src.swizzle = surface_info->swizzle; + src.scan = stream_ctx->scan; + src.format = 0; + + if (surface_info->address.type == VPE_PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) { + + addrloc = &surface_info->address.video_progressive.luma_addr; + + src.base_addr_lo = addrloc->u.low_part; + src.base_addr_hi = (uint32_t)addrloc->u.high_part; + src.pitch = (uint16_t)surface_info->plane_size.surface_pitch; + + addrloc = &surface_info->address.video_progressive.luma_meta_addr; + src.meta_base_addr_lo = addrloc->u.low_part; + src.meta_base_addr_hi = (uint32_t)addrloc->u.high_part; + src.meta_pitch = (uint16_t)surface_info->dcc.src.meta_pitch; + src.dcc_ind_blk = surface_info->dcc.src.dcc_ind_blk_c; + src.comp_mode = surface_info->dcc.enable; + + src.viewport_x = (uint16_t)dscl_data->viewport.x; + src.viewport_y = (uint16_t)dscl_data->viewport.y; + src.viewport_w = (uint16_t)dscl_data->viewport.width; + src.viewport_h = (uint16_t)dscl_data->viewport.height; + src.elem_size = (uint8_t)(vpe_get_element_size(surface_info->format, 0)); + if (vpe_is_yuv_packed(surface_info->format) && vpe_is_yuv422(surface_info->format)) { + if (dscl_data->viewport_c.x < (dscl_data->viewport.x / 2)) + src.viewport_x = (uint16_t)dscl_data->viewport_c.x; + else + src.viewport_x = (uint16_t)dscl_data->viewport.x / 2; + + if ((dscl_data->viewport_c.width * 2) > dscl_data->viewport.width) + src.viewport_w = (uint16_t)dscl_data->viewport_c.width; + else + src.viewport_w = (uint16_t)dscl_data->viewport.width / 2; + + src.pitch = (uint16_t)surface_info->plane_size.surface_pitch / 2; + } + + plane_desc_writer->add_source(&vpe_priv->plane_desc_writer, &src, true); + // log vpe event - plane0 + log_plane_desc_event( + vpe_priv, cmd_info, &header, &src, &dst, cmd_idx, i, 0, LOG_INPUT_PLANE); + + if (vpe_is_dual_plane_format(surface_info->format)) { + addrloc = &surface_info->address.video_progressive.chroma_addr; + + src.base_addr_lo = addrloc->u.low_part; + src.base_addr_hi = (uint32_t)addrloc->u.high_part; + src.pitch = (uint16_t)surface_info->plane_size.chroma_pitch; + + src.viewport_x = (uint16_t)dscl_data->viewport_c.x; + src.viewport_y = (uint16_t)dscl_data->viewport_c.y; + src.viewport_w = (uint16_t)dscl_data->viewport_c.width; + src.viewport_h = (uint16_t)dscl_data->viewport_c.height; + src.elem_size = (uint8_t)(vpe_get_element_size(surface_info->format, 1)); + + plane_desc_writer->add_source(&vpe_priv->plane_desc_writer, &src, false); + // log vpe event - plane1 + log_plane_desc_event( + vpe_priv, cmd_info, &header, &src, &dst, cmd_idx, i, 1, LOG_INPUT_PLANE); + } + } else if (surface_info->address.type == VPE_PLN_ADDR_TYPE_PLANAR) { + /* Planar Formats always packed into VPEC as: + PLane0 = Y_g + Plane1 = Cb_b + Plane2 = Cr_r + */ + + // assuming all planes have the same rect/pitch properties + src.viewport_x = (uint16_t)cmd_info->inputs[i].scaler_data.dscl_prog_data.viewport.x; + src.viewport_y = (uint16_t)cmd_info->inputs[i].scaler_data.dscl_prog_data.viewport.y; + src.viewport_w = + (uint16_t)cmd_info->inputs[i].scaler_data.dscl_prog_data.viewport.width; + src.viewport_h = + (uint16_t)cmd_info->inputs[i].scaler_data.dscl_prog_data.viewport.height; + src.elem_size = (uint8_t)(vpe_get_element_size(surface_info->format, 0)); + src.pitch = (uint16_t)surface_info->plane_size.surface_pitch; + + // Y_g + addrloc = &surface_info->address.planar.y_g_addr; + src.base_addr_lo = addrloc->u.low_part; + src.base_addr_hi = (uint32_t)addrloc->u.high_part; + plane_desc_writer->add_source(&vpe_priv->plane_desc_writer, &src, true); + // log vpe event - plane0 + log_plane_desc_event( + vpe_priv, cmd_info, &header, &src, &dst, cmd_idx, i, 0, LOG_INPUT_PLANE); + + // Cb_b + addrloc = &surface_info->address.planar.cb_b_addr; + src.base_addr_lo = addrloc->u.low_part; + src.base_addr_hi = (uint32_t)addrloc->u.high_part; + plane_desc_writer->add_source(&vpe_priv->plane_desc_writer, &src, false); + // log vpe event - plane1 + log_plane_desc_event( + vpe_priv, cmd_info, &header, &src, &dst, cmd_idx, i, 1, LOG_INPUT_PLANE); + + // Cr_r + addrloc = &surface_info->address.planar.cr_r_addr; + src.base_addr_lo = addrloc->u.low_part; + src.base_addr_hi = (uint32_t)addrloc->u.high_part; + plane_desc_writer->add_source(&vpe_priv->plane_desc_writer, &src, false); + // log vpe event - plane2 + log_plane_desc_event( + vpe_priv, cmd_info, &header, &src, &dst, cmd_idx, i, 2, LOG_INPUT_PLANE); + } else { + addrloc = &surface_info->address.grph.addr; + + src.base_addr_lo = addrloc->u.low_part; + src.base_addr_hi = (uint32_t)addrloc->u.high_part; + src.pitch = (uint16_t)surface_info->plane_size.surface_pitch; + + src.viewport_x = (uint16_t)dscl_data->viewport.x; + src.viewport_y = (uint16_t)dscl_data->viewport.y; + src.viewport_w = (uint16_t)dscl_data->viewport.width; + src.viewport_h = (uint16_t)dscl_data->viewport.height; + src.elem_size = (uint8_t)(vpe_get_element_size(surface_info->format, 0)); + + plane_desc_writer->add_source(&vpe_priv->plane_desc_writer, &src, true); + // log vpe event - plane0 + log_plane_desc_event( + vpe_priv, cmd_info, &header, &src, &dst, cmd_idx, i, 0, LOG_INPUT_PLANE); + } + } + + if (plane_desc_writer->add_meta && (header.dcomp0 || header.dcomp1)) { + for (int i = 0; i < cmd_info->num_inputs && i < MAX_INPUT_PIPE; i++) { + if ((header.dcomp0 && i == 0) || (header.dcomp1 && i == 1)) { + stream_idx = cmd_info->inputs[i].stream_idx; + stream_ctx = &vpe_priv->stream_ctx[stream_idx]; + surface_info = &stream_ctx->stream.surface_info; + addrloc = &surface_info->address.video_progressive.luma_meta_addr; + src.meta_base_addr_lo = addrloc->u.low_part; + src.meta_base_addr_hi = (uint32_t)addrloc->u.high_part; + src.meta_pitch = (uint16_t)surface_info->dcc.src.meta_pitch; + src.dcc_ind_blk = surface_info->dcc.src.dcc_ind_blk_c; + src.comp_mode = surface_info->dcc.enable; + src.format = vpe20_get_hw_surface_format(surface_info->format); + plane_desc_writer->add_meta(&vpe_priv->plane_desc_writer, &src); + } + } + } + + for (int i = 0; i < cmd_info->num_outputs && i < MAX_OUTPUT_PIPE; i++) { + surface_info = &vpe_priv->output_ctx.surface; + if ((cmd_info->frod_param.enable_frod) && (i > 0)) { + surface_info = &vpe_priv->output_ctx.frod_surface[i-1]; + vpe_priv->resource.set_frod_output_viewport(&cmd_info->outputs[i], + &cmd_info->outputs[0], viewport_divider, surface_info->format); + viewport_divider *= FROD_DOWNSAMPLING_RATIO; + } + if (surface_info->address.type == VPE_PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) { + addrloc = &surface_info->address.video_progressive.luma_addr; + dst.tmz = surface_info->address.tmz_surface; + dst.swizzle = surface_info->swizzle; + + dst.base_addr_lo = addrloc->u.low_part; + dst.base_addr_hi = (uint32_t)addrloc->u.high_part; + dst.pitch = (uint16_t)surface_info->plane_size.surface_pitch; + + dst.viewport_x = (uint16_t)cmd_info->outputs[i].dst_viewport.x; + dst.viewport_y = (uint16_t)cmd_info->outputs[i].dst_viewport.y; + dst.viewport_w = (uint16_t)cmd_info->outputs[i].dst_viewport.width; + dst.viewport_h = (uint16_t)cmd_info->outputs[i].dst_viewport.height; + dst.elem_size = (uint8_t)(vpe_get_element_size(surface_info->format, 0)); + if (vpe_is_yuv_packed(surface_info->format) && vpe_is_yuv422(surface_info->format)) { + dst.viewport_x = (uint16_t)cmd_info->outputs[i].dst_viewport.x / 2; + dst.viewport_w = (uint16_t)cmd_info->outputs[i].dst_viewport.width / 2; + dst.pitch = (uint16_t)surface_info->plane_size.surface_pitch / 2; + } + plane_desc_writer->add_destination(&vpe_priv->plane_desc_writer, &dst, true); + // log vpe event - plane0 + log_plane_desc_event( + vpe_priv, cmd_info, &header, &src, &dst, cmd_idx, i, 0, LOG_OUTPUT_PLANE); + if (vpe_is_dual_plane_format(surface_info->format)) { + addrloc = &surface_info->address.video_progressive.chroma_addr; + dst.tmz = surface_info->address.tmz_surface; + dst.swizzle = surface_info->swizzle; + + dst.base_addr_lo = addrloc->u.low_part; + dst.base_addr_hi = (uint32_t)addrloc->u.high_part; + dst.pitch = (uint16_t)surface_info->plane_size.chroma_pitch; + + dst.viewport_x = (uint16_t)cmd_info->outputs[i].dst_viewport_c.x; + dst.viewport_y = (uint16_t)cmd_info->outputs[i].dst_viewport_c.y; + dst.viewport_w = (uint16_t)cmd_info->outputs[i].dst_viewport_c.width; + dst.viewport_h = (uint16_t)cmd_info->outputs[i].dst_viewport_c.height; + dst.elem_size = (uint8_t)(vpe_get_element_size(surface_info->format, 1)); + + plane_desc_writer->add_destination(&vpe_priv->plane_desc_writer, &dst, false); + // log vpe event - plane1 + log_plane_desc_event( + vpe_priv, cmd_info, &header, &src, &dst, cmd_idx, i, 1, LOG_OUTPUT_PLANE); + } + } else if (surface_info->address.type == VPE_PLN_ADDR_TYPE_PLANAR) { + /* Planar Formats always packed as: + PLane0 = Y_g + Plane1 = Cb_b + Plane2 = Cr_r + */ + + // assuming all planes have the same rect/pitch/tmz/swizzle properties + dst.tmz = surface_info->address.tmz_surface; + dst.swizzle = surface_info->swizzle; + dst.viewport_x = (uint16_t)cmd_info->outputs[i].dst_viewport_c.x; + dst.viewport_y = (uint16_t)cmd_info->outputs[i].dst_viewport_c.y; + dst.viewport_w = (uint16_t)cmd_info->outputs[i].dst_viewport_c.width; + dst.viewport_h = (uint16_t)cmd_info->outputs[i].dst_viewport_c.height; + dst.elem_size = (uint8_t)(vpe_get_element_size(surface_info->format, 1)); + dst.pitch = (uint16_t)surface_info->plane_size.surface_pitch; + + // Y_g + addrloc = &surface_info->address.planar.y_g_addr; + dst.base_addr_lo = addrloc->u.low_part; + dst.base_addr_hi = (uint32_t)addrloc->u.high_part; + plane_desc_writer->add_destination(&vpe_priv->plane_desc_writer, &dst, true); + // log vpe event - plane0 + log_plane_desc_event( + vpe_priv, cmd_info, &header, &src, &dst, cmd_idx, i, 0, LOG_OUTPUT_PLANE); + + // Cb_b + addrloc = &surface_info->address.planar.cb_b_addr; + dst.base_addr_lo = addrloc->u.low_part; + dst.base_addr_hi = (uint32_t)addrloc->u.high_part; + plane_desc_writer->add_destination(&vpe_priv->plane_desc_writer, &dst, false); + // log vpe event - plane1 + log_plane_desc_event( + vpe_priv, cmd_info, &header, &src, &dst, cmd_idx, i, 1, LOG_OUTPUT_PLANE); + + // Cr_r + addrloc = &surface_info->address.planar.cr_r_addr; + dst.base_addr_lo = addrloc->u.low_part; + dst.base_addr_hi = (uint32_t)addrloc->u.high_part; + plane_desc_writer->add_destination(&vpe_priv->plane_desc_writer, &dst, false); + // log vpe event - plane2 + log_plane_desc_event( + vpe_priv, cmd_info, &header, &src, &dst, cmd_idx, i, 2, LOG_OUTPUT_PLANE); + } else { + addrloc = &surface_info->address.grph.addr; + dst.tmz = surface_info->address.tmz_surface; + dst.swizzle = surface_info->swizzle; + + dst.base_addr_lo = addrloc->u.low_part; + dst.base_addr_hi = (uint32_t)addrloc->u.high_part; + dst.pitch = (uint16_t)surface_info->plane_size.surface_pitch; + + dst.viewport_x = (uint16_t)cmd_info->outputs[i].dst_viewport.x; + dst.viewport_y = (uint16_t)cmd_info->outputs[i].dst_viewport.y; + dst.viewport_w = (uint16_t)cmd_info->outputs[i].dst_viewport.width; + dst.viewport_h = (uint16_t)cmd_info->outputs[i].dst_viewport.height; + dst.elem_size = (uint8_t)(vpe_get_element_size(surface_info->format, 0)); + + plane_desc_writer->add_destination(&vpe_priv->plane_desc_writer, &dst, true); + // log vpe event - plane0 + log_plane_desc_event( + vpe_priv, cmd_info, &header, &src, &dst, cmd_idx, i, 0, LOG_OUTPUT_PLANE); + } + } + + for (int i = 0; i < cmd_info->num_inputs && i < MAX_INPUT_PIPE; i++) { + if ((header.hist0_dsets > 0) || (header.hist1_dsets > 0)) { + stream_idx = cmd_info->inputs[i].stream_idx; + stream_ctx = &vpe_priv->stream_ctx[stream_idx]; + num_pipes = vpe_priv->resource.get_num_pipes_available(vpe_priv, stream_ctx); + hist_dsets = header.hist0_dsets; + if(i > 0) + hist_dsets = header.hist1_dsets; + for (uint32_t histIndex = 0; histIndex < hist_dsets; histIndex++) { + surface_info = &stream_ctx->stream.hist_params.hist_collection_param[histIndex].hist_output; + if ((surface_info != NULL) && + ((cmd_info->cd * num_pipes) < + surface_info->plane_size.surface_size + .height)) { // writing to valid address within surface + performance_mode_offset = (num_pipes > 1) ? i : 0; + line_offset = + hist_size * ((cmd_info->cd * num_pipes) + performance_mode_offset); + addrhist.quad_part = surface_info->address.video_progressive.luma_addr.quad_part; + addrhist.quad_part += line_offset; // count down value on segments + dst.base_addr_lo = addrhist.u.low_part; + dst.base_addr_hi = (uint32_t)addrhist.u.high_part; + plane_desc_writer->add_histo( + &vpe_priv->plane_desc_writer, &dst, histIndex, NULL); + } + } + } + } + return vpe_priv->plane_desc_writer.status; +} + +// Function logs plane descriptor information like number of planes, plane +// descriptor type, base address, pitch, viewport, swizzle, etc. to etw events +static void log_plane_desc_event(struct vpe_priv *vpe_priv, struct vpe_cmd_info *cmd_info, + struct vpe20_plane_desc_header *header, struct vpe20_plane_desc_src *src, + struct vpe20_plane_desc_dst *dst, uint32_t cmd_idx, uint32_t io_idx, uint32_t plane_idx, + bool input_flag) +{ + // check if event is for input or output plane + if (input_flag) { + vpe_event(VPE_EVENT_PLANE_DESC_INPUT, vpe_priv->pub.level, + vpe_priv->vpe_cmd_vector->num_elements, cmd_idx, cmd_info->num_inputs, io_idx, + (header->nps0 + 1), (header->nps1 + 1), 0, plane_idx, 0, 0, 0, src->base_addr_lo, + src->base_addr_hi, src->viewport_x, src->viewport_y, src->viewport_w, src->viewport_h, + src->swizzle, header->dcomp0, header->dcomp1); + } else { + vpe_event(VPE_EVENT_PLANE_DESC_OUTPUT, vpe_priv->pub.level, + vpe_priv->vpe_cmd_vector->num_elements, cmd_idx, cmd_info->num_outputs, io_idx, + (header->npd0 + 1), (header->npd1 + 1), plane_idx, dst->base_addr_lo, dst->base_addr_hi, + dst->viewport_x, dst->viewport_y, dst->viewport_w, dst->viewport_h, dst->swizzle); + } +} + +static void get_np_and_subop(struct vpe_priv *vpe_priv, struct vpe_cmd_info *cmd_info, + struct vpe20_plane_desc_header *header) +{ + + // Init second pipe src and destination plane count to 0 + header->nps1 = 0; + header->npd1 = 0; + + // Populate number of planes for source 0. + if (vpe_is_planar_format( + vpe_priv->stream_ctx[cmd_info->inputs[0].stream_idx].stream.surface_info.format)) + header->nps0 = VPE_PLANE_CFG_THREE_PLANES; + else if (vpe_is_dual_plane_format( + vpe_priv->stream_ctx[cmd_info->inputs[0].stream_idx].stream.surface_info.format)) + header->nps0 = VPE_PLANE_CFG_TWO_PLANES; + else + header->nps0 = VPE_PLANE_CFG_ONE_PLANE; + + // Populate number of planes for source 1 if it exists. + if (cmd_info->num_inputs == 2) { + if (vpe_is_planar_format( + vpe_priv->stream_ctx[cmd_info->inputs[1].stream_idx].stream.surface_info.format)) + header->nps1 = VPE_PLANE_CFG_THREE_PLANES; + else if (vpe_is_dual_plane_format(vpe_priv->stream_ctx[cmd_info->inputs[1].stream_idx] + .stream.surface_info.format)) + header->nps1 = VPE_PLANE_CFG_TWO_PLANES; + else + header->nps1 = VPE_PLANE_CFG_ONE_PLANE; + } + + // Populate number of planes for destination 0. + if (vpe_is_planar_format(vpe_priv->output_ctx.surface.format)) + header->npd0 = VPE_PLANE_CFG_THREE_PLANES; + else if (vpe_is_dual_plane_format(vpe_priv->output_ctx.surface.format)) + header->npd0 = VPE_PLANE_CFG_TWO_PLANES; + else + header->npd0 = VPE_PLANE_CFG_ONE_PLANE; + + // Populate number of planes for destination 1 if it exists. + if (cmd_info->num_outputs == 2) { + if (vpe_is_planar_format(vpe_priv->output_ctx.surface.format)) + header->npd1 = VPE_PLANE_CFG_THREE_PLANES; + else if (vpe_is_dual_plane_format(vpe_priv->output_ctx.surface.format)) + header->npd1 = VPE_PLANE_CFG_TWO_PLANES; + else + header->npd1 = VPE_PLANE_CFG_ONE_PLANE; + } + + /* + * Populate subop. + * Note: In the FROD case, num_outputs will be four but sub_op is expected to be x_TO_1 + */ + if (cmd_info->num_inputs == 1) + header->subop = VPE_PLANE_CFG_SUBOP_1_TO_1; + else if (cmd_info->num_outputs == 2) + header->subop = VPE_PLANE_CFG_SUBOP_2_TO_2; + else + header->subop = VPE_PLANE_CFG_SUBOP_2_TO_1; +} + +static enum VPE_PLANE_CFG_ELEMENT_SIZE vpe_get_element_size( + enum vpe_surface_pixel_format format, int plane_idx) +{ + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_GRPH_R8: /* Monochrome 8BPE (R8)*/ + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_RGB: /* Planar RGB 8BPE */ + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_YCbCr: /* Planar YCbCr 8BPE */ + return VPE_PLANE_CFG_ELEMENT_SIZE_8BPE; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: /* Semi-Planar 420 8BPE (NV12 + NV12) */ + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrCb: /* Semi-Planar 422 8BPE (YUY2)*/ + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ALPHA_THRU_LUMA: + if (plane_idx == 0) + return VPE_PLANE_CFG_ELEMENT_SIZE_8BPE; + else + return VPE_PLANE_CFG_ELEMENT_SIZE_16BPE; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: /* Semi-Planar 420 (P010 & P016) */ + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrCb: /* Semi-Planar 422 16BPE (Y210, Y216) */ + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbCr: + if (plane_idx == 0) + return VPE_PLANE_CFG_ELEMENT_SIZE_16BPE; + else + return VPE_PLANE_CFG_ELEMENT_SIZE_32BPE; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_R16: /* Monochrome 16BPE (R16)*/ + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB: /* Planar RGB 16BPE */ + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_YCbCr: /* Planar YCbCr 16BPE */ + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB_FLOAT: /* Planar FP16 */ + return VPE_PLANE_CFG_ELEMENT_SIZE_16BPE; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrYCb: /* Packed 422 16BPE (Y210, Y216) */ + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CbYCrY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CbYCrY: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: /* RGB 16BPE */ + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_UNORM: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616_UNORM: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_SNORM: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616_SNORM: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb12121212: /* Packed YUV444 16BPE (Y416) */ + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA12121212: + return VPE_PLANE_CFG_ELEMENT_SIZE_64BPE; + default: + break; + } + return VPE_PLANE_CFG_ELEMENT_SIZE_32BPE; +} diff --git a/src/amd/vpelib/src/chip/vpe20/vpe20_config_writer.c b/src/amd/vpelib/src/chip/vpe20/vpe20_config_writer.c new file mode 100644 index 00000000000..dcae26b7157 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/vpe20_config_writer.c @@ -0,0 +1,29 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include "vpe20_config_writer.h" + +void vpe20_config_writer_init(struct config_writer *writer) +{ + writer->gpu_addr_alignment = 0x3F; +} diff --git a/src/amd/vpelib/src/chip/vpe20/vpe20_dpp.c b/src/amd/vpelib/src/chip/vpe20/vpe20_dpp.c new file mode 100644 index 00000000000..01f24707b9a --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/vpe20_dpp.c @@ -0,0 +1,351 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include +#include "common.h" +#include "vpe_priv.h" +#include "vpe10_dpp.h" +#include "vpe20_dpp.h" +#include "color.h" +#include "hw_shared.h" +#include "reg_helper.h" + +#define CTX_BASE dpp +#define CTX vpe20_dpp + +static struct dpp_funcs vpe20_dpp_funcs = { + .enable_clocks = vpe20_dpp_enable_clocks, + + // cnv + .program_cnv = vpe20_dpp_program_cnv, + .program_pre_dgam = vpe10_dpp_cnv_program_pre_dgam, + .program_cnv_bias_scale = vpe10_dpp_program_cnv_bias_scale, + .build_keyer_params = vpe10_dpp_build_keyer_params, + .program_alpha_keyer = vpe20_dpp_cnv_program_alpha_keyer, + .program_crc = vpe10_dpp_program_crc, + + // cm + .program_input_transfer_func = vpe20_dpp_program_input_transfer_func, + .program_gamut_remap = NULL, + .program_post_csc = vpe10_dpp_program_post_csc, + .set_hdr_multiplier = vpe10_dpp_set_hdr_multiplier, + .program_histogram = vpe20_dpp_program_histo, + // scaler + .get_optimal_number_of_taps = vpe10_dpp_get_optimal_number_of_taps, + .dscl_calc_lb_num_partitions = vpe10_dscl_calc_lb_num_partitions, + .set_segment_scaler = vpe20_dpp_set_segment_scaler, + .dscl_set_scaler_position = vpe20_dpp_dscl_set_scaler_position, + .set_frame_scaler = vpe20_dpp_set_frame_scaler, + .get_line_buffer_size = vpe10_get_line_buffer_size, + .validate_number_of_taps = vpe10_dpp_validate_number_of_taps, + + .dscl_program_easf = vpe20_dscl_program_easf, + .dscl_disable_easf = vpe20_dscl_disable_easf, + .dscl_program_isharp = vpe20_dscl_program_isharp, +}; + +void vpe20_construct_dpp(struct vpe_priv *vpe_priv, struct dpp *dpp) +{ + dpp->vpe_priv = vpe_priv; + dpp->funcs = &vpe20_dpp_funcs; +} + +/* Not used as we do not have special 2bit LUT currently + * Can skip for optimize performance and use default val + */ +static void vpe20_dpp_program_alpha_2bit_lut( + struct dpp *dpp, struct cnv_alpha_2bit_lut *alpha_2bit_lut) +{ + PROGRAM_ENTRY(); + + if (alpha_2bit_lut != NULL) { + REG_SET_2(VPCNVC_ALPHA_2BIT_LUT01, 0, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0, + ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); + REG_SET_2(VPCNVC_ALPHA_2BIT_LUT23, 0, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2, + ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3); + } else { // restore to default + REG_SET_DEFAULT(VPCNVC_ALPHA_2BIT_LUT01); + REG_SET_DEFAULT(VPCNVC_ALPHA_2BIT_LUT23); + } +} + +void vpe20_dpp_enable_clocks(struct dpp *dpp, bool enable) +{ + PROGRAM_ENTRY(); + + REG_SET(VPDPP_CONTROL, REG_DEFAULT(VPDPP_CONTROL), VPECLK_G_GATE_DISABLE, enable); +} + +void vpe20_dpp_cnv_program_alpha_keyer(struct dpp *dpp, const struct cnv_keyer_params *keyer_params) +{ + PROGRAM_ENTRY(); + + if (keyer_params->keyer_en) { + uint8_t keyer_mode = 0; + + switch (keyer_params->keyer_mode) { + case VPE_KEYER_MODE_FORCE_00: + keyer_mode = 0; + break; + case VPE_KEYER_MODE_FORCE_FF: + keyer_mode = 1; + break; + case VPE_KEYER_MODE_RANGE_FF: + keyer_mode = 2; + break; + case VPE_KEYER_MODE_RANGE_00: + default: + keyer_mode = 3; + break; + } + + if (!keyer_params->is_color_key) { // Luma Keying + REG_SET_3(VPCNVC_COLOR_KEYER_CONTROL, 0, COLOR_KEYER_EN, 0, LUMA_KEYER_EN, 1, + COLOR_KEYER_MODE, keyer_mode); + REG_SET_2(VPCNVC_COLOR_KEYER_GREEN, 0, COLOR_KEYER_GREEN_LOW, + keyer_params->luma_keyer.lower_luma_bound, COLOR_KEYER_GREEN_HIGH, + keyer_params->luma_keyer.upper_luma_bound); + } else { // Color Keying + REG_SET_3(VPCNVC_COLOR_KEYER_CONTROL, 0, COLOR_KEYER_EN, 1, LUMA_KEYER_EN, 0, + COLOR_KEYER_MODE, keyer_mode); + REG_SET_2(VPCNVC_COLOR_KEYER_GREEN, 0, COLOR_KEYER_GREEN_LOW, + keyer_params->color_keyer.color_keyer_green_low, COLOR_KEYER_GREEN_HIGH, + keyer_params->color_keyer.color_keyer_green_high); + REG_SET_2(VPCNVC_COLOR_KEYER_BLUE, 0, COLOR_KEYER_BLUE_LOW, + keyer_params->color_keyer.color_keyer_blue_low, COLOR_KEYER_BLUE_HIGH, + keyer_params->color_keyer.color_keyer_blue_high); + REG_SET_2(VPCNVC_COLOR_KEYER_RED, 0, COLOR_KEYER_RED_LOW, + keyer_params->color_keyer.color_keyer_red_low, COLOR_KEYER_RED_HIGH, + keyer_params->color_keyer.color_keyer_red_high); + REG_SET_2(VPCNVC_COLOR_KEYER_ALPHA, 0, COLOR_KEYER_ALPHA_LOW, + keyer_params->color_keyer.color_keyer_alpha_low, COLOR_KEYER_ALPHA_HIGH, + keyer_params->color_keyer.color_keyer_alpha_high); + } + } else { + REG_SET_DEFAULT(VPCNVC_COLOR_KEYER_CONTROL); + } +} + +void vpe20_dpp_program_cnv( + struct dpp *dpp, enum vpe_surface_pixel_format format, enum vpe_expansion_mode mode) +{ + uint32_t alpha_en = 1; + uint32_t pixel_format = 0; + uint32_t hw_expansion_mode = 0; + + PROGRAM_ENTRY(); + + switch (mode) { + case VPE_EXPANSION_MODE_DYNAMIC: + hw_expansion_mode = 0; + break; + case VPE_EXPANSION_MODE_ZERO: + hw_expansion_mode = 1; + break; + default: + VPE_ASSERT(0); + break; + } + + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XRGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888: + pixel_format = 8; + alpha_en = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: + pixel_format = 8; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_RGB: + pixel_format = 9; + alpha_en = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888: + pixel_format = 9; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: + pixel_format = 10; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102: + pixel_format = 11; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrCb: + pixel_format = 64; + alpha_en = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbCr: + pixel_format = 65; + alpha_en = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrCb: + pixel_format = 66; + alpha_en = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbCr: + pixel_format = 67; + alpha_en = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /* use crossbar */ + pixel_format = 20; + break; + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB: + pixel_format = 21; + alpha_en = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616: + pixel_format = 21; + break; + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB_FLOAT: + pixel_format = 24; + alpha_en = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: /* FP16 */ + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: /* used crossbar */ + pixel_format = 24; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F: /* FP16 */ + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F: /* used crossbar */ + pixel_format = 25; + break; + + // VPE 2.0 Supported Modes + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888: /* used crossbar */ + pixel_format = 12; + break; + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_YCbCr: + pixel_format = 13; + alpha_en = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_YCrCbA8888: + pixel_format = 13; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb8888: + pixel_format = 14; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrCbYA8888: + pixel_format = 15; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616_UNORM: + pixel_format = 26; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_UNORM: + pixel_format = 27; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_SNORM: + pixel_format = 28; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616_SNORM: + pixel_format = 29; + break; + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_YCbCr: + pixel_format = 42; + alpha_en = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb12121212: /* Y416 */ + pixel_format = 44; /* 12 bit slice MSB */ + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA12121212: + pixel_format = 46; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCrCb: /* P016 */ + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrCb: /* P216 */ + pixel_format = 68; + alpha_en = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCbCr: /* P016 */ + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbCr: /* P216 */ + pixel_format = 69; + alpha_en = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ALPHA_THRU_LUMA: + pixel_format = 70; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrYCb: /* YUY12 */ + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbYCr: /* used crossbar */ + pixel_format = 72; + alpha_en = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CrYCbY: /* YUY12 */ + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CbYCrY: /* used crossbar */ + pixel_format = 74; + alpha_en = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrYCb: /* Y210 */ + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbYCr: /* used crossbar */ + pixel_format = 76; + alpha_en = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CrYCbY: /* Y210 */ + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CbYCrY: /* used crossbar */ + pixel_format = 78; + alpha_en = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbYCr: /* used crossbar */ + pixel_format = 80; + alpha_en = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CrYCbY: /* Y216 */ + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CbYCrY: // use crossbar + pixel_format = 82; + alpha_en = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: /* Y410 */ + pixel_format = 114; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102: /* Y410 */ + pixel_format = 115; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_R8: // use crossbar + pixel_format = 120; + alpha_en = 0; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_R16: // use crossbar + pixel_format = 125; + alpha_en = 0; + break; + default: + break; + } + + REG_SET(VPCNVC_SURFACE_PIXEL_FORMAT, 0, VPCNVC_SURFACE_PIXEL_FORMAT, pixel_format); + REG_SET_7(VPCNVC_FORMAT_CONTROL, REG_DEFAULT(VPCNVC_FORMAT_CONTROL), FORMAT_EXPANSION_MODE, + hw_expansion_mode, FORMAT_CNV16, 0, FORMAT_CONTROL__ALPHA_EN, alpha_en, VPCNVC_BYPASS, + dpp->vpe_priv->init.debug.vpcnvc_bypass, VPCNVC_BYPASS_MSB_ALIGN, 0, CLAMP_POSITIVE, 0, + CLAMP_POSITIVE_C, 0); +} + diff --git a/src/amd/vpelib/src/chip/vpe20/vpe20_dpp_cm.c b/src/amd/vpelib/src/chip/vpe20/vpe20_dpp_cm.c new file mode 100644 index 00000000000..a45b50e733c --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/vpe20_dpp_cm.c @@ -0,0 +1,173 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "vpe_priv.h" +#include "reg_helper.h" +#include "vpe10/inc/vpe10_cm_common.h" +#include "vpe20/inc/vpe20_cm_common.h" +#include "vpe10_dpp.h" +#include "vpe20_dpp.h" +#include "custom_float.h" +#include "fixed31_32.h" +#include "conversion.h" + +#define CTX vpe20_dpp +#define CTX_BASE dpp + + +enum histo_xbar { + select_R_Cr_Max = 0, + select_G_Luma, + select_B_Cb_Min +}; + +#define HIST_SRC1_SET_MAX 1 +#define HIST_SRC2_SET_LUMA 1 +#define HIST_SRC3_SET_MIN 1 + +void vpe20_dpp_program_input_transfer_func(struct dpp *dpp, struct transfer_func *input_tf) +{ + struct pwl_params *params = NULL; + + PROGRAM_ENTRY(); + + struct stream_ctx *stream_ctx = &vpe_priv->stream_ctx[vpe_priv->fe_cb_ctx.stream_idx]; + bool bypass; + + VPE_ASSERT(input_tf); + // There should always have input_tf + // Only accept either DISTRIBUTED_POINTS or BYPASS + // No support for PREDEFINED case + VPE_ASSERT(input_tf->type == TF_TYPE_DISTRIBUTED_POINTS || input_tf->type == TF_TYPE_BYPASS); + + // VPE always do NL scaling using gamcor, thus skipping dgam (default bypass) + // dpp->funcs->program_pre_dgam(dpp, tf); + if (input_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { + vpe10_cm_helper_translate_curve_to_degamma_hw_format(input_tf, &dpp->degamma_params, input_tf->dirty[dpp->inst]); + params = &dpp->degamma_params; + } + + bypass = ((input_tf->type == TF_TYPE_BYPASS) || dpp->vpe_priv->init.debug.bypass_gamcor); + + CONFIG_CACHE(input_tf, stream_ctx, vpe_priv->init.debug.disable_lut_caching, bypass, + vpe10_dpp_program_gamcor_lut(dpp, params), dpp->inst); +} + +static bool calculate_hist_rgb_luma_coeffs(uint32_t * rgbcoff_reg, enum color_space cs) +{ + struct fixed31_32 rgb_luma_coeffs[3] = { 0 }; + struct custom_float_format const vpefmt = { 12, 6, false }; + switch (cs) { + case COLOR_SPACE_RGB601: + case COLOR_SPACE_RGB601_LIMITED: + rgb_luma_coeffs[0] = vpe_convfix31_32(vpe_output_full_csc_matrix_fixed[1].regval[4]); + rgb_luma_coeffs[1] = vpe_convfix31_32(vpe_output_full_csc_matrix_fixed[1].regval[5]); + rgb_luma_coeffs[2] = vpe_convfix31_32(vpe_output_full_csc_matrix_fixed[1].regval[6]); + break; + case COLOR_SPACE_SRGB: + rgb_luma_coeffs[0] = vpe_convfix31_32(vpe_output_full_csc_matrix_fixed[2].regval[4]); + rgb_luma_coeffs[1] = vpe_convfix31_32(vpe_output_full_csc_matrix_fixed[2].regval[5]); + rgb_luma_coeffs[2] = vpe_convfix31_32(vpe_output_full_csc_matrix_fixed[2].regval[6]); + break; + case COLOR_SPACE_2020_RGB_FULLRANGE: + case COLOR_SPACE_2020_RGB_LIMITEDRANGE: + rgb_luma_coeffs[0] = vpe_convfix31_32(vpe_output_full_csc_matrix_fixed[3].regval[4]); + rgb_luma_coeffs[1] = vpe_convfix31_32(vpe_output_full_csc_matrix_fixed[3].regval[5]); + rgb_luma_coeffs[2] = vpe_convfix31_32(vpe_output_full_csc_matrix_fixed[3].regval[6]); + break; + default: + return false; + break; + } + if( (vpe_convert_to_custom_float_format(rgb_luma_coeffs[0], &vpefmt, &rgbcoff_reg[0])) && + (vpe_convert_to_custom_float_format(rgb_luma_coeffs[1], &vpefmt, &rgbcoff_reg[1])) && + (vpe_convert_to_custom_float_format(rgb_luma_coeffs[2], &vpefmt, &rgbcoff_reg[2]))) { + return true; + } + return false; +} + +void vpe20_dpp_program_histo(struct dpp* dpp, struct vpe_histogram_param* hist_param, enum color_space cs) +{ + uint32_t hist_chan_mask = 0; + uint32_t hist_chan_en = 0; + uint32_t reg_xbar[hist_max_channel] = { 0 }; + uint32_t reg_src_sel[hist_max_channel] = { 0 }; + uint32_t rgbcoff_reg[3] = { 0 }; + const uint32_t tapPoint = 0; + enum hist_channels hist_crt_channel; + bool rgb_luma_transform = false; + + PROGRAM_ENTRY(); + + for (hist_crt_channel = hist_channel1; hist_crt_channel < hist_max_channel; hist_crt_channel++) { + if (hist_param->hist_collection_param[hist_crt_channel].hist_types != VPE_HISTOGRAM_NONE) { + hist_chan_mask |= 1 << hist_crt_channel; + hist_chan_en++; + switch (hist_param->hist_collection_param[hist_crt_channel].hist_types) { + case VPE_HISTOGRAM_MAX_RGB_YCbCr: + reg_xbar[hist_crt_channel] = select_R_Cr_Max; + reg_src_sel[hist_channel1] = HIST_SRC1_SET_MAX; + break; + case VPE_HISTOGRAM_G_Y: + reg_xbar[hist_crt_channel] = select_G_Luma; + break; + case VPE_HISTOGRAM_RGB_TRANSFORMED_Y: + reg_xbar[hist_crt_channel] = select_G_Luma; + reg_src_sel[hist_channel2] = HIST_SRC2_SET_LUMA; + rgb_luma_transform = true; + break; + case VPE_HISTOGRAM_B_CB: + reg_xbar[hist_crt_channel] = select_B_Cb_Min; + break; + case VPE_HISTOGRAM_MIN_RGB_YCbCr: + reg_xbar[hist_crt_channel] = select_B_Cb_Min; + reg_src_sel[hist_channel3] = HIST_SRC3_SET_MIN; + break; + default: + break; + } + } + } + + if ( (rgb_luma_transform) && + (calculate_hist_rgb_luma_coeffs(rgbcoff_reg, cs))) { + REG_SET(VPCM_HIST_COEFA_SRC2, REG_DEFAULT(VPCM_HIST_COEFA_SRC2), VPCM_HIST_COEFA_SRC2, rgbcoff_reg[0]); + REG_SET(VPCM_HIST_COEFB_SRC2, REG_DEFAULT(VPCM_HIST_COEFB_SRC2), VPCM_HIST_COEFB_SRC2, rgbcoff_reg[1]); + REG_SET(VPCM_HIST_COEFC_SRC2, REG_DEFAULT(VPCM_HIST_COEFC_SRC2), VPCM_HIST_COEFC_SRC2, rgbcoff_reg[2]); + } + + REG_SET_10(VPCM_HIST_CNTL, REG_DEFAULT(VPCM_HIST_CNTL), + VPCM_HIST_SEL, (uint32_t)tapPoint, + VPCM_HIST_CH_EN, (uint32_t)hist_chan_en, + VPCM_HIST_CH1_XBAR, (uint32_t)reg_xbar[hist_channel1], + VPCM_HIST_CH2_XBAR, (uint32_t)reg_xbar[hist_channel2], + VPCM_HIST_CH3_XBAR, (uint32_t)reg_xbar[hist_channel3], + VPCM_HIST_FORMAT, (uint32_t)hist_param->hist_format, + VPCM_HIST_SRC1_SEL, (uint32_t)reg_src_sel[hist_channel1], + VPCM_HIST_SRC2_SEL, (uint32_t)reg_src_sel[hist_channel2], + VPCM_HIST_SRC3_SEL, (uint32_t)reg_src_sel[hist_channel3], + VPCM_HIST_READ_CHANNEL_MASK, (uint32_t)hist_chan_mask); + +} diff --git a/src/amd/vpelib/src/chip/vpe20/vpe20_dpp_dscl.c b/src/amd/vpelib/src/chip/vpe20/vpe20_dpp_dscl.c new file mode 100644 index 00000000000..67006a115ab --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/vpe20_dpp_dscl.c @@ -0,0 +1,566 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "vpe_priv.h" +#include "vpe20_dpp.h" + +#define CTX vpe20_dpp +#define CTX_BASE dpp + +#define LB_MAX_PARTITION 12 +#define NUM_PHASES 64 +#define NUM_ISHARP_LEVELS 32 + +enum vpe10_dscl_mode_sel vpe20_dpp_dscl_get_dscl_mode(const struct scaler_data *data) +{ + return (enum vpe10_dscl_mode_sel)data->dscl_prog_data.dscl_mode; +} + +/** + * vpe20_dscl_program_easf - Program EASF + * + * This is the primary function to program EASF + * + */ +void vpe20_dscl_program_easf(struct dpp *dpp, const struct scaler_data *scl_data) +{ + PROGRAM_ENTRY(); + + REG_SET_2(VPDSCL_SC_MODE, REG_DEFAULT(VPDSCL_SC_MODE), + SCL_SC_MATRIX_MODE, scl_data->dscl_prog_data.easf_matrix_mode, + SCL_SC_LTONL_EN, scl_data->dscl_prog_data.easf_ltonl_en); + /* DSCL_EASF_V_MODE */ + REG_SET_3(VPDSCL_EASF_V_MODE, REG_DEFAULT(VPDSCL_EASF_V_MODE), + SCL_EASF_V_EN, scl_data->dscl_prog_data.easf_v_en, + SCL_EASF_V_2TAP_SHARP_FACTOR, scl_data->dscl_prog_data.easf_v_sharp_factor, + SCL_EASF_V_RINGEST_FORCE_EN, scl_data->dscl_prog_data.easf_v_ring); + REG_SET_6(VPDSCL_EASF_V_BF_CNTL, REG_DEFAULT(VPDSCL_EASF_V_BF_CNTL), + SCL_EASF_V_BF1_EN, scl_data->dscl_prog_data.easf_v_bf1_en, + SCL_EASF_V_BF2_MODE, scl_data->dscl_prog_data.easf_v_bf2_mode, + SCL_EASF_V_BF3_MODE, scl_data->dscl_prog_data.easf_v_bf3_mode, + SCL_EASF_V_BF2_FLAT1_GAIN, scl_data->dscl_prog_data.easf_v_bf2_flat1_gain, + SCL_EASF_V_BF2_FLAT2_GAIN, scl_data->dscl_prog_data.easf_v_bf2_flat2_gain, + SCL_EASF_V_BF2_ROC_GAIN, scl_data->dscl_prog_data.easf_v_bf2_roc_gain); + REG_SET_2(VPDSCL_EASF_V_RINGEST_3TAP_CNTL1, REG_DEFAULT(VPDSCL_EASF_V_RINGEST_3TAP_CNTL1), + SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT, scl_data->dscl_prog_data.easf_v_ringest_3tap_dntilt_uptilt, + SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt_max); + REG_SET_2(VPDSCL_EASF_V_RINGEST_3TAP_CNTL2, REG_DEFAULT(VPDSCL_EASF_V_RINGEST_3TAP_CNTL2), + SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE, scl_data->dscl_prog_data.easf_v_ringest_3tap_dntilt_slope, + SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt1_slope); + REG_SET_2(VPDSCL_EASF_V_RINGEST_3TAP_CNTL3, REG_DEFAULT(VPDSCL_EASF_V_RINGEST_3TAP_CNTL3), + SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt2_slope, + SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt2_offset); + REG_SET_2(VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE, REG_DEFAULT(VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE), + SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1, scl_data->dscl_prog_data.easf_v_ringest_eventap_reduceg1, + SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2, scl_data->dscl_prog_data.easf_v_ringest_eventap_reduceg2); + REG_SET_2(VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN, REG_DEFAULT(VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN), + SCL_EASF_V_RINGEST_EVENTAP_GAIN1, scl_data->dscl_prog_data.easf_v_ringest_eventap_gain1, + SCL_EASF_V_RINGEST_EVENTAP_GAIN2, scl_data->dscl_prog_data.easf_v_ringest_eventap_gain2); + REG_SET_4(VPDSCL_EASF_V_BF_FINAL_MAX_MIN, REG_DEFAULT(VPDSCL_EASF_V_BF_FINAL_MAX_MIN), + SCL_EASF_V_BF_MAXA, scl_data->dscl_prog_data.easf_v_bf_maxa, + SCL_EASF_V_BF_MAXB, scl_data->dscl_prog_data.easf_v_bf_maxb, + SCL_EASF_V_BF_MINA, scl_data->dscl_prog_data.easf_v_bf_mina, + SCL_EASF_V_BF_MINB, scl_data->dscl_prog_data.easf_v_bf_minb); + REG_SET_3(VPDSCL_EASF_V_BF1_PWL_SEG0, REG_DEFAULT(VPDSCL_EASF_V_BF1_PWL_SEG0), + SCL_EASF_V_BF1_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg0, + SCL_EASF_V_BF1_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg0, + SCL_EASF_V_BF1_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg0); + REG_SET_3(VPDSCL_EASF_V_BF1_PWL_SEG1, REG_DEFAULT(VPDSCL_EASF_V_BF1_PWL_SEG1), + SCL_EASF_V_BF1_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg1, + SCL_EASF_V_BF1_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg1, + SCL_EASF_V_BF1_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg1); + REG_SET_3(VPDSCL_EASF_V_BF1_PWL_SEG2, REG_DEFAULT(VPDSCL_EASF_V_BF1_PWL_SEG2), + SCL_EASF_V_BF1_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg2, + SCL_EASF_V_BF1_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg2, + SCL_EASF_V_BF1_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg2); + REG_SET_3(VPDSCL_EASF_V_BF1_PWL_SEG3, REG_DEFAULT(VPDSCL_EASF_V_BF1_PWL_SEG3), + SCL_EASF_V_BF1_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg3, + SCL_EASF_V_BF1_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg3, + SCL_EASF_V_BF1_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg3); + REG_SET_3(VPDSCL_EASF_V_BF1_PWL_SEG4, REG_DEFAULT(VPDSCL_EASF_V_BF1_PWL_SEG4), + SCL_EASF_V_BF1_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg4, + SCL_EASF_V_BF1_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg4, + SCL_EASF_V_BF1_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg4); + REG_SET_3(VPDSCL_EASF_V_BF1_PWL_SEG5, REG_DEFAULT(VPDSCL_EASF_V_BF1_PWL_SEG5), + SCL_EASF_V_BF1_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg5, + SCL_EASF_V_BF1_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg5, + SCL_EASF_V_BF1_PWL_SLOPE_SEG5, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg5); + REG_SET_3(VPDSCL_EASF_V_BF1_PWL_SEG6, REG_DEFAULT(VPDSCL_EASF_V_BF1_PWL_SEG6), + SCL_EASF_V_BF1_PWL_IN_SEG6, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg6, + SCL_EASF_V_BF1_PWL_BASE_SEG6, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg6, + SCL_EASF_V_BF1_PWL_SLOPE_SEG6, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg6); + REG_SET_2(VPDSCL_EASF_V_BF1_PWL_SEG7, REG_DEFAULT(VPDSCL_EASF_V_BF1_PWL_SEG7), + SCL_EASF_V_BF1_PWL_IN_SEG7, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg7, + SCL_EASF_V_BF1_PWL_BASE_SEG7, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg7); + REG_SET_3(VPDSCL_EASF_V_BF3_PWL_SEG0, REG_DEFAULT(VPDSCL_EASF_V_BF3_PWL_SEG0), + SCL_EASF_V_BF3_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set0, + SCL_EASF_V_BF3_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set0, + SCL_EASF_V_BF3_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set0); + REG_SET_3(VPDSCL_EASF_V_BF3_PWL_SEG1, REG_DEFAULT(VPDSCL_EASF_V_BF3_PWL_SEG1), + SCL_EASF_V_BF3_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set1, + SCL_EASF_V_BF3_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set1, + SCL_EASF_V_BF3_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set1); + REG_SET_3(VPDSCL_EASF_V_BF3_PWL_SEG2, REG_DEFAULT(VPDSCL_EASF_V_BF3_PWL_SEG2), + SCL_EASF_V_BF3_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set2, + SCL_EASF_V_BF3_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set2, + SCL_EASF_V_BF3_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set2); + REG_SET_3(VPDSCL_EASF_V_BF3_PWL_SEG3, REG_DEFAULT(VPDSCL_EASF_V_BF3_PWL_SEG3), + SCL_EASF_V_BF3_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set3, + SCL_EASF_V_BF3_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set3, + SCL_EASF_V_BF3_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set3); + REG_SET_3(VPDSCL_EASF_V_BF3_PWL_SEG4, REG_DEFAULT(VPDSCL_EASF_V_BF3_PWL_SEG4), + SCL_EASF_V_BF3_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set4, + SCL_EASF_V_BF3_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set4, + SCL_EASF_V_BF3_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set4); + REG_SET_2(VPDSCL_EASF_V_BF3_PWL_SEG5, REG_DEFAULT(VPDSCL_EASF_V_BF3_PWL_SEG5), + SCL_EASF_V_BF3_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set5, + SCL_EASF_V_BF3_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set5); + /* DSCL_EASF_H_MODE */ + REG_SET_3(VPDSCL_EASF_H_MODE, REG_DEFAULT(VPDSCL_EASF_H_MODE), + SCL_EASF_H_EN, scl_data->dscl_prog_data.easf_h_en, + SCL_EASF_H_2TAP_SHARP_FACTOR, scl_data->dscl_prog_data.easf_h_sharp_factor, + SCL_EASF_H_RINGEST_FORCE_EN, scl_data->dscl_prog_data.easf_h_ring); + REG_SET_6(VPDSCL_EASF_H_BF_CNTL, REG_DEFAULT(VPDSCL_EASF_H_BF_CNTL), + SCL_EASF_H_BF1_EN, scl_data->dscl_prog_data.easf_h_bf1_en, + SCL_EASF_H_BF2_MODE, scl_data->dscl_prog_data.easf_h_bf2_mode, + SCL_EASF_H_BF3_MODE, scl_data->dscl_prog_data.easf_h_bf3_mode, + SCL_EASF_H_BF2_FLAT1_GAIN, scl_data->dscl_prog_data.easf_h_bf2_flat1_gain, + SCL_EASF_H_BF2_FLAT2_GAIN, scl_data->dscl_prog_data.easf_h_bf2_flat2_gain, + SCL_EASF_H_BF2_ROC_GAIN, scl_data->dscl_prog_data.easf_h_bf2_roc_gain); + REG_SET_2(VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE, REG_DEFAULT(VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE), + SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1, scl_data->dscl_prog_data.easf_h_ringest_eventap_reduceg1, + SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2, scl_data->dscl_prog_data.easf_h_ringest_eventap_reduceg2); + REG_SET_2(VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN, REG_DEFAULT(VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN), + SCL_EASF_H_RINGEST_EVENTAP_GAIN1, scl_data->dscl_prog_data.easf_h_ringest_eventap_gain1, + SCL_EASF_H_RINGEST_EVENTAP_GAIN2, scl_data->dscl_prog_data.easf_h_ringest_eventap_gain2); + REG_SET_4(VPDSCL_EASF_H_BF_FINAL_MAX_MIN, REG_DEFAULT(VPDSCL_EASF_H_BF_FINAL_MAX_MIN), + SCL_EASF_H_BF_MAXA, scl_data->dscl_prog_data.easf_h_bf_maxa, + SCL_EASF_H_BF_MAXB, scl_data->dscl_prog_data.easf_h_bf_maxb, + SCL_EASF_H_BF_MINA, scl_data->dscl_prog_data.easf_h_bf_mina, + SCL_EASF_H_BF_MINB, scl_data->dscl_prog_data.easf_h_bf_minb); + REG_SET_3(VPDSCL_EASF_H_BF1_PWL_SEG0, REG_DEFAULT(VPDSCL_EASF_H_BF1_PWL_SEG0), + SCL_EASF_H_BF1_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg0, + SCL_EASF_H_BF1_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg0, + SCL_EASF_H_BF1_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg0); + REG_SET_3(VPDSCL_EASF_H_BF1_PWL_SEG1, REG_DEFAULT(VPDSCL_EASF_H_BF1_PWL_SEG1), + SCL_EASF_H_BF1_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg1, + SCL_EASF_H_BF1_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg1, + SCL_EASF_H_BF1_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg1); + REG_SET_3(VPDSCL_EASF_H_BF1_PWL_SEG2, REG_DEFAULT(VPDSCL_EASF_H_BF1_PWL_SEG2), + SCL_EASF_H_BF1_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg2, + SCL_EASF_H_BF1_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg2, + SCL_EASF_H_BF1_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg2); + REG_SET_3(VPDSCL_EASF_H_BF1_PWL_SEG3, REG_DEFAULT(VPDSCL_EASF_H_BF1_PWL_SEG3), + SCL_EASF_H_BF1_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg3, + SCL_EASF_H_BF1_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg3, + SCL_EASF_H_BF1_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg3); + REG_SET_3(VPDSCL_EASF_H_BF1_PWL_SEG4, REG_DEFAULT(VPDSCL_EASF_H_BF1_PWL_SEG4), + SCL_EASF_H_BF1_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg4, + SCL_EASF_H_BF1_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg4, + SCL_EASF_H_BF1_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg4); + REG_SET_3(VPDSCL_EASF_H_BF1_PWL_SEG5, REG_DEFAULT(VPDSCL_EASF_H_BF1_PWL_SEG5), + SCL_EASF_H_BF1_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg5, + SCL_EASF_H_BF1_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg5, + SCL_EASF_H_BF1_PWL_SLOPE_SEG5, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg5); + REG_SET_3(VPDSCL_EASF_H_BF1_PWL_SEG6, REG_DEFAULT(VPDSCL_EASF_H_BF1_PWL_SEG6), + SCL_EASF_H_BF1_PWL_IN_SEG6, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg6, + SCL_EASF_H_BF1_PWL_BASE_SEG6, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg6, + SCL_EASF_H_BF1_PWL_SLOPE_SEG6, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg6); + REG_SET_2(VPDSCL_EASF_H_BF1_PWL_SEG7, REG_DEFAULT(VPDSCL_EASF_H_BF1_PWL_SEG7), + SCL_EASF_H_BF1_PWL_IN_SEG7, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg7, + SCL_EASF_H_BF1_PWL_BASE_SEG7, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg7); + REG_SET_3(VPDSCL_EASF_H_BF3_PWL_SEG0, REG_DEFAULT(VPDSCL_EASF_H_BF3_PWL_SEG0), + SCL_EASF_H_BF3_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set0, + SCL_EASF_H_BF3_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set0, + SCL_EASF_H_BF3_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set0); + REG_SET_3(VPDSCL_EASF_H_BF3_PWL_SEG1, REG_DEFAULT(VPDSCL_EASF_H_BF3_PWL_SEG1), + SCL_EASF_H_BF3_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set1, + SCL_EASF_H_BF3_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set1, + SCL_EASF_H_BF3_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set1); + REG_SET_3(VPDSCL_EASF_H_BF3_PWL_SEG2, REG_DEFAULT(VPDSCL_EASF_H_BF3_PWL_SEG2), + SCL_EASF_H_BF3_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set2, + SCL_EASF_H_BF3_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set2, + SCL_EASF_H_BF3_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set2); + REG_SET_3(VPDSCL_EASF_H_BF3_PWL_SEG3, REG_DEFAULT(VPDSCL_EASF_H_BF3_PWL_SEG3), + SCL_EASF_H_BF3_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set3, + SCL_EASF_H_BF3_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set3, + SCL_EASF_H_BF3_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set3); + REG_SET_3(VPDSCL_EASF_H_BF3_PWL_SEG4, REG_DEFAULT(VPDSCL_EASF_H_BF3_PWL_SEG4), + SCL_EASF_H_BF3_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set4, + SCL_EASF_H_BF3_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set4, + SCL_EASF_H_BF3_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set4); + REG_SET_2(VPDSCL_EASF_H_BF3_PWL_SEG5, REG_DEFAULT(VPDSCL_EASF_H_BF3_PWL_SEG5), + SCL_EASF_H_BF3_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set5, + SCL_EASF_H_BF3_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set5); + /* DSCL_EASF_SC_MATRIX_C0C1, DSCL_EASF_SC_MATRIX_C2C3 */ + REG_SET_2(VPDSCL_SC_MATRIX_C0C1, REG_DEFAULT(VPDSCL_SC_MATRIX_C0C1), + SCL_SC_MATRIX_C0, scl_data->dscl_prog_data.easf_matrix_c0, + SCL_SC_MATRIX_C1, scl_data->dscl_prog_data.easf_matrix_c1); + REG_SET_2(VPDSCL_SC_MATRIX_C2C3, REG_DEFAULT(VPDSCL_SC_MATRIX_C2C3), + SCL_SC_MATRIX_C2, scl_data->dscl_prog_data.easf_matrix_c2, + SCL_SC_MATRIX_C3, scl_data->dscl_prog_data.easf_matrix_c3); +} + +/** + * vpe20_dscl_disable_easf - Disable EASF when no scaling (1:1) + * + */ +void vpe20_dscl_disable_easf(struct dpp *dpp, const struct scaler_data *scl_data) +{ + PROGRAM_ENTRY(); + + /* DSCL_EASF_V_MODE */ + REG_SET(VPDSCL_EASF_V_MODE, REG_DEFAULT(VPDSCL_EASF_V_MODE), + SCL_EASF_V_EN, scl_data->dscl_prog_data.easf_v_en); + /* DSCL_EASF_H_MODE */ + REG_SET(VPDSCL_EASF_H_MODE, REG_DEFAULT(VPDSCL_EASF_H_MODE), + SCL_EASF_H_EN, scl_data->dscl_prog_data.easf_h_en); + /*Set the color conversion matrices even when the scaler is not active*/ + REG_SET_2(VPDSCL_SC_MODE, REG_DEFAULT(VPDSCL_SC_MODE), SCL_SC_MATRIX_MODE, + scl_data->dscl_prog_data.easf_matrix_mode, SCL_SC_LTONL_EN, + scl_data->dscl_prog_data.easf_ltonl_en); + REG_SET_2(VPDSCL_SC_MATRIX_C0C1, REG_DEFAULT(VPDSCL_SC_MATRIX_C0C1), SCL_SC_MATRIX_C0, + scl_data->dscl_prog_data.easf_matrix_c0, SCL_SC_MATRIX_C1, + scl_data->dscl_prog_data.easf_matrix_c1); + REG_SET_2(VPDSCL_SC_MATRIX_C2C3, REG_DEFAULT(VPDSCL_SC_MATRIX_C2C3), SCL_SC_MATRIX_C2, + scl_data->dscl_prog_data.easf_matrix_c2, SCL_SC_MATRIX_C3, + scl_data->dscl_prog_data.easf_matrix_c3); +} + +static void dpp2_dscl_set_isharp_filter(struct dpp *dpp, const uint32_t *filter) +{ + PROGRAM_ENTRY(); + + uint32_t level = 0; + uint32_t filter_data; + if (filter == NULL) + return; + + REG_SET_3(VPISHARP_DELTA_LUT_MEM_PWR_CTRL, REG_DEFAULT(VPISHARP_DELTA_LUT_MEM_PWR_CTRL), + ISHARP_DELTA_LUT_MEM_PWR_FORCE, 0, ISHARP_DELTA_LUT_MEM_PWR_DIS, 1, + ISHARP_DELTA_LUT_MEM_PWR_STATE, 0); + + REG_SET(VPISHARP_DELTA_CTRL, REG_DEFAULT(VPISHARP_DELTA_CTRL), + ISHARP_DELTA_LUT_HOST_SELECT, 0); + REG_SET(VPISHARP_DELTA_INDEX, 0, + ISHARP_DELTA_INDEX, level); + + for (level = 0; level < NUM_ISHARP_LEVELS; level++) { + filter_data = filter[level]; + REG_SET(VPISHARP_DELTA_DATA, REG_DEFAULT(VPISHARP_DELTA_DATA), + ISHARP_DELTA_DATA, filter_data); + } + + REG_SET_3(VPISHARP_DELTA_LUT_MEM_PWR_CTRL, REG_DEFAULT(VPISHARP_DELTA_LUT_MEM_PWR_CTRL), + ISHARP_DELTA_LUT_MEM_PWR_FORCE, 0, ISHARP_DELTA_LUT_MEM_PWR_DIS, 0, + ISHARP_DELTA_LUT_MEM_PWR_STATE, 0); +} + +/** + * vpe20_dscl_program_isharp - Program isharp + * + * This is the primary function to program isharp + * + */ +void vpe20_dscl_program_isharp(struct dpp *dpp, const struct scaler_data *scl_data) +{ + PROGRAM_ENTRY(); + + /* ISHARP_MDOE */ + REG_SET_6(VPISHARP_MODE, REG_DEFAULT(VPISHARP_MODE), + ISHARP_EN, scl_data->dscl_prog_data.isharp_en, + ISHARP_NOISEDET_EN, scl_data->dscl_prog_data.isharp_noise_det.enable, + ISHARP_NOISEDET_MODE, scl_data->dscl_prog_data.isharp_noise_det.mode, + ISHARP_LBA_MODE, scl_data->dscl_prog_data.isharp_lba.mode, + ISHARP_FMT_MODE, scl_data->dscl_prog_data.isharp_fmt.mode, + ISHARP_FMT_NORM, scl_data->dscl_prog_data.isharp_fmt.norm); + + if (scl_data->dscl_prog_data.isharp_en == 0) + return; + + /* ISHARP_NOISEDET_THRESHOLD */ + REG_SET_2(VPISHARP_NOISEDET_THRESHOLD, REG_DEFAULT(VPISHARP_NOISEDET_THRESHOLD), + ISHARP_NOISEDET_UTHRE, scl_data->dscl_prog_data.isharp_noise_det.uthreshold, + ISHARP_NOISEDET_DTHRE, scl_data->dscl_prog_data.isharp_noise_det.dthreshold); + /* ISHARP_NOISE_GAIN_PWL */ + REG_SET_3(VPISHARP_NOISE_GAIN_PWL, REG_DEFAULT(VPISHARP_NOISE_GAIN_PWL), + ISHARP_NOISEDET_PWL_START_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_start_in, + ISHARP_NOISEDET_PWL_END_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_end_in, + ISHARP_NOISEDET_PWL_SLOPE, scl_data->dscl_prog_data.isharp_noise_det.pwl_slope); + /* ISHARP_LBA: IN_SEG, BASE_SEG, SLOPE_SEG */ + REG_SET_3(VPISHARP_LBA_PWL_SEG0, REG_DEFAULT(VPISHARP_LBA_PWL_SEG0), + ISHARP_LBA_PWL_IN_SEG0, scl_data->dscl_prog_data.isharp_lba.in_seg[0], + ISHARP_LBA_PWL_BASE_SEG0, scl_data->dscl_prog_data.isharp_lba.base_seg[0], + ISHARP_LBA_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.isharp_lba.slope_seg[0]); + REG_SET_3(VPISHARP_LBA_PWL_SEG1, REG_DEFAULT(VPISHARP_LBA_PWL_SEG1), + ISHARP_LBA_PWL_IN_SEG1, scl_data->dscl_prog_data.isharp_lba.in_seg[1], + ISHARP_LBA_PWL_BASE_SEG1, scl_data->dscl_prog_data.isharp_lba.base_seg[1], + ISHARP_LBA_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.isharp_lba.slope_seg[1]); + REG_SET_3(VPISHARP_LBA_PWL_SEG2, REG_DEFAULT(VPISHARP_LBA_PWL_SEG2), + ISHARP_LBA_PWL_IN_SEG2, scl_data->dscl_prog_data.isharp_lba.in_seg[2], + ISHARP_LBA_PWL_BASE_SEG2, scl_data->dscl_prog_data.isharp_lba.base_seg[2], + ISHARP_LBA_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.isharp_lba.slope_seg[2]); + REG_SET_3(VPISHARP_LBA_PWL_SEG3, REG_DEFAULT(VPISHARP_LBA_PWL_SEG3), + ISHARP_LBA_PWL_IN_SEG3, scl_data->dscl_prog_data.isharp_lba.in_seg[3], + ISHARP_LBA_PWL_BASE_SEG3, scl_data->dscl_prog_data.isharp_lba.base_seg[3], + ISHARP_LBA_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.isharp_lba.slope_seg[3]); + REG_SET_3(VPISHARP_LBA_PWL_SEG4, REG_DEFAULT(VPISHARP_LBA_PWL_SEG4), + ISHARP_LBA_PWL_IN_SEG4, scl_data->dscl_prog_data.isharp_lba.in_seg[4], + ISHARP_LBA_PWL_BASE_SEG4, scl_data->dscl_prog_data.isharp_lba.base_seg[4], + ISHARP_LBA_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.isharp_lba.slope_seg[4]); + REG_SET_2(VPISHARP_LBA_PWL_SEG5, REG_DEFAULT(VPISHARP_LBA_PWL_SEG5), + ISHARP_LBA_PWL_IN_SEG5, scl_data->dscl_prog_data.isharp_lba.in_seg[5], + ISHARP_LBA_PWL_BASE_SEG5, scl_data->dscl_prog_data.isharp_lba.base_seg[5]); + + /* ISHARP_DELTA_LUT */ + dpp2_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta); + + /* ISHARP_NLDELTA_SOFT_CLIP */ + REG_SET_6(VPISHARP_NLDELTA_SOFT_CLIP, REG_DEFAULT(VPISHARP_NLDELTA_SOFT_CLIP), + ISHARP_NLDELTA_SCLIP_EN_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_p, + ISHARP_NLDELTA_SCLIP_PIVOT_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_p, + ISHARP_NLDELTA_SCLIP_SLOPE_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_p, + ISHARP_NLDELTA_SCLIP_EN_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_n, + ISHARP_NLDELTA_SCLIP_PIVOT_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_n, + ISHARP_NLDELTA_SCLIP_SLOPE_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_n); + + /* Blur and Scale Coefficients - SCL_COEF_RAM_TAP_SELECT */ + if (scl_data->dscl_prog_data.isharp_en) { + if (scl_data->dscl_prog_data.filter_blur_scale_v) { + vpe10_dpp_dscl_set_scaler_filter(dpp, scl_data->taps.v_taps, + SCL_COEF_VERTICAL_BLUR_SCALE, scl_data->dscl_prog_data.filter_blur_scale_v); + } + if (scl_data->dscl_prog_data.filter_blur_scale_h) { + vpe10_dpp_dscl_set_scaler_filter(dpp, scl_data->taps.h_taps, + SCL_COEF_HORIZONTAL_BLUR_SCALE, scl_data->dscl_prog_data.filter_blur_scale_h); + } + } +} + +static void dpp2_set_recout(struct dpp *dpp, const struct vpe_rect *recout) +{ + PROGRAM_ENTRY(); + + REG_SET_2(VPDSCL_RECOUT_START, 0, RECOUT_START_X, recout->x, RECOUT_START_Y, recout->y); + + REG_SET_2(VPDSCL_RECOUT_SIZE, 0, RECOUT_WIDTH, recout->width, RECOUT_HEIGHT, recout->height); +} + +static void dpp2_power_on_dscl(struct dpp *dpp, bool power_on) +{ + PROGRAM_ENTRY(); + + if (dpp->vpe_priv->init.debug.enable_mem_low_power.bits.dscl) { + if (power_on) { + REG_SET_2(VPDSCL_MEM_PWR_CTRL, REG_DEFAULT(VPDSCL_MEM_PWR_CTRL), LUT_MEM_PWR_DIS, 0, + LUT_MEM_PWR_FORCE, 0); + + // introduce a delay by dummy set + REG_SET_2(VPDSCL_MEM_PWR_CTRL, REG_DEFAULT(VPDSCL_MEM_PWR_CTRL), LUT_MEM_PWR_DIS, 0, + LUT_MEM_PWR_FORCE, 0); + + REG_SET_2(VPDSCL_MEM_PWR_CTRL, REG_DEFAULT(VPDSCL_MEM_PWR_CTRL), LUT_MEM_PWR_DIS, 0, + LUT_MEM_PWR_FORCE, 0); + } else { + REG_SET_2(VPDSCL_MEM_PWR_CTRL, REG_DEFAULT(VPDSCL_MEM_PWR_CTRL), LUT_MEM_PWR_DIS, 0, + LUT_MEM_PWR_FORCE, 3); + } + } else { + if (power_on) { + REG_SET_2(VPDSCL_MEM_PWR_CTRL, REG_DEFAULT(VPDSCL_MEM_PWR_CTRL), LUT_MEM_PWR_DIS, 1, + LUT_MEM_PWR_FORCE, 0); + } else { + REG_SET_2(VPDSCL_MEM_PWR_CTRL, REG_DEFAULT(VPDSCL_MEM_PWR_CTRL), LUT_MEM_PWR_DIS, 0, + LUT_MEM_PWR_FORCE, 0); + } + } +} + +static void dpp2_dscl_set_scale_ratio(struct dpp *dpp, const struct scaler_data *data) +{ + PROGRAM_ENTRY(); + + REG_SET(VPDSCL_HORZ_FILTER_SCALE_RATIO, 0, + SCL_H_SCALE_RATIO, data->dscl_prog_data.ratios.h_scale_ratio); + + REG_SET(VPDSCL_VERT_FILTER_SCALE_RATIO, 0, + SCL_V_SCALE_RATIO, data->dscl_prog_data.ratios.v_scale_ratio); + + REG_SET(VPDSCL_HORZ_FILTER_SCALE_RATIO_C, 0, + SCL_H_SCALE_RATIO_C, data->dscl_prog_data.ratios.h_scale_ratio_c); + + REG_SET(VPDSCL_VERT_FILTER_SCALE_RATIO_C, 0, + SCL_V_SCALE_RATIO_C, data->dscl_prog_data.ratios.v_scale_ratio_c); +} + +void vpe20_dpp_dscl_set_scaler_position(struct dpp *dpp, const struct scaler_data *data) +{ + PROGRAM_ENTRY(); + + REG_SET_2(VPDSCL_HORZ_FILTER_INIT, 0, + SCL_H_INIT_FRAC, data->dscl_prog_data.init.h_filter_init_frac, + SCL_H_INIT_INT, data->dscl_prog_data.init.h_filter_init_int); + + REG_SET_2(VPDSCL_HORZ_FILTER_INIT_C, 0, + SCL_H_INIT_FRAC_C, data->dscl_prog_data.init.h_filter_init_frac_c, + SCL_H_INIT_INT_C, data->dscl_prog_data.init.h_filter_init_int_c); + + REG_SET_2(VPDSCL_VERT_FILTER_INIT, 0, + SCL_V_INIT_FRAC, data->dscl_prog_data.init.v_filter_init_frac, + SCL_V_INIT_INT, data->dscl_prog_data.init.v_filter_init_int); + + REG_SET_2(VPDSCL_VERT_FILTER_INIT_BOT, 0, + SCL_V_INIT_FRAC_BOT, data->dscl_prog_data.init.v_filter_init_bot_frac, + SCL_V_INIT_INT_BOT, data->dscl_prog_data.init.v_filter_init_bot_int); + + REG_SET_2(VPDSCL_VERT_FILTER_INIT_C, 0, + SCL_V_INIT_FRAC_C, data->dscl_prog_data.init.v_filter_init_frac_c, + SCL_V_INIT_INT_C, data->dscl_prog_data.init.v_filter_init_int_c); + + REG_SET_2(VPDSCL_VERT_FILTER_INIT_BOT_C, 0, + SCL_V_INIT_FRAC_BOT_C, data->dscl_prog_data.init.v_filter_init_bot_frac_c, + SCL_V_INIT_INT_BOT_C, data->dscl_prog_data.init.v_filter_init_bot_int_c); +} + +static void dpp2_dscl_set_scl_filter_and_dscl_mode(struct dpp *dpp, + const struct scaler_data *scl_data, enum vpe10_dscl_mode_sel scl_mode, bool chroma_coef_mode) +{ + PROGRAM_ENTRY(); + + const uint16_t *filter_h = NULL; + const uint16_t *filter_v = NULL; + const uint16_t *filter_h_c = NULL; + const uint16_t *filter_v_c = NULL; + + if (scl_mode != DSCL_MODE_DSCL_BYPASS) { + filter_h = scl_data->dscl_prog_data.filter_h; + filter_v = scl_data->dscl_prog_data.filter_v; + filter_h_c = scl_data->dscl_prog_data.filter_h_c; + filter_v_c = scl_data->dscl_prog_data.filter_v_c; + + if (filter_h) { + vpe10_dpp_dscl_set_scaler_filter( + dpp, scl_data->taps.h_taps, SCL_COEF_LUMA_HORZ_FILTER, filter_h); + } + + if (filter_v) { + vpe10_dpp_dscl_set_scaler_filter( + dpp, scl_data->taps.v_taps, SCL_COEF_LUMA_VERT_FILTER, filter_v); + } + + if (chroma_coef_mode) { + if (filter_h_c) { + vpe10_dpp_dscl_set_scaler_filter( + dpp, scl_data->taps.h_taps_c, SCL_COEF_CHROMA_HORZ_FILTER, filter_h_c); + } + if (filter_v_c) { + vpe10_dpp_dscl_set_scaler_filter( + dpp, scl_data->taps.v_taps_c, SCL_COEF_CHROMA_VERT_FILTER, filter_v_c); + } + } + } + + REG_SET_2(VPDSCL_MODE, 0, VPDSCL_MODE, scl_mode, SCL_CHROMA_COEF_MODE, chroma_coef_mode); +} + + +static void dpp2_dscl_set_taps(struct dpp *dpp, const struct scaler_data *scl_data) +{ + PROGRAM_ENTRY(); + + /* HTaps/VTaps */ + REG_SET_4(VPDSCL_TAP_CONTROL, REG_DEFAULT(VPDSCL_TAP_CONTROL), SCL_V_NUM_TAPS, + scl_data->taps.v_taps - 1, SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1, SCL_V_NUM_TAPS_C, + scl_data->taps.v_taps_c - 1, SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1); +} + +void vpe20_dpp_set_segment_scaler(struct dpp *dpp, const struct scaler_data *scl_data) +{ + PROGRAM_ENTRY(); + + const struct vpe_rect *rect = + (struct vpe_rect *)&scl_data->dscl_prog_data.recout; + enum scl_mode dscl_mode = + (enum scl_mode) scl_data->dscl_prog_data.dscl_mode; + + uint32_t mpc_width = scl_data->dscl_prog_data.mpc_size.width; + uint32_t mpc_height = scl_data->dscl_prog_data.mpc_size.height; + + if (dpp->vpe_priv->init.debug.opp_background_gen) { + // We set the x and y of the DPP rect out to 0, since OPP does the top and left extend + struct vpe_rect new_rect; + new_rect.y = 0; + new_rect.width = rect->width; + new_rect.x = 0; + new_rect.height = rect->height; + + dpp2_set_recout(dpp, &new_rect); + } else { + dpp2_set_recout(dpp, rect); + } + + REG_SET_2(VPMPC_SIZE, REG_DEFAULT(VPMPC_SIZE), VPMPC_WIDTH, mpc_width, + VPMPC_HEIGHT, mpc_height); + + if (dscl_mode == SCL_MODE_DSCL_BYPASS) + return; + + dpp->funcs->dscl_set_scaler_position(dpp, scl_data); +} + +/** + * vpe20_dpp_set_frame_scaler - program scaler from dscl_prog_data + * + * This is the primary function to program scaler and line buffer in manual + * scaling mode. To execute the required operations for manual scale, we need + * to disable AutoCal first. + */ +void vpe20_dpp_set_frame_scaler(struct dpp *dpp, const struct scaler_data *scl_data) +{ + PROGRAM_ENTRY(); + + enum vpe10_dscl_mode_sel dscl_mode = vpe20_dpp_dscl_get_dscl_mode(scl_data); + bool ycbcr = vpe10_dpp_dscl_is_ycbcr(scl_data->format); + + if (dscl_mode == DSCL_MODE_DSCL_BYPASS) { + dpp2_dscl_set_scl_filter_and_dscl_mode(dpp, scl_data, dscl_mode, ycbcr); + vpe20_dscl_program_isharp(dpp, scl_data); + vpe20_dscl_disable_easf(dpp, scl_data); + vpe10_dpp_power_on_dscl(dpp, false); + } else { + vpe10_dpp_power_on_dscl(dpp, true); + vpe10_dpp_dscl_set_lb(dpp, &scl_data->lb_params, LB_MEMORY_CONFIG_0); + dpp2_dscl_set_scale_ratio(dpp, scl_data); + dpp2_dscl_set_taps(dpp, scl_data); + dpp2_dscl_set_scl_filter_and_dscl_mode(dpp, scl_data, dscl_mode, ycbcr); + vpe20_dscl_program_isharp(dpp, scl_data); + + if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS || + (!scl_data->dscl_prog_data.easf_v_en && !scl_data->dscl_prog_data.easf_h_en)) { + vpe20_dscl_disable_easf(dpp, scl_data); + } else { + vpe20_dscl_program_easf(dpp, scl_data); + } + } +} diff --git a/src/amd/vpelib/src/chip/vpe20/vpe20_mpc.c b/src/amd/vpelib/src/chip/vpe20/vpe20_mpc.c new file mode 100644 index 00000000000..41434a59b63 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/vpe20_mpc.c @@ -0,0 +1,853 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include "vpe_assert.h" +#include "common.h" +#include "vpe_priv.h" +#include "vpe10_mpc.h" +#include "vpe20_mpc.h" +#include "reg_helper.h" +#include "vpe10_cm_common.h" +#include "custom_fp16.h" +#include "conversion.h" + +#define CTX_BASE mpc +#define CTX vpe20_mpc +#define MPC_RMCM_3DLUT_FL_ENABLE (0x0) +#define MPC_RMCM_3DLUT_FL_DISABLE (0xf) + +static struct mpc_funcs mpc_funcs = { + .program_mpcc_mux = vpe20_mpc_program_mpcc_mux, + .program_mpcc_blending = vpe20_mpc_program_mpcc_blending, + .program_mpc_bypass_bg_color = vpe10_mpc_program_mpc_bypass_bg_color, + .power_on_ogam_lut = vpe10_mpc_power_on_ogam_lut, + .set_output_csc = vpe10_mpc_set_output_csc, + .set_ocsc_default = vpe10_mpc_set_ocsc_default, + .program_output_csc = vpe10_program_output_csc, + .set_output_gamma = vpe10_mpc_set_output_gamma, + .set_gamut_remap = NULL, + .set_gamut_remap2 = vpe20_mpc_set_gamut_remap2, + .power_on_1dlut_shaper_3dlut = vpe20_mpc_power_on_1dlut_shaper_3dlut, + .program_shaper = vpe20_mpc_program_shaper, + .program_3dlut = vpe20_mpc_program_3dlut, + .program_3dlut_indirect = vpe20_mpc_program_3dlut_indirect, + .program_1dlut = vpe10_mpc_program_1dlut, + .program_cm_location = vpe10_mpc_program_cm_location, + .set_denorm = vpe10_mpc_set_denorm, + .set_out_float_en = vpe10_mpc_set_out_float_en, + .program_mpc_out = vpe10_mpc_program_mpc_out, + .set_output_transfer_func = vpe10_mpc_set_output_transfer_func, + .set_mpc_shaper_3dlut = vpe20_mpc_set_mpc_shaper_3dlut, + .shaper_bypass = vpe20_mpc_shaper_bypass, + .set_blend_lut = vpe10_mpc_set_blend_lut, + .program_movable_cm = vpe20_mpc_program_movable_cm, + .program_crc = vpe10_mpc_program_crc, + .attach_3dlut_to_mpc_inst = vpe20_attach_3dlut_to_mpc_inst, + .update_3dlut_fl_bias_scale = vpe20_update_3dlut_fl_bias_scale, + .program_mpc_3dlut_fl_config = vpe20_mpc_program_3dlut_fl_config, + .program_mpc_3dlut_fl = vpe20_mpc_program_3dlut_fl, +}; + +void vpe20_construct_mpc(struct vpe_priv *vpe_priv, struct mpc *mpc) +{ + mpc->vpe_priv = vpe_priv; + mpc->funcs = &mpc_funcs; +} + +void vpe20_mpc_program_mpcc_mux(struct mpc *mpc, enum mpc_mpccid mpcc_idx, + enum mpc_mux_topsel topsel, enum mpc_mux_botsel botsel, enum mpc_mux_outmux outmux, + enum mpc_mux_oppid oppid) +{ + PROGRAM_ENTRY(); + + /* program mux and MPCC_MODE */ + REG_SET(VPMPCC_TOP_SEL, 0, VPMPCC_TOP_SEL, topsel); + REG_SET(VPMPCC_BOT_SEL, 0, VPMPCC_BOT_SEL, botsel); + REG_SET(VPMPC_OUT_MUX, 0, VPMPC_OUT_MUX, outmux); + REG_SET(VPMPCC_VPOPP_ID, 0, VPMPCC_VPOPP_ID, oppid); +} + +void vpe20_mpc_program_mpcc_blending( + struct mpc *mpc, enum mpc_mpccid mpcc_idx, struct mpcc_blnd_cfg *blnd_cfg) +{ + PROGRAM_ENTRY(); + float r_cr, g_y, b_cb; + int bg_r_cr, bg_g_y, bg_b_cb; + struct vpe_custom_float_format2 fmt; + + REG_SET_5(VPMPCC_CONTROL, REG_DEFAULT(VPMPCC_CONTROL), VPMPCC_MODE, blnd_cfg->blend_mode, + VPMPCC_ALPHA_BLND_MODE, blnd_cfg->alpha_mode, VPMPCC_ALPHA_MULTIPLIED_MODE, + blnd_cfg->pre_multiplied_alpha, VPMPCC_BLND_ACTIVE_OVERLAP_ONLY, blnd_cfg->overlap_only, + VPMPCC_BOT_GAIN_MODE, blnd_cfg->bottom_gain_mode); + + REG_SET_2(VPMPCC_CONTROL2, REG_DEFAULT(VPMPCC_CONTROL2), VPMPCC_GLOBAL_ALPHA, + blnd_cfg->global_alpha, VPMPCC_GLOBAL_GAIN, blnd_cfg->global_gain); + + REG_SET(VPMPCC_TOP_GAIN, 0, VPMPCC_TOP_GAIN, blnd_cfg->top_gain); + REG_SET(VPMPCC_BOT_GAIN_INSIDE, 0, VPMPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain); + REG_SET(VPMPCC_BOT_GAIN_OUTSIDE, 0, VPMPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain); + + if (blnd_cfg->bg_color.is_ycbcr) { + r_cr = blnd_cfg->bg_color.ycbcra.cr; + g_y = blnd_cfg->bg_color.ycbcra.y; + b_cb = blnd_cfg->bg_color.ycbcra.cb; + } else { + r_cr = blnd_cfg->bg_color.rgba.r; + g_y = blnd_cfg->bg_color.rgba.g; + b_cb = blnd_cfg->bg_color.rgba.b; + } + + fmt.flags.Uint = 0; + fmt.flags.bits.sign = 1; + fmt.mantissaBits = 12; + fmt.exponentaBits = 6; + + vpe_convert_to_custom_float_generic((double)r_cr, &fmt, &bg_r_cr); + vpe_convert_to_custom_float_generic((double)g_y, &fmt, &bg_g_y); + vpe_convert_to_custom_float_generic((double)b_cb, &fmt, &bg_b_cb); + + // Set background color + REG_SET(VPMPCC_BG_R_CR, 0, VPMPCC_BG_R_CR, bg_r_cr); + REG_SET(VPMPCC_BG_G_Y, 0, VPMPCC_BG_G_Y, bg_g_y); + REG_SET(VPMPCC_BG_B_CB, 0, VPMPCC_BG_B_CB, bg_b_cb); +} + +void vpe20_mpc_power_on_1dlut_shaper_3dlut(struct mpc *mpc, bool power_on) +{ + PROGRAM_ENTRY(); + // int max_retries = 10; + + // VPE1 has a single register. + // VPE2 is split into two that reflects that shaper+3DLUT are in RMCM while (post)1D is stil in MCM + REG_SET(VPMPCC_MCM_MEM_PWR_CTRL, REG_DEFAULT(VPMPCC_MCM_MEM_PWR_CTRL), + VPMPCC_MCM_1DLUT_MEM_PWR_DIS, power_on == true ? 1 : 0); + REG_SET_2(VPMPC_RMCM_MEM_PWR_CTRL, REG_DEFAULT(VPMPC_RMCM_MEM_PWR_CTRL), + VPMPC_RMCM_SHAPER_MEM_PWR_DIS, power_on == true ? 1 : 0, + VPMPC_RMCM_3DLUT_MEM_PWR_DIS, power_on == true ? 1 : 0); + + /* wait for memory to fully power up */ + if (power_on && vpe_priv->init.debug.enable_mem_low_power.bits.mpc) { + // REG_WAIT(VPMPCC_MCM_MEM_PWR_CTRL, VPMPCC_MCM_SHAPER_MEM_PWR_STATE, 0, 1, max_retries); + // Use two REG_SET instead of wait for State + REG_SET(VPMPCC_MCM_MEM_PWR_CTRL, REG_DEFAULT(VPMPCC_MCM_MEM_PWR_CTRL), + VPMPCC_MCM_1DLUT_MEM_PWR_DIS, power_on == true ? 1 : 0); + REG_SET_2(VPMPC_RMCM_MEM_PWR_CTRL, REG_DEFAULT(VPMPC_RMCM_MEM_PWR_CTRL), + VPMPC_RMCM_SHAPER_MEM_PWR_DIS, power_on == true ? 1 : 0, + VPMPC_RMCM_3DLUT_MEM_PWR_DIS, power_on == true ? 1 : 0); + + REG_SET(VPMPCC_MCM_MEM_PWR_CTRL, REG_DEFAULT(VPMPCC_MCM_MEM_PWR_CTRL), + VPMPCC_MCM_1DLUT_MEM_PWR_DIS, power_on == true ? 1 : 0); + REG_SET_2(VPMPC_RMCM_MEM_PWR_CTRL, REG_DEFAULT(VPMPC_RMCM_MEM_PWR_CTRL), + VPMPC_RMCM_SHAPER_MEM_PWR_DIS, power_on == true ? 1 : 0, + VPMPC_RMCM_3DLUT_MEM_PWR_DIS, power_on == true ? 1 : 0); + + // REG_WAIT(VPMPCC_MCM_MEM_PWR_CTRL, VPMPCC_MCM_3DLUT_MEM_PWR_STATE, 0, 1, max_retries); + } +} + +static void vpe20_mpc_configure_shaper_lut(struct mpc *mpc, bool is_ram_a) +{ + PROGRAM_ENTRY(); + + REG_SET(VPMPC_RMCM_SHAPER_LUT_INDEX, 0, VPMPC_RMCM_SHAPER_LUT_INDEX, 0); + + REG_SET_2(VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, 0, VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, 7, + VPMPC_RMCM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0 : 1); +} + +static void vpe20_mpc_program_shaper_luta_settings(struct mpc *mpc, const struct pwl_params *params) +{ + PROGRAM_ENTRY(); + const struct gamma_curve *curve; + uint16_t packet_data_size; + uint16_t i; + + REG_SET_2(VPMPC_RMCM_SHAPER_RAMA_START_CNTL_B, 0, VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B, + params->corner_points[0].blue.custom_float_x, + VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); + REG_SET_2(VPMPC_RMCM_SHAPER_RAMA_START_CNTL_G, 0, VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B, + params->corner_points[0].green.custom_float_x, + VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); + REG_SET_2(VPMPC_RMCM_SHAPER_RAMA_START_CNTL_R, 0, VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B, + params->corner_points[0].red.custom_float_x, + VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); + + REG_SET_2(VPMPC_RMCM_SHAPER_RAMA_END_CNTL_B, 0, VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B, + params->corner_points[1].blue.custom_float_x, VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, + params->corner_points[1].blue.custom_float_y); + REG_SET_2(VPMPC_RMCM_SHAPER_RAMA_END_CNTL_G, 0, VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B, + params->corner_points[1].green.custom_float_x, VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, + params->corner_points[1].green.custom_float_y); + REG_SET_2(VPMPC_RMCM_SHAPER_RAMA_END_CNTL_R, 0, VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B, + params->corner_points[1].red.custom_float_x, VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, + params->corner_points[1].red.custom_float_y); + + // Optimized by single VPEP config packet with auto inc + + packet_data_size = (uint16_t)(REG_OFFSET(VPMPC_RMCM_SHAPER_RAMA_REGION_32_33) - + REG_OFFSET(VPMPC_RMCM_SHAPER_RAMA_REGION_0_1) + 1); + + VPE_ASSERT(packet_data_size <= MAX_CONFIG_PACKET_DATA_SIZE_DWORD); + packet.bits.INC = 1; // set the auto increase bit + packet.bits.VPEP_CONFIG_DATA_SIZE = + packet_data_size - 1; // number of "continuous" dwords, 1-based + packet.bits.VPEP_CONFIG_REGISTER_OFFSET = REG_OFFSET(VPMPC_RMCM_SHAPER_RAMA_REGION_0_1); + + config_writer_fill_direct_config_packet_header(config_writer, &packet); + + curve = params->arr_curve_points; + + for (i = 0; i < packet_data_size; i++) { + config_writer_fill(config_writer, + REG_FIELD_VALUE(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset) | + REG_FIELD_VALUE( + VPMPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num) | + REG_FIELD_VALUE(VPMPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset) | + REG_FIELD_VALUE( + VPMPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num)); + curve += 2; + } +} + +static void vpe20_mpc_program_shaper_lut( + struct mpc *mpc, const struct pwl_result_data *rgb, uint32_t num) +{ + PROGRAM_ENTRY(); + uint32_t i, red, green, blue; + uint32_t red_delta, green_delta, blue_delta; + uint32_t red_value, green_value, blue_value; + uint16_t packet_data_size; + + // Optimized by single VPEP config packet for same address with multiple write + packet_data_size = (uint16_t)num * 3; // num writes for each channel in (R, G, B) + + VPE_ASSERT(packet_data_size <= MAX_CONFIG_PACKET_DATA_SIZE_DWORD); + packet.bits.INC = 0; + packet.bits.VPEP_CONFIG_DATA_SIZE = + packet_data_size - 1; // number of "continuous" dwords, 1-based + packet.bits.VPEP_CONFIG_REGISTER_OFFSET = REG_OFFSET(VPMPC_RMCM_SHAPER_LUT_DATA); + + config_writer_fill_direct_config_packet_header(config_writer, &packet); + + for (i = 0; i < num; i++) { + red = rgb[i].red_reg; + green = rgb[i].green_reg; + blue = rgb[i].blue_reg; + + red_delta = rgb[i].delta_red_reg; + green_delta = rgb[i].delta_green_reg; + blue_delta = rgb[i].delta_blue_reg; + + red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff); + green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff); + blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff); + + config_writer_fill(config_writer, REG_FIELD_VALUE(VPMPC_RMCM_SHAPER_LUT_DATA, red_value)); + config_writer_fill(config_writer, REG_FIELD_VALUE(VPMPC_RMCM_SHAPER_LUT_DATA, green_value)); + config_writer_fill(config_writer, REG_FIELD_VALUE(VPMPC_RMCM_SHAPER_LUT_DATA, blue_value)); + } +} + +void vpe20_mpc_shaper_bypass(struct mpc *mpc, bool bypass) +{ + PROGRAM_ENTRY(); + + REG_SET(VPMPC_RMCM_SHAPER_CONTROL, 0, VPMPC_RMCM_SHAPER_LUT_MODE, bypass ? 0 : 1); +} + +bool vpe20_mpc_program_shaper(struct mpc *mpc, const struct pwl_params *params) +{ + PROGRAM_ENTRY(); + + if (params == NULL) { + REG_SET(VPMPC_RMCM_SHAPER_CONTROL, 0, VPMPC_RMCM_SHAPER_LUT_MODE, 0); + return false; + } + + vpe20_mpc_configure_shaper_lut(mpc, true); // Always use LUT_RAM_A + + // if (vpe_priv->init.debug.enable_mem_low_power.bits.mpc) + // should always turn it on + vpe20_mpc_power_on_1dlut_shaper_3dlut(mpc, true); + + vpe20_mpc_program_shaper_luta_settings(mpc, params); + + vpe20_mpc_program_shaper_lut(mpc, params->rgb_resulted, params->hw_points_num); + + REG_SET(VPMPC_RMCM_SHAPER_CONTROL, 0, VPMPC_RMCM_SHAPER_LUT_MODE, 1); + REG_SET_DEFAULT(VPMPC_RMCM_SHAPER_SCALE_R); + REG_SET_DEFAULT(VPMPC_RMCM_SHAPER_SCALE_G_B); + + //? Should we check debug option before turn off shaper? -- should be yes + if (vpe_priv->init.debug.enable_mem_low_power.bits.mpc) + vpe20_mpc_power_on_1dlut_shaper_3dlut(mpc, false); + + return true; +} + +static void vpe20_mpc_select_3dlut_ram_and_mask(struct mpc *mpc, enum vpe_lut_mode mode, + bool is_color_channel_12bits, uint32_t ram_selection_mask) +{ + PROGRAM_ENTRY(); + + VPE_ASSERT(mode == LUT_RAM_A); + + REG_SET_3(VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL, REG_DEFAULT(VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL), + VPMPC_RMCM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1, VPMPC_RMCM_3DLUT_30BIT_EN, + is_color_channel_12bits ? 0 : 1, VPMPC_RMCM_3DLUT_WRITE_EN_MASK, ram_selection_mask); + REG_SET(VPMPC_RMCM_3DLUT_INDEX, 0, VPMPC_RMCM_3DLUT_INDEX, 0); +} + +static void vpe20_mpc_set3dlut_ram12(struct mpc *mpc, const struct vpe_rgb *lut, uint32_t entries) +{ + PROGRAM_ENTRY(); + uint32_t i, red, green, blue, red1, green1, blue1; + uint16_t MaxLutEntriesPerPacket = + (MAX_CONFIG_PACKET_DATA_SIZE_DWORD / 3) * 2; // each two entries consumes 3 DWORDs + uint16_t ActualEntriesInPacket = 0; + uint16_t ActualPacketSize; + + // Optimized by single VPEP config packet for same address with multiple write + + for (i = 0; i < entries; i += 2) { + if (i % MaxLutEntriesPerPacket == 0) { // need generate one another new packet + ActualEntriesInPacket = MaxLutEntriesPerPacket; + + // If single packet is big enough to contain remaining entries + if ((entries - i) < MaxLutEntriesPerPacket) { + ActualEntriesInPacket = (uint16_t)(entries - i); + if ((entries - i) % 2) { + // odd entries, round up to even as we need to program in pair + ActualEntriesInPacket++; + } + } + + ActualPacketSize = ActualEntriesInPacket * 3 / 2; + + VPE_ASSERT(ActualPacketSize <= MAX_CONFIG_PACKET_DATA_SIZE_DWORD); + packet.bits.INC = 0; + packet.bits.VPEP_CONFIG_DATA_SIZE = + ActualPacketSize - 1; // number of "continuous" dwords, 1-based + packet.bits.VPEP_CONFIG_REGISTER_OFFSET = REG_OFFSET(VPMPC_RMCM_3DLUT_DATA); + + config_writer_fill_direct_config_packet_header(config_writer, &packet); + } + + red = lut[i].red << 4; + green = lut[i].green << 4; + blue = lut[i].blue << 4; + if (i + 1 < entries) { + red1 = lut[i + 1].red << 4; + green1 = lut[i + 1].green << 4; + blue1 = lut[i + 1].blue << 4; + } + else { + // last odd entry, program 0 for extra one that accompany with it. + red1 = 0; + green1 = 0; + blue1 = 0; + } + + config_writer_fill(config_writer, REG_FIELD_VALUE(VPMPC_RMCM_3DLUT_DATA0, red) | + REG_FIELD_VALUE(VPMPC_RMCM_3DLUT_DATA1, red1)); + config_writer_fill(config_writer, REG_FIELD_VALUE(VPMPC_RMCM_3DLUT_DATA0, green) | + REG_FIELD_VALUE(VPMPC_RMCM_3DLUT_DATA1, green1)); + config_writer_fill(config_writer, REG_FIELD_VALUE(VPMPC_RMCM_3DLUT_DATA0, blue) | + REG_FIELD_VALUE(VPMPC_RMCM_3DLUT_DATA1, blue1)); + } +} + +static void vpe20_mpc_set3dlut_ram10(struct mpc *mpc, const struct vpe_rgb *lut, uint32_t entries) +{ + PROGRAM_ENTRY(); + uint32_t i, red, green, blue, value; + uint16_t MaxLutEntriesPerPacket = + MAX_CONFIG_PACKET_DATA_SIZE_DWORD; // each entries consumes 1 DWORDs + uint16_t ActualPacketSize; + + // Optimize to VPEP direct with multiple data + for (i = 0; i < entries; i++) { + // Need to revisit about the new config writer handling , DO WE STILL NEED IT? + // Yes, this is to ensure how many "packets" we need due to each packet have max data size + // i.e. need to split into diff packets (but might still in one direct config descriptor) + // The new config writer handles the "descriptor" size exceeded issue. + // i.e. need to split into diff direct config descriptors. + if (i % MaxLutEntriesPerPacket == 0) { // need generate one another new packet + if ((entries - i) < + MaxLutEntriesPerPacket) // Single packet is big enough to contain remaining entries + MaxLutEntriesPerPacket = (uint16_t)(entries - i); + + ActualPacketSize = MaxLutEntriesPerPacket; + + VPE_ASSERT(ActualPacketSize <= MAX_CONFIG_PACKET_DATA_SIZE_DWORD); + packet.bits.INC = 0; + packet.bits.VPEP_CONFIG_DATA_SIZE = + ActualPacketSize - 1; // number of "continuous" dwords, 1-based + packet.bits.VPEP_CONFIG_REGISTER_OFFSET = REG_OFFSET(VPMPC_RMCM_3DLUT_DATA_30BIT); + + config_writer_fill_direct_config_packet_header(config_writer, &packet); + } + + red = lut[i].red; + green = lut[i].green; + blue = lut[i].blue; + // should we shift red 22bit and green 12? + // Yes, accroding to spec. + // let's do it instead of just shift 10 bits + value = (red << 22) | (green << 12) | blue << 2; + + config_writer_fill(config_writer, REG_FIELD_VALUE(VPMPC_RMCM_3DLUT_DATA_30BIT, value)); + } +} + +static void vpe20_mpc_set_3dlut_mode( + struct mpc *mpc, enum vpe_lut_mode mode, bool is_lut_size17x17x17) +{ + PROGRAM_ENTRY(); + uint32_t lut_mode; + + if (mode == LUT_BYPASS) + lut_mode = 0; + else if (mode == LUT_RAM_A) + lut_mode = 1; + else + lut_mode = 2; + + // 0 = 17x17x17, 1 = 9x9x9, 2 = 33x33x33 + // VPE2 does not support 9x9x9 + REG_SET_2(VPMPC_RMCM_3DLUT_MODE, 0, VPMPC_RMCM_3DLUT_MODE, lut_mode, VPMPC_RMCM_3DLUT_SIZE, + is_lut_size17x17x17 == true ? 0 : 2); +} + +// using direct config to program the 3dlut specified in params +void vpe20_mpc_program_3dlut(struct mpc *mpc, const struct tetrahedral_params *params) +{ + PROGRAM_ENTRY(); + enum vpe_lut_mode mode; + bool is_17x17x17; + bool is_12bits_color_channel; + const struct vpe_rgb *lut0; + const struct vpe_rgb *lut1; + const struct vpe_rgb *lut2; + const struct vpe_rgb *lut3; + uint32_t lut_size0; + uint32_t lut_size; + + if (params == NULL) { + vpe20_mpc_set_3dlut_mode(mpc, LUT_BYPASS, false); + return; + } + + vpe20_mpc_power_on_1dlut_shaper_3dlut(mpc, true); + + // always use LUT_RAM_A except for bypass mode which is not the case here + mode = LUT_RAM_A; + + is_17x17x17 = (params->lut_dim == LUT_DIM_17); + + is_12bits_color_channel = params->use_12bits; + if (is_17x17x17) { + lut0 = params->tetrahedral_17.lut0; + lut1 = params->tetrahedral_17.lut1; + lut2 = params->tetrahedral_17.lut2; + lut3 = params->tetrahedral_17.lut3; + lut_size0 = sizeof(params->tetrahedral_17.lut0) / sizeof(params->tetrahedral_17.lut0[0]); + lut_size = sizeof(params->tetrahedral_17.lut1) / sizeof(params->tetrahedral_17.lut1[0]); + } + else if (params->lut_dim == LUT_DIM_33) { + lut0 = params->tetrahedral_33.lut0; + lut1 = params->tetrahedral_33.lut1; + lut2 = params->tetrahedral_33.lut2; + lut3 = params->tetrahedral_33.lut3; + lut_size0 = sizeof(params->tetrahedral_33.lut0) / sizeof(params->tetrahedral_33.lut0[0]); + lut_size = sizeof(params->tetrahedral_33.lut1) / sizeof(params->tetrahedral_33.lut1[0]); + } + else { + // 9x9x9 mode not supported on VPE2 + VPE_ASSERT(false); + vpe20_mpc_set_3dlut_mode(mpc, LUT_BYPASS, false); + return; + } + + if (is_12bits_color_channel) + vpe20_mpc_set3dlut_ram12(mpc, lut0, lut_size0); + else + vpe20_mpc_set3dlut_ram10(mpc, lut0, lut_size0); + + if (is_12bits_color_channel) + vpe20_mpc_set3dlut_ram12(mpc, lut1, lut_size); + else + vpe20_mpc_set3dlut_ram10(mpc, lut1, lut_size); + + if (is_12bits_color_channel) + vpe20_mpc_set3dlut_ram12(mpc, lut2, lut_size); + else + vpe20_mpc_set3dlut_ram10(mpc, lut2, lut_size); + + if (is_12bits_color_channel) + vpe20_mpc_set3dlut_ram12(mpc, lut3, lut_size); + else + vpe20_mpc_set3dlut_ram10(mpc, lut3, lut_size); + + vpe20_mpc_set_3dlut_mode(mpc, mode, is_17x17x17); + + if (vpe_priv->init.debug.enable_mem_low_power.bits.mpc) + vpe20_mpc_power_on_1dlut_shaper_3dlut(mpc, false); + + return; +} + +static void vpe20_mpc_set3dlut_ram10_indirect( + struct mpc *mpc, const uint64_t lut_gpuva, uint32_t entries) +{ + PROGRAM_ENTRY(); + + uint32_t data_array_size = entries; // DW size of config data array, actual size + // Optimized by single VPEP indirect config packet + // The layout inside the lut buf must be: (each element is 10bit, but LSB[1:0] are always 0) + // DW0: R0<<22 | G0<<12 | B0 <<2 + // DW0: R1<<22 | G1<<12 | B1 <<2 + //... + + config_writer_set_type(config_writer, CONFIG_TYPE_INDIRECT, mpc->inst); + + // Optimized by single VPEP indirect config packet + // Fill the 3dLut array pointer + config_writer_fill_indirect_data_array(config_writer, lut_gpuva, data_array_size); + + // Start from index 0 + config_writer_fill_indirect_destination( + config_writer, REG_OFFSET(VPMPC_RMCM_3DLUT_INDEX), 0, REG_OFFSET(VPMPC_RMCM_3DLUT_DATA)); + + // resume back to direct + config_writer_set_type(config_writer, CONFIG_TYPE_DIRECT, mpc->inst); +} + +static void vpe20_mpc_set3dlut_ram12_indirect( + struct mpc *mpc, const uint64_t lut_gpuva, uint32_t entries) +{ + PROGRAM_ENTRY(); + // The layout inside the lut buf must be: (each element is 16bit, but LSB[3:0] are always 0) + // DW0: R1<<16 | R0 + // DW1: G1<<16 | G0 + // DW2: B1<<16 | B0 + // DW3: R3<<16 | R2 + // DW4: G3<<16 | G2 + // DW5: B3<<16 | B2 + //... + + uint32_t data_array_size = (entries / 2 * 3); // DW size of config data array, actual size + + config_writer_set_type(config_writer, CONFIG_TYPE_INDIRECT, mpc->inst); + + // Optimized by single VPEP indirect config packet + // Fill the 3dLut array pointer + config_writer_fill_indirect_data_array(config_writer, lut_gpuva, data_array_size); + + // Start from index 0 + config_writer_fill_indirect_destination( + config_writer, REG_OFFSET(VPMPC_RMCM_3DLUT_INDEX), 0, REG_OFFSET(VPMPC_RMCM_3DLUT_DATA)); + + // restore back to direct + config_writer_set_type(config_writer, CONFIG_TYPE_DIRECT, mpc->inst); +} + +// using indirect config to configure the 3DLut +// note that we still need direct config to switch the mask between lut0 - lut3 +bool vpe20_mpc_program_3dlut_indirect(struct mpc *mpc, + struct vpe_buf *lut0_3_buf, // 3d lut buf which contains the data for lut0-lut3 + bool use_tetrahedral_9, bool use_12bits) +{ + PROGRAM_ENTRY(); + enum vpe_lut_mode mode; + bool is_12bits_color_channel; + uint64_t lut0_gpuva; + uint64_t lut1_gpuva; + uint64_t lut2_gpuva; + uint64_t lut3_gpuva; + uint32_t lut_size0; + uint32_t lut_size; + // see struct tetrahedral_17x17x17 definition + const uint32_t tetra17_lut_size = 1228; + + // make sure it is in DIRECT type + config_writer_set_type(config_writer, CONFIG_TYPE_DIRECT, mpc->inst); + + if (lut0_3_buf == NULL || use_tetrahedral_9) { + vpe20_mpc_set_3dlut_mode(mpc, LUT_BYPASS, false); + return false; + } + + vpe20_mpc_power_on_1dlut_shaper_3dlut(mpc, true); + + // always use LUT_RAM_A except for bypass mode which is not the case here + mode = LUT_RAM_A; + + is_12bits_color_channel = use_12bits; + + lut0_gpuva = lut0_3_buf->gpu_va; + lut1_gpuva = lut0_3_buf->gpu_va + (uint64_t)(offsetof(struct tetrahedral_17x17x17, lut1)); + lut2_gpuva = lut0_3_buf->gpu_va + (uint64_t)(offsetof(struct tetrahedral_17x17x17, lut2)); + lut3_gpuva = lut0_3_buf->gpu_va + (uint64_t)(offsetof(struct tetrahedral_17x17x17, lut3)); + lut_size0 = tetra17_lut_size + 1; // lut0 has an extra element (vertex (0,0,0)) + lut_size = tetra17_lut_size; + + if (is_12bits_color_channel) + vpe20_mpc_set3dlut_ram12_indirect(mpc, lut0_gpuva, lut_size0); + else + vpe20_mpc_set3dlut_ram10_indirect(mpc, lut0_gpuva, lut_size0); + + if (is_12bits_color_channel) + vpe20_mpc_set3dlut_ram12_indirect(mpc, lut1_gpuva, lut_size); + else + vpe20_mpc_set3dlut_ram10_indirect(mpc, lut1_gpuva, lut_size); + + if (is_12bits_color_channel) + vpe20_mpc_set3dlut_ram12_indirect(mpc, lut2_gpuva, lut_size); + else + vpe20_mpc_set3dlut_ram10_indirect(mpc, lut2_gpuva, lut_size); + + if (is_12bits_color_channel) + vpe20_mpc_set3dlut_ram12_indirect(mpc, lut3_gpuva, lut_size); + else + vpe20_mpc_set3dlut_ram10_indirect(mpc, lut3_gpuva, lut_size); + + vpe20_mpc_set_3dlut_mode(mpc, mode, !use_tetrahedral_9); // always true here + + if (vpe_priv->init.debug.enable_mem_low_power.bits.mpc) + vpe20_mpc_power_on_1dlut_shaper_3dlut(mpc, false); + + return true; +} + +void vpe20_attach_3dlut_to_mpc_inst(struct mpc *mpc, enum mpc_mpccid mpcc_idx) +{ + PROGRAM_ENTRY(); + + REG_SET(VPMPC_RMCM_CNTL, REG_DEFAULT(VPMPC_RMCM_CNTL), VPMPC_RMCM_CNTL, mpcc_idx); +} + +void vpe20_mpc_set_mpc_shaper_3dlut( + struct mpc *mpc, struct transfer_func *func_shaper, struct vpe_3dlut *lut3d_func) +{ + const struct pwl_params *shaper_lut = NULL; + const struct tetrahedral_params *lut3d_params; + + PROGRAM_ENTRY(); + struct stream_ctx *stream_ctx = &vpe_priv->stream_ctx[vpe_priv->fe_cb_ctx.stream_idx]; + bool bypass; + + // get the shaper lut params + if (func_shaper) { + if (func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { + vpe10_cm_helper_translate_curve_to_hw_format(func_shaper, &mpc->shaper_params, true, + func_shaper->dirty[mpc->inst]); // should init shaper_params first + shaper_lut = &mpc->shaper_params; // are there shaper prams in dpp instead? + } + else if (func_shaper->type == TF_TYPE_HWPWL) { + shaper_lut = &func_shaper->pwl; + } + } + + bypass = (!shaper_lut || (func_shaper && func_shaper->type == TF_TYPE_BYPASS)); + CONFIG_CACHE(func_shaper, stream_ctx, vpe_priv->init.debug.disable_lut_caching, bypass, + mpc->funcs->program_shaper(mpc, shaper_lut), mpc->inst); + + if (lut3d_func && !lut3d_func->state.bits.is_dma) { + bypass = (!lut3d_func || !lut3d_func->state.bits.initialized); + lut3d_params = (bypass) ? (NULL) : (&lut3d_func->lut_3d); + CONFIG_CACHE(lut3d_func, stream_ctx, vpe_priv->init.debug.disable_lut_caching, bypass, + mpc->funcs->program_3dlut(mpc, lut3d_params), mpc->inst); + } + return; +} + +bool vpe20_mpc_program_movable_cm(struct mpc *mpc, struct transfer_func *func_shaper, + struct vpe_3dlut *lut3d_func, struct transfer_func *blend_tf, bool afterblend) +{ + struct pwl_params *params = NULL; + bool ret = false; + + /*program shaper and 3dlut and 1dlut in MPC*/ + /*only 1 3dlut inst so only program once*/ + if ((func_shaper || lut3d_func) && (mpc->funcs->set_mpc_shaper_3dlut != NULL)) + mpc->funcs->set_mpc_shaper_3dlut(mpc, func_shaper, lut3d_func); + mpc->funcs->set_blend_lut(mpc, blend_tf); + mpc->funcs->program_cm_location(mpc, afterblend); + + return ret; +} + +static void vpe20_program_gamut_remap(struct mpc *mpc, + enum mpcc_gamut_remap_id gamut_remap_block_id, const uint16_t *regval, + enum gamut_remap_select select) +{ + uint16_t selection = 0; + struct color_matrices_reg gam_regs; + PROGRAM_ENTRY(); + + switch (gamut_remap_block_id) { + case VPE_MPC_GAMUT_REMAP: + + if (regval == NULL || select == GAMUT_REMAP_BYPASS) { + REG_SET(VPMPCC_GAMUT_REMAP_MODE, 0, VPMPCC_GAMUT_REMAP_MODE, GAMUT_REMAP_BYPASS); + return; + } + + gam_regs.shifts.csc_c11 = REG_FIELD_SHIFT(VPMPCC_GAMUT_REMAP_C11_A); + gam_regs.masks.csc_c11 = REG_FIELD_MASK(VPMPCC_GAMUT_REMAP_C11_A); + gam_regs.shifts.csc_c12 = REG_FIELD_SHIFT(VPMPCC_GAMUT_REMAP_C12_A); + gam_regs.masks.csc_c12 = REG_FIELD_MASK(VPMPCC_GAMUT_REMAP_C12_A); + gam_regs.csc_c11_c12 = REG_OFFSET(VPMPC_GAMUT_REMAP_C11_C12_A); + gam_regs.csc_c33_c34 = REG_OFFSET(VPMPC_GAMUT_REMAP_C33_C34_A); + + vpe10_cm_helper_program_color_matrices(config_writer, regval, &gam_regs); + + REG_SET(VPMPCC_GAMUT_REMAP_MODE, 0, VPMPCC_GAMUT_REMAP_MODE, GAMUT_REMAP_COMA_COEFF); + + break; + + case VPE_MPC_RMCM_GAMUT_REMAP: + if (regval == NULL || select == GAMUT_REMAP_BYPASS) { + REG_SET( + VPMPC_RMCM_GAMUT_REMAP_MODE, 0, VPMPC_RMCM_GAMUT_REMAP_MODE, GAMUT_REMAP_BYPASS); + return; + } + + gam_regs.shifts.csc_c11 = REG_FIELD_SHIFT(VPMPC_RMCM_GAMUT_REMAP_C11_SETA); + gam_regs.masks.csc_c11 = REG_FIELD_MASK(VPMPC_RMCM_GAMUT_REMAP_C11_SETA); + gam_regs.shifts.csc_c12 = REG_FIELD_SHIFT(VPMPC_RMCM_GAMUT_REMAP_C12_SETA); + gam_regs.masks.csc_c12 = REG_FIELD_MASK(VPMPC_RMCM_GAMUT_REMAP_C12_SETA); + gam_regs.csc_c11_c12 = REG_OFFSET(VPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA); + gam_regs.csc_c33_c34 = REG_OFFSET(VPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA); + + vpe10_cm_helper_program_color_matrices(config_writer, regval, &gam_regs); + + REG_SET( + VPMPC_RMCM_GAMUT_REMAP_MODE, 0, VPMPC_RMCM_GAMUT_REMAP_MODE, GAMUT_REMAP_COMA_COEFF); + + break; + + case VPE_MPC_MCM_FIRST_GAMUT_REMAP: + if (regval == NULL || select == GAMUT_REMAP_BYPASS) { + REG_SET(VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE, 0, VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE, + GAMUT_REMAP_BYPASS); + return; + } + + gam_regs.shifts.csc_c11 = REG_FIELD_SHIFT(VPMPCC_MCM_FIRST_GAMUT_REMAP_C11_SETA); + gam_regs.masks.csc_c11 = REG_FIELD_MASK(VPMPCC_MCM_FIRST_GAMUT_REMAP_C11_SETA); + gam_regs.shifts.csc_c12 = REG_FIELD_SHIFT(VPMPCC_MCM_FIRST_GAMUT_REMAP_C12_SETA); + gam_regs.masks.csc_c12 = REG_FIELD_MASK(VPMPCC_MCM_FIRST_GAMUT_REMAP_C12_SETA); + gam_regs.csc_c11_c12 = REG_OFFSET(VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA); + gam_regs.csc_c33_c34 = REG_OFFSET(VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA); + + vpe10_cm_helper_program_color_matrices(config_writer, regval, &gam_regs); + + REG_SET(VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE, 0, VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE, + GAMUT_REMAP_COMA_COEFF); + + break; + + case VPE_MPC_MCM_SECOND_GAMUT_REMAP: + + if (regval == NULL || select == GAMUT_REMAP_BYPASS) { + REG_SET(VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE, 0, VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE, + GAMUT_REMAP_BYPASS); + return; + } + + gam_regs.shifts.csc_c11 = REG_FIELD_SHIFT(VPMPCC_MCM_SECOND_GAMUT_REMAP_C11_SETA); + gam_regs.masks.csc_c11 = REG_FIELD_MASK(VPMPCC_MCM_SECOND_GAMUT_REMAP_C11_SETA); + gam_regs.shifts.csc_c12 = REG_FIELD_SHIFT(VPMPCC_MCM_SECOND_GAMUT_REMAP_C12_SETA); + gam_regs.masks.csc_c12 = REG_FIELD_MASK(VPMPCC_MCM_SECOND_GAMUT_REMAP_C12_SETA); + gam_regs.csc_c11_c12 = REG_OFFSET(VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA); + gam_regs.csc_c33_c34 = REG_OFFSET(VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA); + + vpe10_cm_helper_program_color_matrices(config_writer, regval, &gam_regs); + + REG_SET(VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE, 0, VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE, + GAMUT_REMAP_COMA_COEFF); + break; + + default: + VPE_ASSERT(0); + break; + } +} + +void vpe20_mpc_set_gamut_remap2(struct mpc *mpc, struct colorspace_transform *gamut_remap, + enum mpcc_gamut_remap_id mpcc_gamut_remap_block_id) +{ + uint16_t arr_reg_val[12] = {0}; // Initialize to zero + PROGRAM_ENTRY(); + int i = 0; + + enum gamut_remap_select gamutSel = GAMUT_REMAP_COMA_COEFF; + + if (!gamut_remap || !gamut_remap->enable_remap) + gamutSel = GAMUT_REMAP_BYPASS; + else { + conv_convert_float_matrix(arr_reg_val, gamut_remap->matrix, 12); + } + + vpe20_program_gamut_remap(mpc, mpcc_gamut_remap_block_id, + (gamutSel == GAMUT_REMAP_COMA_COEFF) ? arr_reg_val : NULL, gamutSel); +} + +void vpe20_update_3dlut_fl_bias_scale(struct mpc *mpc, uint16_t bias, uint16_t scale) +{ + PROGRAM_ENTRY(); + + REG_SET_2(VPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE, 0, VPCDC0_3DLUT_FL_BIAS, bias, + VPCDC0_3DLUT_FL_SCALE, scale); +} + +void vpe20_mpc_program_3dlut_fl_config(struct mpc *mpc, enum vpe_3dlut_mem_layout layout, + enum vpe_3dlut_mem_format format, bool enable) +{ + PROGRAM_ENTRY(); + + if (enable) { + REG_SET(VPMPC_RMCM_3DLUT_FAST_LOAD_SELECT, 0, VPMPC_RMCM_3DLUT_FL_SEL, + MPC_RMCM_3DLUT_FL_ENABLE); + REG_SET_2(VPMPC_VPCDC0_3DLUT_FL_CONFIG, 0, VPCDC0_3DLUT_FL_MODE, layout, + VPCDC0_3DLUT_FL_FORMAT, format); + } else + REG_SET(VPMPC_RMCM_3DLUT_FAST_LOAD_SELECT, 0, VPMPC_RMCM_3DLUT_FL_SEL, + MPC_RMCM_3DLUT_FL_DISABLE); +} + +void vpe20_mpc_program_3dlut_fl(struct mpc *mpc, enum lut_dimension lut_dimension, bool use_12bit) +{ + PROGRAM_ENTRY(); + enum vpe_lut_mode mode = LUT_RAM_A; + + vpe20_mpc_power_on_1dlut_shaper_3dlut(mpc, true); + + // always use LUT_RAM_A except for bypass mode which is not the case here + vpe20_mpc_set_3dlut_mode(mpc, mode, lut_dimension == LUT_DIM_17 ? 1 : 0); + + if (vpe_priv->init.debug.enable_mem_low_power.bits.mpc) + vpe20_mpc_power_on_1dlut_shaper_3dlut(mpc, false); +} diff --git a/src/amd/vpelib/src/chip/vpe20/vpe20_opp.c b/src/amd/vpelib/src/chip/vpe20/vpe20_opp.c new file mode 100644 index 00000000000..e123eb3920c --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/vpe20_opp.c @@ -0,0 +1,335 @@ +/* Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include +#include "common.h" +#include "vpe_priv.h" +#include "vpe20_opp.h" +#include "hw_shared.h" +#include "reg_helper.h" +#include "custom_fp16.h" + +#define CTX_BASE opp +#define CTX vpe20_opp + +static struct opp_funcs opp20_funcs = { + .program_pipe_control = vpe20_opp_program_pipe_control, + .program_pipe_crc = vpe20_opp_program_pipe_crc, + .set_clamping = vpe10_opp_set_clamping, + .program_bit_depth_reduction = vpe20_opp_program_bit_depth_reduction, + .set_dyn_expansion = vpe10_opp_set_dyn_expansion, + .program_fmt = vpe10_opp_program_fmt, + .program_fmt_control = vpe20_opp_program_fmt_control, + .build_fmt_subsample_params = vpe20_opp_build_fmt_subsample_params, + .set_bg = vpe20_opp_set_bg, + .program_frod = vpe20_opp_program_frod, + .get_fmt_extra_pixel = vpe20_opp_get_fmt_extra_pixel, +}; + +enum fmt_pixel { + PIXEL_ENCODING_RGB444_YCBCR444 = 0, + PIXEL_ENCODING_YCBCR422 = 1, + PIXEL_ENCODING_YCBCR420 = 2 +}; + +enum fmt_taps { + TAPS2 = 0, + TAPS3 = 1, + TAPS4 = 2, + TAPS5 = 3 +}; + +void vpe20_construct_opp(struct vpe_priv *vpe_priv, struct opp *opp) +{ + opp->vpe_priv = vpe_priv; + opp->funcs = &opp20_funcs; +} + +void vpe20_opp_program_pipe_control(struct opp *opp, const struct opp_pipe_control_params *params) +{ + PROGRAM_ENTRY(); + REG_SET_3(VPOPP_PIPE_CONTROL, REG_DEFAULT(VPOPP_PIPE_CONTROL), VPOPP_PIPE_ALPHA, params->alpha, + VPOPP_PIPE_DIGITAL_BYPASS_EN, params->bypass_enable, VPOPP_PIPE_ALPHA_SEL, + params->alpha_select); +} + +void vpe20_opp_program_pipe_crc(struct opp *opp, bool enable) +{ + PROGRAM_ENTRY(); + // REG_SET(VPOPP_PIPE_CRC_CONTROL, REG_DEFAULT(VPOPP_PIPE_CRC_CONTROL), VPOPP_PIPE_CRC_EN, + // enable); +} + +static void get_fmt_chroma_taps(enum vpe_surface_pixel_format format, + enum subsampling_quality subsample_quality, enum chroma_cositing cositing, + struct chroma_taps *ctaps) +{ + memset(ctaps, 0, sizeof(*ctaps)); + + if (vpe_is_yuv420(format)) { + ctaps->v_taps_c = 2; + ctaps->h_taps_c = 2; + switch (cositing) { + case CHROMA_COSITING_LEFT: + ctaps->h_taps_c = 3; + break; + case CHROMA_COSITING_TOPLEFT: + ctaps->v_taps_c = 3; + ctaps->h_taps_c = 3; + break; + default: + break; + } + if (subsample_quality == SUBSAMPLING_QUALITY_HIGH) { + ctaps->v_taps_c += 2; + ctaps->h_taps_c += 2; + } + } else if (vpe_is_yuv422(format)) { + if (subsample_quality == SUBSAMPLING_QUALITY_HIGH) + ctaps->h_taps_c = 5; + else + ctaps->h_taps_c = 3; + } +} + +void vpe20_opp_build_fmt_subsample_params(struct opp *opp, enum vpe_surface_pixel_format format, + enum subsampling_quality subsample_quality, enum chroma_cositing cositing, + struct fmt_boundary_mode boundary_mode, struct fmt_subsampling_params *subsample_params) +{ + PROGRAM_ENTRY(); + + struct chroma_taps ctaps; + + uint32_t pixel_encoding = PIXEL_ENCODING_RGB444_YCBCR444; + uint32_t bit_reduction_bypass = 0; + uint32_t vtaps = 0; + uint32_t htaps = 0; + + if (!subsample_params) + return; + + get_fmt_chroma_taps(format, subsample_quality, cositing, &ctaps); + + if (vpe_is_yuv420(format)) { + pixel_encoding = PIXEL_ENCODING_YCBCR420; + bit_reduction_bypass = 1; + } else if (vpe_is_yuv422(format)) { + pixel_encoding = PIXEL_ENCODING_YCBCR422; + bit_reduction_bypass = 1; + } else { + pixel_encoding = PIXEL_ENCODING_RGB444_YCBCR444; + } + + switch (ctaps.h_taps_c) { + case 2: + htaps = TAPS2; + break; + case 3: + htaps = TAPS3; + break; + case 4: + htaps = TAPS4; + break; + case 5: + htaps = TAPS5; + break; + default: + break; + } + + switch (ctaps.v_taps_c) { + case 2: + vtaps = TAPS2; + break; + case 3: + vtaps = TAPS3; + break; + case 4: + vtaps = TAPS4; + break; + case 5: + vtaps = TAPS5; + break; + default: + break; + } + + subsample_params->pixel_encoding = pixel_encoding; + subsample_params->bit_reduction_bypass = bit_reduction_bypass; + subsample_params->htaps = htaps; + subsample_params->vtaps = vtaps; + subsample_params->boundary_mode = boundary_mode; +} + +void vpe20_opp_program_fmt_control(struct opp *opp, struct fmt_control_params *fmt_ctrl) +{ + PROGRAM_ENTRY(); + + REG_SET_10(VPFMT_CONTROL, REG_DEFAULT(VPFMT_CONTROL), VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, + fmt_ctrl->fmt_spatial_dither_frame_counter_max, VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, + fmt_ctrl->fmt_spatial_dither_frame_counter_bit_swap, VPFMT_PIXEL_ENCODING, + fmt_ctrl->subsampling_params.pixel_encoding, VPFMT_CBCR_BIT_REDUCTION_BYPASS, + fmt_ctrl->subsampling_params.bit_reduction_bypass, VPFMT_SUBSAMPLE_HTAPS, + fmt_ctrl->subsampling_params.htaps, VPFMT_SUBSAMPLE_VTAPS, + fmt_ctrl->subsampling_params.vtaps, VPFMT_SUBSAMPLE_BOTTOM_EDGE, + fmt_ctrl->subsampling_params.boundary_mode.bottom, VPFMT_SUBSAMPLE_TOP_EDGE, + fmt_ctrl->subsampling_params.boundary_mode.top, VPFMT_SUBSAMPLE_RIGHT_EDGE, + fmt_ctrl->subsampling_params.boundary_mode.right, VPFMT_SUBSAMPLE_LEFT_EDGE, + fmt_ctrl->subsampling_params.boundary_mode.left); +} + +void vpe20_opp_set_bg(struct opp* opp, struct vpe_rect target_rect, struct vpe_rect dst_rect, + enum vpe_surface_pixel_format format, struct vpe_color bgcolor) +{ + PROGRAM_ENTRY(); + + uint32_t top_lines, bot_lines, left_lines, right_lines; + uint16_t r_cr, g_y, b_cb; + top_lines = dst_rect.y >= target_rect.y ? dst_rect.y - target_rect.y : 0; + bot_lines = (target_rect.y + target_rect.height) >= (dst_rect.y + dst_rect.height) + ? (target_rect.y + target_rect.height) - (dst_rect.y + dst_rect.height) + : 0; + left_lines = dst_rect.x >= target_rect.x ? dst_rect.x - target_rect.x : 0; + right_lines = (target_rect.x + target_rect.width) >= (dst_rect.x + dst_rect.width) + ? (target_rect.x + target_rect.width) - (dst_rect.x + dst_rect.width) + : 0; + + if (vpe_is_fp16(format)) { + vpe_convert_from_float_to_fp16(bgcolor.rgba.r, &r_cr); + vpe_convert_from_float_to_fp16(bgcolor.rgba.g, &g_y); + vpe_convert_from_float_to_fp16(bgcolor.rgba.b, &b_cb); + } else if (bgcolor.is_ycbcr) { + g_y = (uint16_t)(bgcolor.ycbcra.y * 0xffff); + r_cr = (uint16_t)(bgcolor.ycbcra.cr * 0xffff); + b_cb = (uint16_t)(bgcolor.ycbcra.cb * 0xffff); + } else { + r_cr = (uint16_t)(bgcolor.rgba.r * 0xffff); + g_y = (uint16_t)(bgcolor.rgba.g * 0xffff); + b_cb = (uint16_t)(bgcolor.rgba.b * 0xffff); + } + + if (vpe_is_yuv420(format)) { + if (top_lines % 2 != 0) + top_lines += 1; + if (bot_lines % 2 != 0) + bot_lines += 1; + if (left_lines % 2 != 0) + left_lines += 1; + if (right_lines % 2 != 0) + right_lines += 1; + } else if (vpe_is_yuv422(format)) { + if (left_lines % 2 != 0) + left_lines += 1; + if (right_lines % 2 != 0) + right_lines += 1; + } + + REG_SET_2(VPOPP_PIPE_OUTBG_EXT1, 0, OUTBG_EXT_TOP, top_lines, OUTBG_EXT_BOT, bot_lines); + REG_SET_2(VPOPP_PIPE_OUTBG_EXT2, 0, OUTBG_EXT_LEFT, left_lines, OUTBG_EXT_RIGHT, right_lines); + + REG_SET_2(VPOPP_PIPE_OUTBG_COL1, 0, OUTBG_R_CR, r_cr, OUTBG_B_CB, b_cb); + REG_SET(VPOPP_PIPE_OUTBG_COL2, 0, OUTBG_Y, g_y); +} + +void vpe20_opp_program_frod(struct opp *opp, struct opp_frod_param *frod_param) +{ + PROGRAM_ENTRY(); + REG_SET(VPOPP_FROD_CONTROL, 0, FROD_EN, frod_param->enable_frod); +} + +void vpe20_opp_get_fmt_extra_pixel(enum vpe_surface_pixel_format format, + enum subsampling_quality subsample_quality, enum chroma_cositing cositing, + struct fmt_extra_pixel_info *extra_pixel) +{ + (void)format; + (void)subsample_quality; + (void)cositing; + + extra_pixel->left_pixels = 2; + extra_pixel->right_pixels = 1; + extra_pixel->top_pixels = 2; + extra_pixel->bottom_pixels = 1; +} + +void vpe20_opp_program_bit_depth_reduction( + struct opp *opp, const struct bit_depth_reduction_params *params) +{ + PROGRAM_ENTRY(); + + if (params->flags.SPATIAL_DITHER_ENABLED == 0) { + /*Disable spatial (random) dithering*/ + REG_SET_9(VPFMT_BIT_DEPTH_CONTROL, REG_DEFAULT(VPFMT_BIT_DEPTH_CONTROL), VPFMT_TRUNCATE_EN, + params->flags.TRUNCATE_ENABLED, VPFMT_TRUNCATE_DEPTH, params->flags.TRUNCATE_DEPTH, + VPFMT_TRUNCATE_MODE, params->flags.TRUNCATE_MODE, VPFMT_SPATIAL_DITHER_EN, 0, + VPFMT_SPATIAL_DITHER_MODE, 0, VPFMT_SPATIAL_DITHER_DEPTH, 0, + VPFMT_HIGHPASS_RANDOM_ENABLE, 0, VPFMT_FRAME_RANDOM_ENABLE, 0, VPFMT_RGB_RANDOM_ENABLE, + 0); + + return; + } + + /* Set seed for random values for + * spatial dithering for R,G,B channels + */ + REG_SET(VPFMT_DITHER_RAND_R_SEED, 0, VPFMT_RAND_R_SEED, params->r_seed_value); + + REG_SET(VPFMT_DITHER_RAND_G_SEED, 0, VPFMT_RAND_G_SEED, params->g_seed_value); + + REG_SET(VPFMT_DITHER_RAND_B_SEED, 0, VPFMT_RAND_B_SEED, params->b_seed_value); + + /* FMT_OFFSET_R_Cr 31:16 0x0 Setting the zero + * offset for the R/Cr channel, lower 4LSB + * is forced to zeros. Typically set to 0 + * RGB and 0x80000 YCbCr. + */ + /* FMT_OFFSET_G_Y 31:16 0x0 Setting the zero + * offset for the G/Y channel, lower 4LSB is + * forced to zeros. Typically set to 0 RGB + * and 0x80000 YCbCr. + */ + /* FMT_OFFSET_B_Cb 31:16 0x0 Setting the zero + * offset for the B/Cb channel, lower 4LSB is + * forced to zeros. Typically set to 0 RGB and + * 0x80000 YCbCr. + */ + + REG_SET_9(VPFMT_BIT_DEPTH_CONTROL, REG_DEFAULT(VPFMT_BIT_DEPTH_CONTROL), VPFMT_TRUNCATE_EN, + params->flags.TRUNCATE_ENABLED, VPFMT_TRUNCATE_DEPTH, params->flags.TRUNCATE_DEPTH, + VPFMT_TRUNCATE_MODE, params->flags.TRUNCATE_MODE, + /*Enable spatial dithering*/ + VPFMT_SPATIAL_DITHER_EN, params->flags.SPATIAL_DITHER_ENABLED, + /* Set spatial dithering mode + * (default is Seed patterrn AAAA...) + */ + VPFMT_SPATIAL_DITHER_MODE, params->flags.SPATIAL_DITHER_MODE, + /*Set spatial dithering bit depth*/ + VPFMT_SPATIAL_DITHER_DEPTH, params->flags.SPATIAL_DITHER_DEPTH, + /*Disable High pass filter*/ + VPFMT_HIGHPASS_RANDOM_ENABLE, params->flags.HIGHPASS_RANDOM, + /*Reset only at startup*/ + VPFMT_FRAME_RANDOM_ENABLE, params->flags.FRAME_RANDOM, + /*Set RGB data dithered with x^28+x^3+1*/ + VPFMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM); +} + diff --git a/src/amd/vpelib/src/chip/vpe20/vpe20_plane_desc_writer.c b/src/amd/vpelib/src/chip/vpe20/vpe20_plane_desc_writer.c new file mode 100644 index 00000000000..c367c7a3553 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/vpe20_plane_desc_writer.c @@ -0,0 +1,231 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "vpe_assert.h" +#include "vpe20_command.h" +#include "vpe20_plane_desc_writer.h" +#include "reg_helper.h" + +void vpe20_construct_plane_desc_writer(struct plane_desc_writer *writer) +{ + writer->init = vpe20_plane_desc_writer_init; + writer->add_source = vpe20_plane_desc_writer_add_source; + writer->add_destination = vpe20_plane_desc_writer_add_destination; + writer->add_meta = vpe20_plane_desc_writer_add_meta; + writer->add_histo = vpe20_plane_desc_writer_add_hist_destination; +} + +void vpe20_plane_desc_writer_init( + struct plane_desc_writer *writer, struct vpe_buf *buf, void *p_header) +{ + uint32_t *cmd_space; + uint64_t size = 4; + struct vpe20_plane_desc_header *header = (struct vpe20_plane_desc_header *)p_header; + + // For VPE 2.0 all config and plane descriptors gpu address must be 6 bit aligned + uint64_t aligned_gpu_address = + (buf->gpu_va + VPE_PLANE_ADDR_ALIGNMENT_MASK) & ~VPE_PLANE_ADDR_ALIGNMENT_MASK; + uint64_t alignment_offset = aligned_gpu_address - buf->gpu_va; + buf->gpu_va = aligned_gpu_address; + buf->cpu_va = buf->cpu_va + alignment_offset; + + if (buf->size < alignment_offset) { + writer->status = VPE_STATUS_BUFFER_OVERFLOW; + return; + } + buf->size -= alignment_offset; + + writer->status = VPE_STATUS_OK; + writer->base_cpu_va = buf->cpu_va; + writer->base_gpu_va = buf->gpu_va; + writer->buf = buf; + writer->num_src = 0; + writer->num_dst = 0; + + /* Buffer does not have enough space to write */ + if (buf->size < size) { + writer->status = VPE_STATUS_BUFFER_OVERFLOW; + return; + } + + cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va; + + *cmd_space++ = VPE_PLANE_CFG_CMD_HEADER(header->subop, header->nps0, header->npd0, header->nps1, + header->npd1, header->dcomp0, header->dcomp1, header->frod, header->hist0_dsets, + header->hist1_dsets); + + writer->buf->cpu_va += size; + writer->buf->gpu_va += size; + writer->buf->size -= size; +} + +/** fill the value to the embedded buffer. */ +void vpe20_plane_desc_writer_add_source( + struct plane_desc_writer *writer, void *p_source, bool is_plane0) +{ + uint32_t *cmd_space, *cmd_start; + uint32_t num_wd = is_plane0 ? 6 : 5; + uint64_t size = num_wd * sizeof(uint32_t); + struct vpe20_plane_desc_src *src = (struct vpe20_plane_desc_src *)p_source; + + if (writer->status != VPE_STATUS_OK) + return; + + /* Buffer does not have enough space to write */ + if (writer->buf->size < size) { + writer->status = VPE_STATUS_BUFFER_OVERFLOW; + return; + } + cmd_start = cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va; + + if (is_plane0) { + *cmd_space++ = VPEC_FIELD_VALUE(VPE_PLANE_CFG_TMZ, src->tmz) | + VPEC_FIELD_VALUE(VPE_PLANE_CFG_SWIZZLE_MODE, src->swizzle) | + VPEC_FIELD_VALUE(VPE_PLANE_CFG_SCAN_PATTERN, src->scan); + } + + VPE_ASSERT(!(src->base_addr_lo & 0xFF)); + + *cmd_space++ = src->base_addr_lo; + *cmd_space++ = src->base_addr_hi; + + *cmd_space++ = VPEC_FIELD_VALUE(VPE_PLANE_CFG_PITCH, src->pitch - 1) | + VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_ELEMENT_SIZE, src->elem_size); + *cmd_space++ = VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_X, src->viewport_x) | + VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_Y, src->viewport_y); + *cmd_space++ = VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_WIDTH, src->viewport_w - 1) | + VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_HEIGHT, src->viewport_h - 1); + + writer->buf->cpu_va += size; + writer->buf->gpu_va += size; + writer->buf->size -= size; +} + +/** fill the value to the embedded buffer. */ +void vpe20_plane_desc_writer_add_destination( + struct plane_desc_writer *writer, void *p_destination, bool write_header) +{ + uint32_t *cmd_space, *cmd_start; + uint32_t num_wd = write_header ? 6 : 5; + uint64_t size = num_wd * sizeof(uint32_t); + struct vpe20_plane_desc_dst *dst = (struct vpe20_plane_desc_dst *)p_destination; + + if (writer->status != VPE_STATUS_OK) + return; + + /* Buffer does not have enough space to write */ + if (writer->buf->size < size) { + writer->status = VPE_STATUS_BUFFER_OVERFLOW; + return; + } + + cmd_start = cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va; + + if (write_header) { + *cmd_space++ = VPEC_FIELD_VALUE(VPE_PLANE_CFG_TMZ, dst->tmz) | + VPEC_FIELD_VALUE(VPE_PLANE_CFG_SWIZZLE_MODE, dst->swizzle); + } + writer->num_dst++; + + VPE_ASSERT(!(dst->base_addr_lo & 0xFF)); + + *cmd_space++ = dst->base_addr_lo; + *cmd_space++ = dst->base_addr_hi; + + *cmd_space++ = VPEC_FIELD_VALUE(VPE_PLANE_CFG_PITCH, dst->pitch - 1) | + VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_ELEMENT_SIZE, dst->elem_size); + + *cmd_space++ = VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_X, dst->viewport_x) | + VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_Y, dst->viewport_y); + *cmd_space++ = VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_WIDTH, dst->viewport_w - 1) | + VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_HEIGHT, dst->viewport_h - 1); + + writer->buf->cpu_va += size; + writer->buf->gpu_va += size; + writer->buf->size -= size; +} + +void vpe20_plane_desc_writer_add_meta(struct plane_desc_writer *writer, void *p_source) +{ + uint32_t *cmd_space, *cmd_start; + uint32_t num_wd = 3; + uint64_t size = num_wd * sizeof(uint32_t); + struct vpe20_plane_desc_src *src = (struct vpe20_plane_desc_src *)p_source; + + if (writer == NULL || src == NULL) + return; + + if (writer->status != VPE_STATUS_OK) + return; + + /* Buffer does not have enough space to write */ + if (writer->buf->size < size) { + writer->status = VPE_STATUS_BUFFER_OVERFLOW; + return; + } + cmd_start = cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va; + + *cmd_space++ = src->meta_base_addr_lo | VPEC_FIELD_VALUE(VPE_PLANE_CFG_META_TMZ, src->tmz); + *cmd_space++ = src->meta_base_addr_hi; + *cmd_space++ = VPEC_FIELD_VALUE(VPE_PLANE_CFG_META_PITCH, src->meta_pitch - 1) | + VPEC_FIELD_VALUE(VPE_PLANE_CFG_PIXEL_FORMAT, src->format) | + VPEC_FIELD_VALUE(VPE_PLANE_CFG_INDEPENDENT_BLOCKS, src->dcc_ind_blk) | + VPEC_FIELD_VALUE(VPE_PLANE_CFG_PA, 0); + writer->buf->cpu_va += size; + writer->buf->gpu_va += size; + writer->buf->size -= size; +} + +void vpe20_plane_desc_writer_add_hist_destination(struct plane_desc_writer *writer, + void *p_destination, uint32_t hist_idx, uint8_t hist_dsets_array[]) +{ + uint32_t* cmd_space, * cmd_start; + uint32_t num_wd = (hist_idx == 0) ? 3 : 2; + uint64_t size = num_wd * sizeof(uint32_t); + struct vpe20_plane_desc_dst *dst = (struct vpe20_plane_desc_dst *)p_destination; + + if (writer->status != VPE_STATUS_OK) + return; + + /* Buffer does not have enough space to write */ + if (writer->buf->size < size) { + writer->status = VPE_STATUS_BUFFER_OVERFLOW; + return; + } + + cmd_start = cmd_space = (uint32_t*)(uintptr_t)writer->buf->cpu_va; + + if (hist_idx == 0) { + *cmd_space++ = 2; // Number of bytes of each data set 2^(8+2) = 1024 + } // equal to 256bins * 4bytes per bin + writer->num_dst++; + VPE_ASSERT(!(dst->base_addr_lo & 0xFF)); + + *cmd_space++ = dst->base_addr_lo; + *cmd_space++ = dst->base_addr_hi; + + writer->buf->cpu_va += size; + writer->buf->gpu_va += size; + writer->buf->size -= size; +} diff --git a/src/amd/vpelib/src/chip/vpe20/vpe20_resource.c b/src/amd/vpelib/src/chip/vpe20/vpe20_resource.c new file mode 100644 index 00000000000..059c668ee03 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/vpe20_resource.c @@ -0,0 +1,3374 @@ +/* Copyright 2024-2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include +#include "vpe_priv.h" +#include "common.h" +#include "vpe20_cmd_builder.h" +#include "vpe20_vpe_desc_writer.h" +#include "vpe20_plane_desc_writer.h" +#include "vpe20_config_writer.h" +#include "vpe20_resource.h" +#include "vpe10_resource.h" +#include "vpe10_vpec.h" +#include "vpe10_cdc_fe.h" +#include "vpe10_cdc_be.h" +#include "vpe20_cdc_fe.h" +#include "vpe20_cdc_be.h" +#include "vpe10_dpp.h" +#include "vpe20_dpp.h" +#include "vpe10_mpc.h" +#include "vpe20_mpc.h" +#include "vpe10_opp.h" +#include "vpe20_opp.h" +#include "vpe10_background.h" +#include "vpe20/inc/asic/chip_offset.h" +#include "vpe20/inc/asic/chip_mask.h" +#include "vpe20/inc/asic/chip_shift.h" +#include "vpe20/inc/asic/chip_default.h" +#include "custom_fp16.h" +#include "custom_float.h" +#include "background.h" +#include "vpe_visual_confirm.h" +#include "vpe_spl_translation.h" +#include "SPL/dc_spl.h" +#include "multi_pipe_segmentation.h" + +#define LUT_NUM_ENTRIES (17 * 17 * 17) +#define LUT_ENTRY_SIZE (2) +#define LUT_NUM_COMPONENT (3) +#define LUT_BUFFER_SIZE (LUT_NUM_ENTRIES * LUT_ENTRY_SIZE * LUT_NUM_COMPONENT) + +#define LUT_FL_SIZE_17X17X17 (4916) +#define LUT_FL_SIZE_33X33X33 (35940) + +#define BYTES_PER_ENTRY (4) +#define SHAPER_LUT_CHANNELS (3) +#define SHAPER_LUT_DATA_POINTS_PER_CHANNEL (256) +#define SHAPER_LUT_CONFIG_ENTRIES (28) +#define SHAPER_LUT_DMA_DATA_SIZE \ + (SHAPER_LUT_DATA_POINTS_PER_CHANNEL * SHAPER_LUT_CHANNELS * BYTES_PER_ENTRY) +#define SHAPER_LUT_DMA_CONFIG_SIZE \ + (SHAPER_LUT_CONFIG_ENTRIES * (BYTES_PER_ENTRY + SHAPER_LUT_DMA_CONFIG_PADDING)) +#define SHAPER_LUT_DMA_DATA_ALIGNMENT (64) +#define SHAPER_LUT_DMA_CONFIG_ALIGNMENT (64) +#define SHAPER_LUT_DMA_CONFIG_PADDING (60) +#define LUT_3D_DMA_ALIGNMENT (256) + +// 0.92f is the max studio range value in floating point +#define BG_COLOR_STUDIO_PQ_MAX_THRESHOLD 0.92f + +// set field/register/bitfield name +#define SFRB(field_name, reg_name, post_fix) .field_name = reg_name##__##field_name##post_fix + +// #ifdef SOC_BRINGUP + +#define SRIDFVL(reg_name, block, id) \ + .reg_name = {mm##block##id##_##reg_name, mm##block##id##_##reg_name##_##DEFAULT, \ + mm##block##id##_##reg_name##_##DEFAULT, false} + +#define SRIDFVL1(reg_name) \ + .reg_name = {mm##reg_name, mm##reg_name##_##DEFAULT, mm##reg_name##_##DEFAULT, false} + +#define SRIDFVL2(reg_name, block, id) \ + .block##_##reg_name = {mm##block##id##_##reg_name, mm##block##id##_##reg_name##_##DEFAULT, \ + mm##block##id##_##reg_name##_##DEFAULT, false} + +#define SRIDFVL3(reg_name, block, id) \ + .block##_##reg_name = {mm##block##_##reg_name, mm##block##_##reg_name##_##DEFAULT, \ + mm##block##_##reg_name##_##DEFAULT, false} + +#define SRIDFVL_CDC(reg_name, block, id) \ + .block##0##_##reg_name = {mm##block##id##_##reg_name, mm##block##id##_##reg_name##_##DEFAULT, \ + mm##block##id##_##reg_name##_##DEFAULT, false} + +/***************** CDC FE registers ****************/ +#define cdc_fe_regs(id) [id] = {CDC_FE_REG_LIST_VPE20(id)} + +static struct vpe20_cdc_fe_registers cdc_fe_regs[] = {cdc_fe_regs(0), cdc_fe_regs(1)}; + +static const struct vpe20_cdc_fe_shift cdc_fe_shift = {CDC_FE_FIELD_LIST_VPE20(__SHIFT)}; + +static const struct vpe20_cdc_fe_mask cdc_fe_mask = {CDC_FE_FIELD_LIST_VPE20(_MASK)}; + +/***************** CDC BE registers ****************/ +#define cdc_be_regs(id) [id] = {CDC_BE_REG_LIST_VPE20(id)} +static struct vpe20_cdc_be_registers cdc_be_regs[] = { + cdc_be_regs(0), cdc_be_regs(1), cdc_be_regs(2), cdc_be_regs(3)}; + +static const struct vpe20_cdc_be_shift cdc_be_shift = {CDC_BE_FIELD_LIST_VPE20(__SHIFT)}; + +static const struct vpe20_cdc_be_mask cdc_be_mask = {CDC_BE_FIELD_LIST_VPE20(_MASK)}; + +/***************** DPP registers ****************/ +#define dpp_regs(id) [id] = {DPP_REG_LIST_VPE20(id)} + +static struct vpe20_dpp_registers dpp_regs[] = {dpp_regs(0), dpp_regs(1)}; + +static const struct vpe20_dpp_shift dpp_shift = {DPP_FIELD_LIST_VPE20(__SHIFT)}; + +static const struct vpe20_dpp_mask dpp_mask = {DPP_FIELD_LIST_VPE20(_MASK)}; + +/***************** OPP registers ****************/ +#define opp_regs(id) [id] = {OPP_REG_LIST_VPE20(id)} + +static struct vpe20_opp_registers opp_regs[] = {opp_regs(0), opp_regs(1)}; + +static const struct vpe20_opp_shift opp_shift = {OPP_FIELD_LIST_VPE20(__SHIFT)}; + +static const struct vpe20_opp_mask opp_mask = {OPP_FIELD_LIST_VPE20(_MASK)}; + +/***************** MPC registers ****************/ +#define mpc_regs(id) [id] = {MPC_REG_LIST_VPE20(id)} + +static struct vpe20_mpc_registers mpc_regs[] = {mpc_regs(0), mpc_regs(1)}; + +static const struct vpe20_mpc_shift mpc_shift = {MPC_FIELD_LIST_VPE20(__SHIFT)}; + +static const struct vpe20_mpc_mask mpc_mask = {MPC_FIELD_LIST_VPE20(_MASK)}; + +static struct vpe_caps + caps = + { + .max_input_size = + { + .width = 16384, + .height = 16384, + }, + .max_output_size = + { + .width = 16384, + .height = 16384, + }, + .min_input_size = + { + .width = 1, + .height = 1, + }, + .min_output_size = + { + .width = 1, + .height = 1, + }, + .lut_size = LUT_BUFFER_SIZE, + .rotation_support = 1, + .h_mirror_support = 1, + .v_mirror_support = 1, + .is_apu = 1, + .bg_color_check_support = 0, + + .prefer_external_scaler_coef = 0, + + .resource_caps = + { + .num_dpp = 2, + .num_opp = 2, + .num_mpc_3dlut = 1, + .num_queue = 8, + .num_cdc_be = 4, + }, + .color_caps = {.dpp = + { + .pre_csc = 1, + .luma_key = 1, + .color_key = 1, + .dgam_ram = 0, + .post_csc = 1, + .gamma_corr = 1, + .hw_3dlut = 1, + .ogam_ram = 1, /**< programmable gam in output -> gamma_corr */ + .ocsc = 0, + .dgam_rom_caps = + { + .srgb = 1, + .bt2020 = 1, + .gamma2_2 = 1, + .pq = 1, + .hlg = 1, + }, + }, + .mpc = + { + .gamut_remap = 1, + .ogam_ram = 1, + .ocsc = 1, + .shared_3d_lut = 1, + .global_alpha = 1, + .top_bottom_blending = 1, + .dma_3d_lut = 1, + .yuv_linear_blend = 0, + .lut_dim_caps = + { + .dim_9 = 0, + .dim_17 = 1, + .dim_33 = 1, + }, + .fast_load_caps = + { + .lut_3d_17 = 0, + .lut_3d_33 = 1, + }, + .lut_caps = + { + .lut_shaper_caps = + { + .dma_data = 0, + .dma_config = 0, + .non_monotonic = 0, + .data_alignment = SHAPER_LUT_DMA_DATA_ALIGNMENT, + .config_alignment = SHAPER_LUT_DMA_CONFIG_ALIGNMENT, + .config_padding = SHAPER_LUT_DMA_CONFIG_PADDING, + .data_size = SHAPER_LUT_DMA_DATA_SIZE, + .config_size = SHAPER_LUT_DMA_CONFIG_SIZE, + .data_pts_per_channel = SHAPER_LUT_DATA_POINTS_PER_CHANNEL, + }, + .lut_3dlut_caps = + { + .data_dim_9 = 0, + .data_dim_17 = 1, + .data_dim_33 = 1, + .dma_dim_9 = 0, + .dma_dim_17 = 0, + .dma_dim_33 = 1, + .alignment = LUT_3D_DMA_ALIGNMENT, + }, + .lut_3d_compound = 0, + }, + }}, + .plane_caps = + { + .per_pixel_alpha = 1, + .input_pixel_format_support = + { + .argb_packed_32b = 1, + .argb_packed_64b = 1, + .nv12 = 1, + .fp16 = 1, + .p010 = 1, /**< planar 4:2:0 10-bit */ + .p016 = 1, /**< planar 4:2:0 16-bit */ + .ayuv = 1, /**< packed 4:4:4 */ + .yuy2 = 1, /**< packed 4:2:2 */ + .y210 = 1, /**< packed 4:2:2 10-bit */ + .y216 = 1, /**< packed 4:2:2 16-bit */ + .p210 = 1, /**< planar 4:2:2 10-bit */ + .p216 = 1, /**< planar 4:2:2 16-bit */ + .rgb8_planar = 1, /**< planar RGB 8-bit */ + .rgb16_planar = 1, /**< planar RGB 16-bit */ + .yuv8_planar = 1, /**< planar YUV 16-bit */ + .yuv16_planar = 1, /**< planar YUV 16-bit */ + .fp16_planar = 1, /**< planar RGB 8-bit */ + .rgbe = 0, /**< shared exponent R9G9B9E5 */ + .rgb111110_fix = 0, /**< fixed R11G11B10 */ + .rgb111110_float = 0, /**< float R11G11B10 */ + }, + .output_pixel_format_support = + { + .argb_packed_32b = 1, + .argb_packed_64b = 1, + .nv12 = 1, + .fp16 = 1, + .p010 = 1, /**< planar 4:2:0 10-bit */ + .p016 = 1, /**< planar 4:2:0 16-bit */ + .ayuv = 1, /**< packed 4:4:4 */ + .yuy2 = 1, /**< packed 4:2:2 */ + .y210 = 1, /**< packed 4:2:2 10-bit */ + .y216 = 1, /**< packed 4:2:2 16-bit */ + .p210 = 1, /**< planar 4:2:2 10-bit */ + .p216 = 1, /**< planar 4:2:2 16-bit */ + .rgb8_planar = 1, /**< planar RGB 8-bit */ + .rgb16_planar = 1, /**< planar RGB 16-bit */ + .yuv8_planar = 1, /**< planar YUV 16-bit */ + .yuv16_planar = 1, /**< planar YUV 16-bit */ + .fp16_planar = 1, /**< planar RGB 8-bit */ + .rgbe = 0, /**< shared exponent R9G9B9E5 */ + .rgb111110_fix = 0, /**< fixed R11G11B10 */ + .rgb111110_float = 0, /**< float R11G11B10 */ + }, + .max_upscale_factor = 64000, + + // limit to 4:1 downscaling ratio: 1000/4 = 250 + .max_downscale_factor = 250, + + .pitch_alignment = 256, + .addr_alignment = 256, + .max_viewport_width = 1024, + .max_viewport_width_64bpp = 540, + }, + .isharp_caps = + { + .support = true, + .range = + { + .min = 0, + .max = 10, + .step = 1, + }, + }, + .easf_support = 1, + .input_dcc_support = 1, + .input_internal_dcc = 1, + .output_dcc_support = 0, + .output_internal_dcc = 0, + .histogram_support = 1, + .frod_support = 1, + .alpha_blending_support = 1, + .alpha_fill_caps = + { + .opaque = 1, + .bg_color = 1, + .destination = 0, + .source_stream = 0, + }, +}; + +uint32_t vpe20_get_max_seg_width(struct output_ctx *output_ctx, + enum vpe_surface_pixel_format format, enum vpe_scan_direction scan) +{ + if ((vpe_get_element_size_in_bytes(format, 0) == (uint8_t)8) && + ((scan == VPE_SCAN_PATTERN_90_DEGREE) || (scan == VPE_SCAN_PATTERN_270_DEGREE) || + (scan == VPE_SCAN_PATTERN_90_DEGREE_V_MIRROR) || + (scan == VPE_SCAN_PATTERN_270_DEGREE_V_MIRROR))) { + return caps.plane_caps.max_viewport_width_64bpp; + } + + return caps.plane_caps.max_viewport_width; +} + +static bool is_two_pass_blend_stream(struct stream_ctx *stream_ctx) +{ + return (stream_ctx->stream_type == VPE_STREAM_TYPE_BKGR_ALPHA || stream_ctx->mps_ctx != NULL || + stream_ctx->stream.blend_info.blending == false || + vpe_should_generate_cmd_info(stream_ctx) == false) + ? false + : true; +} + +void vpe20_update_opp_adjust_and_boundary(struct stream_ctx *stream_ctx, uint16_t seg_idx, + bool dst_subsampled, const struct vpe_rect *src_rect, const struct vpe_rect *dst_rect, + struct output_ctx *output_ctx, struct spl_opp_adjust *opp_recout_adjust) +{ + struct segment_ctx *segment_ctx = &stream_ctx->segment_ctx[seg_idx]; + + memset(opp_recout_adjust, 0, sizeof(struct spl_opp_adjust)); + + if (dst_subsampled) { + struct fmt_extra_pixel_info extra_info; + + struct vpe_rect *unclipped_dst_rect = &stream_ctx->stream.scaling_info.dst_rect; + struct vpe_rect *target_rect = &output_ctx->target_rect; + + struct opp *opp = stream_ctx->vpe_priv->resource.opp[0]; + bool extra_left_available = + !(is_two_pass_blend_stream(stream_ctx) && (target_rect->x > unclipped_dst_rect->x)); + bool extra_right_available = !(is_two_pass_blend_stream(stream_ctx) && + ((target_rect->x + target_rect->width) < + (unclipped_dst_rect->x + unclipped_dst_rect->width))); + + opp->funcs->get_fmt_extra_pixel(output_ctx->surface.format, + stream_ctx->vpe_priv->init.debug.subsampling_quality, + (enum chroma_cositing)output_ctx->surface.cs.cositing, &extra_info); + + if (seg_idx == 0) { + segment_ctx->boundary_mode.left = + extra_left_available ? stream_ctx->left : FMT_SUBSAMPLING_BOUNDARY_REPEAT; + if (segment_ctx->boundary_mode.left == FMT_SUBSAMPLING_BOUNDARY_EXTRA) { + opp_recout_adjust->x -= extra_info.left_pixels; + opp_recout_adjust->width += extra_info.left_pixels; + } + } else { + opp_recout_adjust->x -= extra_info.left_pixels; + opp_recout_adjust->width += extra_info.left_pixels; + segment_ctx->boundary_mode.left = FMT_SUBSAMPLING_BOUNDARY_EXTRA; + } + + // see if the RIGHT most needs more for output boundary handling, right needs 1 extra + + if (seg_idx == stream_ctx->num_segments - 1) { + segment_ctx->boundary_mode.right = + extra_right_available ? stream_ctx->right : FMT_SUBSAMPLING_BOUNDARY_REPEAT; + if (segment_ctx->boundary_mode.right == FMT_SUBSAMPLING_BOUNDARY_EXTRA) { + opp_recout_adjust->width += extra_info.right_pixels; + } + } else { + segment_ctx->boundary_mode.right = FMT_SUBSAMPLING_BOUNDARY_EXTRA; + opp_recout_adjust->width += extra_info.right_pixels; + } + } else { + segment_ctx->boundary_mode.left = FMT_SUBSAMPLING_BOUNDARY_REPEAT; + segment_ctx->boundary_mode.right = FMT_SUBSAMPLING_BOUNDARY_REPEAT; + } + + segment_ctx->boundary_mode.top = FMT_SUBSAMPLING_BOUNDARY_REPEAT; + segment_ctx->boundary_mode.bottom = FMT_SUBSAMPLING_BOUNDARY_REPEAT; + segment_ctx->opp_recout_adjust = *opp_recout_adjust; +} + +static void vpe20_spl_calc_lb_num_partitions(bool alpha_en, const struct spl_scaler_data *scl_data, + enum lb_memory_config lb_config, int *num_part_y, int *num_part_c) +{ + int memory_line_size_y, memory_line_size_c, memory_line_size_a, lb_memory_size, + lb_memory_size_c, lb_memory_size_a, num_partitions_a; + + uint32_t line_size = scl_data->viewport.width < scl_data->recout.width + ? scl_data->viewport.width + : scl_data->recout.width; + uint32_t line_size_c = scl_data->viewport_c.width < scl_data->recout.width + ? scl_data->viewport_c.width + : scl_data->recout.width; + + if (line_size == 0) + line_size = 1; + + if (line_size_c == 0) + line_size_c = 1; + + memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */ + memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */ + memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */ + + // only has 1-piece lb config in vpe1 + lb_memory_size = 696; + lb_memory_size_c = 696; + lb_memory_size_a = 696; + + *num_part_y = lb_memory_size / memory_line_size_y; + *num_part_c = lb_memory_size_c / memory_line_size_c; + num_partitions_a = lb_memory_size_a / memory_line_size_a; + + if (alpha_en && (num_partitions_a < *num_part_y)) + *num_part_y = num_partitions_a; + + if (*num_part_y > 12) + *num_part_y = 12; + if (*num_part_c > 12) + *num_part_c = 12; +} + +static void vpe20_spl_calc_lb_num_partitions_init(bool alpha_en, + const struct spl_scaler_data *scl_data, enum lb_memory_config lb_config, int *num_part_y, + int *num_part_c) +{ + if (num_part_y) + *num_part_y = 12; + if (num_part_c) + *num_part_c = 12; +} + +void vpe20_update_recout_dst_viewport(struct scaler_data *data, + enum vpe_surface_pixel_format format, struct spl_opp_adjust *opp_adjust, + bool opp_background_gen) +{ + uint32_t vpc_h_div = (vpe_is_yuv420(format) || vpe_is_yuv422(format)) ? 2 : 1; + uint32_t vpc_v_div = vpe_is_yuv420(format) ? 2 : 1; + struct vpe_rect *dst_viewport = &data->dst_viewport; + struct vpe_rect *dst_viewport_c = &data->dst_viewport_c; + struct dscl_prog_data *dscl_prog_data = &data->dscl_prog_data; + + + dst_viewport_c->x = dst_viewport->x / (int32_t)vpc_h_div; + dst_viewport_c->y = dst_viewport->y / (int32_t)vpc_v_div; + dst_viewport_c->width = dst_viewport->width / vpc_h_div; + dst_viewport_c->height = dst_viewport->height / vpc_v_div; + + // [h/v]_active + if (opp_background_gen) { + data->h_active = data->recout.width; + data->v_active = data->recout.height; + dscl_prog_data->mpc_size.width = data->recout.width; + dscl_prog_data->mpc_size.height = data->recout.height; + } else { + dscl_prog_data->mpc_size.width = dst_viewport->width; + dscl_prog_data->mpc_size.height = dst_viewport->height; + + if (opp_adjust != NULL) { + dscl_prog_data->mpc_size.width += opp_adjust->width; + dscl_prog_data->mpc_size.height += opp_adjust->height; + } + } + + // recout + dscl_prog_data->recout.x = data->recout.x; + dscl_prog_data->recout.y = data->recout.y; + dscl_prog_data->recout.width = data->recout.width; + dscl_prog_data->recout.height = data->recout.height; +} + +static void vpe20_build_mpcc_mux_params(struct vpe_priv *vpe_priv, enum vpe_cmd_ops ops, + uint32_t pipe_idx, uint16_t cmd_num_input, enum mpc_mux_topsel *topsel, + enum mpc_mux_botsel *botsel, enum mpc_mux_outmux *outmux, enum mpc_mux_oppid *oppid, + enum mpcc_blend_mode *blend_mode) +{ + *topsel = pipe_idx; + *oppid = MPC_MUX_OPPID_OPP0; + + switch (ops) { + case VPE_CMD_OPS_BLENDING: + *botsel = pipe_idx + 1; + *outmux = (pipe_idx == 0) ? MPC_MUX_OUTMUX_MPCC0 : MPC_MUX_OUTMUX_DISABLE; + *blend_mode = MPCC_BLEND_MODE_TOP_BOT_BLENDING; + // Need to disable botsel based on the last input of each cmd_inputs. + if (pipe_idx == (uint32_t)(cmd_num_input - 1)) { + *botsel = MPC_MUX_BOTSEL_DISABLE; + + *blend_mode = MPCC_BLEND_MODE_TOP_LAYER_ONLY; + } + + // num dpp == num mpcc + if (pipe_idx == (uint32_t)(vpe_priv->pub.caps->resource_caps.num_dpp - 1)) { + *botsel = MPC_MUX_BOTSEL_DISABLE; + *blend_mode = MPCC_BLEND_MODE_TOP_LAYER_ONLY; + } + break; + case VPE_CMD_OPS_ALPHA_THROUGH_LUMA: + if (pipe_idx == 0) { // pipe 0 - User input plane to have bg removed + *botsel = 1; + *outmux = MPC_MUX_OUTMUX_MPCC0; + *blend_mode = MPCC_BLEND_MODE_TOP_BOT_BLENDING; + } else { // pipe 1 - Alpha Luma plane + *botsel = MPC_MUX_BOTSEL_DISABLE; + *outmux = MPC_MUX_OUTMUX_DISABLE; + *blend_mode = MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH; + } + break; + default: + // single pipe compositing / performance mode + *outmux = pipe_idx; + *botsel = MPC_MUX_BOTSEL_DISABLE; + *oppid = pipe_idx; + *blend_mode = MPCC_BLEND_MODE_TOP_LAYER_ONLY; + } + + if (vpe_priv->init.debug.mpc_bypass) + *blend_mode = MPCC_BLEND_MODE_BYPASS; +} + +void vpe20_update_src_viewport(struct scaler_data *data, enum vpe_surface_pixel_format format) +{ + uint32_t vpc_h_div = (vpe_is_yuv420(format) || vpe_is_yuv422(format)) ? 2 : 1; + uint32_t vpc_v_div = vpe_is_yuv420(format) ? 2 : 1; + struct vpe_rect *viewport = &data->viewport; + struct vpe_rect *viewport_c = &data->viewport_c; + struct dscl_prog_data *dscl_prog_data = &data->dscl_prog_data; + + viewport_c->x = viewport->x / (int32_t)vpc_h_div; + viewport_c->y = viewport->y / (int32_t)vpc_v_div; + viewport_c->width = viewport->width / vpc_h_div; + viewport_c->height = viewport->height / vpc_v_div; + + dscl_prog_data->viewport.x = viewport->x; + dscl_prog_data->viewport.y = viewport->y; + + dscl_prog_data->viewport.width = viewport->width; + dscl_prog_data->viewport.height = viewport->height; + dscl_prog_data->viewport_c.width = viewport_c->width; + dscl_prog_data->viewport_c.height = viewport_c->height; +} + +// Note - No additional adjustments are made for rotation here as YUV422 does not support rotation +static void adjust_packed_422_scaler_params(struct spl_out *spl_output, bool is_h_mirror) +{ + uint32_t hinit_int = spl_output->dscl_prog_data->init.h_filter_init_int; + uint32_t hinit_c_int = spl_output->dscl_prog_data->init.h_filter_init_int_c; + int luma_x_start = spl_output->dscl_prog_data->viewport.x; + int luma_x_end = luma_x_start + spl_output->dscl_prog_data->viewport.width; + int chroma_x_start = spl_output->dscl_prog_data->viewport_c.x; + int chroma_x_end = chroma_x_start + spl_output->dscl_prog_data->viewport_c.width; + + int luma_x_start_aligned = luma_x_start & ~1; + int luma_x_end_aligned = (luma_x_end + 1) & ~1; + int chroma_x_start_aligned = chroma_x_start * 2; + int chroma_x_end_aligned = chroma_x_end * 2; + int x_start_aligned = (luma_x_start_aligned < chroma_x_start_aligned) ? luma_x_start_aligned + : chroma_x_start_aligned; + int x_end_aligned = + (luma_x_end_aligned > chroma_x_end_aligned) ? luma_x_end_aligned : chroma_x_end_aligned; + + if (is_h_mirror == false) { + if (luma_x_start > x_start_aligned) { + uint32_t drop = luma_x_start - x_start_aligned; + hinit_int += drop; + } + + if (chroma_x_start > (x_start_aligned / 2)) { + uint32_t drop = chroma_x_start - (x_start_aligned / 2); + hinit_c_int += drop; + } + } else { + if (x_end_aligned > luma_x_end) { + uint32_t drop = x_end_aligned - luma_x_end; + hinit_int += drop; + } + + if ((x_end_aligned / 2) > (chroma_x_end)) { + uint32_t drop = (x_end_aligned / 2) - chroma_x_end; + hinit_c_int += drop; + } + } + + spl_output->dscl_prog_data->init.h_filter_init_int = hinit_int; + spl_output->dscl_prog_data->init.h_filter_init_int_c = hinit_c_int; + spl_output->dscl_prog_data->viewport.x = x_start_aligned; + spl_output->dscl_prog_data->viewport.width = x_end_aligned - x_start_aligned; + spl_output->dscl_prog_data->viewport_c.x = x_start_aligned / 2; + spl_output->dscl_prog_data->viewport_c.width = (x_end_aligned - x_start_aligned) / 2; +} + +static void set_dst_cmd_boundary_mode_and_opp_adjust(struct vpe_priv *vpe_priv, + struct vpe_rect dst_viewport, struct fmt_boundary_mode *output_boundary_mode, + struct spl_opp_adjust *output_opp_adjust) +{ + struct fmt_extra_pixel_info extra_pixel; + + struct opp *opp = vpe_priv->resource.opp[0]; + struct output_ctx *output_ctx = &vpe_priv->output_ctx; + + opp->funcs->get_fmt_extra_pixel(output_ctx->surface.format, + vpe_priv->init.debug.subsampling_quality, + (enum chroma_cositing)output_ctx->surface.cs.cositing, &extra_pixel); + + // Ensure both streams have same seam size, and if not set to BOUNDARY_REPEAT + if (output_boundary_mode->left == FMT_SUBSAMPLING_BOUNDARY_EXTRA) { + bool do_streams_have_same_seam_size = + (dst_viewport.x >= output_ctx->target_rect.x) && + (extra_pixel.left_pixels == (uint32_t)(abs(output_opp_adjust->x))); + + if (!do_streams_have_same_seam_size) { + output_boundary_mode->left = FMT_SUBSAMPLING_BOUNDARY_REPEAT; + output_opp_adjust->width += output_opp_adjust->x; + output_opp_adjust->x = 0; + } + } + + if (output_boundary_mode->top == FMT_SUBSAMPLING_BOUNDARY_EXTRA) { + bool do_streams_have_same_seam_size = + (dst_viewport.y >= output_ctx->target_rect.y) && + (extra_pixel.top_pixels == (uint32_t)(abs(output_opp_adjust->y))); + + if (!do_streams_have_same_seam_size) { + output_boundary_mode->top = FMT_SUBSAMPLING_BOUNDARY_REPEAT; + output_opp_adjust->height += output_opp_adjust->y; + output_opp_adjust->y = 0; + } + } + + if (output_boundary_mode->right == FMT_SUBSAMPLING_BOUNDARY_EXTRA) { + uint32_t right_seam = (uint32_t)(output_opp_adjust->width + output_opp_adjust->x); + bool do_streams_have_same_seam_size = + (dst_viewport.x + dst_viewport.width <= + output_ctx->target_rect.x + output_ctx->target_rect.width) && + (extra_pixel.right_pixels == right_seam); + + if (!do_streams_have_same_seam_size) { + output_boundary_mode->right = FMT_SUBSAMPLING_BOUNDARY_REPEAT; + output_opp_adjust->width -= right_seam; + } + } + + if (output_boundary_mode->bottom == FMT_SUBSAMPLING_BOUNDARY_EXTRA) { + uint32_t bottom_seam = (uint32_t)(output_opp_adjust->height + output_opp_adjust->y); + bool do_streams_have_same_seam_size = + (dst_viewport.y + dst_viewport.height <= + output_ctx->target_rect.y + output_ctx->target_rect.height) && + (extra_pixel.bottom_pixels == bottom_seam); + + if (!do_streams_have_same_seam_size) { + output_boundary_mode->bottom = FMT_SUBSAMPLING_BOUNDARY_REPEAT; + output_opp_adjust->height -= bottom_seam; + } + } +} + +static void update_pipe_ctrl_param(struct opp_pipe_control_params *param, + struct output_ctx *output_ctx, struct vpe_surface_info *surface_info, + struct vpe_cmd_info *cmd_info) +{ + uint16_t alpha_16; + bool opp_dig_bypass = false; + + if (cmd_info->ops == VPE_CMD_OPS_ALPHA_THROUGH_LUMA) { + param->alpha = 0; + param->bypass_enable = true; + param->alpha_select = 1; + } else { + if (vpe_is_fp16(surface_info->format)) { + if (output_ctx->alpha_mode == VPE_ALPHA_BGCOLOR) + vpe_convert_from_float_to_fp16((double)output_ctx->mpc_bg_color.rgba.a, &alpha_16); + else + vpe_convert_from_float_to_fp16(1.0, &alpha_16); + + opp_dig_bypass = true; + } else { + if (output_ctx->alpha_mode == VPE_ALPHA_BGCOLOR) + alpha_16 = (uint16_t)(output_ctx->mpc_bg_color.rgba.a * 0xffff); + else + alpha_16 = 0xffff; + } + + param->alpha = alpha_16; + param->bypass_enable = opp_dig_bypass; + param->alpha_select = 0; + } +} + +bool vpe20_set_dst_cmd_info_scaler(struct stream_ctx *dst_stream_ctx, + struct scaler_data *dst_scaler_data, struct vpe_rect recout, struct vpe_rect dst_viewport, + struct fmt_boundary_mode *boundary_mode, struct spl_opp_adjust *opp_adjust) +{ + struct vpe_priv *vpe_priv = dst_stream_ctx->vpe_priv; + struct spl_in *spl_input = &dst_stream_ctx->spl_input; + struct spl_out *spl_output = &dst_stream_ctx->spl_output; + struct vpe_scaling_info *scaling_info = &dst_stream_ctx->stream.scaling_info; + struct output_ctx *output_ctx = &vpe_priv->output_ctx; + + dst_scaler_data->format = output_ctx->surface.format; + + // Set the vpe_scaling_info for the destination stream + + scaling_info->src_rect = recout; + scaling_info->dst_rect = recout; + + scaling_info->src_rect.x += dst_viewport.x + opp_adjust->x; + scaling_info->src_rect.y += dst_viewport.y; + scaling_info->dst_rect.x += dst_viewport.x + opp_adjust->x; + scaling_info->dst_rect.y += dst_viewport.y; + + // Set SPL input / output params in preparation for spl_calculate_scaler_params + + spl_output->dscl_prog_data = &dst_scaler_data->dscl_prog_data; + spl_input->callbacks.spl_calc_lb_num_partitions = vpe20_spl_calc_lb_num_partitions; + spl_input->basic_out.max_downscale_src_width = 0; // Set to zero to bypass SPL sanity checks + spl_input->basic_in.mpc_h_slice_index = 0; + + // In two pass stuations, we need to check LLS support for dst stream as well + vpe_priv->resource.set_lls_pref( + vpe_priv, spl_input, dst_stream_ctx->tf, dst_stream_ctx->stream.surface_info.format); + + dst_stream_ctx->num_segments = 1; + dst_stream_ctx->left = boundary_mode->left; + dst_stream_ctx->right = boundary_mode->right; + + vpe_init_spl_in(spl_input, dst_stream_ctx, output_ctx); + + if (!SPL_NAMESPACE(spl_calculate_scaler_params(spl_input, spl_output))) + return false; + + if (vpe_is_yuv422(output_ctx->surface.format) && vpe_is_yuv_packed(output_ctx->surface.format)) + adjust_packed_422_scaler_params(spl_output, false); + + vpe_spl_scl_to_vpe_scl(spl_output, dst_scaler_data); + + // Set src/dst viewport and recout info + + dst_scaler_data->viewport.x = recout.x + dst_viewport.x + opp_adjust->x; + dst_scaler_data->viewport.y = recout.y + dst_viewport.y + opp_adjust->y; + dst_scaler_data->viewport.width = dst_scaler_data->recout.width; + dst_scaler_data->viewport.height = dst_scaler_data->recout.height; + dst_scaler_data->dst_viewport.x = recout.x + dst_viewport.x; + dst_scaler_data->dst_viewport.y = recout.y + dst_viewport.y; + dst_scaler_data->dst_viewport.width = dst_viewport.width; + dst_scaler_data->dst_viewport.height = dst_viewport.height; + + if (vpe_priv->init.debug.opp_background_gen == 1) { + dst_scaler_data->recout.y = 0; + dst_scaler_data->recout.x = 0; + } else { + dst_scaler_data->recout.y = recout.y; + dst_scaler_data->recout.x = recout.x; + } + + // Calculate extra pixel info for subsampling + + set_dst_cmd_boundary_mode_and_opp_adjust(vpe_priv, dst_viewport, boundary_mode, opp_adjust); + + vpe20_update_recout_dst_viewport(dst_scaler_data, dst_stream_ctx->stream.surface_info.format, + opp_adjust, dst_stream_ctx->vpe_priv->init.debug.opp_background_gen == 1); + vpe20_update_src_viewport(dst_scaler_data, dst_stream_ctx->stream.surface_info.format); + + return true; +} + +static bool should_stream_generate_background(struct stream_ctx *stream_ctx) +{ + uint32_t stream_idx_to_generate_background; + + if (stream_ctx->vpe_priv->stream_ctx[0].stream.flags.is_alpha_plane != false) + // If our first op is BGKR, then the BKGR background stream will do gen background + stream_idx_to_generate_background = VPE_BKGR_STREAM_BACKGROUND_OFFSET; + else + // Otherwise, first stream will always generate background + stream_idx_to_generate_background = 0; + + return stream_idx_to_generate_background == (uint32_t)stream_ctx->stream_idx; +} + +enum vpe_status vpe20_fill_performance_mode_cmd_info( + struct vpe_priv *vpe_priv, uint16_t stream_idx, uint16_t avail_pipe_count) +{ + struct stream_ctx *stream_ctx = &vpe_priv->stream_ctx[stream_idx]; + uint16_t segment_idx = 0; + uint16_t i; + struct vpe_cmd_info cmd_info = {0}; + enum lut3d_type lut3d_type = vpe_get_stream_lut3d_type(stream_ctx); + + while (segment_idx < stream_ctx->num_segments) { + uint16_t cmd_pipe_count = min(avail_pipe_count, stream_ctx->num_segments - segment_idx); + cmd_info.num_inputs = cmd_pipe_count; + cmd_info.num_outputs = cmd_pipe_count; + cmd_info.ops = VPE_CMD_OPS_COMPOSITING; + cmd_info.lut3d_type = lut3d_type; + cmd_info.insert_start_csync = false; + cmd_info.insert_end_csync = false; + cmd_info.cd = (uint16_t)int_divide_with_ceil(stream_ctx->num_segments - segment_idx, avail_pipe_count) - 1; + + for (i = 0; i < cmd_pipe_count; i++) { + cmd_info.inputs[i].stream_idx = stream_idx; + memcpy(&(cmd_info.inputs[i].scaler_data), + &(stream_ctx->segment_ctx[segment_idx + i].scaler_data), + sizeof(struct scaler_data)); + + cmd_info.outputs[i].dst_viewport = + stream_ctx->segment_ctx[segment_idx + i].scaler_data.dst_viewport; + cmd_info.outputs[i].dst_viewport_c = + stream_ctx->segment_ctx[segment_idx + i].scaler_data.dst_viewport_c; + cmd_info.outputs[i].boundary_mode = + stream_ctx->segment_ctx[segment_idx + i].boundary_mode; + cmd_info.outputs[i].opp_recout_adjust = + stream_ctx->segment_ctx[segment_idx + i].opp_recout_adjust; + } + segment_idx += cmd_pipe_count; + vpe_vector_push(vpe_priv->vpe_cmd_vector, &cmd_info); + + } + + return VPE_STATUS_OK; +} + +enum vpe_status vpe20_fill_blending_cmd_info( + struct vpe_priv *vpe_priv, uint16_t top_stream_idx, uint16_t bot_stream_idx) +{ + struct fmt_boundary_mode *boundary_mode; + struct segment_ctx *segment_ctx; + uint16_t dest_cmd_info_idx, input_cmd_info_idx; + + struct stream_ctx *top_stream_ctx = NULL; + struct stream_ctx *bot_stream_ctx = NULL; + struct stream_ctx *input_stream_ctx = NULL; + struct stream_ctx *dest_stream_ctx = NULL; + struct vpe_cmd_info cmd_info = {0}; + struct vpe_rect dst_viewport = {0}; + struct vpe_rect dst_viewport_c = {0}; + struct vpe_rect recout = {0}; + uint16_t segment_idx = 0; + enum lut3d_type lut3d_type = LUT3D_TYPE_NONE; + uint16_t num_segments = 0; + enum vpe_status status = VPE_STATUS_OK; + struct spl_opp_adjust *opp_adjust; + + if ((top_stream_idx == VPE_DESTINATION_AS_INPUT_STREAM_INDEX) || + (bot_stream_idx == VPE_DESTINATION_AS_INPUT_STREAM_INDEX)) { + dest_stream_ctx = vpe_get_virtual_stream(vpe_priv, VPE_STREAM_TYPE_DESTINATION); + if (dest_stream_ctx == NULL) + status = VPE_STATUS_ERROR; + } else { + status = VPE_STATUS_ERROR; // at least one stream must be destination as input + } + + if (top_stream_idx != VPE_DESTINATION_AS_INPUT_STREAM_INDEX) { + top_stream_ctx = &vpe_priv->stream_ctx[top_stream_idx]; + bot_stream_ctx = dest_stream_ctx; + input_stream_ctx = top_stream_ctx; + dest_cmd_info_idx = 1; + input_cmd_info_idx = 0; + } else if (bot_stream_idx != VPE_DESTINATION_AS_INPUT_STREAM_INDEX) { + top_stream_ctx = dest_stream_ctx; + bot_stream_ctx = &vpe_priv->stream_ctx[bot_stream_idx]; + input_stream_ctx = bot_stream_ctx; + dest_cmd_info_idx = 0; + input_cmd_info_idx = 1; + } else { + dest_cmd_info_idx = 0; // need to set these for compilation + input_cmd_info_idx = 0; + status = VPE_STATUS_ERROR; + } + + if ((input_stream_ctx != NULL) && (status == VPE_STATUS_OK)) { + lut3d_type = vpe_get_stream_lut3d_type(input_stream_ctx); + num_segments = input_stream_ctx->num_segments; + } else { + status = VPE_STATUS_ERROR; + } + + if ((top_stream_ctx == NULL) || (bot_stream_ctx == NULL)) + status = VPE_STATUS_ERROR; + + if (status == VPE_STATUS_OK) { + for (segment_idx = 0; segment_idx < num_segments; segment_idx++) { + + cmd_info.num_inputs = 2; + cmd_info.ops = VPE_CMD_OPS_BLENDING; + cmd_info.lut3d_type = lut3d_type; + cmd_info.insert_start_csync = false; + cmd_info.insert_end_csync = false; + cmd_info.cd = (uint16_t)(num_segments - segment_idx - 1); + + cmd_info.inputs[0].stream_idx = (uint16_t)top_stream_ctx->stream_idx; + cmd_info.inputs[1].stream_idx = (uint16_t)bot_stream_ctx->stream_idx; + + if (input_stream_ctx == NULL) { + status = VPE_STATUS_ERROR; + break; + } + + // Build scaler data for destination as input stream + + segment_ctx = &input_stream_ctx->segment_ctx[segment_idx]; + boundary_mode = &segment_ctx->boundary_mode; + dst_viewport = segment_ctx->scaler_data.dst_viewport; + dst_viewport_c = segment_ctx->scaler_data.dst_viewport_c; + opp_adjust = &segment_ctx->opp_recout_adjust; + + if (!vpe_priv->resource.set_dst_cmd_info_scaler(dest_stream_ctx, + &cmd_info.inputs[dest_cmd_info_idx].scaler_data, + segment_ctx->scaler_data.recout, dst_viewport, boundary_mode, opp_adjust)) { + status = VPE_STATUS_SCALER_NOT_SET; + break; + } + + cmd_info.inputs[dest_cmd_info_idx].scaler_data.lb_params.alpha_en = + dest_stream_ctx->per_pixel_alpha; + + if (status != VPE_STATUS_OK) + break; + + memcpy(&(cmd_info.inputs[input_cmd_info_idx].scaler_data), &segment_ctx->scaler_data, + sizeof(struct scaler_data)); + + // Validate that recout + MPC sizes line up (recout) so blending works + + VPE_ASSERT((cmd_info.inputs[0].scaler_data.recout.width == + cmd_info.inputs[1].scaler_data.recout.width) && + (cmd_info.inputs[0].scaler_data.recout.height == + cmd_info.inputs[1].scaler_data.recout.height)); + + VPE_ASSERT((cmd_info.inputs[0].scaler_data.dscl_prog_data.mpc_size.width == + cmd_info.inputs[1].scaler_data.dscl_prog_data.mpc_size.width) && + (cmd_info.inputs[0].scaler_data.dscl_prog_data.mpc_size.height == + cmd_info.inputs[1].scaler_data.dscl_prog_data.mpc_size.height)); + + // Program cmd output valus + + cmd_info.num_outputs = 1; + cmd_info.outputs[0].dst_viewport = dst_viewport; + cmd_info.outputs[0].dst_viewport_c = dst_viewport_c; + cmd_info.outputs[0].boundary_mode = *boundary_mode; + cmd_info.outputs[0].opp_recout_adjust = *opp_adjust; + if (vpe_priv->output_ctx.frod_param.enable_frod) { + cmd_info.num_outputs = FROD_NUM_OUTPUTS; + cmd_info.frod_param.enable_frod = true; + } + + vpe_vector_push(vpe_priv->vpe_cmd_vector, &cmd_info); + } + } + + return status; +} + +enum vpe_status vpe20_fill_alpha_through_luma_cmd_info( + struct vpe_priv *vpe_priv, uint16_t alpha_stream_idx) +{ + struct stream_ctx *alpha_stream = + &vpe_priv->stream_ctx[alpha_stream_idx + VPE_BKGR_STREAM_ALPHA_OFFSET]; + struct stream_ctx *video_stream = + &vpe_priv->stream_ctx[alpha_stream_idx + VPE_BKGR_STREAM_VIDEO_OFFSET]; + struct vpe_cmd_info cmd_info = {0}; + uint16_t segment_idx = 0; + enum lut3d_type lut3d_type = vpe_get_stream_lut3d_type(video_stream); + + for (segment_idx = 0; segment_idx < video_stream->num_segments; segment_idx++) { + + cmd_info.num_inputs = 2; + cmd_info.inputs[0].stream_idx = alpha_stream_idx + VPE_BKGR_STREAM_ALPHA_OFFSET; + cmd_info.inputs[1].stream_idx = alpha_stream_idx + VPE_BKGR_STREAM_VIDEO_OFFSET; + cmd_info.cd = (uint16_t)(video_stream->num_segments - segment_idx - 1); + + // For alpha luma stream, NV12 stream treated as one plane, so same chroma viewport as luma + // viewport + alpha_stream->segment_ctx[segment_idx].scaler_data.dst_viewport_c = + alpha_stream->segment_ctx[segment_idx].scaler_data.dst_viewport; + + memcpy(&(cmd_info.inputs[1].scaler_data), + &(video_stream->segment_ctx[segment_idx].scaler_data), sizeof(struct scaler_data)); + memcpy(&(cmd_info.inputs[0].scaler_data), + &(alpha_stream->segment_ctx[segment_idx].scaler_data), sizeof(struct scaler_data)); + + // Ensure MPC sizes line up (recout) so blending works + VPE_ASSERT((cmd_info.inputs[0].scaler_data.recout.width == + cmd_info.inputs[1].scaler_data.recout.width) && + (cmd_info.inputs[0].scaler_data.recout.height == + cmd_info.inputs[1].scaler_data.recout.height)); + + cmd_info.num_outputs = 1; + cmd_info.outputs[0].dst_viewport = + alpha_stream->segment_ctx[segment_idx].scaler_data.dst_viewport; + cmd_info.outputs[0].dst_viewport_c = + alpha_stream->segment_ctx[segment_idx].scaler_data.dst_viewport_c; + cmd_info.outputs[0].boundary_mode = alpha_stream->segment_ctx[segment_idx].boundary_mode; + cmd_info.outputs[0].opp_recout_adjust = + alpha_stream->segment_ctx[segment_idx].opp_recout_adjust; + cmd_info.ops = VPE_CMD_OPS_ALPHA_THROUGH_LUMA; + cmd_info.lut3d_type = lut3d_type; + cmd_info.insert_start_csync = false; + cmd_info.insert_end_csync = false; + + vpe_vector_push(vpe_priv->vpe_cmd_vector, &cmd_info); + } + + return VPE_STATUS_OK; +} + +enum vpe_status vpe20_fill_non_performance_mode_cmd_info( + struct vpe_priv *vpe_priv, uint16_t stream_idx) +{ + struct stream_ctx *stream_ctx = &vpe_priv->stream_ctx[stream_idx]; + uint16_t segment_idx; + struct vpe_cmd_info cmd_info = {0}; + struct fmt_boundary_mode *boundary_mode; + enum lut3d_type lut3d_type = vpe_get_stream_lut3d_type(stream_ctx); + + for (segment_idx = 0; segment_idx < stream_ctx->num_segments; segment_idx++) { + boundary_mode = &stream_ctx->segment_ctx[segment_idx].boundary_mode; + cmd_info.inputs[0].stream_idx = stream_idx; + cmd_info.cd = (uint16_t)(stream_ctx->num_segments - segment_idx - 1); + cmd_info.inputs[0].scaler_data = stream_ctx->segment_ctx[segment_idx].scaler_data; + cmd_info.num_outputs = 1; + if (vpe_priv->output_ctx.frod_param.enable_frod) { + cmd_info.num_outputs = FROD_NUM_OUTPUTS; + cmd_info.frod_param.enable_frod = true; + } + cmd_info.outputs[0].dst_viewport = + stream_ctx->segment_ctx[segment_idx].scaler_data.dst_viewport; + cmd_info.outputs[0].dst_viewport_c = + stream_ctx->segment_ctx[segment_idx].scaler_data.dst_viewport_c; + cmd_info.outputs[0].boundary_mode = stream_ctx->segment_ctx[segment_idx].boundary_mode; + cmd_info.outputs[0].opp_recout_adjust = + stream_ctx->segment_ctx[segment_idx].opp_recout_adjust; + cmd_info.num_inputs = 1; + cmd_info.ops = VPE_CMD_OPS_COMPOSITING; + cmd_info.lut3d_type = lut3d_type; + cmd_info.insert_start_csync = false; + cmd_info.insert_end_csync = false; + + vpe_vector_push(vpe_priv->vpe_cmd_vector, &cmd_info); + } + + return VPE_STATUS_OK; +} + +static struct vpe_rect generate_opp_dst_rect(uint32_t pipe_idx, struct vpe_cmd_info *cmd_info) +{ + uint32_t input_idx; + struct vpe_rect opp_dst_rect = {0}; + struct scaler_data *s_data; + + // Determine which front-end input we should be mapping the OPP background generation to + if (cmd_info->frod_param.enable_frod) { + // For FROD, only 2 cases are 1-pipe normal operation, and blending. For both of these + // we pick pipe 0 (refer to comments below) + input_idx = 0; + } else { + if (cmd_info->num_inputs == cmd_info->num_outputs) { + // perf mode and normal 1 pipe case: each pipe should generate its own background + input_idx = pipe_idx; + } else if (cmd_info->num_inputs > 1 && cmd_info->num_outputs == 1) { // blending case + // If blending we only want to generate bg around the final output, which will be the + // top-most input (aka input 0) + input_idx = 0; + } else { + VPE_ASSERT(false); // Should not ever hit this + input_idx = 0; + } + } + + if (input_idx >= MAX_INPUT_PIPE) { // Need this for compilation + VPE_ASSERT(false); + input_idx = 0; + } + + s_data = &cmd_info->inputs[input_idx].scaler_data; + + opp_dst_rect.x = s_data->dst_viewport.x + s_data->recout.x; + opp_dst_rect.y = s_data->dst_viewport.y + s_data->recout.y; + + // BG segments will set w/h to MIN_VIEWPORT_SIZE, but mpc output is 0. Need opp rect to match + if (cmd_info->ops == VPE_CMD_OPS_BG) { + opp_dst_rect.width = 0; + opp_dst_rect.height = 0; + } else { + opp_dst_rect.width = s_data->recout.width; + opp_dst_rect.height = s_data->recout.height; + } + /* Note: + * After spl, recout.x is non zero for 2nd segment onwards. + * However, calculate_dst_viewport_and_active() will adjust the x/y back to 0. + * it is due to each segment is an independent job to VPE and + * VPE is only seeing this segment's output starting from 0,0 position. + * so recout.x should reset to 0, if it is non-0, meaning that + * background generation is needed. + * Here we have to drop the extra pixels needed by OPP FMT subsampling, + * after OPP FMT, those pixels are dropped before going to OPP OUTBG block, + * thus adjustment to width & height are needed here. + * x, y are not needed as recout.x is reset and dst_viewport.x/y already adjusted + * in calculate_dst_viewport_and_active() + */ + opp_dst_rect.width -= cmd_info->outputs[pipe_idx].opp_recout_adjust.width; + opp_dst_rect.height -= cmd_info->outputs[pipe_idx].opp_recout_adjust.height; + return opp_dst_rect; +} + +static bool init_scaler_data(struct stream_ctx *stream_ctx, struct spl_in *spl_input, + struct spl_out *spl_output, struct scaler_data *scl_data, struct output_ctx *output_ctx, + uint32_t max_seg_width) +{ + struct vpe_priv *vpe_priv = stream_ctx->vpe_priv; + enum vpe_surface_pixel_format pixel_format = stream_ctx->stream.surface_info.format; + struct dscl_prog_data dscl_prog_data; + + if (vpe_rec_is_equal(output_ctx->surface.plane_size.surface_size, output_ctx->target_rect) && + vpe_rec_is_equal(stream_ctx->stream.scaling_info.dst_rect, output_ctx->target_rect)) { + spl_input->is_fullscreen = true; + } else { + spl_input->is_fullscreen = false; + } + + vpe_priv->resource.set_lls_pref(vpe_priv, spl_input, stream_ctx->tf, pixel_format); + + /* To get the number of taps, SPL does not need to check if the input/output frame fits into + * the line buffer since it uses the whole source/destination sizes for getting the number of + * taps. After calculating thenumber of taps VPE calculates the maximum viewport size that fits + * into the line buffer based on the calculated number of vertical taps. + * + * Initially, set the partition function to return maximum number of lines the line buffer can + * fit; otherwise it would fail with frames with src/dst width more than 4176 pixels, e.g. 8K. + * After getting the number of taps, set the partition function to calculate the correct number + * of partitions for each segment. + */ + spl_input->callbacks.spl_calc_lb_num_partitions = vpe20_spl_calc_lb_num_partitions_init; + spl_input->basic_out.max_downscale_src_width = 0; // Set to zero to bypass SPL sanity checks + spl_input->basic_out.always_scale = + (vpe_is_yuv422(pixel_format) && vpe_is_yuv_packed(pixel_format)); + spl_input->basic_in.mpc_h_slice_index = 0; + spl_output->dscl_prog_data = &dscl_prog_data; + stream_ctx->num_segments = 1; + + vpe_init_spl_in(spl_input, stream_ctx, output_ctx); + + if (!SPL_NAMESPACE(spl_get_number_of_taps(spl_input, spl_output))) + return false; + + spl_input->callbacks.spl_calc_lb_num_partitions = vpe20_spl_calc_lb_num_partitions; + + scl_data->taps.h_taps = spl_output->dscl_prog_data->taps.h_taps + 1; + scl_data->taps.v_taps = spl_output->dscl_prog_data->taps.v_taps + 1; + scl_data->taps.h_taps_c = spl_output->dscl_prog_data->taps.h_taps_c + 1; + scl_data->taps.v_taps_c = spl_output->dscl_prog_data->taps.h_taps_c + 1; + + return true; +} + +struct cdc_fe *vpe20_cdc_fe_create(struct vpe_priv *vpe_priv, int inst) +{ + struct vpe20_cdc_fe *vpe_cdc_fe = vpe_zalloc(sizeof(struct vpe20_cdc_fe)); + + if (!vpe_cdc_fe) + return NULL; + + vpe20_construct_cdc_fe(vpe_priv, &vpe_cdc_fe->base); + + vpe_cdc_fe->base.inst = inst; + vpe_cdc_fe->regs = &cdc_fe_regs[inst]; + vpe_cdc_fe->mask = &cdc_fe_mask; + vpe_cdc_fe->shift = &cdc_fe_shift; + + return &vpe_cdc_fe->base; +} + +struct cdc_be *vpe20_cdc_be_create(struct vpe_priv *vpe_priv, int inst) +{ + struct vpe20_cdc_be *vpe_cdc_be = vpe_zalloc(sizeof(struct vpe20_cdc_be)); + + if (!vpe_cdc_be) + return NULL; + + vpe20_construct_cdc_be(vpe_priv, &vpe_cdc_be->base); + + vpe_cdc_be->base.inst = inst; + vpe_cdc_be->regs = &cdc_be_regs[inst]; + vpe_cdc_be->mask = &cdc_be_mask; + vpe_cdc_be->shift = &cdc_be_shift; + + return &vpe_cdc_be->base; +} + +struct dpp *vpe20_dpp_create(struct vpe_priv *vpe_priv, int inst) +{ + struct vpe20_dpp *vpe_dpp = vpe_zalloc(sizeof(struct vpe20_dpp)); + + if (!vpe_dpp) + return NULL; + + vpe20_construct_dpp(vpe_priv, &vpe_dpp->base); + + vpe_dpp->base.inst = inst; + vpe_dpp->regs = &dpp_regs[inst]; + vpe_dpp->mask = &dpp_mask; + vpe_dpp->shift = &dpp_shift; + + return &vpe_dpp->base; +} + +struct opp *vpe20_opp_create(struct vpe_priv *vpe_priv, int inst) +{ + struct vpe20_opp *vpe_opp = vpe_zalloc(sizeof(struct vpe20_opp)); + + if (!vpe_opp) + return NULL; + + vpe20_construct_opp(vpe_priv, &vpe_opp->base); + + vpe_opp->base.inst = inst; + vpe_opp->regs = &opp_regs[inst]; + vpe_opp->mask = &opp_mask; + vpe_opp->shift = &opp_shift; + + return &vpe_opp->base; +} + +struct mpc *vpe20_mpc_create(struct vpe_priv *vpe_priv, int inst) +{ + struct vpe20_mpc *vpe_mpc = vpe_zalloc(sizeof(struct vpe20_mpc)); + + if (!vpe_mpc) + return NULL; + + vpe20_construct_mpc(vpe_priv, &vpe_mpc->base); + + vpe_mpc->base.inst = inst; + vpe_mpc->regs = &mpc_regs[inst]; + vpe_mpc->mask = &mpc_mask; + vpe_mpc->shift = &mpc_shift; + + return &vpe_mpc->base; +} + +enum vpe_status vpe20_construct_resource(struct vpe_priv *vpe_priv, struct resource *res) +{ + struct vpe *vpe = &vpe_priv->pub; + uint32_t i; + + vpe->caps = ∩︀ + + vpe10_construct_vpec(vpe_priv, &res->vpec); + + for (i = 0; i < vpe->caps->resource_caps.num_dpp; i++) { // num pipes = num dpp = num_mpc + res->cdc_fe[i] = vpe20_cdc_fe_create(vpe_priv, i); + if (res->cdc_fe[i] == NULL) + goto err; + + res->dpp[i] = vpe20_dpp_create(vpe_priv, i); + if (res->dpp[i] == NULL) + goto err; + + res->mpc[i] = vpe20_mpc_create(vpe_priv, i); + if (res->mpc[i] == NULL) + goto err; + } + + for (i = 0; i < vpe->caps->resource_caps.num_cdc_be; i++) { + res->cdc_be[i] = vpe20_cdc_be_create(vpe_priv, i); + if (res->cdc_be[i] == NULL) + goto err; + } + + for (i = 0; i < vpe->caps->resource_caps.num_opp; i++) { // num opp = num dpp + res->opp[i] = vpe20_opp_create(vpe_priv, i); + if (res->opp[i] == NULL) + goto err; + } + + vpe20_construct_cmd_builder(vpe_priv, &res->cmd_builder); + vpe20_construct_vpe_desc_writer(&vpe_priv->vpe_desc_writer); + vpe20_construct_plane_desc_writer(&vpe_priv->plane_desc_writer); + vpe20_config_writer_init(&vpe_priv->config_writer); + + vpe_priv->num_pipe = 2; + + res->internal_hdr_normalization = 1; + + // Many of the below will need VPE20 versions. + res->check_h_mirror_support = vpe20_check_h_mirror_support; + res->calculate_segments = vpe20_calculate_segments; + res->get_max_seg_width = vpe20_get_max_seg_width; + res->set_num_segments = vpe20_set_num_segments; + res->split_bg_gap = vpe10_split_bg_gap; + res->calculate_dst_viewport_and_active = vpe20_calculate_dst_viewport_and_active; + res->get_bg_stream_idx = vpe20_get_bg_stream_idx; + res->find_bg_gaps = vpe_find_bg_gaps; + res->create_bg_segments = vpe20_create_bg_segments; + res->populate_cmd_info = vpe20_populate_cmd_info; + res->program_frontend = vpe20_program_frontend; + res->program_backend = vpe20_program_backend; + res->get_bufs_req = vpe20_get_bufs_req; + res->check_bg_color_support = vpe20_check_bg_color_support; + res->bg_color_convert = vpe20_bg_color_convert; + res->check_mirror_rotation_support = vpe20_check_mirror_rotation_support; + res->update_blnd_gamma = vpe20_update_blnd_gamma; + res->update_output_gamma = vpe20_update_output_gamma; + res->validate_cached_param = vpe20_validate_cached_param; + res->fill_alpha_through_luma_cmd_info = vpe20_fill_alpha_through_luma_cmd_info; + res->fill_non_performance_mode_cmd_info = vpe20_fill_non_performance_mode_cmd_info; + res->fill_performance_mode_cmd_info = vpe20_fill_performance_mode_cmd_info; + res->fill_blending_cmd_info = vpe20_fill_blending_cmd_info; + res->get_num_pipes_available = vpe20_get_num_pipes_available; + res->set_frod_output_viewport = vpe20_set_frod_output_viewport; + res->check_alpha_fill_support = vpe10_check_alpha_fill_support; + res->reset_pipes = vpe20_reset_pipes; + res->populate_frod_param = vpe20_populate_frod_param; + res->check_lut3d_compound = vpe20_check_lut3d_compound; + res->set_lls_pref = vpe20_set_lls_pref; + res->program_fastload = vpe20_program_3dlut_fl; + res->calculate_shaper = vpe10_calculate_shaper; + res->set_dst_cmd_info_scaler = vpe20_set_dst_cmd_info_scaler; + res->update_opp_adjust_and_boundary = vpe20_update_opp_adjust_and_boundary; + + return VPE_STATUS_OK; + +err: + vpe20_destroy_resource(vpe_priv, res); + return VPE_STATUS_ERROR; +} + +void vpe20_calculate_dst_viewport_and_active( + struct segment_ctx *segment_ctx, uint32_t max_seg_width) +{ + struct scaler_data *data = &segment_ctx->scaler_data; + struct stream_ctx *stream_ctx = segment_ctx->stream_ctx; + struct vpe_priv *vpe_priv = stream_ctx->vpe_priv; + struct vpe_rect *dst_rect = &stream_ctx->stream.scaling_info.dst_rect; + struct vpe_rect *target_rect = &vpe_priv->output_ctx.target_rect; + struct fmt_boundary_mode *boundary_mode = &segment_ctx->boundary_mode; + + data->dst_viewport.x = data->recout.x + dst_rect->x; + data->dst_viewport.width = data->recout.width; + + // dst viewport is used by vpec, which see no boundary extra pixels as opp drops them + // remove extra pixels here if exists + if ((boundary_mode->left == FMT_SUBSAMPLING_BOUNDARY_EXTRA) || + (boundary_mode->right == FMT_SUBSAMPLING_BOUNDARY_EXTRA) + ) { + data->dst_viewport.x -= segment_ctx->opp_recout_adjust.x; + data->dst_viewport.width -= segment_ctx->opp_recout_adjust.width; + } + + // 1st stream will cover the background + // extends the v_active to cover the full target_rect's height + if (should_stream_generate_background(segment_ctx->stream_ctx)) { + data->recout.x = 0; + data->recout.y = dst_rect->y >= target_rect->y ? dst_rect->y - target_rect->y : 0; + data->dst_viewport.y = target_rect->y; + data->dst_viewport.height = target_rect->height; + + if (!stream_ctx->flip_horizonal_output) { + /* first segment : + * if the dst_viewport.width is not 1024, + * and we need background on the left, extend the active to cover as much as it can + */ + if (segment_ctx->segment_idx == 0) { + uint32_t remain_gap = min(max_seg_width - data->dst_viewport.width, + (uint32_t)(data->dst_viewport.x - target_rect->x)); + data->recout.x = (int32_t)remain_gap; + + data->dst_viewport.x -= (int32_t)remain_gap; + data->dst_viewport.width += remain_gap; + } + // last segment + if (segment_ctx->segment_idx == stream_ctx->num_segments - 1) { + uint32_t remain_gap = min(max_seg_width - data->dst_viewport.width, + (uint32_t)((target_rect->x + (int32_t)target_rect->width) - + (data->dst_viewport.x + (int32_t)data->dst_viewport.width))); + + data->dst_viewport.width += remain_gap; + } + } + } else { + data->dst_viewport.y = data->recout.y + dst_rect->y; + data->dst_viewport.height = data->recout.height; + data->recout.y = 0; + data->recout.x = 0; + if ((boundary_mode->top == FMT_SUBSAMPLING_BOUNDARY_EXTRA) || + (boundary_mode->bottom == FMT_SUBSAMPLING_BOUNDARY_EXTRA)) { + data->dst_viewport.y -= segment_ctx->opp_recout_adjust.y; + data->dst_viewport.height -= segment_ctx->opp_recout_adjust.height; + } + } + + vpe20_update_recout_dst_viewport(data, vpe_priv->output_ctx.surface.format, + &segment_ctx->opp_recout_adjust, (vpe_priv->init.debug.opp_background_gen == 1)); +} + +bool vpe20_validate_cached_param(struct vpe_priv *vpe_priv, const struct vpe_build_param *param) +{ + uint32_t i; + struct output_ctx *output_ctx; + + if (vpe_priv->num_input_streams != param->num_streams && + !(vpe_priv->init.debug.bg_color_fill_only == true && vpe_priv->num_streams == 1)) + return false; + + for (i = 0; i < vpe_priv->num_input_streams; i++) { + struct vpe_stream stream = param->streams[i]; + + if (memcmp(&vpe_priv->stream_ctx[i].stream, &stream, sizeof(struct vpe_stream))) + return false; + } + + output_ctx = &vpe_priv->output_ctx; + if (output_ctx->alpha_mode != param->alpha_mode) + return false; + + if (memcmp(&output_ctx->mpc_bg_color, ¶m->bg_color, sizeof(struct vpe_color))) + return false; + + if (memcmp(&output_ctx->opp_bg_color, ¶m->bg_color, sizeof(struct vpe_color))) + return false; + + if (memcmp(&output_ctx->target_rect, ¶m->target_rect, sizeof(struct vpe_rect))) + return false; + + if (memcmp(&output_ctx->surface, ¶m->dst_surface, sizeof(struct vpe_surface_info))) + return false; + + return true; +} + +bool vpe20_check_h_mirror_support(bool* input_mirror, bool* output_mirror) +{ + *input_mirror = true; + *output_mirror = false; + return true; +} + +// To determine where to program OPP alpha. +// - Per segment in background replacement mode +// - Once per stream in non-background replacement mode +static bool is_background_replacement_ops(struct vpe_priv *vpe_priv, uint32_t cmd_idx) +{ + struct vpe_cmd_info *cmd_info = vpe_vector_get(vpe_priv->vpe_cmd_vector, cmd_idx); + VPE_ASSERT(cmd_info); + if (!cmd_info) + return false; + + if (cmd_info->ops == VPE_CMD_OPS_ALPHA_THROUGH_LUMA) { + return true; + } + if (cmd_idx != 0) { + struct vpe_cmd_info *last_cmd_info = vpe_vector_get(vpe_priv->vpe_cmd_vector, cmd_idx - 1); + VPE_ASSERT(last_cmd_info); + if (!last_cmd_info) + return false; + if (last_cmd_info->ops == VPE_CMD_OPS_ALPHA_THROUGH_LUMA) + return true; + } + return false; +} + +static bool should_program_backend_config(struct vpe_priv *vpe_priv, struct vpe_cmd_info *cmd_info, + uint32_t pipe_idx, uint32_t max_opp_pipes) +{ + /* this function only control skip programming or not. + * i.e. programming is the same. + * if fundamental programming is different, + * it should fall into stream op specific programming instead. + */ + bool res = false; + + if (!cmd_info->frod_param.enable_frod) { + if (vpe_priv->stream_ctx[cmd_info->inputs[0].stream_idx].mps_parent_stream != NULL) { + res = true; + } else + if (cmd_info->ops == VPE_CMD_OPS_BLENDING) { + // only pipe0 has blended output + if (pipe_idx == 0) { + res = true; + } + } else if (pipe_idx < max_opp_pipes) { // this is more of a sanity check only + // performance mode, need to program both pipes + res = true; + } + } else { // FROD case + // frod only pipe0 can output data + res = (pipe_idx == 0); + } + return res; +} + +int32_t vpe20_program_backend( + struct vpe_priv *vpe_priv, uint32_t pipe_idx, uint32_t cmd_idx, bool seg_only) +{ + struct output_ctx *output_ctx = &vpe_priv->output_ctx; + struct vpe_surface_info *surface_info = &vpe_priv->output_ctx.surface; + struct stream_ctx *stream_ctx = vpe_priv->stream_ctx; + struct cdc_be *cdc_be = vpe_priv->resource.cdc_be[pipe_idx]; + struct vpe_cmd_info *cmd_info = vpe_vector_get(vpe_priv->vpe_cmd_vector, cmd_idx); + struct opp *opp = vpe_priv->resource.opp[pipe_idx]; + struct mpc *mpc = vpe_priv->resource.mpc[pipe_idx]; + + struct bit_depth_reduction_params fmt_bit_depth; + struct clamping_and_pixel_encoding_params clamp_param; + enum color_depth display_color_depth; + struct opp_pipe_control_params pipe_ctrl_param; + bool opp_dig_bypass = false; + struct fmt_subsampling_params subsampling_params = {0}; + struct fmt_control_params fmt_ctrl = {0}; + + VPE_ASSERT(cmd_info); + if (!cmd_info) + return -1; + + vpe_priv->be_cb_ctx.vpe_priv = vpe_priv; + config_writer_set_callback( + &vpe_priv->config_writer, &vpe_priv->be_cb_ctx, vpe_backend_config_callback); + + config_writer_set_type(&vpe_priv->config_writer, CONFIG_TYPE_DIRECT, pipe_idx); + + if (!seg_only) { + /* start back-end programming that can be shared among segments */ + if (stream_ctx->mps_parent_stream == NULL) + vpe_priv->be_cb_ctx.share = true; + + cdc_be->funcs->program_global_sync(cdc_be, VPE20_CDC_VUPDATE_OFFSET_DEFAULT, + VPE20_CDC_VUPDATE_WIDTH_DEFAULT, VPE20_CDC_VREADY_OFFSET_DEFAULT); + + if (should_program_backend_config( + vpe_priv, cmd_info, pipe_idx, vpe_priv->pub.caps->resource_caps.num_opp)) { + mpc->funcs->set_output_transfer_func(mpc, output_ctx); + mpc->funcs->program_mpc_out(mpc, surface_info->format); + mpc->funcs->program_output_csc(mpc, output_ctx->surface.format, output_ctx->cs, NULL); + + display_color_depth = vpe_get_color_depth(surface_info->format); + + // disable dynamic expansion for now as no use case + opp->funcs->set_dyn_expansion(opp, false, display_color_depth); + + if (!is_background_replacement_ops(vpe_priv, cmd_idx)) { + update_pipe_ctrl_param(&pipe_ctrl_param, output_ctx, surface_info, cmd_info); + opp->funcs->program_pipe_control(opp, &pipe_ctrl_param); + } + + if (vpe_priv->init.debug.opp_pipe_crc_ctrl) + opp->funcs->program_pipe_crc(opp, true); + } + + config_writer_complete(&vpe_priv->config_writer); + } + + // Segment Specific programming + vpe_priv->be_cb_ctx.share = false; + + // Segment specific programming that should be skipped for FROD. + // In the blending case there is only one output so the entire back end programming is skipped + if (should_program_backend_config( + vpe_priv, cmd_info, pipe_idx, vpe_priv->pub.caps->resource_caps.num_opp)) { + if (!(cmd_info->frod_param.enable_frod && pipe_idx != 0) && + vpe_priv->init.debug.opp_background_gen) { + struct vpe_rect opp_dst_rect = generate_opp_dst_rect(pipe_idx, cmd_info); + + opp->funcs->set_bg(opp, cmd_info->outputs[pipe_idx].dst_viewport, opp_dst_rect, + surface_info->format, output_ctx->opp_bg_color); + } + + vpe_build_clamping_params(opp, &clamp_param); + vpe_resource_build_bit_depth_reduction_params(opp, &fmt_bit_depth); + // output cositing and boundary mode + opp->funcs->build_fmt_subsample_params(opp, surface_info->format, + vpe_priv->init.debug.subsampling_quality, + (enum chroma_cositing)surface_info->cs.cositing, + cmd_info->outputs[pipe_idx].boundary_mode, &fmt_ctrl.subsampling_params); + + opp->funcs->program_fmt(opp, &fmt_bit_depth, &fmt_ctrl, &clamp_param); + + if (is_background_replacement_ops(vpe_priv, cmd_idx)) { + update_pipe_ctrl_param(&pipe_ctrl_param, output_ctx, surface_info, cmd_info); + opp->funcs->program_pipe_control(opp, &pipe_ctrl_param); + } + } + + if (pipe_idx == 0) { + // frod control has to be programmed here + // As visual confirm should not have frod/histogram enabled vs the main output may have it + // enabled. + cdc_be->funcs->program_cdc_control( + cdc_be, cmd_info->frod_param.enable_frod, cmd_info->histo_dsets); + opp->funcs->program_frod(opp, &cmd_info->frod_param); + } + + cdc_be->funcs->program_p2b_config(cdc_be, surface_info->format, surface_info->swizzle, + &cmd_info->outputs[pipe_idx].dst_viewport, &cmd_info->outputs[pipe_idx].dst_viewport_c); + + config_writer_complete(&vpe_priv->config_writer); + + return 0; +} + +enum vpe_status vpe20_check_bg_color_support(struct vpe_priv* vpe_priv, struct vpe_color* bg_color) +{ + enum vpe_status status = VPE_STATUS_OK; + struct vpe_color_space *p_cs = &vpe_priv->output_ctx.surface.cs; + + // Check if output is studio format and RGB values are >= 0.92, return BG color out of range + if ((p_cs->tf == VPE_TF_PQ) && (p_cs->range == VPE_COLOR_RANGE_STUDIO) && + (bg_color->rgba.r > BG_COLOR_STUDIO_PQ_MAX_THRESHOLD || + bg_color->rgba.g > BG_COLOR_STUDIO_PQ_MAX_THRESHOLD || + bg_color->rgba.b > BG_COLOR_STUDIO_PQ_MAX_THRESHOLD)) { + return VPE_STATUS_BG_COLOR_OUT_OF_RANGE; + } + + return status; +} + +// To understand the logic for background color conversion, +// please refer to vpe_update_output_gamma_sequence in color.c +void vpe20_bg_color_convert(enum color_space output_cs, struct transfer_func *output_tf, + enum vpe_surface_pixel_format pixel_format, struct vpe_color *mpc_bg_color, + struct vpe_color *opp_bg_color, bool enable_3dlut) +{ + // inverse OCSC studio/format conversion and convert from bg input format to in-pipe format + if (vpe_is_limited_cs(output_cs) || mpc_bg_color->is_ycbcr) + vpe_bg_format_and_limited_conversion(output_cs, pixel_format, mpc_bg_color); + + if (opp_bg_color != NULL) { + if ((opp_bg_color->is_ycbcr && !vpe_is_yuv_cs(output_cs)) || + (!opp_bg_color->is_ycbcr && vpe_is_yuv_cs(output_cs))) { + vpe_bg_color_space_conversion(output_cs, opp_bg_color); + } + } + if (output_tf->type != TF_TYPE_BYPASS) { + // inverse degam + if (output_tf->tf == TRANSFER_FUNC_PQ2084) + vpe_bg_degam(output_tf, mpc_bg_color); + // inverse gamut remap + if (enable_3dlut && output_cs != COLOR_SPACE_MSREF_SCRGB) + vpe_bg_inverse_gamut_remap(output_cs, output_tf, mpc_bg_color); + } + // for TF_TYPE_BYPASS, bg color should be programmed to mpc as linear +} + +void vpe20_destroy_resource(struct vpe_priv *vpe_priv, struct resource *res) +{ + uint32_t i = 0; + + for (i = 0; i < vpe_priv->num_pipe; i++) { + if (res->cdc_fe[i] != NULL) { + vpe_free(container_of(res->cdc_fe[i], struct vpe20_cdc_fe, base)); + res->cdc_fe[i] = NULL; + } + + if (res->dpp[i] != NULL) { + vpe_free(container_of(res->dpp[i], struct vpe20_dpp, base)); + res->dpp[i] = NULL; + } + + if (res->mpc[i] != NULL) { + vpe_free(container_of(res->mpc[i], struct vpe20_mpc, base)); + res->mpc[i] = NULL; + } + } + + for (i = 0; i < vpe_priv->pub.caps->resource_caps.num_cdc_be; i++) { + vpe_free(container_of(res->cdc_be[i], struct vpe20_cdc_be, base)); + res->cdc_be[i] = NULL; + } + + for (i = 0; i < vpe_priv->pub.caps->resource_caps.num_opp; i++) { + if (res->opp[i] != NULL) { + vpe_free(container_of(res->opp[i], struct vpe20_opp, base)); + res->opp[i] = NULL; + } + } +} + +void vpe20_create_stream_ops_config(struct vpe_priv *vpe_priv, uint32_t pipe_idx, + uint32_t cmd_input_idx, struct stream_ctx *stream_ctx, struct vpe_cmd_info *cmd_info) +{ + /* put all hw programming that can be shared according to the cmd type within a stream here */ + struct mpcc_blnd_cfg blndcfg = {0}; + + struct dpp *dpp = vpe_priv->resource.dpp[pipe_idx]; + struct mpc *mpc = vpe_priv->resource.mpc[pipe_idx]; + enum vpe_cmd_type cmd_type = VPE_CMD_TYPE_COUNT; + struct vpe_vector *config_vector; + struct vpe_cmd_input *cmd_input = &cmd_info->inputs[cmd_input_idx]; + + // MPCC programming + enum mpc_mpccid mpccid = pipe_idx; + enum mpc_mux_topsel topsel; + enum mpc_mux_outmux outmux; + enum mpc_mux_botsel botsel; + enum mpc_mux_oppid oppid; + enum mpcc_blend_mode blend_mode; + + vpe_priv->fe_cb_ctx.stream_op_sharing = true; + vpe_priv->fe_cb_ctx.stream_sharing = false; + + switch (cmd_info->ops) { + case VPE_CMD_OPS_BG: + cmd_type = VPE_CMD_TYPE_BG; + break; + case VPE_CMD_OPS_COMPOSITING: + cmd_type = VPE_CMD_TYPE_COMPOSITING; + break; + case VPE_CMD_OPS_BLENDING: + cmd_type = VPE_CMD_TYPE_BLENDING; + break; + case VPE_CMD_OPS_BG_VSCF_INPUT: + cmd_type = VPE_CMD_TYPE_BG_VSCF_INPUT; + break; + case VPE_CMD_OPS_BG_VSCF_OUTPUT: + cmd_type = VPE_CMD_TYPE_BG_VSCF_OUTPUT; + break; + case VPE_CMD_OPS_BG_VSCF_PIPE0: + cmd_type = VPE_CMD_TYPE_BG_VSCF_PIPE0; + break; + case VPE_CMD_OPS_BG_VSCF_PIPE1: + cmd_type = VPE_CMD_TYPE_BG_VSCF_PIPE1; + break; + case VPE_CMD_OPS_ALPHA_THROUGH_LUMA: + cmd_type = VPE_CMD_TYPE_ALPHA_THROUGH_LUMA; + break; + default: + return; + break; + } + + // return if already generated + config_vector = stream_ctx->stream_op_configs[pipe_idx][cmd_type]; + + // mps blend can have any stream generate BG, so blend cfg must be programmed every time + if (config_vector->num_elements && stream_ctx->mps_parent_stream == NULL) + return; + + vpe_priv->fe_cb_ctx.cmd_type = cmd_type; + + // out mux depends on cmd type (blend vs composition) + vpe20_build_mpcc_mux_params(vpe_priv, cmd_info->ops, pipe_idx, cmd_info->num_inputs, &topsel, + &botsel, &outmux, &oppid, &blend_mode); + + mpc->funcs->program_mpcc_mux(mpc, mpccid, topsel, botsel, outmux, oppid); + + dpp->funcs->set_frame_scaler(dpp, &cmd_input->scaler_data); + + if (cmd_info->ops == VPE_CMD_OPS_BG_VSCF_INPUT) { + blndcfg.bg_color = vpe_get_visual_confirm_color(vpe_priv, + stream_ctx->stream.surface_info.format, stream_ctx->stream.surface_info.cs, + vpe_priv->output_ctx.cs, vpe_priv->output_ctx.output_tf, + vpe_priv->output_ctx.surface.format, + (stream_ctx->stream.tm_params.UID != 0 || stream_ctx->stream.tm_params.enable_3dlut)); + } else if (cmd_info->ops == VPE_CMD_OPS_BG_VSCF_OUTPUT) { + blndcfg.bg_color = + vpe_get_visual_confirm_color(vpe_priv, vpe_priv->output_ctx.surface.format, + vpe_priv->output_ctx.surface.cs, vpe_priv->output_ctx.cs, + vpe_priv->output_ctx.output_tf, vpe_priv->output_ctx.surface.format, + false); // 3DLUT should only affect input visual confirm + } else if (cmd_info->ops == VPE_CMD_OPS_BG_VSCF_PIPE0) { + blndcfg.bg_color.is_ycbcr = false; + blndcfg.bg_color.rgba.r = 1.0f; + blndcfg.bg_color.rgba.g = 1.0f; + blndcfg.bg_color.rgba.b = 0.0f; + blndcfg.bg_color.rgba.a = 0.0f; + } else if (cmd_info->ops == VPE_CMD_OPS_BG_VSCF_PIPE1) { + blndcfg.bg_color.is_ycbcr = false; + blndcfg.bg_color.rgba.r = 0.0f; + blndcfg.bg_color.rgba.g = 1.0f; + blndcfg.bg_color.rgba.b = 1.0f; + blndcfg.bg_color.rgba.a = 0.0f; + } else { + blndcfg.bg_color = vpe_priv->output_ctx.mpc_bg_color; + } + blndcfg.global_gain = 0xfff; + blndcfg.pre_multiplied_alpha = false; + + if (cmd_type == VPE_CMD_TYPE_ALPHA_THROUGH_LUMA) { + if (pipe_idx == 0) { // Alpha plane goes through pipe 1 and blending happens here + blndcfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_ALPHA_THROUGH_LUMA; + blndcfg.global_alpha = 0xfff; + } else { + blndcfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; + blndcfg.global_alpha = 0xfff; + blndcfg.pre_multiplied_alpha = 1; + } + } else if (stream_ctx->stream.blend_info.blending || + (stream_ctx->stream_type == VPE_STREAM_TYPE_DESTINATION && + pipe_idx == 0)) { // Top stream as destination means bg replace + if (stream_ctx->per_pixel_alpha) { + blndcfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN; + + blndcfg.pre_multiplied_alpha = stream_ctx->stream.blend_info.pre_multiplied_alpha; + if (stream_ctx->stream.blend_info.global_alpha) { + blndcfg.global_gain = + (uint16_t)(stream_ctx->stream.blend_info.global_alpha_value * 0xfff); + } + } else { + blndcfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; + if (stream_ctx->stream.blend_info.global_alpha == true) { + VPE_ASSERT(stream_ctx->stream.blend_info.global_alpha_value <= 1.0f); + blndcfg.global_alpha = + (uint16_t)(stream_ctx->stream.blend_info.global_alpha_value * 0xfff); + } else { + // Global alpha not enabled, make top layer opaque + blndcfg.global_alpha = 0xfff; + } + } + } else { + blndcfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; + blndcfg.global_alpha = 0xfff; + } + + if (cmd_type == VPE_CMD_TYPE_BG || cmd_type == VPE_CMD_TYPE_BG_VSCF_INPUT || + cmd_type == VPE_CMD_TYPE_BG_VSCF_OUTPUT || + (stream_ctx->mps_parent_stream != NULL && + cmd_input->scaler_data.recout.width == VPE_MIN_VIEWPORT_SIZE && + cmd_input->scaler_data.recout.height == VPE_MIN_VIEWPORT_SIZE)) { + // for bg commands, make top layer transparent + // as global alpha only works when global alpha mode, set global alpha mode as well + blndcfg.global_alpha = 0; + blndcfg.global_gain = 0xfff; + blndcfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; + } + + blndcfg.overlap_only = false; + blndcfg.bottom_gain_mode = 0; + + switch (vpe_priv->init.debug.bg_bit_depth) { + case 8: + blndcfg.background_color_bpc = 0; + break; + case 9: + blndcfg.background_color_bpc = 1; + break; + case 10: + blndcfg.background_color_bpc = 2; + break; + case 11: + blndcfg.background_color_bpc = 3; + break; + case 12: + default: + blndcfg.background_color_bpc = 4; // 12 bit. DAL's choice; + break; + } + + blndcfg.top_gain = 0x1f000; + blndcfg.bottom_inside_gain = 0x1f000; + blndcfg.bottom_outside_gain = 0x1f000; + blndcfg.blend_mode = blend_mode; + + mpc->funcs->program_mpcc_blending(mpc, pipe_idx, &blndcfg); + + config_writer_complete(&vpe_priv->config_writer); +} + +void vpe20_set_lls_pref(struct vpe_priv *vpe_priv, struct spl_in *spl_input, + enum color_transfer_func tf, enum vpe_surface_pixel_format pixel_format) +{ + if (tf == TRANSFER_FUNC_LINEAR) { + spl_input->lls_pref = LLS_PREF_YES; + } else { + spl_input->lls_pref = LLS_PREF_NO; + } +} + +void vpe20_program_3dlut_fl(struct vpe_priv *vpe_priv, uint32_t cmd_idx) +{ + struct vpe_cmd_info *cmd_info = vpe_vector_get(vpe_priv->vpe_cmd_vector, cmd_idx); + VPE_ASSERT(cmd_info); + if (!cmd_info) + return; + + uint32_t num_3dluts = + min(vpe_priv->pub.caps->resource_caps.num_mpc_3dlut, cmd_info->num_inputs); + uint32_t used_3dluts = 0; + uint32_t pipe_idx = 0; + + config_writer_set_callback( + &vpe_priv->config_writer, &vpe_priv->fe_cb_ctx, vpe_frontend_config_callback); + + vpe_priv->fe_cb_ctx.stream_sharing = false; + vpe_priv->fe_cb_ctx.stream_op_sharing = false; + + // Program CDC & mpc for 3DLUT FL + for (pipe_idx = 0; pipe_idx < cmd_info->num_inputs; pipe_idx++) { + + struct stream_ctx *stream_ctx = + &vpe_priv->stream_ctx[cmd_info->inputs[pipe_idx].stream_idx]; + struct cdc_fe *cdc_fe = vpe_priv->resource.cdc_fe[pipe_idx]; + struct mpc *mpc = vpe_priv->resource.mpc[pipe_idx]; + struct vpe_surface_info *surface_info = &stream_ctx->stream.surface_info; + struct vpe_cmd_input *cmd_input = &cmd_info->inputs[pipe_idx]; + uint16_t lut3d_bias = 0x0; + uint16_t lut3d_scale = 0x3C00; + + vpe_priv->fe_cb_ctx.stream_idx = cmd_input->stream_idx; + vpe_priv->fe_cb_ctx.vpe_priv = vpe_priv; + + config_writer_set_type(&vpe_priv->config_writer, CONFIG_TYPE_DIRECT, pipe_idx); + + if ((stream_ctx->stream.tm_params.UID != 0 || stream_ctx->stream.tm_params.enable_3dlut) && + (stream_ctx->stream.tm_params.lut_type > VPE_LUT_TYPE_CPU) && + stream_ctx->lut3d_func->state.bits.is_dma) { // FL enabled + + VPE_ASSERT(used_3dluts < num_3dluts); + + /* Fast Load Programming. Always force LUT_DIM_33 */ + used_3dluts++; + cdc_fe->funcs->program_3dlut_fl_config(cdc_fe, LUT_DIM_33, stream_ctx->lut3d_func); + + vpe_convert_from_float_to_fp16(stream_ctx->stream.dma_info.lut3d.bias, &lut3d_bias); + vpe_convert_from_float_to_fp16(stream_ctx->stream.dma_info.lut3d.scale, &lut3d_scale); + mpc->funcs->update_3dlut_fl_bias_scale(mpc, lut3d_bias, lut3d_scale); + + if (mpc->funcs->program_mpc_3dlut_fl_config) { + mpc->funcs->program_mpc_3dlut_fl_config(mpc, + stream_ctx->lut3d_func->dma_params.layout, + stream_ctx->lut3d_func->dma_params.format, true); + } + + mpc->funcs->program_mpc_3dlut_fl( + mpc, LUT_DIM_33, stream_ctx->lut3d_func->lut_3d.use_12bits); + + config_writer_complete(&vpe_priv->config_writer); + + // Start 3dlut Config + config_writer_set_type(&vpe_priv->config_writer, CONFIG_TYPE_3DLUT_FL, pipe_idx); + + config_writer_fill_3dlut_fl_addr(&vpe_priv->config_writer, + (uint64_t)stream_ctx->stream.dma_info.lut3d.data, + stream_ctx->lut3d_func->dma_params.addr_mode, + stream_ctx->stream.dma_info.lut3d.mem_align, LUT_FL_SIZE_33X33X33, false, + stream_ctx->stream.dma_info.lut3d.tmz); + } else { + if (mpc->funcs->program_mpc_3dlut_fl_config != NULL) { + mpc->funcs->program_mpc_3dlut_fl_config(mpc, VPE_3DLUT_MEM_LAYOUT_DISABLE, + VPE_3DLUT_MEM_FORMAT_16161616_UNORM_12MSB, false); + config_writer_complete(&vpe_priv->config_writer); + } + } + } +} + +int32_t vpe20_program_frontend(struct vpe_priv* vpe_priv, uint32_t pipe_idx, uint32_t cmd_idx, + uint32_t cmd_input_idx, bool seg_only) +{ + struct vpe_cmd_info *cmd_info = vpe_vector_get(vpe_priv->vpe_cmd_vector, cmd_idx); + VPE_ASSERT(cmd_info); + if (!cmd_info) + return -1; + + struct vpe_cmd_input *cmd_input = &cmd_info->inputs[cmd_input_idx]; + struct stream_ctx *stream_ctx = &vpe_priv->stream_ctx[cmd_input->stream_idx]; + struct output_ctx *output_ctx = &vpe_priv->output_ctx; + struct vpe_surface_info *surface_info = &stream_ctx->stream.surface_info; + struct cdc_fe *cdc_fe = vpe_priv->resource.cdc_fe[pipe_idx]; + struct dpp *dpp = vpe_priv->resource.dpp[pipe_idx]; + struct mpc *mpc = vpe_priv->resource.mpc[pipe_idx]; + enum input_csc_select select = INPUT_CSC_SELECT_BYPASS; + uint32_t hw_mult = 0; + struct custom_float_format fmt; + struct cnv_keyer_params keyer_params; + enum lut3d_type lut3d_type = vpe_get_stream_lut3d_type(stream_ctx); + bool is_enabled_precsc = false; + + enum mpc_mpccid mpccid = pipe_idx; + enum mpc_mux_topsel topsel; + enum mpc_mux_outmux outmux; + enum mpc_mux_botsel botsel; + enum mpc_mux_oppid oppid; + enum mpcc_blend_mode blend_mode; + + vpe_priv->fe_cb_ctx.stream_idx = cmd_input->stream_idx; + vpe_priv->fe_cb_ctx.vpe_priv = vpe_priv; + + config_writer_set_callback( + &vpe_priv->config_writer, &vpe_priv->fe_cb_ctx, vpe_frontend_config_callback); + + config_writer_set_type(&vpe_priv->config_writer, CONFIG_TYPE_DIRECT, pipe_idx); + + vpe20_build_mpcc_mux_params(vpe_priv, cmd_info->ops, pipe_idx, cmd_info->num_inputs, &topsel, + &botsel, &outmux, &oppid, &blend_mode); + + if (!seg_only) { + /* start front-end programming that can be shared among segments */ + vpe_priv->fe_cb_ctx.stream_sharing = true; + + config_writer_set_type(&vpe_priv->config_writer, CONFIG_TYPE_DIRECT, pipe_idx); + + cdc_fe->funcs->program_surface_config(cdc_fe, surface_info->format, + stream_ctx->stream.rotation, stream_ctx->stream.horizontal_mirror, + surface_info->swizzle); + cdc_fe->funcs->program_crossbar_config(cdc_fe, surface_info->format); + + dpp->funcs->program_cnv(dpp, surface_info->format, vpe_priv->expansion_mode); + dpp->funcs->build_keyer_params(dpp, stream_ctx, &keyer_params); + dpp->funcs->program_alpha_keyer(dpp, &keyer_params); + + if (stream_ctx->bias_scale) + dpp->funcs->program_cnv_bias_scale(dpp, stream_ctx->bias_scale); + + /* If input adjustment exists, program the ICSC with those values. */ + if (stream_ctx->input_cs) { + if (!is_enabled_precsc) + select = INPUT_CSC_SELECT_ICSC; + dpp->funcs->program_post_csc(dpp, stream_ctx->cs, select, stream_ctx->input_cs); + } else { + dpp->funcs->program_post_csc(dpp, stream_ctx->cs, select, NULL); + } + dpp->funcs->program_input_transfer_func(dpp, stream_ctx->input_tf); + + // RMCM LOCATION MUST BE SET BEFORE PROGRAMMING RMCM COMPONENTS + // program shaper, 3dlut and 1dlut in MPC for stream before blend + if (stream_ctx->enable_3dlut) { + mpc->funcs->attach_3dlut_to_mpc_inst(mpc, pipe_idx); + } + + if (stream_ctx->stream.hist_params.hist_dsets > 0) + { + dpp->funcs->program_histogram(dpp, &stream_ctx->stream.hist_params, stream_ctx->cs); + } + + // top mux has to be set first before mpc programming + mpc->funcs->program_mpcc_mux(mpc, mpccid, topsel, botsel, outmux, oppid); + /** VPE2.0 Gamut Remaps + * 4 gamut remaps in the pipe available. + * 1 in RMCM before 3dlut + Shaper. Only 1 RMCM shared for all pipes + * 2 in MCM (Gamut-First -> BlndGamma -> Gamut Second). Each pipe has an MCM. + * 1 post blend. Each pipe has one. + */ + struct colorspace_transform *gamut_matrix_mcm1 = stream_ctx->gamut_remap; + struct colorspace_transform *gamut_matrix_rmcm = NULL; + struct vpe_3dlut *lut3d_func = NULL; + struct transfer_func *func_shaper = NULL; + + if (stream_ctx->stream.tm_params.enable_3dlut) { + // RMCM Programming. Only Programmed Once. + func_shaper = stream_ctx->in_shaper_func; + lut3d_func = stream_ctx->lut3d_func; + gamut_matrix_rmcm = stream_ctx->gamut_remap; + gamut_matrix_mcm1 = NULL; + + mpc->funcs->set_gamut_remap2(mpc, gamut_matrix_rmcm, VPE_MPC_RMCM_GAMUT_REMAP); + } + + // Always Pre-Blend. RMCM (RMCM_GAMUT + 3dLUT + Shaper) + mpc->funcs->program_movable_cm(mpc, func_shaper, lut3d_func, stream_ctx->blend_tf, false); + + // Program if RMCM is not used + mpc->funcs->set_gamut_remap2(mpc, gamut_matrix_mcm1, VPE_MPC_MCM_FIRST_GAMUT_REMAP); + + // Always Program Pre-Blend Gamut + mpc->funcs->set_gamut_remap2(mpc, output_ctx->gamut_remap, VPE_MPC_MCM_SECOND_GAMUT_REMAP); + + // Always Bypass Post-Blend Gamut Remap + mpc->funcs->set_gamut_remap2(mpc, NULL, VPE_MPC_GAMUT_REMAP); + + // program hdr_mult + fmt.exponenta_bits = 6; + fmt.mantissa_bits = 12; + fmt.sign = true; + if (stream_ctx->stream.tm_params.UID || stream_ctx->stream.tm_params.enable_3dlut) { + if (!vpe_convert_to_custom_float_format( + stream_ctx->lut3d_func->hdr_multiplier, &fmt, &hw_mult)) { + VPE_ASSERT(0); + } + } else { + if (!vpe_convert_to_custom_float_format(stream_ctx->white_point_gain, &fmt, &hw_mult)) { + VPE_ASSERT(0); + } + } + dpp->funcs->set_hdr_multiplier(dpp, hw_mult); + + if (vpe_priv->init.debug.dpp_crc_ctrl) + dpp->funcs->program_crc(dpp, true); + + if (vpe_priv->init.debug.mpc_crc_ctrl) + mpc->funcs->program_crc(mpc, true); + + config_writer_complete(&vpe_priv->config_writer); + // put other hw programming for stream specific that can be shared here + } else if (stream_ctx->mps_parent_stream != NULL) { + vpe_priv->fe_cb_ctx.stream_sharing = false; + mpc->funcs->program_mpcc_mux(mpc, mpccid, topsel, botsel, outmux, oppid); + + config_writer_complete(&vpe_priv->config_writer); + } + + vpe20_create_stream_ops_config(vpe_priv, pipe_idx, cmd_input_idx, stream_ctx, cmd_info); + + /* start segment specific programming */ + vpe_priv->fe_cb_ctx.stream_sharing = false; + vpe_priv->fe_cb_ctx.stream_op_sharing = false; + vpe_priv->fe_cb_ctx.cmd_type = VPE_CMD_TYPE_COMPOSITING; + + // Due to MPS algorithm, you may have two streams in a single build command, + // where one of the streams requires tone mapping and the pipe processing that + // stream has changed since the previous command. Thus there is a need for per + // segment RMCM programming. + // RMCM LOCATION MUST BE SET BEFORE PROGRAMMING RMCM COMPONENTS + // program shaper, 3dlut and 1dlut in MPC for stream before blend + // if !seg_only, this would be programmed before + if (seg_only) { + if (stream_ctx->enable_3dlut) { + mpc->funcs->attach_3dlut_to_mpc_inst(mpc, pipe_idx); + mpc->funcs->shaper_bypass(mpc, false); + } + } + + + cdc_fe->funcs->program_viewport( + cdc_fe, &cmd_input->scaler_data.viewport, &cmd_input->scaler_data.viewport_c); + + dpp->funcs->set_segment_scaler(dpp, &cmd_input->scaler_data); + + if (cmd_info->num_inputs > 1) { + if (pipe_idx < (uint32_t)(cmd_info->num_inputs - 1)) { + // Need to enable next pipes dpp clocks before starting programming, so enable at + // end of previous (current) pipe + + // This if statement required to avoid warning compilation error + if (pipe_idx + 1 < MAX_INPUT_PIPE) + vpe_priv->resource.dpp[pipe_idx + 1]->funcs->enable_clocks( + vpe_priv->resource.dpp[pipe_idx + 1], true); + } + if (pipe_idx != 0) { + // After finishing the pipe programming, we can disable the clock of the current pipe. + dpp->funcs->enable_clocks(dpp, false); + } + } + + config_writer_complete(&vpe_priv->config_writer); + + return 0; +} + +enum vpe_status vpe20_populate_cmd_info(struct vpe_priv *vpe_priv) +{ + uint16_t stream_idx; + struct stream_ctx *stream_ctx; + enum vpe_status status; + uint16_t avail_pipe_count; + + for (stream_idx = 0; stream_idx < (uint16_t)vpe_priv->num_streams; stream_idx++) { + stream_ctx = &vpe_priv->stream_ctx[stream_idx]; + avail_pipe_count = + (uint16_t)vpe_priv->resource.get_num_pipes_available(vpe_priv, stream_ctx); + if (!vpe_should_generate_cmd_info(stream_ctx)) + continue; + + if (stream_ctx->mps_parent_stream != NULL) { + status = vpe_fill_mps_blend_cmd_info(vpe_priv, stream_ctx->mps_ctx); + if (status != VPE_STATUS_OK) { + return status; + } + } else if (stream_ctx->stream_type == VPE_STREAM_TYPE_BKGR_ALPHA) { + // first pass to generate top layer with alpha + status = vpe_priv->resource.fill_alpha_through_luma_cmd_info(vpe_priv, stream_idx); + if (status != VPE_STATUS_OK) { + return status; + } + // second pass to blend with new background stream (always 2 after alpha stream) + status = vpe_priv->resource.fill_blending_cmd_info(vpe_priv, + VPE_DESTINATION_AS_INPUT_STREAM_INDEX, + stream_idx + VPE_BKGR_STREAM_BACKGROUND_OFFSET); + if (status != VPE_STATUS_OK) { + return status; + } + stream_idx += 2; // skip next two streams - bkgr video and background + } + else if (avail_pipe_count > 1) { + status = vpe_priv->resource.fill_performance_mode_cmd_info( + vpe_priv, stream_idx, avail_pipe_count); + if (status != VPE_STATUS_OK) { + return status; + } + } else if (stream_idx > 0 && stream_ctx->stream.blend_info.blending) { + status = vpe_priv->resource.fill_blending_cmd_info( + vpe_priv, stream_idx, VPE_DESTINATION_AS_INPUT_STREAM_INDEX); + if (status != VPE_STATUS_OK) { + return status; + } + } else { + status = vpe_priv->resource.fill_non_performance_mode_cmd_info(vpe_priv, stream_idx); + if (status != VPE_STATUS_OK) { + return status; + } + } + } + + return VPE_STATUS_OK; +} + +bool vpe20_check_input_format(enum vpe_surface_pixel_format format) +{ + if (vpe_is_32bit_packed_rgb(format)) + return true; + + if (vpe_is_yuv420(format)) + return true; + + if (vpe_is_yuv422(format)) + return true; + + if (vpe_is_yuv444(format)) + return true; + + if (vpe_is_fp16(format)) + return true; + + if (vpe_is_rgb16(format)) + return true; + + if (format == VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_RGB) + return true; + + return false; +} + +bool vpe20_check_output_format(enum vpe_surface_pixel_format format) +{ + if (vpe_is_32bit_packed_rgb(format)) + return true; + if (vpe_is_fp16(format)) + return true; + if (vpe_is_yuv420(format) || vpe_is_yuv422(format)) + return true; + if (vpe_is_rgb16(format)) + return true; + if (vpe_is_yuv444(format)) + return true; + if (format == VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_RGB) + return true; + return false; +} + +bool vpe20_check_output_color_space( + enum vpe_surface_pixel_format format, const struct vpe_color_space *vcs) +{ + enum color_space cs; + enum color_transfer_func tf; + + vpe_color_get_color_space_and_tf(vcs, &cs, &tf); + if (cs == COLOR_SPACE_UNKNOWN || tf == TRANSFER_FUNC_UNKNOWN) + return false; + + if (vpe_is_fp16(format) && tf != TRANSFER_FUNC_LINEAR) + return false; + + return true; +} + +enum vpe_status vpe20_set_num_segments(struct vpe_priv *vpe_priv, struct stream_ctx *stream_ctx, + struct scaler_data *scl_data, struct vpe_rect *src_rect, struct vpe_rect *dst_rect, + uint32_t *max_seg_width, uint32_t recout_width_alignment) +{ + uint16_t num_segs; + uint32_t aligned_width; + double ratio; + uint16_t free_pipes; + struct dpp *dpp = vpe_priv->resource.dpp[0]; + const uint32_t max_lb_size = dpp->funcs->get_line_buffer_size(); + struct vpe_rect local_src_rect = *src_rect; + uint16_t avail_pipe_count = + (uint16_t)vpe_priv->resource.get_num_pipes_available(vpe_priv, stream_ctx); + bool use_aligned = (recout_width_alignment != VPE_NO_ALIGNMENT); + enum vpe_status res = VPE_STATUS_OK; + + *max_seg_width = min(*max_seg_width, max_lb_size / scl_data->taps.v_taps); + + // The src_rect is segmented horizontally during orthogonal rotation + // Swap the src_rect's width and height so the src_rect's height can be examined + // for segmentation in vpe_get_num_segments + if (stream_ctx->stream.rotation == VPE_ROTATION_ANGLE_90 || + stream_ctx->stream.rotation == VPE_ROTATION_ANGLE_270) { + swap(local_src_rect.width, local_src_rect.height); + } + + ratio = (double)local_src_rect.width / dst_rect->width; + + if (stream_ctx->mps_parent_stream == NULL) { + num_segs = vpe_get_num_segments(vpe_priv, &local_src_rect, dst_rect, *max_seg_width); + + if (use_aligned && num_segs > 1) { + aligned_width = dst_rect->width / num_segs; + aligned_width = vpe_align_seg(aligned_width, recout_width_alignment); + if (aligned_width * num_segs != dst_rect->width) { + + // Increase the number of segments if the aligned width is greater than the maximum + // allowed viewport size. Only happens if the split size is too large. + if (aligned_width > *max_seg_width || + (uint32_t)(aligned_width * ratio) > *max_seg_width) + num_segs++; + } + } + + free_pipes = num_segs % avail_pipe_count; + if (avail_pipe_count > 1 && (free_pipes != 0)) { + free_pipes = avail_pipe_count - free_pipes; + // only use the remaining pipes for the segmentation if the segment size is greater + // or equal to the minimum viewport size when adding the extra segments + if (local_src_rect.width / (num_segs + free_pipes) >= VPE_MIN_VIEWPORT_SIZE && + dst_rect->width / (num_segs + free_pipes) >= VPE_MIN_VIEWPORT_SIZE) { + + num_segs += free_pipes; + } + } + res = vpe_alloc_segment_ctx(vpe_priv, stream_ctx, num_segs); + + if (res == VPE_STATUS_OK) { + stream_ctx->num_segments = num_segs; + } + } else { // mps blend + num_segs = + vpe_mps_get_num_segs(vpe_priv, stream_ctx, max_seg_width, recout_width_alignment); + + if (num_segs == 0) + res = VPE_STATUS_ERROR; + + if (res == VPE_STATUS_OK) + res = vpe_alloc_segment_ctx(vpe_priv, stream_ctx, num_segs); + + stream_ctx->num_segments = num_segs; + } + + return res; +} + +uint32_t vpe20_get_hw_surface_format(enum vpe_surface_pixel_format format) +{ + uint32_t surf_format = 8; + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: + surf_format = 1; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB565: + surf_format = 3; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XRGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888: + surf_format = 8; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888: + surf_format = 9; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: + surf_format = 10; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102: + surf_format = 11; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888: // use crossbar + surf_format = 12; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_YCrCbA8888: + surf_format = 13; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb8888: + surf_format = 14; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrCbYA8888: + surf_format = 15; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /* use crossbar */ + surf_format = 20; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616: + surf_format = 21; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: /* use crossbar */ + surf_format = 24; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F: + surf_format = 25; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616_UNORM: + surf_format = 26; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_UNORM: + surf_format = 27; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616_SNORM: + surf_format = 28; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_SNORM: + surf_format = 29; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb12121212: + surf_format = 44; // 12 bit slice MSB + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA12121212: + surf_format = 46; // 12 bit slice MSB + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbCr: + surf_format = 65; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrCb: + surf_format = 64; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbCr: + surf_format = 67; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrCb: + surf_format = 66; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrCb: + surf_format = 68; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbCr: + surf_format = 69; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ALPHA_THRU_LUMA: + surf_format = 70; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: + surf_format = 112; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: + surf_format = 113; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: + surf_format = 114; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102: // use crossbar + surf_format = 115; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: + surf_format = 118; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: + surf_format = 119; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbYCr: // use crossbar + surf_format = 72; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CbYCrY: + surf_format = 74; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbYCr: + surf_format = 76; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CbYCrY: + surf_format = 78; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbYCr: + surf_format = 80; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CbYCrY: + surf_format = 82; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_R8: + surf_format = 120; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_R16: + surf_format = 125; + break; + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_RGB: + surf_format = 265; + break; + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_YCbCr: + surf_format = 269; + break; + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB: + surf_format = 277; + break; + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB_FLOAT: + surf_format = 280; + break; + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_YCbCr: + surf_format = 298; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE: + default: + VPE_ASSERT("Invalid pixel format"); + break; + } + return surf_format; +} + +bool vpe20_get_dcc_compression_output_cap( + const struct vpe_dcc_surface_param *params, struct vpe_surface_dcc_cap *cap) +{ + cap->capable = false; + return cap->capable; +} + +bool vpe20_get_dcc_compression_input_cap( + const struct vpe_dcc_surface_param *params, struct vpe_surface_dcc_cap *cap) +{ + if (!vpe_is_dual_plane_format(params->format) && !vpe_is_planar_format(params->format)) { + cap->capable = true; + cap->is_internal_dcc = true; + } else { + cap->capable = false; + cap->is_internal_dcc = false; + } + return cap->capable; +} + +//(BYTES_IN_DWORD * (HEADER_DWORD + (CONFIG_DWORD * NUM_CONFIG_PER_PIPE * NUM_PIPE)) +// WORST_CASE_ALIGNMENT PER CONFIG IS 60 BYTES +#define VPE20_GENERAL_VPE_DESC_SIZE 288 // 4 * (4 + (2 * MAX_NUM_SAVED_CONFIG * 2)) +#define VPE20_GENERAL_EMB_USAGE_FRAME_SHARED 6400 // 4876(max recorded) + round up margin +#define VPE20_GENERAL_EMB_USAGE_3DLUT_FRAME_SHARED 40960 // currently max 35192 is recorded +#define VPE20_GENERAL_EMB_USAGE_BG_SHARED 4000 +#define VPE20_GENERAL_EMB_USAGE_SEG_NON_SHARED 6400 // 3820 (max recorded) + round up margin + +void vpe20_get_bufs_req(struct vpe_priv *vpe_priv, struct vpe_bufs_req *req) +{ + uint32_t i; + struct vpe_cmd_info *cmd_info; + uint32_t stream_idx = 0xFFFFFFFF; + uint64_t emb_req = 0; + bool have_visual_confirm_input = false; + bool have_visual_confirm_output = false; + + req->cmd_buf_size = 0; + req->emb_buf_size = 0; + + for (i = 0; i < vpe_priv->vpe_cmd_vector->num_elements; i++) { + uint32_t per_pipe_size = 0; + + cmd_info = vpe_vector_get(vpe_priv->vpe_cmd_vector, i); + VPE_ASSERT(cmd_info); + if (!cmd_info) + continue; + + // each cmd consumes one VPE descriptor + req->cmd_buf_size += VPE20_GENERAL_VPE_DESC_SIZE; + + // if a command represents the first segment of a stream, + // total amount of config sizes is added, but for other segments + // just the segment specific config size is added + switch (cmd_info->ops) { + case VPE_CMD_OPS_COMPOSITING: + case VPE_CMD_OPS_BLENDING: + case VPE_CMD_OPS_ALPHA_THROUGH_LUMA: + // embedded buffer only bigger size if DIRECT CONFIG is used + if (stream_idx != cmd_info->inputs[0].stream_idx) { + + per_pipe_size += (cmd_info->lut3d_type == LUT3D_TYPE_CPU) + ? VPE20_GENERAL_EMB_USAGE_3DLUT_FRAME_SHARED + : VPE20_GENERAL_EMB_USAGE_FRAME_SHARED; + per_pipe_size += VPE20_GENERAL_EMB_USAGE_SEG_NON_SHARED; + + stream_idx = cmd_info->inputs[0].stream_idx; + } else { + per_pipe_size += VPE20_GENERAL_EMB_USAGE_SEG_NON_SHARED; + } + + emb_req += (per_pipe_size * cmd_info->num_inputs); + break; + + case VPE_CMD_OPS_BG: + emb_req += (i > 0) ? VPE20_GENERAL_EMB_USAGE_SEG_NON_SHARED + : VPE20_GENERAL_EMB_USAGE_BG_SHARED; + break; + case VPE_CMD_OPS_BG_VSCF_INPUT: + emb_req += have_visual_confirm_input ? VPE20_GENERAL_EMB_USAGE_SEG_NON_SHARED + : VPE20_GENERAL_EMB_USAGE_BG_SHARED; + have_visual_confirm_input = true; + break; + case VPE_CMD_OPS_BG_VSCF_OUTPUT: + emb_req += have_visual_confirm_output ? VPE20_GENERAL_EMB_USAGE_SEG_NON_SHARED + : VPE20_GENERAL_EMB_USAGE_BG_SHARED; + have_visual_confirm_output = true; + break; + case VPE_CMD_OPS_BG_VSCF_PIPE0: + case VPE_CMD_OPS_BG_VSCF_PIPE1: + emb_req += VPE20_GENERAL_EMB_USAGE_SEG_NON_SHARED + VPE20_GENERAL_EMB_USAGE_BG_SHARED; + break; + default: + VPE_ASSERT(0); + break; + } + + req->emb_buf_size += emb_req; + } + + req->cmd_buf_size += VPE_PREDICATION_CMD_SIZE; +} + +enum vpe_status vpe20_check_mirror_rotation_support(const struct vpe_stream *stream) +{ + enum vpe_swizzle_mode_values swizzle_mode; + enum vpe_scan_direction scan_dir; + + VPE_ASSERT(stream != NULL); + + swizzle_mode = stream->surface_info.swizzle; + scan_dir = vpe_get_scan_direction( + stream->rotation, stream->horizontal_mirror, stream->vertical_mirror); + + if (swizzle_mode == VPE_SW_LINEAR) { + + if (!vpe_supported_linear_scan_pattern(scan_dir)) + return VPE_STATUS_ROTATION_NOT_SUPPORTED; + + if (stream->rotation == VPE_ROTATION_ANGLE_90 || stream->rotation == VPE_ROTATION_ANGLE_270) + return VPE_STATUS_ROTATION_NOT_SUPPORTED; + + if (stream->vertical_mirror) + return VPE_STATUS_MIRROR_NOT_SUPPORTED; + } + + if (vpe_is_yuv_packed(stream->surface_info.format) && + vpe_is_yuv422(stream->surface_info.format)) { + + if (stream->rotation != VPE_ROTATION_ANGLE_0) + return VPE_STATUS_ROTATION_NOT_SUPPORTED; + + if (stream->vertical_mirror) + return VPE_STATUS_MIRROR_NOT_SUPPORTED; + } + + return VPE_STATUS_OK; +} + +/* This function generates software points for the blnd gam programming block. + The logic for the blndgam/ogam programming sequence is a function of: + 1. Output Range (Studio Full) + 2. 3DLUT usage + 3. Output format (HDR SDR) + + SDR Out + TM Case + BLNDGAM : NL -> NL*S + B + OGAM : Bypass + Non TM Case + BLNDGAM : L -> NL*S + B + OGAM : Bypass + HDR Out + TM Case + BLNDGAM : NL -> L + OGAM : L -> NL + Non TM Case + BLNDGAM : Bypass + OGAM : L -> NL + +*/ +enum vpe_status vpe20_update_blnd_gamma(struct vpe_priv *vpe_priv, + const struct vpe_build_param *param, const struct vpe_stream *stream, + struct transfer_func *blnd_tf) +{ + struct output_ctx *output_ctx; + struct vpe_color_space tm_out_cs; + struct fixed31_32 x_scale = vpe_fixpt_one; + struct fixed31_32 y_scale = vpe_fixpt_one; + struct fixed31_32 y_bias = vpe_fixpt_zero; + bool can_bypass = false; + bool lut3d_enabled = false; + enum color_space cs = COLOR_SPACE_2020_RGB_FULLRANGE; + enum color_transfer_func tf = TRANSFER_FUNC_LINEAR; + enum vpe_status status = VPE_STATUS_OK; + const struct vpe_tonemap_params *tm_params = &stream->tm_params; + + output_ctx = &vpe_priv->output_ctx; + lut3d_enabled = tm_params->UID != 0 || tm_params->enable_3dlut; + + if (stream->flags.geometric_scaling) { + vpe_color_update_degamma_tf(vpe_priv, tf, x_scale, y_scale, y_bias, true, blnd_tf); + } else { + // If SDR out -> Blend should be NL + if (!vpe_is_HDR(output_ctx->tf)) { + if (lut3d_enabled) { + tf = TRANSFER_FUNC_LINEAR; + } else { + tf = output_ctx->tf; + } + vpe_color_update_regamma_tf( + vpe_priv, tf, x_scale, y_scale, y_bias, can_bypass, blnd_tf); + } else { + + if (lut3d_enabled) { + vpe_color_build_tm_cs(tm_params, ¶m->dst_surface, &tm_out_cs); + vpe_color_get_color_space_and_tf(&tm_out_cs, &cs, &tf); + } else { + can_bypass = true; + } + + vpe_color_update_degamma_tf(vpe_priv, tf, x_scale, y_scale, y_bias, can_bypass, blnd_tf); + } + } + return status; +} + +/* This function generates software points for the ogam gamma programming block. + The logic for the blndgam/ogam programming sequence is a function of: + 1. 3DLUT usage + 2. Output format (HDR SDR) + SDR Out + TM Case + BLNDGAM : Bypass + OGAM : Bypass + Non TM Case + BLNDGAM : L -> NL + OGAM : Bypass + Full range HDR Out + TM Case + BLNDGAM : NL -> L + OGAM : L -> NL + Non TM Case + BLNDGAM : Bypass + OGAM : L -> NL +*/ +enum vpe_status vpe20_update_output_gamma(struct vpe_priv *vpe_priv, + const struct vpe_build_param *param, struct transfer_func *output_tf, bool geometric_scaling) +{ + bool can_bypass = false; + struct output_ctx *output_ctx = &vpe_priv->output_ctx; + enum vpe_status status = VPE_STATUS_OK; + struct fixed31_32 y_scale = vpe_fixpt_one; + + if (vpe_is_fp16(param->dst_surface.format)) { + y_scale = vpe_fixpt_mul_int(y_scale, CCCS_NORM); + } + + if (!geometric_scaling && vpe_is_HDR(output_ctx->tf)) + can_bypass = false; + else + can_bypass = true; + + vpe_color_update_regamma_tf( + vpe_priv, output_ctx->tf, vpe_fixpt_one, y_scale, vpe_fixpt_zero, can_bypass, output_tf); + + return status; +} + +static bool needs_segmentation(enum vpe_stream_type type) +{ + switch (type) { + case VPE_STREAM_TYPE_INPUT: + case VPE_STREAM_TYPE_BKGR_VIDEO: + case VPE_STREAM_TYPE_BKGR_ALPHA: + case VPE_STREAM_TYPE_BKGR_BACKGROUND: + return true; + default: + return false; + } +} + +static void update_spl_recout_width_align(struct basic_in *basic_in, uint32_t num_segs, + struct vpe_rect *dst_rect, uint32_t recout_width_alignment) +{ + // If the alignment is needed, use the alignment value to calculate the number of segments + if (recout_width_alignment != VPE_NO_ALIGNMENT) { + uint32_t aligned_width; + aligned_width = (dst_rect->width + num_segs - 1) / num_segs; + aligned_width = vpe_align_seg(aligned_width, recout_width_alignment); + + basic_in->num_h_slices_recout_width_align.use_recout_width_aligned = true; + basic_in->num_h_slices_recout_width_align.num_slices_recout_width.mpc_recout_width_align = + aligned_width; + } else { + basic_in->num_h_slices_recout_width_align.use_recout_width_aligned = false; + basic_in->num_h_slices_recout_width_align.num_slices_recout_width.mpc_num_h_slices = + num_segs; + } +} + +uint16_t vpe20_get_bg_stream_idx(struct vpe_priv *vpe_priv) +{ + // For BGR we insert background in later stream + if (vpe_priv->stream_ctx[0].stream.flags.is_alpha_plane == false) + return 0; + else + return VPE_BKGR_STREAM_BACKGROUND_OFFSET; +} + +static bool rect_contained_in_rect(struct vpe_rect inside_rect, struct vpe_rect containing_rect) +{ + return !(inside_rect.x < containing_rect.x || inside_rect.y < containing_rect.y || + inside_rect.x + inside_rect.width > containing_rect.x + containing_rect.width || + inside_rect.y + inside_rect.height > containing_rect.y + containing_rect.height); +} + +static enum vpe_status segment_stream(struct vpe_priv *vpe_priv, struct stream_ctx *stream_ctx, + struct vpe_rect target_rect, bool dst_subsampled, bool enable_frod, uint32_t recout_alignment) +{ + uint16_t seg_idx; + struct segment_ctx *segment_ctx; + struct scaler_data scl_data; + struct vpe_rect src_rect; + struct vpe_rect dst_rect; + enum vpe_surface_pixel_format pixel_format; + struct spl_in *spl_input; + struct spl_out *spl_output; + uint32_t max_seg_width; + struct dpp *dpp = vpe_priv->resource.dpp[0]; + enum vpe_status res = VPE_STATUS_OK; + bool skip_program_scl = false; + + if (!needs_segmentation(stream_ctx->stream_type)) + return res; + + spl_input = &stream_ctx->spl_input; + spl_output = &stream_ctx->spl_output; + src_rect = stream_ctx->stream.scaling_info.src_rect; + dst_rect = stream_ctx->stream.scaling_info.dst_rect; + stream_ctx->scan = vpe_get_scan_direction(stream_ctx->stream.rotation, + stream_ctx->stream.horizontal_mirror, stream_ctx->stream.vertical_mirror); + pixel_format = stream_ctx->stream.surface_info.format; + max_seg_width = vpe_priv->resource.get_max_seg_width( + &vpe_priv->output_ctx, stream_ctx->stream.surface_info.format, stream_ctx->scan); + + if (dst_rect.width == 0 && dst_rect.height == 0) { + stream_ctx->num_segments = 0; + return VPE_STATUS_OK; + } + + if (!vpe_is_valid_vp(&src_rect, &dst_rect)) + return VPE_STATUS_VIEWPORT_SIZE_NOT_SUPPORTED; + if (enable_frod) { + if ((src_rect.width < (VPE_MIN_VIEWPORT_SIZE * MAX_FROD_VIEWPORT_DIVIDER)) || + (src_rect.height < (VPE_MIN_VIEWPORT_SIZE * MAX_FROD_VIEWPORT_DIVIDER)) || + (dst_rect.width < (VPE_MIN_VIEWPORT_SIZE * MAX_FROD_VIEWPORT_DIVIDER)) || + (dst_rect.height < (VPE_MIN_VIEWPORT_SIZE * MAX_FROD_VIEWPORT_DIVIDER))) { + return VPE_STATUS_VIEWPORT_SIZE_NOT_SUPPORTED; + } + } + vpe_clip_stream(&src_rect, &dst_rect, &target_rect); + + if (vpe_is_zero_rect(&src_rect) || vpe_is_zero_rect(&dst_rect)) { + vpe_log("calculate_segments: after clipping, src or dst rect contains no area. Skip " + "this stream.\n"); + stream_ctx->num_segments = 0; + return res; + } + + if (!vpe_is_valid_vp(&src_rect, &dst_rect)) + return VPE_STATUS_VIEWPORT_SIZE_NOT_SUPPORTED; + + if (!vpe_is_scaling_factor_supported( + vpe_priv, &src_rect, &dst_rect, stream_ctx->stream.rotation)) + return VPE_STATUS_SCALING_RATIO_NOT_SUPPORTED; + + // init scaler data to get the number of taps for calculating the number of segments and + // maximum viewport + if (!init_scaler_data( + stream_ctx, spl_input, spl_output, &scl_data, &vpe_priv->output_ctx, max_seg_width)) + return VPE_STATUS_SCALING_RATIO_NOT_SUPPORTED; + if (stream_ctx->mps_parent_stream == NULL && stream_ctx->stream_idx == 0 && + vpe_priv->num_input_streams > 1) { + struct stream_ctx *mps_stream_ctx[2] = {&vpe_priv->stream_ctx[0], &vpe_priv->stream_ctx[1]}; + + if (vpe_is_mps_possible(vpe_priv, mps_stream_ctx, 2, recout_alignment)) + if (vpe_init_mps_ctx(vpe_priv, mps_stream_ctx, 2) != VPE_STATUS_OK) + return VPE_STATUS_ERROR; + } + + res = vpe_priv->resource.set_num_segments(vpe_priv, stream_ctx, &scl_data, + &stream_ctx->stream.scaling_info.src_rect, &stream_ctx->stream.scaling_info.dst_rect, + &max_seg_width, recout_alignment); + if (res != VPE_STATUS_OK) + return res; + if (stream_ctx->mps_parent_stream == NULL) + update_spl_recout_width_align( + &spl_input->basic_in, stream_ctx->num_segments, &dst_rect, recout_alignment); + else + update_spl_recout_width_align( + &spl_input->basic_in, stream_ctx->num_segments, &dst_rect, VPE_NO_ALIGNMENT); + for (seg_idx = 0; seg_idx < stream_ctx->num_segments; seg_idx++) { + + segment_ctx = &stream_ctx->segment_ctx[seg_idx]; + segment_ctx->segment_idx = seg_idx; + segment_ctx->stream_ctx = stream_ctx; + segment_ctx->scaler_data.format = stream_ctx->stream.surface_info.format; + segment_ctx->scaler_data.lb_params.alpha_en = stream_ctx->per_pixel_alpha; + + // SPL Calculation + spl_output->dscl_prog_data = &segment_ctx->scaler_data.dscl_prog_data; + spl_input->basic_in.mpc_h_slice_index = seg_idx; + vpe_priv->resource.update_opp_adjust_and_boundary(stream_ctx, seg_idx, dst_subsampled, + &src_rect, &dst_rect, &vpe_priv->output_ctx, &spl_input->basic_in.opp_recout_adjust); + + if (stream_ctx->mps_parent_stream == NULL) { + spl_input->basic_in.custom_width = 0; + spl_input->basic_in.custom_x = 0; + } else { + // For mps we need to pass custom start_x and width in SPL in + struct vpe_mps_ctx *mps_ctx = stream_ctx->mps_parent_stream->mps_ctx; + for (int i = 0; i < mps_ctx->num_streams; i++) { + if (mps_ctx->stream_idx[i] == stream_ctx->stream_idx) { + VPE_ASSERT( + mps_ctx->segment_widths[i]->num_elements == stream_ctx->num_segments); + + int32_t rect_x = stream_ctx->stream.scaling_info.dst_rect.x; + int32_t target_x = vpe_priv->output_ctx.target_rect.x; + + int start_x = rect_x > target_x ? 0 : target_x - rect_x; + int width = 0; + for (int j = 0; j <= seg_idx; j++) { + start_x += width; + width = *(uint32_t *)vpe_vector_get(mps_ctx->segment_widths[i], j); + } + + spl_input->basic_in.custom_width = width; + spl_input->basic_in.custom_x = start_x; + break; + } + } + } + if (!SPL_NAMESPACE(spl_calculate_scaler_params(spl_input, spl_output))) + return VPE_STATUS_SCALER_NOT_SET; + + if ((!skip_program_scl) && vpe_is_yuv422(pixel_format) && vpe_is_yuv_packed(pixel_format)) + adjust_packed_422_scaler_params(spl_output, stream_ctx->stream.horizontal_mirror); + + vpe_spl_scl_to_vpe_scl(spl_output, &segment_ctx->scaler_data); + + // Update vpe values based on SPL_out + vpe_priv->resource.calculate_dst_viewport_and_active(segment_ctx, max_seg_width); + } + return res; +} + +enum vpe_status vpe20_calculate_segments( + struct vpe_priv *vpe_priv, const struct vpe_build_param *params) +{ + struct vpe_rect *gaps; + uint16_t gaps_cnt, max_gaps; + uint16_t stream_idx; + uint32_t max_seg_width = vpe_priv->pub.caps->plane_caps.max_viewport_width; + bool dst_subsampled = vpe_is_subsampled_format(params->dst_surface.format); + uint32_t recout_alignment = vpe_get_recout_width_alignment(params); + enum vpe_status res = VPE_STATUS_OK; + + for (stream_idx = 0; stream_idx < (uint16_t)params->num_streams; stream_idx++) { + res = segment_stream(vpe_priv, &vpe_priv->stream_ctx[stream_idx], params->target_rect, + dst_subsampled, params->frod_param.enable_frod, recout_alignment); + + if (res != VPE_STATUS_OK) + break; + } + + /* If the stream width is less than max_seg_width - 1024, and it + * lies inside a max_seg_width window of the background, vpe needs + * an extra bg segment to store that. + 1 2 3 4 5 + |....|....|.**.|....| + |....|....|.**.|....| + |....|....|.**.|....| + + (*: stream + .: background + |: 1k separator) + + */ + + if (res == VPE_STATUS_OK) { + // mps does its own bg generation + if (vpe_priv->stream_ctx[0].mps_parent_stream == NULL) { + // Background doesn't need rotation, so we can use max_viewport_width + max_seg_width = vpe_priv->pub.caps->plane_caps.max_viewport_width; + max_gaps = + (uint16_t)(max((int_divide_with_ceil(params->target_rect.width, max_seg_width)), + 1) + + 1); + + gaps = vpe_zalloc(sizeof(struct vpe_rect) * max_gaps); + if (!gaps) + return VPE_STATUS_NO_MEMORY; + + gaps_cnt = vpe_priv->resource.find_bg_gaps( + vpe_priv, &(params->target_rect), gaps, recout_alignment, max_gaps); + if (gaps_cnt > 0) + vpe_priv->resource.create_bg_segments(vpe_priv, gaps, gaps_cnt, VPE_CMD_OPS_BG); + + if (gaps != NULL) { + vpe_free(gaps); + gaps = NULL; + } + } + + vpe_handle_output_h_mirror(vpe_priv); + + res = vpe_priv->resource.populate_cmd_info(vpe_priv); + } + + if (res == VPE_STATUS_OK) + res = vpe_create_visual_confirm_segs(vpe_priv, params, max_seg_width); + + return res; +} + +void vpe20_fill_bg_cmd_scaler_data( + struct stream_ctx *stream_ctx, struct vpe_rect *dst_viewport, struct scaler_data *scaler_data) +{ + struct vpe_priv *vpe_priv = stream_ctx->vpe_priv; + int32_t vp_x = stream_ctx->stream.scaling_info.src_rect.x; + int32_t vp_y = stream_ctx->stream.scaling_info.src_rect.y; + uint16_t src_h_div = vpe_is_yuv420(stream_ctx->stream.surface_info.format) ? 2 : 1; + uint16_t src_v_div = vpe_is_yuv420(stream_ctx->stream.surface_info.format) ? 2 : 1; + uint16_t dst_h_div = vpe_is_yuv420(vpe_priv->output_ctx.surface.format) ? 2 : 1; + uint16_t dst_v_div = vpe_is_yuv420(vpe_priv->output_ctx.surface.format) ? 2 : 1; + + if (vpe_is_yuv422(stream_ctx->stream.surface_info.format)) + src_h_div = 2; + if (vpe_is_yuv422(vpe_priv->output_ctx.surface.format)) + dst_h_div = 2; + + /* format */ + scaler_data->format = stream_ctx->stream.surface_info.format; + scaler_data->lb_params.alpha_en = stream_ctx->per_pixel_alpha; + + /* recout */ + + scaler_data->recout.x = 0; + scaler_data->recout.y = 0; + scaler_data->recout.height = VPE_MIN_VIEWPORT_SIZE; + scaler_data->recout.width = VPE_MIN_VIEWPORT_SIZE; + + /* ratios */ + scaler_data->ratios.horz = vpe_fixpt_one; + scaler_data->ratios.vert = vpe_fixpt_one; + + if (vpe_is_yuv420(scaler_data->format)) { + scaler_data->ratios.horz_c = vpe_fixpt_from_fraction(1, 2); + scaler_data->ratios.vert_c = vpe_fixpt_from_fraction(1, 2); + } + else if (vpe_is_yuv422(scaler_data->format)) { + scaler_data->ratios.horz_c = vpe_fixpt_from_fraction(1, 2); + scaler_data->ratios.vert_c = vpe_fixpt_one; + } + else { + scaler_data->ratios.horz_c = vpe_fixpt_one; + scaler_data->ratios.vert_c = vpe_fixpt_one; + } + + /* Active region */ + scaler_data->h_active = dst_viewport->width; + scaler_data->v_active = dst_viewport->height; + + /* viewport */ + + scaler_data->viewport.x = vp_x; + scaler_data->viewport.y = vp_y; + scaler_data->viewport.width = VPE_MIN_VIEWPORT_SIZE; + scaler_data->viewport.height = VPE_MIN_VIEWPORT_SIZE; + + scaler_data->viewport_c.x = scaler_data->viewport.x / src_h_div; + scaler_data->viewport_c.y = scaler_data->viewport.y / src_v_div; + scaler_data->viewport_c.width = scaler_data->viewport.width / src_h_div; + scaler_data->viewport_c.height = scaler_data->viewport.height / src_v_div; + + /* destination viewport */ + scaler_data->dst_viewport = *dst_viewport; + + scaler_data->dst_viewport_c.x = scaler_data->dst_viewport.x / dst_h_div; + scaler_data->dst_viewport_c.y = scaler_data->dst_viewport.y / dst_v_div; + scaler_data->dst_viewport_c.width = scaler_data->dst_viewport.width / dst_h_div; + scaler_data->dst_viewport_c.height = scaler_data->dst_viewport.height / dst_v_div; + + /* taps and inits */ + scaler_data->taps.h_taps = scaler_data->taps.v_taps = 1; + + if (scaler_data->ratios.horz_c.value == vpe_fixpt_one.value) + scaler_data->taps.h_taps_c = 1; + else + scaler_data->taps.h_taps_c = 2; + + if (scaler_data->ratios.vert_c.value == vpe_fixpt_one.value) + scaler_data->taps.v_taps_c = 1; + else + scaler_data->taps.v_taps_c = 2; + + scaler_data->inits.h = vpe_fixpt_div_int( + vpe_fixpt_add_int(scaler_data->ratios.horz, (int)(scaler_data->taps.h_taps + 1)), 2); + scaler_data->inits.v = vpe_fixpt_div_int( + vpe_fixpt_add_int(scaler_data->ratios.vert, (int)(scaler_data->taps.v_taps + 1)), 2); + scaler_data->inits.h_c = vpe_fixpt_div_int( + vpe_fixpt_add_int(scaler_data->ratios.horz_c, (int)(scaler_data->taps.h_taps_c + 1)), 2); + scaler_data->inits.v_c = vpe_fixpt_div_int( + vpe_fixpt_add_int(scaler_data->ratios.vert_c, (int)(scaler_data->taps.v_taps_c + 1)), 2); + + /** Translate scaling data to dscl_prog_data.The dscl mode sets in here since the hardcoded + * info did not go through the regular scaler process. + */ + scaler_data->dscl_prog_data.dscl_mode = vpe10_dpp_dscl_get_dscl_mode(scaler_data); + vpe_scl_to_dscl_bg(scaler_data); + + if (vpe_priv->init.debug.opp_background_gen == 1) { + // spl sets bg segments mpc_size to dst_viewport, but bg is generated in OPP so set MPC 0 + scaler_data->dscl_prog_data.mpc_size.width = 0; + scaler_data->dscl_prog_data.mpc_size.height = 0; + } +} + +void vpe20_create_bg_segments( + struct vpe_priv *vpe_priv, struct vpe_rect *gaps, uint16_t gaps_cnt, enum vpe_cmd_ops ops) +{ + uint16_t gap_index; + uint16_t bg_index = vpe_priv->resource.get_bg_stream_idx(vpe_priv); + struct vpe_cmd_info cmd_info = {0}; + struct scaler_data *scaler_data = &(cmd_info.inputs[bg_index].scaler_data); + struct stream_ctx *stream_ctx = &(vpe_priv->stream_ctx[bg_index]); + + for (gap_index = 0; gap_index < gaps_cnt; gap_index++) { + + VPE_ASSERT(gaps_cnt - gap_index - 1 <= (uint16_t)0xF); + + // generate the scaler data for this bg gap + vpe20_fill_bg_cmd_scaler_data(stream_ctx, &gaps[gap_index], scaler_data); + + // background takes stream_idx 0 as its input + cmd_info.inputs[0].stream_idx = 0; + cmd_info.num_outputs = 1; + cmd_info.outputs[0].dst_viewport = scaler_data->dst_viewport; + cmd_info.outputs[0].dst_viewport_c = scaler_data->dst_viewport_c; + + // make sure frod/histogram are disabled for bg segments + cmd_info.frod_param.enable_frod = 0; + memset(&cmd_info.histo_dsets, 0, sizeof(cmd_info.histo_dsets)); + + cmd_info.num_inputs = 1; + cmd_info.ops = ops; + cmd_info.cd = (uint16_t)(gaps_cnt - gap_index - 1); + cmd_info.lut3d_type = LUT3D_TYPE_NONE; // currently only support frontend tm + vpe_vector_push(vpe_priv->vpe_cmd_vector, &cmd_info); + } +} + +uint32_t vpe20_get_num_pipes_available(struct vpe_priv *vpe_priv, struct stream_ctx *stream_ctx) +{ + uint32_t pipe_count = 1; + + if (vpe_priv->init.debug.disable_performance_mode) + return pipe_count; + + if (vpe_priv->output_ctx.frod_param.enable_frod) + return pipe_count; + + if (stream_ctx->stream_type == VPE_STREAM_TYPE_BKGR_ALPHA || + stream_ctx->stream_type == VPE_STREAM_TYPE_BKGR_VIDEO) + return pipe_count; + + if (stream_ctx->stream.blend_info.blending && stream_ctx->stream_idx != 0) + return pipe_count; + /* if 3D LUT is enabled and 3D LUT mpc does not equal to number of pipes */ + if (stream_ctx->stream.tm_params.enable_3dlut || stream_ctx->stream.tm_params.UID != 0) { + pipe_count = vpe_priv->pub.caps->resource_caps.num_mpc_3dlut; + } else { + pipe_count = vpe_priv->pub.caps->resource_caps.num_dpp; + } + + return pipe_count; +} + +void vpe20_set_frod_output_viewport(struct vpe_cmd_output *dst_output, + struct vpe_cmd_output *src_output, uint32_t viewport_divider, + enum vpe_surface_pixel_format format) +{ + if ((viewport_divider > 0) && (dst_output != NULL) && (src_output != NULL)) { + dst_output->dst_viewport.x = + (int32_t)int_divide_with_ceil(src_output->dst_viewport.x, viewport_divider); + dst_output->dst_viewport.y = + (int32_t)int_divide_with_ceil(src_output->dst_viewport.y, viewport_divider); + dst_output->dst_viewport.width = + (int32_t)int_divide_with_ceil(src_output->dst_viewport.width, viewport_divider); + dst_output->dst_viewport.height = + (int32_t)int_divide_with_ceil(src_output->dst_viewport.height, viewport_divider); + dst_output->dst_viewport_c.x = + (int32_t)int_divide_with_ceil(src_output->dst_viewport_c.x, viewport_divider); + dst_output->dst_viewport_c.y = + (int32_t)int_divide_with_ceil(src_output->dst_viewport_c.y, viewport_divider); + dst_output->dst_viewport_c.width = + (int32_t)int_divide_with_ceil(src_output->dst_viewport_c.width, viewport_divider); + dst_output->dst_viewport_c.height = + (int32_t)int_divide_with_ceil(src_output->dst_viewport_c.height, viewport_divider); + if (vpe_is_yuv422(format)) { + if (dst_output->dst_viewport.width & 1) { + dst_output->dst_viewport.width++; + } + } else if (vpe_is_yuv(format) && vpe_is_dual_plane_format(format)) { + if (dst_output->dst_viewport.width & 1) { + dst_output->dst_viewport.width++; + dst_output->dst_viewport_c.width = dst_output->dst_viewport.width / 2; + } + if (dst_output->dst_viewport.height & 1) { + dst_output->dst_viewport.height++; + dst_output->dst_viewport_c.height = dst_output->dst_viewport.height / 2; + } + } + } +} + +/* + * Because we only touch the back end of the output pipes associated with the current command, + * and the number of output pipes can vary between commands, there is a need to reset certain + * registers in the back end that may have been leftover from a previous job. Specfically the + * OPP BG Gen registers need to be reset because this block can generate its own signal. This + * is not the case for the other back end blocks, so we don't need to reset them. + */ +void vpe20_reset_pipes(struct vpe_priv *vpe_priv) +{ + struct mpc *mpc; + struct opp *opp; + struct vpe_rect zero_dim_rect = {0, 0, 0, 0}; + struct vpe_color bg_color = {.is_ycbcr = false, .rgba = {0, 0, 0}}; + + // Reset necessary frontend registers + vpe_priv->fe_cb_ctx.vpe_priv = vpe_priv; + vpe_priv->fe_cb_ctx.stream_sharing = false; + vpe_priv->fe_cb_ctx.stream_op_sharing = false; + config_writer_set_callback( + &vpe_priv->config_writer, &vpe_priv->fe_cb_ctx, vpe_frontend_config_callback); + + for (uint32_t rmcm_idx = 0; rmcm_idx < vpe_priv->pub.caps->resource_caps.num_mpc_3dlut; + rmcm_idx++) { + config_writer_set_type(&vpe_priv->config_writer, CONFIG_TYPE_DIRECT, rmcm_idx); + mpc = vpe_priv->resource.mpc[rmcm_idx]; + mpc->funcs->attach_3dlut_to_mpc_inst(mpc, RMCM_MPCC_DISCONNECTED); + mpc->funcs->shaper_bypass(mpc, true); + mpc->funcs->program_3dlut(mpc, NULL); + } + + config_writer_complete(&vpe_priv->config_writer); + + // Reset necessary backend registers + vpe_priv->be_cb_ctx.vpe_priv = vpe_priv; + vpe_priv->be_cb_ctx.share = false; + config_writer_set_callback( + &vpe_priv->config_writer, &vpe_priv->be_cb_ctx, vpe_backend_config_callback); + + for (uint32_t pipe_idx = 0; pipe_idx < vpe_priv->pub.caps->resource_caps.num_opp; pipe_idx++) { + config_writer_set_type(&vpe_priv->config_writer, CONFIG_TYPE_DIRECT, pipe_idx); + opp = vpe_priv->resource.opp[pipe_idx]; + opp->funcs->set_bg( + opp, zero_dim_rect, zero_dim_rect, VPE_SURFACE_PIXEL_FORMAT_INVALID, bg_color); + + mpc = vpe_priv->resource.mpc[pipe_idx]; + mpc->funcs->program_mpcc_mux(mpc, pipe_idx, MPC_MUX_TOPSEL_DISABLE, MPC_MUX_BOTSEL_DISABLE, + MPC_MUX_OUTMUX_DISABLE, MPC_MUX_OPPID_DISABLE); + } + + config_writer_complete(&vpe_priv->config_writer); +} + +enum vpe_status vpe20_populate_frod_param( + struct vpe_priv *vpe_priv, const struct vpe_build_param *param) +{ + struct output_ctx *output_ctx = &vpe_priv->output_ctx; + enum vpe_status status = VPE_STATUS_OK; + + // FROD can't support negative numbers and FP16 can go negative + if ((status == VPE_STATUS_OK) && vpe_is_fp16(output_ctx->surface.format)) { + status = VPE_STATUS_FROD_NOT_SUPPORTED; + } + + if (status == VPE_STATUS_OK) { + for (uint32_t i = 0; i < VPE_FROD_MAX_STAGE; i++) { + memcpy(&output_ctx->frod_surface[i], ¶m->frod_surface[i], + sizeof(struct vpe_surface_info)); + } + output_ctx->frod_param.enable_frod = param->frod_param.enable_frod; + } + + return status; +} + +const struct vpe_caps *vpe20_get_capability(void) +{ + return ∩︀ +} + +void vpe20_setup_check_funcs(struct vpe_check_support_funcs *funcs) +{ + funcs->check_input_format = vpe20_check_input_format; + funcs->check_output_format = vpe20_check_output_format; + funcs->check_input_color_space = vpe10_check_input_color_space; + funcs->check_output_color_space = vpe20_check_output_color_space; + funcs->get_dcc_compression_input_cap = vpe20_get_dcc_compression_input_cap; + funcs->get_dcc_compression_output_cap = vpe20_get_dcc_compression_output_cap; +} + +enum vpe_status vpe20_check_lut3d_compound( + const struct vpe_stream *stream, const struct vpe_build_param *param) +{ + enum vpe_status status = VPE_STATUS_OK; + + /* 3DLUT compound not enabled is trivially supported */ + if (stream->lut_compound.enabled == false) { + status = VPE_STATUS_OK; + } else { + if (stream->surface_info.cs.primaries != VPE_PRIMARIES_CUSTOM) { + status = VPE_STATUS_LUT_COMPOUND_NOT_SUPPORTED; + } else if (stream->surface_info.cs.tf != VPE_TF_CUSTOM) { + status = VPE_STATUS_LUT_COMPOUND_NOT_SUPPORTED; + } else if (stream->tm_params.lut_out_tf == VPE_TF_G10) { + status = VPE_STATUS_LUT_COMPOUND_NOT_SUPPORTED; + } else if (vpe_is_fp16(stream->dma_info.lut3d.format)) { + status = VPE_STATUS_LUT_COMPOUND_NOT_SUPPORTED; + } else if (param->dst_surface.cs.encoding != VPE_PIXEL_ENCODING_RGB) { + enum color_space cs; + enum color_transfer_func tf; + vpe_color_get_color_space_and_tf(¶m->dst_surface.cs, &cs, &tf); + + // SDR output with blending and YUV not supported + if (!vpe_is_HDR(tf) && (stream->blend_info.blending)) { + status = VPE_STATUS_LUT_COMPOUND_NOT_SUPPORTED; + } + } + } + + return status; +} diff --git a/src/amd/vpelib/src/chip/vpe20/vpe20_vpe_desc_writer.c b/src/amd/vpelib/src/chip/vpe20/vpe20_vpe_desc_writer.c new file mode 100644 index 00000000000..8ec2712f162 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe20/vpe20_vpe_desc_writer.c @@ -0,0 +1,129 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "vpe_assert.h" +#include "common.h" +#include "reg_helper.h" +#include "vpe10_vpe_desc_writer.h" +#include "vpe20_vpe_desc_writer.h" +#include "vpe20_command.h" + +void vpe20_construct_vpe_desc_writer(struct vpe_desc_writer *writer) +{ + writer->init = vpe20_vpe_desc_writer_init; + writer->add_plane_desc = vpe20_vpe_desc_writer_add_plane_desc; + writer->add_config_desc = vpe20_vpe_desc_writer_add_config_desc; + writer->complete = vpe10_vpe_desc_writer_complete; +} + +enum vpe_status vpe20_vpe_desc_writer_init( + struct vpe_desc_writer *writer, struct vpe_buf *buf, int cd) +{ + uint32_t *cmd_space; + uint64_t size = sizeof(uint32_t); + + writer->base_cpu_va = buf->cpu_va; + writer->base_gpu_va = buf->gpu_va; + writer->buf = buf; + writer->num_config_desc = 0; + writer->plane_desc_added = false; + writer->status = VPE_STATUS_OK; + + if (buf->size < size) { + writer->status = VPE_STATUS_BUFFER_OVERFLOW; + return writer->status; + } + + if (writer->status == VPE_STATUS_OK) { + cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va; + *cmd_space++ = VPE_DESC_CMD_HEADER(cd); + + writer->buf->cpu_va += size; + writer->buf->gpu_va += size; + writer->buf->size -= size; + } + + return writer->status; +} + +void vpe20_vpe_desc_writer_add_plane_desc( + struct vpe_desc_writer *writer, uint64_t plane_desc_addr, uint8_t tmz) +{ + uint32_t *cmd_space; + uint64_t size = 3 * sizeof(uint32_t); + + if (writer->status != VPE_STATUS_OK) + return; + + /* Buffer does not have enough space to write */ + if (writer->buf->size < size) { + writer->status = VPE_STATUS_BUFFER_OVERFLOW; + return; + } + + cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va; + + VPE_ASSERT(!(plane_desc_addr & 0x3f)); + VPE_ASSERT(!writer->plane_desc_added); + + *cmd_space++ = (ADDR_LO(plane_desc_addr) | (unsigned)(tmz & 0xf)); + *cmd_space++ = ADDR_HI(plane_desc_addr); + + // skip the DW3 as well, which is finalized during complete + + writer->buf->cpu_va += size; + writer->buf->gpu_va += size; + writer->buf->size -= size; + writer->plane_desc_added = true; +} + +void vpe20_vpe_desc_writer_add_config_desc( + struct vpe_desc_writer* writer, uint64_t config_desc_addr, bool reuse, uint8_t tmz) +{ + uint32_t* cmd_space; + uint64_t size = 2 * sizeof(uint32_t); + + if (writer->status != VPE_STATUS_OK) + return; + + /* Buffer does not have enough space to write */ + if (writer->buf->size < size) { + writer->status = VPE_STATUS_BUFFER_OVERFLOW; + return; + } + + cmd_space = (uint32_t*)(uintptr_t)writer->buf->cpu_va; + + VPE_ASSERT(!(config_desc_addr & 0x3f)); + + *cmd_space++ = (ADDR_LO(config_desc_addr) | ((unsigned)reuse << 5) | (unsigned)(tmz & 0xf)); + *cmd_space++ = ADDR_HI(config_desc_addr); + + writer->buf->cpu_va += size; + writer->buf->gpu_va += size; + writer->buf->size -= size; + writer->num_config_desc++; +} + + diff --git a/src/amd/vpelib/src/core/3dlut_builder.c b/src/amd/vpelib/src/core/3dlut_builder.c index bdca1e90794..02ba08fb2fa 100644 --- a/src/amd/vpelib/src/core/3dlut_builder.c +++ b/src/amd/vpelib/src/core/3dlut_builder.c @@ -36,6 +36,13 @@ static void convert_3dlut_to_tetrahedral_params( int num_values; switch (params->lut_dim) { + case LUT_DIM_33: + lut0 = params->tetrahedral_33.lut0; + lut1 = params->tetrahedral_33.lut1; + lut2 = params->tetrahedral_33.lut2; + lut3 = params->tetrahedral_33.lut3; + num_values = LUT3D_SIZE_33x33x33; + break; case LUT_DIM_9: lut0 = params->tetrahedral_9.lut0; lut1 = params->tetrahedral_9.lut1; @@ -102,6 +109,10 @@ bool vpe_convert_to_tetrahedral( params->lut_3d.lut_dim = LUT_DIM_17; effective_lut_dim = 17; break; + case 33: + params->lut_3d.lut_dim = LUT_DIM_33; + effective_lut_dim = 33; + break; default: params->lut_3d.lut_dim = LUT_DIM_INVALID; VPE_ASSERT(false); diff --git a/src/amd/vpelib/src/core/background.c b/src/amd/vpelib/src/core/background.c index fa45fa3e172..1b679372b39 100644 --- a/src/amd/vpelib/src/core/background.c +++ b/src/amd/vpelib/src/core/background.c @@ -41,6 +41,11 @@ void vpe_create_bg_segments( uint16_t dst_h_div = vpe_is_yuv420(vpe_priv->output_ctx.surface.format) ? 2 : 1; uint16_t dst_v_div = vpe_is_yuv420(vpe_priv->output_ctx.surface.format) ? 2 : 1; + if (vpe_is_yuv422(stream_ctx->stream.surface_info.format)) + src_h_div = 2; + if (vpe_is_yuv422(vpe_priv->output_ctx.surface.format)) + dst_h_div = 2; + for (gap_index = 0; gap_index < gaps_cnt; gap_index++) { /* format */ @@ -62,6 +67,10 @@ void vpe_create_bg_segments( scaler_data->ratios.horz_c = vpe_fixpt_from_fraction(1, 2); scaler_data->ratios.vert_c = vpe_fixpt_from_fraction(1, 2); } + else if (vpe_is_yuv422(scaler_data->format)) { + scaler_data->ratios.horz_c = vpe_fixpt_from_fraction(1, 2); + scaler_data->ratios.vert_c = vpe_fixpt_one; + } else { scaler_data->ratios.horz_c = vpe_fixpt_one; scaler_data->ratios.vert_c = vpe_fixpt_one; diff --git a/src/amd/vpelib/src/core/color.c b/src/amd/vpelib/src/core/color.c index ae537d7b517..529d4187ac8 100644 --- a/src/amd/vpelib/src/core/color.c +++ b/src/amd/vpelib/src/core/color.c @@ -392,6 +392,24 @@ static bool build_scale_and_bias(struct bias_and_scale *bias_and_scale, is_chroma_different = true; } // else report error? not sure if default is right } + else if (vpe_is_rgb16(format)) { + if (vcs->range == VPE_COLOR_RANGE_FULL) { + scale = vpe_fixpt_from_fraction(65536, 65535); + } else if (vcs->range == VPE_COLOR_RANGE_STUDIO) { + scale = vpe_fixpt_from_fraction(65536, 60160 - 4096); + bias = vpe_fixpt_from_fraction(-4096, 65536); + } // else report error? here just go with default (1.0, 0.0) + } else if (vpe_is_yuv12(format)) { + if (vcs->range == VPE_COLOR_RANGE_FULL) { + scale = vpe_fixpt_from_fraction(65536, 65535); + } else if (vcs->range == VPE_COLOR_RANGE_STUDIO) { + scale = vpe_fixpt_from_fraction(65536, 60160 - 4096); + bias = vpe_fixpt_from_fraction(-4096, 65536); + scale_c = vpe_fixpt_from_fraction(65536, 61440 - 4096); + bias_c = vpe_fixpt_from_fraction(-4096, 65536); // See notes in function comment + is_chroma_different = true; + } + } if (!vpe_convert_to_custom_float_format(scale, &fmt, &bias_and_scale->scale_green)) { VPE_ASSERT(0); @@ -597,6 +615,7 @@ enum vpe_status vpe_color_update_3dlut( } } stream_ctx->lut3d_func->state.bits.initialized = 1; + stream_ctx->lut3d_func->state.bits.is_dma = 0; } stream_ctx->uid_3dlut = stream_ctx->stream.tm_params.UID; @@ -604,6 +623,41 @@ enum vpe_status vpe_color_update_3dlut( return VPE_STATUS_OK; } +// This only updates the matrix as provided in the 3DLUT compound case +// 3DLUT itself is updated elsewhere +static enum vpe_status vpe_color_update_3dlut_matrix( + struct vpe_priv *vpe_priv, struct stream_ctx *stream_ctx) +{ + float *matrix_ptr = &stream_ctx->stream.lut_compound.pCscMatrix[0][0]; + float max_coeff = matrix_ptr[0]; + float max_allowed = 4.0f - 1.0f / 4096.0f; // max coeff allowed is 4.0 - smallest step + float renorm_factor = 1.0f; + + struct fixed31_32 renorm_fixed[12]; + + // Find the maximum element in the 3x4 matrix (12 elements total) + for (int i = 0; i < 12; i++) { + if (matrix_ptr[i] > max_coeff) { + max_coeff = matrix_ptr[i]; + } + } + + if (max_coeff > max_allowed) { + renorm_factor = max_coeff / max_allowed; + } + stream_ctx->csc_renorm_factor.value = vpe_double_to_fixed_point(renorm_factor, 0, 32, true); + + for (int i = 0; i < 12; i++) { + // renorm_factor is always >= 1.0f, so division is safe + renorm_fixed[i].value = + vpe_double_to_fixed_point(matrix_ptr[i] / renorm_factor, 0, 32, true); + } + + conv_convert_float_matrix(&stream_ctx->input_cs->regval[0], renorm_fixed, 12); + + return VPE_STATUS_OK; +} + enum vpe_status vpe_color_update_color_space_and_tf( struct vpe_priv *vpe_priv, const struct vpe_build_param *param) { @@ -636,6 +690,12 @@ enum vpe_status vpe_color_update_color_space_and_tf( stream_ctx->stream.tm_params.UID != 0 || stream_ctx->stream.tm_params.enable_3dlut; bool require_update = stream_ctx->uid_3dlut != stream_ctx->stream.tm_params.UID; + if (stream_ctx->stream.lut_compound.enabled) { + // handle 3dlut compound case + vpe_color_update_3dlut_matrix(vpe_priv, stream_ctx); + continue; // skip the rest of color space and tf update + } + color_check_input_cm_update(vpe_priv, stream_ctx, &stream_ctx->stream.surface_info.cs, &stream_ctx->stream.color_adj, is_3dlut_enable, geometric_update); @@ -669,6 +729,8 @@ enum vpe_status vpe_color_update_color_space_and_tf( } if (stream_ctx->dirty_bits.color_space || output_ctx->dirty_bits.color_space) { + if (stream_ctx->stream_type == VPE_STREAM_TYPE_DESTINATION) + stream_ctx->cs = output_ctx->cs; enum color_space shaper_in_cs; bool can_bypass_gamut = geometric_scaling; if (is_3dlut_enable) { @@ -765,6 +827,8 @@ enum vpe_status vpe_color_update_shaper(const struct vpe_priv *vpe_priv, uint16_ shaper_in.shaper_in_max = 1 << 16; shaper_in.use_const_hdr_mult = false; // can not be true. Fix is required. + shaper_in.index_mode = vpe_get_shaper_index_mode(stream_ctx->lut3d_func->state.bits.is_dma, + stream_ctx->lut3d_func->lut_3d.lut_dim, stream_ctx->stream.tm_params.lut_container_dim); ret = vpe_build_shaper(&shaper_in, shaper_func->tf, pq_norm_gain, &shaper_func->pwl); @@ -779,6 +843,95 @@ enum vpe_status vpe_color_update_shaper(const struct vpe_priv *vpe_priv, uint16_ return ret; } +enum vpe_status vpe_color_setup_dma_lut(struct vpe_3dlut *lut3d_func, struct stream_ctx *stream_ctx) +{ + lut3d_func->state.bits.is_dma = 1; + lut3d_func->lut_3d.use_12bits = true; + + switch (stream_ctx->stream.tm_params.lut_type) { + case VPE_LUT_TYPE_GPU_1D_PACKED: + lut3d_func->dma_params.layout = VPE_3DLUT_MEM_LAYOUT_1D_PACKED_LINEAR; + lut3d_func->dma_params.addr_mode = VPE_3DLUT_SIMPLE_LINEAR; + break; + case VPE_LUT_TYPE_GPU_3D_SWIZZLE: + lut3d_func->dma_params.layout = VPE_3DLUT_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB; + lut3d_func->dma_params.addr_mode = VPE_3DLUT_SW_LINEAR; + break; + default: + lut3d_func->dma_params.layout = VPE_3DLUT_MEM_LAYOUT_DISABLE; + } + + switch (stream_ctx->stream.tm_params.lut_dim) { + case 9: + lut3d_func->lut_3d.lut_dim = LUT_DIM_9; + break; + case 17: + lut3d_func->lut_3d.lut_dim = LUT_DIM_17; + break; + case 33: + lut3d_func->lut_3d.lut_dim = LUT_DIM_33; + break; + default: + lut3d_func->lut_3d.lut_dim = LUT_DIM_INVALID; + VPE_ASSERT(false); + return VPE_STATUS_BAD_TONE_MAP_PARAMS; + } + + switch (stream_ctx->stream.dma_info.lut3d.format) { + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB_FLOAT: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: + lut3d_func->dma_params.crossbar_r = VPE_3DLUT_CROSSBAR_BIT_SLICE_32_47; + lut3d_func->dma_params.crossbar_g = VPE_3DLUT_CROSSBAR_BIT_SLICE_16_31; + lut3d_func->dma_params.crossbar_b = VPE_3DLUT_CROSSBAR_BIT_SLICE_0_15; + lut3d_func->dma_params.format = VPE_3DLUT_MEM_FORMAT_16161616_FLOAT_FP1_5_10; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: + lut3d_func->dma_params.crossbar_b = VPE_3DLUT_CROSSBAR_BIT_SLICE_32_47; + lut3d_func->dma_params.crossbar_g = VPE_3DLUT_CROSSBAR_BIT_SLICE_16_31; + lut3d_func->dma_params.crossbar_r = VPE_3DLUT_CROSSBAR_BIT_SLICE_0_15; + lut3d_func->dma_params.format = VPE_3DLUT_MEM_FORMAT_16161616_FLOAT_FP1_5_10; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F: + lut3d_func->dma_params.crossbar_r = VPE_3DLUT_CROSSBAR_BIT_SLICE_48_63; + lut3d_func->dma_params.crossbar_g = VPE_3DLUT_CROSSBAR_BIT_SLICE_32_47; + lut3d_func->dma_params.crossbar_b = VPE_3DLUT_CROSSBAR_BIT_SLICE_16_31; + lut3d_func->dma_params.format = VPE_3DLUT_MEM_FORMAT_16161616_FLOAT_FP1_5_10; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F: + lut3d_func->dma_params.crossbar_b = VPE_3DLUT_CROSSBAR_BIT_SLICE_48_63; + lut3d_func->dma_params.crossbar_g = VPE_3DLUT_CROSSBAR_BIT_SLICE_32_47; + lut3d_func->dma_params.crossbar_r = VPE_3DLUT_CROSSBAR_BIT_SLICE_16_31; + lut3d_func->dma_params.format = VPE_3DLUT_MEM_FORMAT_16161616_FLOAT_FP1_5_10; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + lut3d_func->dma_params.crossbar_r = VPE_3DLUT_CROSSBAR_BIT_SLICE_32_47; + lut3d_func->dma_params.crossbar_g = VPE_3DLUT_CROSSBAR_BIT_SLICE_16_31; + lut3d_func->dma_params.crossbar_b = VPE_3DLUT_CROSSBAR_BIT_SLICE_0_15; + lut3d_func->dma_params.format = VPE_3DLUT_MEM_FORMAT_16161616_UNORM_12MSB; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: + lut3d_func->dma_params.crossbar_b = VPE_3DLUT_CROSSBAR_BIT_SLICE_32_47; + lut3d_func->dma_params.crossbar_g = VPE_3DLUT_CROSSBAR_BIT_SLICE_16_31; + lut3d_func->dma_params.crossbar_r = VPE_3DLUT_CROSSBAR_BIT_SLICE_0_15; + lut3d_func->dma_params.format = VPE_3DLUT_MEM_FORMAT_16161616_UNORM_12MSB; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616: + lut3d_func->dma_params.crossbar_r = VPE_3DLUT_CROSSBAR_BIT_SLICE_48_63; + lut3d_func->dma_params.crossbar_g = VPE_3DLUT_CROSSBAR_BIT_SLICE_32_47; + lut3d_func->dma_params.crossbar_b = VPE_3DLUT_CROSSBAR_BIT_SLICE_16_31; + lut3d_func->dma_params.format = VPE_3DLUT_MEM_FORMAT_16161616_UNORM_12MSB; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616: + default: + lut3d_func->dma_params.crossbar_b = VPE_3DLUT_CROSSBAR_BIT_SLICE_48_63; + lut3d_func->dma_params.crossbar_g = VPE_3DLUT_CROSSBAR_BIT_SLICE_32_47; + lut3d_func->dma_params.crossbar_r = VPE_3DLUT_CROSSBAR_BIT_SLICE_16_31; + lut3d_func->dma_params.format = VPE_3DLUT_MEM_FORMAT_16161616_UNORM_12MSB; + break; + } + return VPE_STATUS_OK; +} + enum vpe_status vpe_calculate_shaper(struct vpe_priv *vpe_priv, struct stream_ctx *stream_ctx) { struct vpe_color_space cs; @@ -856,16 +1009,28 @@ enum vpe_status vpe_color_update_movable_cm( goto exit; } } - // Get the normalization factor for the shaper based on tone mapping parameters. - get_shaper_norm_factor(&stream_ctx->stream.tm_params, stream_ctx, &shaper_norm_factor); + if (stream_ctx->stream.lut_compound.enabled) { + stream_ctx->lut3d_func->hdr_multiplier = stream_ctx->csc_renorm_factor; + } else { + // Get the normalization factor for the shaper based on tone mapping parameters. + get_shaper_norm_factor( + &stream_ctx->stream.tm_params, stream_ctx, &shaper_norm_factor); - // Update the HDR multiplier based on the shaper normalization factor and other - // parameters. - vpe_color_tm_update_hdr_mult(shaper_norm_factor, - &stream_ctx->lut3d_func->hdr_multiplier, enable_3dlut, - stream_ctx->stream.surface_info.cs.tf == VPE_TF_G10); + // Update the HDR multiplier based on the shaper normalization factor and other + // parameters. + vpe_color_tm_update_hdr_mult(shaper_norm_factor, + &stream_ctx->lut3d_func->hdr_multiplier, enable_3dlut, + stream_ctx->stream.surface_info.cs.tf == VPE_TF_G10); + } - vpe_color_update_3dlut(vpe_priv, stream_ctx, enable_3dlut); + // Set up 3DLUT before Shaper to determine indexing mode + if (stream_ctx->stream.tm_params.lut_type > VPE_LUT_TYPE_CPU) { + /* FastLoading */ + vpe_color_setup_dma_lut(stream_ctx->lut3d_func, stream_ctx); + } else { + /* DirectConfig loading case */ + vpe_color_update_3dlut(vpe_priv, stream_ctx, enable_3dlut); + } vpe_priv->resource.calculate_shaper(vpe_priv, stream_ctx); @@ -876,7 +1041,6 @@ enum vpe_status vpe_color_update_movable_cm( vpe_color_update_gamut(vpe_priv, out_lut_cs, vpe_priv->output_ctx.cs, output_ctx->gamut_remap, !enable_3dlut); - vpe_color_update_3dlut(vpe_priv, stream_ctx, enable_3dlut); } } exit: diff --git a/src/amd/vpelib/src/core/color_bg.c b/src/amd/vpelib/src/core/color_bg.c index cac9bb9c597..e7fe96a4a8a 100644 --- a/src/amd/vpelib/src/core/color_bg.c +++ b/src/amd/vpelib/src/core/color_bg.c @@ -524,3 +524,318 @@ void vpe_inverse_output_csc(enum color_space output_cs, struct vpe_color *bg_col vpe_bg_csc(bg_color, bgcolor_cs); } +struct format_range_csc_table { + enum color_space cs; + enum color_range_type range; + bool bg_color_is_yuv; + float val[12]; +}; + +// Used to invert OCSC and convert into pipeline RGB for MPC bg programming +static const struct format_range_csc_table bgcolor_format_range_inversion[] = { + + // RGB BG Color, RGB output + {COLOR_SPACE_SRGB_LIMITED, COLOR_RANGE_LIMITED_8BPC, false, + {1.16438356164384f, 0, 0, -0.0730593607305936f, 0, 1.16438356164384f, 0, + -0.0730593607305936f, 0, 0, 1.16438356164384f, -0.0730593607305936f}}, + {COLOR_SPACE_SRGB_LIMITED, COLOR_RANGE_LIMITED_10BPC, false, + {1.167808219178082f, 0, 0, -0.073059360730594f, 0, 1.167808219178082f, 0, + -0.073059360730594f, 0, 0, 1.167808219178082f, -0.073059360730594f}}, + {COLOR_SPACE_SRGB_LIMITED, COLOR_RANGE_LIMITED_16BPC, false, + {1.168931934931507f, 0, 0, -0.073059360730594f, 0, 1.168931934931507f, 0, + -0.073059360730594f, 0, 0, 1.168931934931507f, -0.073059360730594f}}, + + // RGB BG Color, YUV output + {COLOR_SPACE_YCBCR601_LIMITED, COLOR_RANGE_LIMITED_8BPC, false, + {1.14616407778763f, 0.0152565435443742f, 0.00296294031182745f, -0.0761888250163078f, + 0.00777122064477659f, 1.15364940068723f, 0.00296294031182746f, -0.0706971451680937f, + 0.00777122064477664f, 0.0152565435443742f, 1.14135579745468f, -0.0770147178734506f}}, + {COLOR_SPACE_YCBCR601_LIMITED, COLOR_RANGE_LIMITED_10BPC, false, + {1.14953514860466f, 0.0153014157312695f, 0.00297165484215636f, -0.0738417268020222f, + 0.00779407717608477f, 1.15704248715984f, 0.00297165484215636f, -0.0724688068399686f, + 0.00779407717608482f, 0.0153014157312695f, 1.14471272627073f, -0.0740482000163079f}}, + {COLOR_SPACE_YCBCR601_LIMITED, COLOR_RANGE_LIMITED_16BPC, false, + {1.16893193493151f, 0.0f, 0.0f, -0.0570672980878996f, 0.0f, 1.16893193493151f, 0.0f, + -0.0851306597780037f, 0.0f, 0.0f, 1.16893193493151f, -0.0528468535958906f}}, + + {COLOR_SPACE_YCBCR709_LIMITED, COLOR_RANGE_LIMITED_8BPC, false, + {1.14391848092026f, 0.0185885518580174f, 0.00187652886555610f, -0.0765745393020221f, + 0.00552562377740495f, 1.15698140900087f, 0.00187652886555609f, -0.0715963059404152f, + 0.00552562377740481f, 0.0185885518580174f, 1.14026938600841f, -0.0772013250163077f}}, + {COLOR_SPACE_YCBCR709_LIMITED, COLOR_RANGE_LIMITED_10BPC, false, + {1.14728294704062f, 0.0186432240693645f, 0.00188204806810185f, -0.0739381553734507f, + 0.00554187561204439f, 1.16038429549794f, 0.00188204806810185f, -0.0726935970330490f, + 0.00554187561204425f, 0.0186432240693646f, 1.14362311949667f, -0.0740948518020221f}}, + {COLOR_SPACE_YCBCR709_LIMITED, COLOR_RANGE_LIMITED_16BPC, false, + {1.16893193493151f, 0.0f, 0.0f, -0.0550962364440639f, 0.0f, 1.16893193493151f, 0.0f, + -0.0805358045299480f, 0.0f, 0.0f, 1.16893193493151f, -0.0518932612728311f}}, + + {COLOR_SPACE_2020_YCBCR_LIMITED, COLOR_RANGE_LIMITED_8BPC, false, + {1.14522061521626f, 0.0176216976494039f, 0.00154124877817476f, -0.0763508785877364f, + 0.00682775807339991f, 1.15601455479226f, 0.00154124877817475f, -0.0714167128422008f, + 0.00682775807339991f, 0.0176216976494038f, 1.13993410592103f, -0.0772589143020221f}}, + {COLOR_SPACE_2020_YCBCR_LIMITED, COLOR_RANGE_LIMITED_10BPC, false, + {1.14858891114336f, 0.0176735261719021f, 0.00154578186281643f, -0.0738822401948792f, + 0.00684783971479236f, 1.15941459760047f, 0.00154578186281642f, -0.0726486987584954f, + 0.00684783971479225f, 0.0176735261719021f, 1.14328685329139f, -0.0741092491234507f}}, + {COLOR_SPACE_2020_YCBCR_LIMITED, COLOR_RANGE_LIMITED_16BPC, false, + {1.16893193493151f, 0.0f, 0.0f, -0.0562391784389270f, 0.0f, 1.16893193493151f, 0.0f, + -0.0814535539639162f, 0.0f, 0.0f, 1.16893193493151f, -0.0515989708190638f}}, + + // YUV BG Color, YUV output + {COLOR_SPACE_YCBCR601, COLOR_RANGE_FULL, true, + {1.0f, 0, 1.4020f, -0.7010f, 1.0f, -0.3441362860f, -0.7141362860f, 0.5291362860f, 1.0f, + 1.7720f, 0, -0.8860f}}, + {COLOR_SPACE_YCBCR601_LIMITED, COLOR_RANGE_LIMITED_8BPC, true, + {1.16438356164384f, 0, 1.59602678571429f, -0.874202217873451f, 1.16438356164384f, + -0.391762289866072f, -0.812967647008929f, 0.531667823269406f, 1.16438356164384f, + 2.01723214285714f, 0, -1.08563078930202f}}, + {COLOR_SPACE_YCBCR601_LIMITED, COLOR_RANGE_LIMITED_10BPC, true, + {1.16780821917808f, 0, 1.60072098214286f, -0.874202217873451f, 1.16780821917808f, + -0.392914531895089f, -0.815358728323661f, 0.531667823269406f, 1.16780821917808f, + 2.02316517857143f, 0, -1.08563078930202f}}, + {COLOR_SPACE_YCBCR601_LIMITED, COLOR_RANGE_LIMITED_16BPC, true, + {1.16893193493151f, 0, 1.63884257277397f, -0.876488584474886f, 1.16893193493151f, + -0.402271894674122f, -0.834776710598780f, 0.533393642858448f, 1.16893193493151f, + 2.07134738869863f, 0, -1.08852054794521f}}, + + {COLOR_SPACE_YCBCR709, COLOR_RANGE_FULL, true, + {1.0f, 0, 1.57480f, -0.78740f, 1.0f, -0.1873242730f, -0.4681242730f, 0.3277242730f, 1.0f, + 1.85560f, 0, -0.92780f}}, + {COLOR_SPACE_YCBCR709_LIMITED, COLOR_RANGE_LIMITED_8BPC, true, + {1.16438356164384f, 0, 1.79274107142857f, -0.972945075016308f, 1.16438356164384f, + -0.213248614352679f, -0.532909328638393f, 0.301482665555121f, 1.16438356164384f, + 2.11240178571429f, 0, -1.13340221787345f}}, + {COLOR_SPACE_YCBCR709_LIMITED, COLOR_RANGE_LIMITED_10BPC, true, + {1.16780821917808f, 0, 1.79801383928571f, -0.972945075016308f, 1.16780821917808f, + -0.213875816159598f, -0.534476709016741f, 0.301482665555121f, 1.16780821917808f, + 2.11861473214286f, 0, -1.13340221787345f}}, + {COLOR_SPACE_YCBCR709_LIMITED, COLOR_RANGE_LIMITED_16BPC, true, + {1.16893193493151f, 0, 1.84083401113014f, -0.975513242009132f, 1.16893193493151f, + -0.218969324897528f, -0.547205412226295f, 0.302551564031963f, 1.16893193493151f, + 2.16907009845890f, 0, -1.13642831050228f}}, + + {COLOR_SPACE_2020_YCBCR, COLOR_RANGE_FULL, true, + {1.0f, 0, 1.47460f, -0.73730f, 1.0f, -0.1645531270f, -0.5713531270f, 0.3679531270f, 1.0f, + 1.88140f, 0, -0.94070f}}, + {COLOR_SPACE_2020_YCBCR_LIMITED, COLOR_RANGE_LIMITED_8BPC, true, + {1.16438356164384f, 0, 1.67867410714286f, -0.915687932159165f, 1.16438356164384f, + -0.187326104397321f, -0.650424318683036f, 0.347458498697978f, 1.16438356164384f, + 2.14177232142857f, 0, -1.14814507501631f}}, + {COLOR_SPACE_2020_YCBCR_LIMITED, COLOR_RANGE_LIMITED_10BPC, true, + {1.16780821917808f, 0, 1.68361138392857f, -0.915687932159165f, 1.16780821917808f, + -0.187877063527902f, -0.652337331385045f, 0.347458498697978f, 1.16780821917808f, + 2.14807165178571f, 0, -1.14814507501631f}}, + {COLOR_SPACE_2020_YCBCR_LIMITED, COLOR_RANGE_LIMITED_16BPC, true, + {1.16893193493151f, 0, 1.723707031250f, -0.918092694063927f, 1.16893193493151f, + -0.192351405143140f, -0.667872916273277f, 0.348658606744292f, 1.16893193493151f, + 2.19922854238014f, 0, -1.15121324200913f}}, + + + // YUV BG Colorf, RGB output + {COLOR_SPACE_RGB601, COLOR_RANGE_FULL, true, + {1.0f, 0, 1.4020f, -0.7010f, 1.0f, -0.3441362860f, -0.7141362860f, 0.5291362860f, 1.0f, + 1.7720f, 0, -0.8860f}}, + {COLOR_SPACE_RGB601_LIMITED, COLOR_RANGE_LIMITED_8BPC, true, + {1.16438356164384f, 0, 1.63246575342466f, -0.889292237442922f, 1.16438356164384f, + -0.400706634383562f, -0.831528552191781f, 0.543058232557078f, 1.16438356164384f, + 2.06328767123288f, 0, -1.10470319634703f}}, + {COLOR_SPACE_RGB601_LIMITED, COLOR_RANGE_LIMITED_10BPC, true, + {1.16780821917808f, 0, 1.63726712328767f, -0.891692922374429f, 1.16780821917808f, + -0.401885183308219f, -0.833974224404110f, 0.544870343125571f, 1.16780821917808f, + 2.06935616438356f, 0, -1.10773744292237f}}, + {COLOR_SPACE_RGB601_LIMITED, COLOR_RANGE_LIMITED_16BPC, true, + {1.16893193493151f, 0, 1.63884257277397f, -0.892480647117580f, 1.16893193493151f, + -0.402271894674122f, -0.834776710598780f, 0.545464941905858f, 1.16893193493151f, + 2.07134738869863f, 0, -1.10873305507991f}}, + + {COLOR_SPACE_SRGB, COLOR_RANGE_FULL, true, + {1.0f, 0, 1.57480f, -0.78740f, 1.0f, -0.1873242730f, -0.4681242730f, 0.3277242730f, 1.0f, + 1.85560f, 0, -0.92780f}}, + {COLOR_SPACE_SRGB_LIMITED, COLOR_RANGE_LIMITED_8BPC, true, + {1.16438356164384f, 0, 1.83367123287671f, -0.989894977168950f, 1.16438356164384f, + -0.218117304178082f, -0.545076208287671f, 0.308537395502283f, 1.16438356164384f, + 2.16063013698630f, 0, -1.15337442922374f}}, + {COLOR_SPACE_SRGB_LIMITED, COLOR_RANGE_LIMITED_10BPC, true, + {1.16780821917808f, 0, 1.83906438356164f, -0.992591552511415f, 1.16780821917808f, + -0.218758825660959f, -0.546679373606164f, 0.309659738902968f, 1.16780821917808f, + 2.16698493150685f, 0, -1.15655182648402f}}, + {COLOR_SPACE_SRGB_LIMITED, COLOR_RANGE_LIMITED_16BPC, true, + {1.16893193493151f, 0, 1.84083401113014f, -0.993476366295662f, 1.16893193493151f, + -0.218969324897528f, -0.547205412226295f, 0.310028007831318f, 1.16893193493151f, + 2.16907009845890f, 0, -1.15759440996005f}}, + + {COLOR_SPACE_2020_RGB_FULLRANGE, COLOR_RANGE_FULL, true, + {1.0f, 0, 1.47460f, -0.73730f, 1.0f, -0.1645531270f, -0.5713531270f, 0.3679531270f, 1.0f, + 1.88140f, 0, -0.94070f}}, + {COLOR_SPACE_2020_RGB_LIMITEDRANGE, COLOR_RANGE_LIMITED_8BPC, true, + {1.16438356164384f, 0, 1.7170f, -0.931559360730594f, 1.16438356164384f, -0.191602956095890f, + -0.665274188972603f, 0.355379211803653f, 1.16438356164384f, 2.19067123287671f, 0, + -1.16839497716895f}}, + {COLOR_SPACE_2020_RGB_LIMITEDRANGE, COLOR_RANGE_LIMITED_10BPC, true, + {1.16780821917808f, 0, 1.722050f, -0.934084360730593f, 1.16780821917808f, + -0.192166494202055f, -0.667230877763699f, 0.356639325252283f, 1.16780821917808f, + 2.19711438356164f, 0, -1.17161655251142f}}, + {COLOR_SPACE_2020_RGB_LIMITEDRANGE, COLOR_RANGE_LIMITED_16BPC, true, + {1.16893193493151f, 0, 1.723707031250f, -0.934912876355594f, 1.16893193493151f, + -0.192351405143140f, -0.667872916273277f, 0.357052799977615f, 1.16893193493151f, + 2.19922854238014f, 0, -1.17267363192066f}}}; + +// Used to convert bg into output cs for OPP programming (so always in full range) +static const struct format_range_csc_table bgcolor_color_space_table[] = { + + // RGB BG Color, YUV output + {COLOR_SPACE_YCBCR601, COLOR_RANGE_FULL, false, + {0.500000000027881f, -0.418687589221465f, -0.0813124108064158f, 0.5f, 0.298999999960911f, + 0.587000000088494f, 0.113999999950595f, 0.0f, -0.168735891625796f, -0.331264108402085f, + 0.500000000027881f, 0.5f}}, + {COLOR_SPACE_YCBCR709, COLOR_RANGE_FULL, false, + {0.499999999987861f, -0.454152908279373f, -0.0458470917084874f, 0.5f, 0.212600000019117f, + 0.715199999958357f, 0.0722000000225260f, 0.0f, -0.114572106067642f, -0.385427893920218f, + 0.499999999987861f, 0.5f}}, + {COLOR_SPACE_2020_YCBCR, COLOR_RANGE_FULL, false, + {0.499999999974095f, -0.459785704538901f, -0.0402142954351941f, 0.5f, 0.262700000038199f, + 0.677999999913064f, 0.0593000000487373f, 0.0f, -0.139630062739555f, -0.360369937234540f, + 0.499999999974095f, 0.5f}}, + + // YUV BG Color, RGB output + {COLOR_SPACE_RGB601, COLOR_RANGE_FULL, true, + {1.0f, 0.0f, 1.40200000000000f, -0.701000000000000f, 1.0f, -0.344136286000000f, + -0.714136286000000f, 0.529136286000000f, 1.0f, 1.77200000000000f, 0.0f, + -0.886000000000000f}}, + {COLOR_SPACE_SRGB, COLOR_RANGE_FULL, true, + {1.0f, 0.0f, 1.57480000000000f, -0.787400000000000f, 1.0f, -0.187324273000000f, + -0.468124273000000f, 0.327724273000000f, 1.0f, 1.85560000000000f, 0.0f, + -0.927800000000000f}}, + {COLOR_SPACE_2020_RGB_FULLRANGE, COLOR_RANGE_FULL, true, + {1.0f, 0.0f, 1.47460000000000f, -0.737300000000000f, 1.0f, -0.164553127000000f, + -0.571353127000000f, 0.367953127000000f, 1.0f, 1.88140000000000f, 0.0f, + -0.940700000000000f}}}; + +bool vpe_is_yuv_cs(enum color_space cs) +{ + switch (cs) { + // output is ycbr cs, follow output's setting + case COLOR_SPACE_YCBCR601: + case COLOR_SPACE_YCBCR709: + case COLOR_SPACE_YCBCR601_LIMITED: + case COLOR_SPACE_YCBCR709_LIMITED: + case COLOR_SPACE_2020_YCBCR: + case COLOR_SPACE_2020_YCBCR_LIMITED: + return true; + default: + return false; + } +} + +void vpe_bg_format_and_limited_conversion(enum color_space output_cs, + enum vpe_surface_pixel_format pixel_format, struct vpe_color *bg_color) +{ + // for limited YUV output, OCSC does studio conversion. Need to calculate RGB value that will + // convert to full range YUV out, after OCSC full-> studio conversion + enum color_range_type range = vpe_get_range_type(output_cs, pixel_format); + enum color_space cs = output_cs; + + if (!vpe_is_yuv_cs(output_cs) && !bg_color->is_ycbcr) + // if RGB BG->RGB out we do not care about which chromaticity to use as in-pipe RGB is + // typeless + cs = COLOR_SPACE_SRGB_LIMITED; + else + // map certain color spaces to their matching one in the matrix array + switch (cs) { + case COLOR_SPACE_MSREF_SCRGB: + cs = COLOR_SPACE_SRGB; + break; + case COLOR_SPACE_YCBCR_JFIF: + cs = COLOR_SPACE_YCBCR601; + break; + case COLOR_SPACE_RGB_JFIF: + cs = COLOR_SPACE_RGB601; + break; + default: + break; + } + + int i; + int arr_size = 12; + for (i = 0; i < arr_size; i++) + if (bgcolor_format_range_inversion[i].cs == cs && + bgcolor_format_range_inversion[i].range == range && + bgcolor_format_range_inversion[i].bg_color_is_yuv == bg_color->is_ycbcr) { + const float *m = bgcolor_format_range_inversion[i].val; + + if (bg_color->is_ycbcr) { + struct vpe_color_ycbcra ycbcra = bg_color->ycbcra; + bg_color->rgba.r = ycbcra.y * m[0] + ycbcra.cb * m[1] + ycbcra.cr * m[2] + m[3]; + bg_color->rgba.g = ycbcra.y * m[4] + ycbcra.cb * m[5] + ycbcra.cr * m[6] + m[7]; + bg_color->rgba.b = ycbcra.y * m[8] + ycbcra.cb * m[9] + ycbcra.cr * m[10] + m[11]; + } else { + struct vpe_color_rgba rgba = bg_color->rgba; + bg_color->rgba.r = rgba.r * m[0] + rgba.g * m[1] + rgba.b * m[2] + m[3]; + bg_color->rgba.g = rgba.r * m[4] + rgba.g * m[5] + rgba.b * m[6] + m[7]; + bg_color->rgba.b = rgba.r * m[8] + rgba.g * m[9] + rgba.b * m[10] + m[11]; + } + break; + } +} + +void vpe_bg_color_space_conversion(enum color_space output_cs, struct vpe_color *bg_color) +{ + enum color_space cs = output_cs; + + // map certain color spaces to their matching one in the matrix array + switch (cs) { + case COLOR_SPACE_RGB601: + case COLOR_SPACE_RGB601_LIMITED: + case COLOR_SPACE_RGB_JFIF: + cs = COLOR_SPACE_RGB601; + break; + case COLOR_SPACE_SRGB: + case COLOR_SPACE_SRGB_LIMITED: + case COLOR_SPACE_MSREF_SCRGB: + cs = COLOR_SPACE_SRGB; + break; + case COLOR_SPACE_2020_RGB_FULLRANGE: + case COLOR_SPACE_2020_RGB_LIMITEDRANGE: + cs = COLOR_SPACE_2020_RGB_FULLRANGE; + break; + case COLOR_SPACE_YCBCR601_LIMITED: + case COLOR_SPACE_YCBCR_JFIF: + case COLOR_SPACE_YCBCR601: + cs = COLOR_SPACE_YCBCR601; + break; + case COLOR_SPACE_YCBCR709_LIMITED: + case COLOR_SPACE_YCBCR709: + cs = COLOR_SPACE_YCBCR709; + break; + case COLOR_SPACE_2020_YCBCR: + case COLOR_SPACE_2020_YCBCR_LIMITED: + cs = COLOR_SPACE_2020_YCBCR; + break; + default: + break; + } + + int i; + int arr_size = 6; + for (i = 0; i < arr_size; i++) + if (bgcolor_color_space_table[i].cs == cs && + bgcolor_color_space_table[i].bg_color_is_yuv == bg_color->is_ycbcr) { + const float *m = bgcolor_color_space_table[i].val; + + if (vpe_is_yuv_cs(cs)) { + struct vpe_color_rgba rgba = bg_color->rgba; + bg_color->ycbcra.cr = rgba.r * m[0] + rgba.g * m[1] + rgba.b * m[2] + m[3]; + bg_color->ycbcra.y = rgba.r * m[4] + rgba.g * m[5] + rgba.b * m[6] + m[7]; + bg_color->ycbcra.cb = rgba.r * m[8] + rgba.g * m[9] + rgba.b * m[10] + m[11]; + bg_color->is_ycbcr = true; + } else { + struct vpe_color_ycbcra ycbcra = bg_color->ycbcra; + bg_color->rgba.r = ycbcra.y * m[0] + ycbcra.cb * m[1] + ycbcra.cr * m[2] + m[3]; + bg_color->rgba.g = ycbcra.y * m[4] + ycbcra.cb * m[5] + ycbcra.cr * m[6] + m[7]; + bg_color->rgba.b = ycbcra.y * m[8] + ycbcra.cb * m[9] + ycbcra.cr * m[10] + m[11]; + bg_color->is_ycbcr = false; + } + break; + } +} diff --git a/src/amd/vpelib/src/core/common.c b/src/amd/vpelib/src/core/common.c index 5e07f7a7df8..975470f95be 100644 --- a/src/amd/vpelib/src/core/common.c +++ b/src/amd/vpelib/src/core/common.c @@ -53,6 +53,14 @@ bool vpe_is_dual_plane_format(enum vpe_surface_pixel_format format) // p010 case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCrCb: /* P016 */ + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrCb: /* YUV 422 */ + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbCr: return true; default: return false; @@ -83,15 +91,23 @@ bool vpe_is_32bit_packed_rgb(enum vpe_surface_pixel_format format) bool vpe_is_8bit(enum vpe_surface_pixel_format format) { return vpe_is_rgb8(format) || vpe_is_yuv420_8(format) || + vpe_is_yuv422_8(format) || + (format == VPE_SURFACE_PIXEL_FORMAT_GRPH_R8) || vpe_is_yuv444_8(format); } bool vpe_is_10bit(enum vpe_surface_pixel_format format) { return vpe_is_rgb10(format) || vpe_is_yuv420_10(format) || + vpe_is_yuv422_10(format) || vpe_is_yuv444_10(format); } +bool vpe_is_16bit(enum vpe_surface_pixel_format format) +{ + return vpe_is_fp16(format) || vpe_is_rgb16(format) || + (format == VPE_SURFACE_PIXEL_FORMAT_GRPH_R16); +} bool vpe_is_rgb8(enum vpe_surface_pixel_format format) { switch (format) { @@ -103,6 +119,7 @@ bool vpe_is_rgb8(enum vpe_surface_pixel_format format) case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888: case VPE_SURFACE_PIXEL_FORMAT_GRPH_XRGB8888: case VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_RGB: return true; default: return false; @@ -121,6 +138,28 @@ bool vpe_is_rgb10(enum vpe_surface_pixel_format format) return false; } } +bool vpe_is_rgb16(enum vpe_surface_pixel_format format) +{ + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_UNORM: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616_UNORM: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_SNORM: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616_SNORM: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB: + return true; + default: + return false; + } +} + +bool vpe_is_planar_format(enum vpe_surface_pixel_format format) +{ + return (format >= VPE_SURFACE_PIXEL_FORMAT_PLANAR_BEGIN) && + (format <= VPE_SURFACE_PIXEL_FORMAT_PLANAR_END); +} bool vpe_is_fp16(enum vpe_surface_pixel_format format) { @@ -129,6 +168,7 @@ bool vpe_is_fp16(enum vpe_surface_pixel_format format) case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F: case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB_FLOAT: return true; default: return false; @@ -140,6 +180,7 @@ bool vpe_is_yuv420_8(enum vpe_surface_pixel_format format) switch (format) { case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ALPHA_THRU_LUMA: return true; default: return false; @@ -175,11 +216,13 @@ bool vpe_is_yuv420(enum vpe_surface_pixel_format format) bool vpe_is_yuv444_8(enum vpe_surface_pixel_format format) { switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrCbYA8888: case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: case VPE_SURFACE_PIXEL_FORMAT_VIDEO_YCrCbA8888: case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb8888: case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA8888: case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_YCbCr: return true; default: return false; @@ -196,36 +239,157 @@ bool vpe_is_yuv444_10(enum vpe_surface_pixel_format format) return false; } } +bool vpe_is_yuv444_12(enum vpe_surface_pixel_format format) +{ + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb12121212: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA12121212: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_YCbCr: + return true; + default: + return false; + } +} bool vpe_is_yuv444(enum vpe_surface_pixel_format format) { return (vpe_is_yuv444_8(format) || + vpe_is_yuv444_12(format) || vpe_is_yuv444_10(format)); } +bool vpe_is_yuv422_8(enum vpe_surface_pixel_format format) +{ + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CbYCrY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbCr: + return true; + default: + return false; + } +} + +bool vpe_is_yuv422_10(enum vpe_surface_pixel_format format) +{ + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CbYCrY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbCr: + return true; + default: + return false; + } +} + +bool vpe_is_yuv422_12(enum vpe_surface_pixel_format format) +{ + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CbYCrY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbCr: + return true; + default: + return false; + } +} + +bool vpe_is_yuv422(enum vpe_surface_pixel_format format) +{ + return (vpe_is_yuv422_8(format) || vpe_is_yuv422_10(format) || vpe_is_yuv422_12(format)); +} +bool vpe_is_yuv_packed(enum vpe_surface_pixel_format format) +{ + switch (format) { + // YUV 422 Packed + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CbYCrY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CbYCrY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CbYCrY: + // YUV 444 Packed + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrCbYA8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_YCrCbA8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb12121212: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA12121212: + return true; + default: + return false; + } +} + +bool vpe_is_mono(enum vpe_surface_pixel_format format) +{ + switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_GRPH_R8: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_R16: + return true; + default: + return false; + } +} + bool vpe_is_yuv8(enum vpe_surface_pixel_format format) { return (vpe_is_yuv420_8(format) || + vpe_is_yuv422_8(format) || vpe_is_yuv444_8(format)); } bool vpe_is_yuv10(enum vpe_surface_pixel_format format) { return (vpe_is_yuv420_10(format) || + vpe_is_yuv422_10(format) || vpe_is_yuv444_10(format)); } +bool vpe_is_yuv12(enum vpe_surface_pixel_format format) +{ + return (vpe_is_yuv420_16(format) + || vpe_is_yuv422_12(format) || vpe_is_yuv444_12(format) + ); +} bool vpe_is_yuv(enum vpe_surface_pixel_format format) { return (vpe_is_yuv420(format) || + vpe_is_yuv8(format) || vpe_is_yuv422(format) || vpe_is_yuv444(format)); } uint8_t vpe_get_element_size_in_bytes(enum vpe_surface_pixel_format format, int plane_idx) { switch (format) { + case VPE_SURFACE_PIXEL_FORMAT_GRPH_R8: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_RGB: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_YCbCr: + return 1; // nv12/21 case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ALPHA_THRU_LUMA: if (plane_idx == 0) return 1; else @@ -233,16 +397,56 @@ uint8_t vpe_get_element_size_in_bytes(enum vpe_surface_pixel_format format, int // P010 case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + // P016 + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCrCb: + // P210 + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbCr: + // P216 + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbCr: if (plane_idx == 0) return 2; else return 4; + // YUY2/UYUV + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CbYCrY: + return 4; + // 16b Monochrome + case VPE_SURFACE_PIXEL_FORMAT_GRPH_R16: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB_FLOAT: + return 2; + // Y210/Y216 + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CbYCrY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CbYCrY: + return 8; + break; // 64bpp case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F: case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_UNORM: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616_UNORM: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_SNORM: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616_SNORM: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb12121212: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA12121212: return 8; default: break; @@ -268,6 +472,17 @@ enum color_depth vpe_get_color_depth(enum vpe_surface_pixel_format format) case VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888: case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CbYCrY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_RGB: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_R8: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ALPHA_THRU_LUMA: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrCbYA8888: case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: case VPE_SURFACE_PIXEL_FORMAT_VIDEO_YCrCbA8888: case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb8888: @@ -281,15 +496,46 @@ enum color_depth vpe_get_color_depth(enum vpe_surface_pixel_format format) case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102: case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CbYCrY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbCr: case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102: c_depth = COLOR_DEPTH_101010; break; + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CbYCrY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb12121212: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA12121212: + c_depth = COLOR_DEPTH_121212; + break; case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F: case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_UNORM: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616_UNORM: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_SNORM: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616_SNORM: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB_FLOAT: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_R16: + // RGBE is technically 9bpc per component + 5 shared, using 16 here instead of default 8 + // c_depth only used in OPP/backend for clamping etc, rgbe is input only so no impact + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE: c_depth = COLOR_DEPTH_161616; break; default: @@ -325,6 +571,11 @@ bool vpe_has_per_pixel_alpha(enum vpe_surface_pixel_format format) case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb8888: case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA8888: case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrCbYA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ALPHA_THRU_LUMA: alpha = true; break; case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB565: @@ -337,6 +588,31 @@ bool vpe_has_per_pixel_alpha(enum vpe_surface_pixel_format format) case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CbYCrY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CbYCrY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CbYCrY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_RGB: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB_FLOAT: case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888: case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888: case VPE_SURFACE_PIXEL_FORMAT_GRPH_XRGB8888: @@ -516,6 +792,23 @@ enum vpe_status vpe_check_input_support(struct vpe *vpe, const struct vpe_stream return VPE_STATUS_PLANE_ADDR_NOT_SUPPORTED; } } + } else if (surface_info->address.type == VPE_PLN_ADDR_TYPE_PLANAR) { + uint32_t addr_check = 0; + uint32_t caps_alignment = vpe->caps->plane_caps.addr_alignment; + + addrloc = &surface_info->address.planar.y_g_addr; + addr_check |= (addrloc->u.low_part % caps_alignment); + + addrloc = &surface_info->address.planar.cb_b_addr; + addr_check |= (addrloc->u.low_part % caps_alignment); + + addrloc = &surface_info->address.planar.cr_r_addr; + addr_check |= (addrloc->u.low_part % caps_alignment); + + if (addr_check) { + vpe_log("failed. addr not aligned to 256 bytes\n"); + return VPE_STATUS_PLANE_ADDR_NOT_SUPPORTED; + } } else { addrloc = &surface_info->address.grph.addr; if (addrloc->u.low_part % vpe->caps->plane_caps.addr_alignment) { @@ -532,6 +825,8 @@ enum vpe_status vpe_check_input_support(struct vpe *vpe, const struct vpe_stream params.format = surface_info->format; params.swizzle_mode = surface_info->swizzle; + params.scan = vpe_get_scan_direction( + stream->rotation, stream->horizontal_mirror, stream->vertical_mirror); support = vpe_priv->pub.check_funcs.get_dcc_compression_input_cap(¶ms, &cap); //only support non dual plane formats if (!support) { @@ -626,9 +921,58 @@ enum vpe_status vpe_check_tone_map_support( } } - if (is_3D_lut_enabled && stream->tm_params.lut_dim != LUT_DIM_9 && - stream->tm_params.lut_dim != LUT_DIM_17) { /* only support 9/17 cube */ - status = VPE_STATUS_BAD_TONE_MAP_PARAMS; + if (is_3D_lut_enabled) { + /* check for 3D LUT dimension support */ + switch (stream->tm_params.lut_dim) { + case LUT_DIM_9: + if (!vpe->caps->color_caps.mpc.lut_caps.lut_3dlut_caps.data_dim_9) + status = VPE_STATUS_BAD_TONE_MAP_PARAMS; + break; + case LUT_DIM_17: + if (!vpe->caps->color_caps.mpc.lut_caps.lut_3dlut_caps.data_dim_17) + status = VPE_STATUS_BAD_TONE_MAP_PARAMS; + break; + case LUT_DIM_33: + if (!vpe->caps->color_caps.mpc.lut_caps.lut_3dlut_caps.data_dim_33) + status = VPE_STATUS_BAD_TONE_MAP_PARAMS; + break; + default: + status = VPE_STATUS_BAD_TONE_MAP_PARAMS; + } + + if (stream->tm_params.lut_type > VPE_LUT_TYPE_CPU) { /* fast loading */ + if (!vpe->caps->color_caps.mpc.dma_3d_lut || /* check capability support */ + ((stream->dma_info.lut3d.data & 0xFF) != 0)) { /* must be 256 byte aligned */ + status = VPE_STATUS_BAD_TONE_MAP_PARAMS; + } else if (!(vpe_is_rgb16(stream->dma_info.lut3d.format) || + vpe_is_fp16(stream->dma_info.lut3d + .format))) { /* check for 3D LUT format support */ + status = VPE_STATUS_BAD_TONE_MAP_PARAMS; + } else { + // Check if the 3D LUT container dimension is supported for fast loading + + switch (stream->tm_params.lut_container_dim) { + case LUT_DIM_INVALID: + // unitialized lut_container_dim will be treated as 33 dimension + if (!vpe->caps->color_caps.mpc.lut_caps.lut_3dlut_caps.dma_dim_33) + status = VPE_STATUS_BAD_TONE_MAP_PARAMS; + break; + case LUT_DIM_17: + // Verify if 17x17x17 LUT dimension is supported for fast loading + if (!vpe->caps->color_caps.mpc.lut_caps.lut_3dlut_caps.dma_dim_17) + status = VPE_STATUS_BAD_TONE_MAP_PARAMS; + break; + case LUT_DIM_33: + // Verify if 33x33x33 LUT dimension is supported for fast loading + if (!vpe->caps->color_caps.mpc.lut_caps.lut_3dlut_caps.dma_dim_33) + status = VPE_STATUS_BAD_TONE_MAP_PARAMS; + break; + default: + // Unsupported LUT container dimension + status = VPE_STATUS_BAD_TONE_MAP_PARAMS; + } + } + } } return status; } @@ -665,3 +1009,136 @@ uint32_t vpe_align_seg(uint32_t seg_size, uint32_t alignment) return aligned_size; } +enum vpe_scan_direction vpe_get_scan_direction( + enum vpe_rotation_angle rotation, bool horizontal_mirror, bool vertical_mirror) +{ + enum vpe_scan_direction scan = VPE_SCAN_PATTERN_0_DEGREE; + switch (rotation) { + case VPE_ROTATION_ANGLE_0: + if (!horizontal_mirror && !vertical_mirror) { + scan = VPE_SCAN_PATTERN_0_DEGREE; + } else if (horizontal_mirror && vertical_mirror) { + scan = VPE_SCAN_PATTERN_180_DEGREE; + } else if (horizontal_mirror) { + scan = VPE_SCAN_PATTERN_0_DEGREE_H_MIRROR; + } else { + scan = VPE_SCAN_PATTERN_180_DEGREE_H_MIRROR; + } + break; + case VPE_ROTATION_ANGLE_90: + if (!horizontal_mirror && !vertical_mirror) { + scan = VPE_SCAN_PATTERN_90_DEGREE; + } else if (horizontal_mirror && vertical_mirror) { + scan = VPE_SCAN_PATTERN_270_DEGREE; + } else if (horizontal_mirror) { + scan = VPE_SCAN_PATTERN_270_DEGREE_V_MIRROR; + } else { + scan = VPE_SCAN_PATTERN_90_DEGREE_V_MIRROR; + } + break; + case VPE_ROTATION_ANGLE_180: + if (!horizontal_mirror && !vertical_mirror) { + scan = VPE_SCAN_PATTERN_180_DEGREE; + } else if (horizontal_mirror && vertical_mirror) { + scan = VPE_SCAN_PATTERN_0_DEGREE; + } else if (horizontal_mirror) { + scan = VPE_SCAN_PATTERN_180_DEGREE_H_MIRROR; + } else { + scan = VPE_SCAN_PATTERN_0_DEGREE_H_MIRROR; + } + break; + case VPE_ROTATION_ANGLE_270: + if (!horizontal_mirror && !vertical_mirror) { + scan = VPE_SCAN_PATTERN_270_DEGREE; + } else if (horizontal_mirror && vertical_mirror) { + scan = VPE_SCAN_PATTERN_90_DEGREE; + } else if (horizontal_mirror) { + scan = VPE_SCAN_PATTERN_90_DEGREE_V_MIRROR; + } else { + scan = VPE_SCAN_PATTERN_270_DEGREE_V_MIRROR; + } + break; + default: + scan = VPE_SCAN_PATTERN_0_DEGREE; + break; + } + + return scan; +} + +bool vpe_supported_linear_scan_pattern(enum vpe_scan_direction scan_dir) +{ + switch (scan_dir) { + case VPE_SCAN_PATTERN_90_DEGREE: + case VPE_SCAN_PATTERN_270_DEGREE: + case VPE_SCAN_PATTERN_90_DEGREE_V_MIRROR: + case VPE_SCAN_PATTERN_270_DEGREE_V_MIRROR: + return false; + case VPE_SCAN_PATTERN_0_DEGREE: + case VPE_SCAN_PATTERN_180_DEGREE: + case VPE_SCAN_PATTERN_0_DEGREE_H_MIRROR: + case VPE_SCAN_PATTERN_180_DEGREE_H_MIRROR: + return true; + default: + return false; + } +} + +bool vpe_validate_hist_collection(struct vpe_stream *stream) +{ + uint16_t histIndex = 0; + uint16_t valid_hist[hist_max_channel]; + uint16_t hist_src = 0; + + memset(valid_hist, 0, sizeof(uint16_t) * hist_max_channel); + for (histIndex = 0; histIndex < hist_max_channel; histIndex++) { + if (stream->hist_params.hist_collection_param[histIndex].hist_types != VPE_HISTOGRAM_NONE) { + for (hist_src = 0; hist_src < hist_max_channel; hist_src++) { + if ( (stream->hist_params.hist_collection_param[histIndex].hist_types == channel_hist_allowed_mode[hist_src][0]) || + (stream->hist_params.hist_collection_param[histIndex].hist_types == channel_hist_allowed_mode[hist_src][1])) { + valid_hist[hist_src]++; + if (valid_hist[hist_src] > 1) { + // two selected histograms set to the same source + return false; + } + } + } + if ( (histIndex > 0) && + (stream->hist_params.hist_collection_param[histIndex - 1].hist_types == VPE_HISTOGRAM_NONE)) { + return false; // the sequence of histogram cannot be "none, valid" or "valid, none, valid" + } // needs to be "valid, none, none" or "valid, valid, none" or valid all 3 + } + } + return true; +} + +enum vpe_status vpe_check_3dlut_compound( + struct vpe *vpe, const struct vpe_stream *stream, const struct vpe_build_param *param) +{ + struct vpe_priv *vpe_priv = container_of(vpe, struct vpe_priv, pub); + + // not enabled, nothing to check, always ok + if (stream->lut_compound.enabled == false) + return VPE_STATUS_OK; + + // no func ptr means no support at all, so cannot be enabled + if (!vpe_priv->resource.check_lut3d_compound) + return VPE_STATUS_LUT_COMPOUND_NOT_SUPPORTED; + + return vpe_priv->resource.check_lut3d_compound(stream, param); +} + +enum vpe_status vpe_check_histogram_support(struct vpe *vpe, const struct vpe_stream *stream) +{ + enum vpe_status result = VPE_STATUS_OK; + + // not enabled, nothing to check, always ok + if (stream->hist_params.hist_dsets == false) + return VPE_STATUS_OK; + + if (!vpe->caps->histogram_support) { + result = VPE_STATUS_HISTOGRAM_NOT_SUPPORTED; + } + + return result; +} diff --git a/src/amd/vpelib/src/core/config_writer.c b/src/amd/vpelib/src/core/config_writer.c index 3c0f4dbbd77..d79c8ea9a3f 100644 --- a/src/amd/vpelib/src/core/config_writer.c +++ b/src/amd/vpelib/src/core/config_writer.c @@ -275,6 +275,23 @@ void config_writer_fill_indirect_destination(struct config_writer *writer, config_writer_fill(writer, VPEC_FIELD_VALUE(VPE_IND_CFG_PKT_REGISTER_OFFSET, offset_data)); } +void config_writer_fill_3dlut_fl_addr(struct config_writer *writer, const uint64_t data_gpuva, + enum vpe_3dlut_addr_mode addr_mode, enum vpe_3dlut_mem_align mem_align, uint32_t size, + bool comp_mode, uint8_t tmz) +{ + VPE_ASSERT(writer->type == CONFIG_TYPE_3DLUT_FL); + VPE_ASSERT(size > 0); + uint32_t tmp_code = + ((comp_mode <base_cpu_va; + + *cmd_space = VPE_3DLUT_CFG_CMD_HEADER(addr_mode, mem_align); //---> this is DW0 + + config_writer_fill(writer, ADDR_LO(data_gpuva) | tmp_code); //----->This is DW1 + config_writer_fill(writer, ADDR_HI(data_gpuva)); //---------------->This is DW2 + config_writer_fill(writer, size - 1); //--------------------------->this is DW3 +} + void config_writer_complete(struct config_writer *writer) { uint32_t *cmd_space = (uint32_t *)(uintptr_t)writer->base_cpu_va; @@ -298,7 +315,7 @@ void config_writer_complete(struct config_writer *writer) // -4 for exclude header // VPEP_DIRECT_CONFIG_ARRAY_SIZE is 1-based, hence need -1 *cmd_space = VPE_DIR_CFG_CMD_HEADER(((size - 4) / sizeof(uint32_t) - 1)); - } else { + } else if (writer->type != CONFIG_TYPE_3DLUT_FL) { // -4 DW for header, data array size, data array lo and data array hi // /3 DW for each destination reg // NUM_DST is 1-based, hence need -1 diff --git a/src/amd/vpelib/src/core/inc/3dlut_builder.h b/src/amd/vpelib/src/core/inc/3dlut_builder.h index 1d766d376fb..1b54a7794ba 100644 --- a/src/amd/vpelib/src/core/inc/3dlut_builder.h +++ b/src/amd/vpelib/src/core/inc/3dlut_builder.h @@ -27,6 +27,7 @@ #include "vpe_priv.h" #include "common.h" +#define LUT3D_SIZE_33x33x33 35937 #define LUT3D_SIZE_17x17x17 4913 #define LUT3D_SIZE_9x9x9 729 diff --git a/src/amd/vpelib/src/core/inc/cdc.h b/src/amd/vpelib/src/core/inc/cdc.h index ccfb7fe695f..ce7ca0efd88 100644 --- a/src/amd/vpelib/src/core/inc/cdc.h +++ b/src/amd/vpelib/src/core/inc/cdc.h @@ -52,12 +52,15 @@ struct cdc_fe_funcs { enum vpe_swizzle_mode_values swizzle, const struct vpe_rect *viewport, const struct vpe_rect *viewport_c); + void (*program_3dlut_fl_config)( + struct cdc_fe *cdc_fe, enum lut_dimension lut_dimension, struct vpe_3dlut *lut_3d); /** segment specific */ void (*program_viewport)( struct cdc_fe *cdc_fe, const struct vpe_rect *viewport, const struct vpe_rect *viewport_c); }; struct cdc_be_funcs { + void (*program_cdc_control)(struct cdc_be *cdc_be, uint8_t enable_frod, uint32_t hist_dsets[]); void (*program_global_sync)(struct cdc_be *cdc_be, uint32_t vupdate_offset, uint32_t vupdate_width, uint32_t vready_offset); diff --git a/src/amd/vpelib/src/core/inc/color.h b/src/amd/vpelib/src/core/inc/color.h index 9ebd4d7d913..ba222c25f43 100644 --- a/src/amd/vpelib/src/core/inc/color.h +++ b/src/amd/vpelib/src/core/inc/color.h @@ -235,7 +235,8 @@ struct color_gamut_data { union vpe_3dlut_state { struct { uint32_t initialized : 1; /*< if 3dlut is went through color module for initialization */ - uint32_t reserved : 15; + uint32_t is_dma : 1; + uint32_t reserved : 14; } bits; uint32_t raw; }; @@ -245,6 +246,14 @@ struct vpe_3dlut { struct tetrahedral_params lut_3d; struct fixed31_32 hdr_multiplier; union vpe_3dlut_state state; + struct { + enum vpe_3dlut_mem_format format; + enum vpe_3dlut_mem_layout layout; + enum vpe_3dlut_addr_mode addr_mode; + enum vpe_3dlut_crossbar crossbar_r; + enum vpe_3dlut_crossbar crossbar_g; + enum vpe_3dlut_crossbar crossbar_b; + } dma_params; // the followings are for optimization: skip if no change bool dirty[MAX_3DLUT]; /*< indicate this object is updated or not */ @@ -302,6 +311,9 @@ bool vpe_color_update_degamma_tf(struct vpe_priv *vpe_priv, enum color_transfer_ enum color_range_type vpe_get_range_type( enum color_space color_space, enum vpe_surface_pixel_format format); +enum vpe_status vpe_color_setup_dma_lut( + struct vpe_3dlut *lut3d_func, struct stream_ctx *stream_ctx); + enum vpe_status vpe_calculate_shaper(struct vpe_priv *vpe_priv, struct stream_ctx *stream_ctx); #ifdef __cplusplus diff --git a/src/amd/vpelib/src/core/inc/color_table.h b/src/amd/vpelib/src/core/inc/color_table.h index 3a536b58945..2cd3114fdbc 100644 --- a/src/amd/vpelib/src/core/inc/color_table.h +++ b/src/amd/vpelib/src/core/inc/color_table.h @@ -52,6 +52,25 @@ struct vpe_csc_matrix { uint16_t regval[12]; }; +// S2.13 +static const struct vpe_csc_matrix vpe_output_full_csc_matrix_fixed[] = { + {COLOR_SPACE_SRGB, {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0}}, + {COLOR_SPACE_YCBCR601, {0x0e00, 0xf447, 0xfdb9, 0x1000, 0x082f, 0x1012, 0x031f, 0x0200, 0xfb47, + 0xf6b9, 0x0e00, 0x1000}}, + {COLOR_SPACE_YCBCR709, {0x0e00, 0xf349, 0xfeb7, 0x1000, 0x05d2, 0x1394, 0x01fa, 0x0200, 0xfccb, + 0xf535, 0x0e00, 0x1000}}, + {COLOR_SPACE_2020_YCBCR, {0x0e04, 0xf31d, 0xfedf, 0x1004, 0x0733, 0x1294, 0x01a0, 0x0201, + 0xfc16, 0xf5e6, 0x0e04, 0x1004}}}; + +static const struct vpe_csc_matrix vpe_output_studio_csc_matrix_fixed[] = { + {COLOR_SPACE_SRGB, {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0}}, + {COLOR_SPACE_YCBCR601, {0x1000, 0xf29a, 0xfd66, 0x1049, 0x0991, 0x12c9, 0x03a6, 0x0057, 0xfa9a, + 0xf566, 0x1000, 0x1049}}, + {COLOR_SPACE_YCBCR709, {0x1000, 0xf178, 0xfe88, 0x1049, 0x06ce, 0x16e3, 0x024f, 0x0057, 0xfc55, + 0xf3ab, 0x1000, 0x1049}}, + {COLOR_SPACE_2020_YCBCR, {0x1004, 0xf146, 0xfeb6, 0x104e, 0x086a, 0x15b8, 0x01e6, 0x0057, + 0xfb87, 0xf475, 0x1004, 0x104e}}}; + static const struct vpe_csc_matrix vpe_input_csc_matrix_fixed[] = { {COLOR_SPACE_SRGB, {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0}}, {COLOR_SPACE_YCBCR601, diff --git a/src/amd/vpelib/src/core/inc/common.h b/src/amd/vpelib/src/core/inc/common.h index cadd968be1f..c006ceada93 100644 --- a/src/amd/vpelib/src/core/inc/common.h +++ b/src/amd/vpelib/src/core/inc/common.h @@ -67,10 +67,13 @@ bool vpe_is_dual_plane_format(enum vpe_surface_pixel_format format); bool vpe_is_32bit_packed_rgb(enum vpe_surface_pixel_format format); bool vpe_is_rgb8(enum vpe_surface_pixel_format format); bool vpe_is_rgb10(enum vpe_surface_pixel_format format); +bool vpe_is_rgb16(enum vpe_surface_pixel_format format); +bool vpe_is_planar_format(enum vpe_surface_pixel_format format); bool vpe_is_fp16(enum vpe_surface_pixel_format format); bool vpe_is_yuv8(enum vpe_surface_pixel_format format); bool vpe_is_yuv10(enum vpe_surface_pixel_format format); +bool vpe_is_yuv12(enum vpe_surface_pixel_format format); // yuv 4:2:0 check bool vpe_is_yuv420_8(enum vpe_surface_pixel_format format); @@ -81,14 +84,23 @@ bool vpe_is_yuv420(enum vpe_surface_pixel_format format); // yuv 4:4:4 check bool vpe_is_yuv444_8(enum vpe_surface_pixel_format format); bool vpe_is_yuv444_10(enum vpe_surface_pixel_format format); +bool vpe_is_yuv444_12(enum vpe_surface_pixel_format format); bool vpe_is_yuv444(enum vpe_surface_pixel_format format); +// yuv 4:2:2 check +bool vpe_is_yuv422_8(enum vpe_surface_pixel_format format); +bool vpe_is_yuv422_10(enum vpe_surface_pixel_format format); +bool vpe_is_yuv422_12(enum vpe_surface_pixel_format format); +bool vpe_is_yuv422(enum vpe_surface_pixel_format format); +bool vpe_is_yuv_packed(enum vpe_surface_pixel_format format); +bool vpe_is_mono(enum vpe_surface_pixel_format format); bool vpe_is_yuv(enum vpe_surface_pixel_format format); bool vpe_is_8bit(enum vpe_surface_pixel_format format); bool vpe_is_10bit(enum vpe_surface_pixel_format format); +bool vpe_is_16bit(enum vpe_surface_pixel_format format); enum color_depth vpe_get_color_depth(enum vpe_surface_pixel_format format); bool vpe_has_per_pixel_alpha(enum vpe_surface_pixel_format format); @@ -107,6 +119,17 @@ uint8_t vpe_get_element_size_in_bytes(enum vpe_surface_pixel_format format, int uint32_t vpe_align_seg(uint32_t seg_size, uint32_t alignment); +enum vpe_status vpe_check_3dlut_compound( + struct vpe *vpe, const struct vpe_stream *stream, const struct vpe_build_param *param); + +enum vpe_status vpe_check_histogram_support(struct vpe *vpe, const struct vpe_stream *stream); + +enum vpe_scan_direction vpe_get_scan_direction( + enum vpe_rotation_angle rotation, bool horizontal_mirror, bool vertical_mirror); +bool vpe_supported_linear_scan_pattern(enum vpe_scan_direction scan_dir); + +bool vpe_validate_hist_collection(struct vpe_stream* stream); + #ifdef __cplusplus } #endif diff --git a/src/amd/vpelib/src/core/inc/config_writer.h b/src/amd/vpelib/src/core/inc/config_writer.h index 1ebc1033920..7eac0579a3e 100644 --- a/src/amd/vpelib/src/core/inc/config_writer.h +++ b/src/amd/vpelib/src/core/inc/config_writer.h @@ -41,6 +41,7 @@ enum config_type { CONFIG_TYPE_UNKNOWN, CONFIG_TYPE_DIRECT, CONFIG_TYPE_INDIRECT, + CONFIG_TYPE_3DLUT_FL, }; typedef void (*config_callback_t)( @@ -178,6 +179,10 @@ void config_writer_fill_indirect_data_array( void config_writer_fill_indirect_destination(struct config_writer *writer, const uint32_t offset_index, const uint32_t start_index, const uint32_t offset_data); +void config_writer_fill_3dlut_fl_addr(struct config_writer *writer, const uint64_t data_gpuva, + enum vpe_3dlut_addr_mode addr_mode, enum vpe_3dlut_mem_align mem_align, uint32_t size, + bool comp_mode, uint8_t tmz); + /** explicitly complete the config */ void config_writer_complete(struct config_writer *writer); diff --git a/src/amd/vpelib/src/core/inc/dpp.h b/src/amd/vpelib/src/core/inc/dpp.h index 71314f565a8..03ceb64ef7b 100644 --- a/src/amd/vpelib/src/core/inc/dpp.h +++ b/src/amd/vpelib/src/core/inc/dpp.h @@ -113,6 +113,15 @@ struct dpp_funcs { uint32_t (*get_line_buffer_size)(void); bool (*validate_number_of_taps)(struct dpp *dpp, struct scaler_data *scl_data); + void (*enable_clocks)(struct dpp *dpp, bool enable); + + void (*dscl_program_easf)(struct dpp *dpp, const struct scaler_data *scl_data); + + void (*dscl_disable_easf)(struct dpp *dpp, const struct scaler_data *scl_data); + + void (*dscl_program_isharp)(struct dpp *dpp, const struct scaler_data *scl_data); + + void (*program_histogram)(struct dpp* dpp, struct vpe_histogram_param* hist_param, enum color_space cs); void (*program_crc)(struct dpp *opp, bool enable); }; diff --git a/src/amd/vpelib/src/core/inc/hw_shared.h b/src/amd/vpelib/src/core/inc/hw_shared.h index fafcc41bdbe..8d4f0538c08 100644 --- a/src/amd/vpelib/src/core/inc/hw_shared.h +++ b/src/amd/vpelib/src/core/inc/hw_shared.h @@ -28,8 +28,11 @@ #define MAX_3DLUT 1 -#define MAX_INPUT_PIPE 1 -#define MAX_OUTPUT_PIPE 1 +#define MAX_INPUT_PIPE 2 +#define MAX_OUTPUT_PIPE 4 +#define FROD_NUM_OUTPUTS 4 /**< 4 outputs for FROD, one pipeline output and 3 downscaled versions 1:2, 1:4 and 1:8*/ +#define FROD_DOWNSAMPLING_RATIO 2 +#define MAX_HISTO_SETS 3 #ifdef __cplusplus extern "C" { @@ -136,6 +139,48 @@ enum hw_point_position { HW_POINT_POSITION_RIGHT, }; +/** @enum vpe_3dlut_mem_format + * @brief 3DLUT memory formats + */ +enum vpe_3dlut_mem_format { + VPE_3DLUT_MEM_FORMAT_16161616_UNORM_12MSB = 0, /**< 12 bit integer in a 16 bit container + aligned MSB */ + VPE_3DLUT_MEM_FORMAT_16161616_UNORM_12LSB = 1, /**< 12 bit integer in a 16 bit container + aligned LSB */ + VPE_3DLUT_MEM_FORMAT_16161616_FLOAT_FP1_5_10 = 2, /**< Floating point with one sign bit, + 5 exponential bits and 10 mantissa */ +}; + +/** @enum vpe_3dlut_mem_layout + * @brief 3DLUT memory layout + */ +enum vpe_3dlut_mem_layout { + VPE_3DLUT_MEM_LAYOUT_DISABLE = 0, /**< Disabled */ + VPE_3DLUT_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB = 1, /**< 3D Swizzle linear surface addressing + incremented as R->G->B */ + VPE_3DLUT_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR = 2, /**< 3D Swizzle linear surface addressing + incremented as B->G->R */ + VPE_3DLUT_MEM_LAYOUT_1D_PACKED_LINEAR = 3, /**< Packed 1d linear addressing */ +}; + +/** @enum vpe_3dlut_crossbar + * @brief 3DLUT Crossbar bit slice + */ +enum vpe_3dlut_crossbar { + VPE_3DLUT_CROSSBAR_BIT_SLICE_0_15 = 0, /**< 3DLUT Crossbar Mux Select bits 0-15 */ + VPE_3DLUT_CROSSBAR_BIT_SLICE_16_31 = 1, /**< 3DLUT Crossbar Mux Select bits 16-31 */ + VPE_3DLUT_CROSSBAR_BIT_SLICE_32_47 = 2, /**< 3DLUT Crossbar Mux Select bits 32-47 */ + VPE_3DLUT_CROSSBAR_BIT_SLICE_48_63 = 3, /**< 3DLUT Crossbar Mux Select bits 48-63 */ +}; + +/** @enum vpe_3dlut_addr_mode + * @brief 3DLUT Swizzle addressing + */ +enum vpe_3dlut_addr_mode { + VPE_3DLUT_SIMPLE_LINEAR = 0, /**< Linear swizzle 3DLUT addressing */ + VPE_3DLUT_SW_LINEAR = 1, /**< Contiguous 3DLUT addressing */ +}; + struct gamma_point { int32_t left_index; int32_t right_index; @@ -158,6 +203,7 @@ enum lut_dimension { LUT_DIM_INVALID = 0, LUT_DIM_9 = 9, LUT_DIM_17 = 17, + LUT_DIM_33 = 33, }; struct vpe_rgb { @@ -166,6 +212,13 @@ struct vpe_rgb { uint32_t blue; }; +struct tetrahedral_33x33x33 { + struct vpe_rgb lut0[8985]; + struct vpe_rgb lut1[8984]; + struct vpe_rgb lut2[8984]; + struct vpe_rgb lut3[8984]; +}; + struct tetrahedral_17x17x17 { struct vpe_rgb lut0[1229]; struct vpe_rgb lut1[1228]; @@ -181,6 +234,7 @@ struct tetrahedral_9x9x9 { struct tetrahedral_params { union { + struct tetrahedral_33x33x33 tetrahedral_33; struct tetrahedral_17x17x17 tetrahedral_17; struct tetrahedral_9x9x9 tetrahedral_9; }; diff --git a/src/amd/vpelib/src/core/inc/mpc.h b/src/amd/vpelib/src/core/inc/mpc.h index bfc140774da..b61cc5935ba 100644 --- a/src/amd/vpelib/src/core/inc/mpc.h +++ b/src/amd/vpelib/src/core/inc/mpc.h @@ -43,21 +43,25 @@ enum mpc_mpccid { enum mpc_mux_topsel { MPC_MUX_TOPSEL_DPP0 = 0, + MPC_MUX_TOPSEL_DPP1 = 1, MPC_MUX_TOPSEL_DISABLE = 0x0f, }; enum mpc_mux_botsel { MPC_MUX_BOTSEL_MPCC0 = 0, + MPC_MUX_BOTSEL_MPCC1 = 1, MPC_MUX_BOTSEL_DISABLE = 0x0f, }; enum mpc_mux_outmux { MPC_MUX_OUTMUX_MPCC0 = 0, + MPC_MUX_OUTMUX_MPCC1 = 1, MPC_MUX_OUTMUX_DISABLE = 0x0f, }; enum mpc_mux_oppid { MPC_MUX_OPPID_OPP0 = 0, + MPC_MUX_OPPID_OPP1 = 1, MPC_MUX_OPPID_DISABLE = 0x0f, }; @@ -72,6 +76,14 @@ enum mpcc_alpha_blend_mode { MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA, MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN, MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA, + MPCC_ALPHA_BLEND_MODE_ALPHA_THROUGH_LUMA, +}; + +enum mpcc_gamut_remap_id { + VPE_MPC_GAMUT_REMAP, + VPE_MPC_RMCM_GAMUT_REMAP, + VPE_MPC_MCM_FIRST_GAMUT_REMAP, + VPE_MPC_MCM_SECOND_GAMUT_REMAP, }; /* @@ -168,6 +180,20 @@ struct mpc_funcs { struct vpe_3dlut *lut3d_func, struct transfer_func *blend_tf, bool afterblend); void (*program_crc)(struct mpc *mpc, bool enable); + void (*attach_3dlut_to_mpc_inst)(struct mpc *mpc, enum mpc_mpccid mpcc_idx); + + void (*set_gamut_remap2)(struct mpc *mpc, struct colorspace_transform *gamut_remap, + enum mpcc_gamut_remap_id mpcc_gamut_remap_block_id); + + void (*update_3dlut_fl_bias_scale)(struct mpc *mpc, uint16_t bias, uint16_t scale); + + void (*program_mpc_3dlut_fl_config)(struct mpc *mpc, enum vpe_3dlut_mem_layout layout, + enum vpe_3dlut_mem_format format, bool enable); + + void (*program_mpc_3dlut_fl)(struct mpc *mpc, enum lut_dimension lut_dimension, bool use_12bit); + + void (*shaper_bypass)(struct mpc *mpc, bool bypass); + }; struct mpc { diff --git a/src/amd/vpelib/src/core/inc/multi_pipe_segmentation.h b/src/amd/vpelib/src/core/inc/multi_pipe_segmentation.h new file mode 100644 index 00000000000..42e39cf9109 --- /dev/null +++ b/src/amd/vpelib/src/core/inc/multi_pipe_segmentation.h @@ -0,0 +1,143 @@ +/* Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#pragma once + +#include "vpe_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct vpe_mps_section { + uint16_t num_streams; + int32_t start_x; + int32_t end_x; + + struct vpe_vector *command_vector; // type struct vpe_mps_command +}; + +struct vpe_mps_command { + uint16_t num_inputs; + uint16_t stream_idx[MAX_INPUT_PIPE]; // stream idx for input in vpe_priv->stream_ctx array + int16_t mps_idx[MAX_INPUT_PIPE]; // track stream idx in mps struct for each input + uint16_t + seg_idx[MAX_INPUT_PIPE]; // track segment idx for each input (segments stores in stream_ctx) + int32_t start_x[MAX_INPUT_PIPE]; // start_x for each input (segment + bg gen) + int32_t end_x[MAX_INPUT_PIPE]; // end_x for each input (segment + bg gen) + bool is_bg_gen[MAX_INPUT_PIPE]; // is this input all bg +}; + +struct vpe_mps_stream_info { + struct stream_ctx *stream_ctx; + struct vpe_rect src_rect; + struct vpe_rect dst_rect; +}; + +struct vpe_mps_ctx { + struct vpe_vector *section_vector; // type struct vpe_mps_section + + uint16_t num_streams; + uint16_t stream_idx[MAX_INPUT_PIPE]; + uint16_t segment_count[MAX_INPUT_PIPE]; // how many segments each stream has + struct vpe_vector + *segment_widths[MAX_INPUT_PIPE]; // type struct vpe_vector : array containing + // vector of segments widths per stream +}; + +struct vpe_mps_stream_ctx { + struct stream_ctx *stream_ctx; + struct vpe_rect src_rect; + struct vpe_rect dst_rect; +}; + +// Everything required to run MPS algo +struct vpe_mps_input { + uint16_t num_inputs; + struct vpe_mps_stream_ctx mps_stream_ctx[MAX_INPUT_PIPE]; + uint32_t max_seg_width; + uint32_t recout_width_alignment; +}; + +/** + * @brief Check if MPS is possible with the streams passed in + * @param[in] vpe_priv vpe_priv + * @param[in] stream_ctx array of stream_ctx involved in MPS blend + * @param[in] num_streams number of streams in stream_ctx array + * @return true if possible, false if not + */ +bool vpe_is_mps_possible(struct vpe_priv *vpe_priv, struct stream_ctx **stream_ctx, + uint16_t num_streams, uint32_t recout_width_alignment); + +/** + * @brief Allocate mps_ctx and initialize it with the stream_idx and num_streams. Run + * vpe_is_mps_possible beforehand! + * @param[in] vpe_priv vpe_priv + * @param[in] stream_ctx array of stream_ctx involved in MPS blend + * @param[in] num_streams number of streams in stream_ctx array + * @return VPE_STATUS_OK if successful, error code otherwise + */ +enum vpe_status vpe_init_mps_ctx( + struct vpe_priv *vpe_priv, struct stream_ctx **stream_ctx, uint16_t num_streams); + +/** + * @brief Clear mps_ctx and NULL mps_parent_stream for non-parents streams involved (mem isn't + * freed) + * @param[in] vpe_priv vpe_priv + * @param[in] mps_ctx mps_ctx to be cleared + * @return VPE_STATUS_OK if successful, error code otherwise + */ +void vpe_clear_mps_ctx(struct vpe_priv *vpe_priv, struct vpe_mps_ctx *mps_ctx); + +/** + * @brief Deallocate and free mps_ctx and NULL mps_parent_stream for all streams involved + * @param[in] vpe_priv vpe_priv + * @param[in] mps_ctx mps_ctx to be freed + * @return VPE_STATUS_OK if successful, error code otherwise + */ +void vpe_free_mps_ctx(struct vpe_priv *vpe_priv, struct vpe_mps_ctx **mps_ctx); + +/** + * @brief Add commands to vpe_priv cmd_vector for this MPS op + * @param[in] vpe_priv vpe_priv + * @param[in] mps_ctx mps_ctx (filled out by vpe_mps_build_mps_ctx) + * @return VPE_STATUS_OK if successful, error code otherwise + */ +enum vpe_status vpe_fill_mps_blend_cmd_info(struct vpe_priv *vpe_priv, struct vpe_mps_ctx *mps_ctx); + +/** + * @brief Get number of segments required for this MPS involved stream. This must be ran on the + * parent stream the first time! + * @param[in] vpe_priv vpe_priv + * @param[in] stream_ctx stream_ctx + * @param[in] max_seg_width maximum segment width for this stream + * @param[in] recout_width_alignment recout width alignment + * @return number of segments required for this stream + */ +uint16_t vpe_mps_get_num_segs(struct vpe_priv *vpe_priv, struct stream_ctx *stream_ctx, + uint32_t *max_seg_width, uint32_t recout_width_alignment); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/inc/opp.h b/src/amd/vpelib/src/core/inc/opp.h index 3e01b646a9d..de0e1df303d 100644 --- a/src/amd/vpelib/src/core/inc/opp.h +++ b/src/amd/vpelib/src/core/inc/opp.h @@ -103,12 +103,59 @@ struct opp_pipe_control_params { /**< Digital bypass enable */ bool bypass_enable; /**< Enable bypass mode for the pipe */ + /**< Pipe alpha select */ + bool alpha_select; +}; + +enum subsampling_quality { + SUBSAMPLING_QUALITY_HIGH, + SUBSAMPLING_QUALITY_LOW, + SUBSAMPLING_QUALITY_COUNT, +}; + +enum fmt_subsampling_boundary_mode { + FMT_SUBSAMPLING_BOUNDARY_REPEAT = 0, + FMT_SUBSAMPLING_BOUNDARY_EXTRA = 1, +}; + +struct fmt_boundary_mode { + enum fmt_subsampling_boundary_mode left; + enum fmt_subsampling_boundary_mode right; + enum fmt_subsampling_boundary_mode top; + enum fmt_subsampling_boundary_mode bottom; +}; + +struct chroma_taps { + uint32_t v_taps_c; /**< Number of vertical taps for chroma plane */ + uint32_t h_taps_c; /**< Number of horizontal taps for chroma plane */ +}; + +struct fmt_extra_pixel_info { + uint32_t left_pixels; + uint32_t right_pixels; + uint32_t top_pixels; + uint32_t bottom_pixels; +}; + +struct fmt_subsampling_params { + uint32_t pixel_encoding; + uint32_t bit_reduction_bypass; + uint32_t vtaps; + uint32_t htaps; + struct fmt_boundary_mode boundary_mode; }; struct fmt_control_params { uint8_t fmt_spatial_dither_frame_counter_max; uint8_t fmt_spatial_dither_frame_counter_bit_swap; + struct fmt_subsampling_params subsampling_params; +}; + +struct opp_frod_param { + union { + uint8_t enable_frod; + }; }; struct opp_funcs { @@ -129,6 +176,19 @@ struct opp_funcs { void (*program_pipe_crc)(struct opp *opp, bool enable); + void (*build_fmt_subsample_params)(struct opp *opp, enum vpe_surface_pixel_format format, + enum subsampling_quality subsample_quality, enum chroma_cositing cositing, + struct fmt_boundary_mode boundary_mode, struct fmt_subsampling_params *subsample_params); + + void (*set_bg)(struct opp* opp, struct vpe_rect target_rect, struct vpe_rect dst_rect, + enum vpe_surface_pixel_format format, struct vpe_color bgcolor); + + void (*program_frod)(struct opp *opp, struct opp_frod_param *frod_param); + + void (*get_fmt_extra_pixel)(enum vpe_surface_pixel_format format, + enum subsampling_quality subsample_quality, enum chroma_cositing cositing, + struct fmt_extra_pixel_info *extra_pixel); + }; struct opp { diff --git a/src/amd/vpelib/src/core/inc/plane_desc_writer.h b/src/amd/vpelib/src/core/inc/plane_desc_writer.h index 948e64cf8aa..676d819ce3e 100644 --- a/src/amd/vpelib/src/core/inc/plane_desc_writer.h +++ b/src/amd/vpelib/src/core/inc/plane_desc_writer.h @@ -45,6 +45,9 @@ struct plane_desc_writer { void (*init)(struct plane_desc_writer *writer, struct vpe_buf *buf, void *p_header); void (*add_source)(struct plane_desc_writer *writer, void *p_source, bool is_plane0); void (*add_destination)(struct plane_desc_writer *writer, void *p_destination, bool is_plane0); + void (*add_meta)(struct plane_desc_writer *writer, void *p_source); + void (*add_histo)(struct plane_desc_writer *writer, void *p_destination, uint32_t hist_index, + uint8_t hist_dsets_array[]); }; #ifdef __cplusplus diff --git a/src/amd/vpelib/src/core/inc/resource.h b/src/amd/vpelib/src/core/inc/resource.h index bbe4015d3b7..536d3645c64 100644 --- a/src/amd/vpelib/src/core/inc/resource.h +++ b/src/amd/vpelib/src/core/inc/resource.h @@ -122,8 +122,46 @@ struct resource { enum vpe_status (*check_alpha_fill_support)( struct vpe *vpe, const struct vpe_build_param *param); + enum vpe_status (*fill_alpha_through_luma_cmd_info)( + struct vpe_priv *vpe_priv, uint16_t alpha_stream_idx); + + enum vpe_status (*fill_non_performance_mode_cmd_info)( + struct vpe_priv *vpe_priv, uint16_t stream_idx); + + enum vpe_status (*fill_performance_mode_cmd_info)( + struct vpe_priv *vpe_priv, uint16_t stream_idx, uint16_t avail_pipe_count); + + enum vpe_status (*fill_blending_cmd_info)( + struct vpe_priv *vpe_priv, uint16_t top_stream_idx, uint16_t bot_stream_idx); + + enum vpe_status (*populate_frod_param)( + struct vpe_priv *vpe_priv, const struct vpe_build_param *param); + + uint32_t (*get_num_pipes_available)(struct vpe_priv *vpe_priv, struct stream_ctx *stream_ctx); + + void (*set_frod_output_viewport)(struct vpe_cmd_output *dst_output, + struct vpe_cmd_output *src_output, uint32_t viewport_divider, + enum vpe_surface_pixel_format format); + + void (*reset_pipes)(struct vpe_priv *vpe_priv); + + enum vpe_status (*check_lut3d_compound)( + const struct vpe_stream *stream, const struct vpe_build_param *param); + + void (*set_lls_pref)(struct vpe_priv *vpe_priv, struct spl_in *spl_input, + enum color_transfer_func tf, enum vpe_surface_pixel_format pixel_format); + void (*program_fastload)(struct vpe_priv *vpe_priv, uint32_t cmd_idx); + enum vpe_status (*calculate_shaper)(struct vpe_priv *vpe_priv, struct stream_ctx *stream_ctx); + void (*update_opp_adjust_and_boundary)(struct stream_ctx *stream_ctx, uint16_t seg_idx, + bool dst_subsampled, const struct vpe_rect *src_rect, const struct vpe_rect *dst_rect, + struct output_ctx *output_ctx, struct spl_opp_adjust *opp_recout_adjust); + + bool (*set_dst_cmd_info_scaler)(struct stream_ctx *dst_stream_ctx, + struct scaler_data *dst_scaler_data, struct vpe_rect recout, struct vpe_rect dst_viewport, + struct fmt_boundary_mode *boundary_mode, struct spl_opp_adjust *opp_adjust); + // Indicates the nominal range hdr input content should be in during processing. int internal_hdr_normalization; @@ -196,6 +234,16 @@ void vpe_backend_config_callback( bool vpe_rec_is_equal(struct vpe_rect rec1, struct vpe_rect rec2); +bool vpe_is_zero_rect(struct vpe_rect *rect); + +bool vpe_is_valid_vp(struct vpe_rect *src_rect, struct vpe_rect *dst_rect); + +bool vpe_is_scaling_factor_supported(struct vpe_priv *vpe_priv, struct vpe_rect *src_rect, + struct vpe_rect *dst_rect, enum vpe_rotation_angle rotation); + +struct stream_ctx *vpe_get_virtual_stream( + struct vpe_priv *vpe_priv, enum vpe_stream_type stream_type); + const struct vpe_caps *vpe_get_capability(enum vpe_ip_level ip_level); void vpe_setup_check_funcs(struct vpe_check_support_funcs *funcs, enum vpe_ip_level ip_level); diff --git a/src/amd/vpelib/src/core/inc/shaper_builder.h b/src/amd/vpelib/src/core/inc/shaper_builder.h index d8d25cf0522..c8a9ce7ba28 100644 --- a/src/amd/vpelib/src/core/inc/shaper_builder.h +++ b/src/amd/vpelib/src/core/inc/shaper_builder.h @@ -31,12 +31,21 @@ #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) #define SHAPER_EXP_MAX_IN 16 +enum vpe_shaper_index_mode { + SHAPER_INDEX_MODE_DEFAULT, + SHAPER_INDEX_MODE_17IN33LUT +}; + struct vpe_shaper_setup_in { double source_luminance; double shaper_in_max; bool use_const_hdr_mult; + enum vpe_shaper_index_mode index_mode; }; enum vpe_status vpe_build_shaper(const struct vpe_shaper_setup_in *shaper_in, enum color_transfer_func shaper_tf, struct fixed31_32 pq_norm_gain, struct pwl_params *shaper_out); + +enum vpe_shaper_index_mode vpe_get_shaper_index_mode( + uint32_t is_dma, enum lut_dimension lut_dim, enum lut_dimension lut_container_dim); diff --git a/src/amd/vpelib/src/core/inc/transform.h b/src/amd/vpelib/src/core/inc/transform.h index a4d7d77bbe4..17975151af9 100644 --- a/src/amd/vpelib/src/core/inc/transform.h +++ b/src/amd/vpelib/src/core/inc/transform.h @@ -29,6 +29,7 @@ #include #include "vpe_hw_types.h" #include "fixed31_32.h" +#include "SPL/dc_spl_types.h" #ifdef __cplusplus extern "C" { @@ -46,22 +47,6 @@ struct gamut_remap_matrix { enum gamut_adjust_type adjust_type; }; -enum lb_memory_config { - /* Enable all 3 pieces of memory */ - LB_MEMORY_CONFIG_0 = 0, - - /* Enable only the first piece of memory */ - LB_MEMORY_CONFIG_1 = 1, - - /* Enable only the second piece of memory */ - LB_MEMORY_CONFIG_2 = 2, - - /* Only applicable in 4:2:0 mode, enable all 3 pieces of memory and the - * last piece of chroma memory used for the luma storage - */ - LB_MEMORY_CONFIG_3 = 3, -}; - struct scaling_ratios { struct fixed31_32 horz; struct fixed31_32 vert; @@ -100,6 +85,7 @@ struct scaler_data { enum vpe_surface_pixel_format format; struct line_buffer_params lb_params; struct vpe_scaling_filter_coeffs *polyphase_filter_coeffs; + struct dscl_prog_data dscl_prog_data; }; const uint16_t *vpe_get_filter_2tap_64p(void); diff --git a/src/amd/vpelib/src/core/inc/vpe_command.h b/src/amd/vpelib/src/core/inc/vpe_command.h index bde5b741e31..d6384cf1a32 100644 --- a/src/amd/vpelib/src/core/inc/vpe_command.h +++ b/src/amd/vpelib/src/core/inc/vpe_command.h @@ -89,6 +89,7 @@ enum VPE_CMD_OPCODE { enum VPE_VPEP_CFG_SUBOP { VPE_VPEP_CFG_SUBOP_DIR_CFG = 0x0, VPE_VPEP_CFG_SUBOP_IND_CFG = 0x1, + VPE_VPEP_CFG_SUBOP_3DLUT_CFG = 0x2, }; // Direct Config Command Header @@ -119,6 +120,22 @@ enum VPE_VPEP_CFG_SUBOP { #define VPE_IND_CFG_PKT_REGISTER_OFFSET__SHIFT 2 #define VPE_IND_CFG_PKT_REGISTER_OFFSET_MASK 0x000FFFFC +// VPEP 3D LUT Config Command Header +#define VPE_3DLUT_CFG_HEADER_ADDR_MOD__SHIFT 31 +#define VPE_3DLUT_CFG_HEADER_ADDR_MOD_MASK 0x80000000 +#define VPE_3DLUT_CFG_HEADER_PITCH_MOD__SHIFT 30 +#define VPE_3DLUT_CFG_HEADER_PITCH_MOD_MASK 0x40000000 + +#define VPE_3DLUT_CFG_CMD_HEADER(addr_mode, mem_align) \ + (VPE_CMD_HEADER(VPE_CMD_OPCODE_VPEP_CFG, VPE_VPEP_CFG_SUBOP_3DLUT_CFG) | \ + ((((uint32_t)addr_mode) << VPE_3DLUT_CFG_HEADER_ADDR_MOD__SHIFT) & \ + VPE_3DLUT_CFG_HEADER_ADDR_MOD_MASK) | \ + ((((uint32_t)mem_align) << VPE_3DLUT_CFG_HEADER_PITCH_MOD__SHIFT) & \ + VPE_3DLUT_CFG_HEADER_PITCH_MOD_MASK)) + +#define VPE_3DLUT_CFG_COMP_MODE__SHIFT 5 +#define VPE_3DLUT_CFG_COMP_MODE_MASK 0x20 + /************************** * Poll Reg/Mem Sub-OpCode **************************/ diff --git a/src/amd/vpelib/src/core/inc/vpe_priv.h b/src/amd/vpelib/src/core/inc/vpe_priv.h index 42fd7485ac4..861ab92f4a6 100644 --- a/src/amd/vpelib/src/core/inc/vpe_priv.h +++ b/src/amd/vpelib/src/core/inc/vpe_priv.h @@ -61,12 +61,24 @@ extern "C" { #define MAX_LINE_CNT 4 #define VPE_NO_ALIGNMENT 1 +#define VPE_SUBSAMPLED_OUT_ALIGNMENT 2 +#define VPE_FROD_ALIGNMENT 16 +#define MAX_FROD_VIEWPORT_DIVIDER 8 + +#define VPE_DESTINATION_AS_INPUT_STREAM_INDEX 0xff + +#define OPTIMAL_MIN_PERFORMACE_MODE_SIZE \ + 400 // Temp smallest value for performance mode to be worth it - need to determine this + // experimentally i.e. values where num_pixels isn't worth cmd_info generation time enum vpe_cmd_ops { VPE_CMD_OPS_BLENDING, VPE_CMD_OPS_BG, VPE_CMD_OPS_COMPOSITING, VPE_CMD_OPS_BG_VSCF_INPUT, // For visual confirm input VPE_CMD_OPS_BG_VSCF_OUTPUT, // For visual confirm output + VPE_CMD_OPS_ALPHA_THROUGH_LUMA, + VPE_CMD_OPS_BG_VSCF_PIPE0, // For visual confirm pipe 0 + VPE_CMD_OPS_BG_VSCF_PIPE1, // For visual confirm pipe 1 }; enum vpe_cmd_type { @@ -74,17 +86,26 @@ enum vpe_cmd_type { VPE_CMD_TYPE_BG, VPE_CMD_TYPE_BG_VSCF_INPUT, // For visual confirm input VPE_CMD_TYPE_BG_VSCF_OUTPUT, // For visual confirm output + VPE_CMD_TYPE_BLENDING, // For alpha blending + VPE_CMD_TYPE_ALPHA_THROUGH_LUMA, + VPE_CMD_TYPE_BG_VSCF_PIPE0, // For visual confirm pipe 0 + VPE_CMD_TYPE_BG_VSCF_PIPE1, // For visual confirm pipe 1 VPE_CMD_TYPE_COUNT }; enum vpe_stream_type { VPE_STREAM_TYPE_INPUT, VPE_STREAM_TYPE_BG_GEN, + VPE_STREAM_TYPE_DESTINATION, + VPE_STREAM_TYPE_BKGR_BACKGROUND, // New background for the bg replacement (BKGR) feature + VPE_STREAM_TYPE_BKGR_VIDEO, // Video which will have its bg replaced + VPE_STREAM_TYPE_BKGR_ALPHA, // Alpha stream for to combine with BKGR video stream }; enum lut3d_type { LUT3D_TYPE_NONE, LUT3D_TYPE_CPU, + LUT3D_TYPE_GPU, }; /** this represents a segement context. @@ -93,6 +114,8 @@ struct segment_ctx { uint16_t segment_idx; struct stream_ctx *stream_ctx; struct scaler_data scaler_data; + struct fmt_boundary_mode boundary_mode; + struct spl_opp_adjust opp_recout_adjust; }; struct vpe_cmd_input { @@ -103,6 +126,8 @@ struct vpe_cmd_input { struct vpe_cmd_output { struct vpe_rect dst_viewport; struct vpe_rect dst_viewport_c; + struct fmt_boundary_mode boundary_mode; + struct spl_opp_adjust opp_recout_adjust; }; struct vpe_cmd_info { @@ -121,6 +146,9 @@ struct vpe_cmd_info { bool insert_start_csync; bool insert_end_csync; + struct vpe_surface_info frod_surface[VPE_FROD_MAX_STAGE]; /**< FROD outputs */ + struct opp_frod_param frod_param; /**< FROD parameters */ + uint32_t histo_dsets[MAX_INPUT_PIPE]; }; struct config_record { @@ -151,6 +179,7 @@ struct stream_ctx { uint64_t uid_3dlut; // UID for current 3D LUT params bool geometric_scaling; bool is_yuv_input; + struct fixed31_32 csc_renorm_factor; // csc was scaled down to fit into HW format union { struct { @@ -169,10 +198,21 @@ struct stream_ctx { struct transfer_func *in_shaper_func; // for shaper lut struct vpe_3dlut *lut3d_func; // for 3dlut struct transfer_func *blend_tf; // for 1dlut + struct vpe_mps_ctx *mps_ctx; // used to store the return values from multi-pipe segmentation. + // Allocated by the base stream. if non-base stream, access this + // through ctx->mps_parent_stream->mps_ctx + struct stream_ctx + *mps_parent_stream; // point to base stream for multi-pipe segmentation + // ex. if blending streams 0, 1 & 2, this will point to stream 0 white_point_gain white_point_gain; bool flip_horizonal_output; struct vpe_color_adjust color_adjustments; // stores the current color adjustments params struct fixed31_32 tf_scaling_factor; // a gain applied on a transfer function + enum vpe_scan_direction scan; // Scan direction based on the h/v mirror and rotation angle + struct spl_in spl_input; + struct spl_out spl_output; + enum fmt_subsampling_boundary_mode left; + enum fmt_subsampling_boundary_mode right; }; struct output_ctx { @@ -200,6 +240,9 @@ struct output_ctx { }; unsigned int u32All; } dirty_bits; + struct vpe_surface_info frod_surface[VPE_FROD_MAX_STAGE]; // surfaces for FROD + struct vpe_csc_matrix* out_csc_matrix; // for mpc out + struct vpe_frod_param frod_param; // FROD parameters struct transfer_func *output_tf; const struct transfer_func *in_shaper_func; // for shaper lut const struct vpe_3dlut *lut3d_func; // for 3dlut diff --git a/src/amd/vpelib/src/core/inc/vpe_spl_translation.h b/src/amd/vpelib/src/core/inc/vpe_spl_translation.h new file mode 100644 index 00000000000..40ef16c0b44 --- /dev/null +++ b/src/amd/vpelib/src/core/inc/vpe_spl_translation.h @@ -0,0 +1,48 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#pragma once + +#include "vpe_types.h" +#include "transform.h" +#include "vpe_priv.h" +#include "SPL/dc_spl_types.h" +#include "SPL/dc_spl.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void vpe_spl_scl_to_vpe_scl(struct spl_out *spl_out, struct scaler_data *vpe_scl_data); + +void vpe_init_spl_in( + struct spl_in *spl_input, struct stream_ctx *stream_ctx, struct output_ctx *output_ctx); + +void vpe_scl_to_dscl_bg(struct scaler_data *scl_data); + +void vpe_get_vp_scan_direction(enum vpe_rotation_angle degree, bool h_mirror, bool v_mirror, + bool *orthogonal_rotation, bool *flip_horz_scan_dir, bool *flip_vert_scan_dir); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/core/multi_pipe_segmentation.c b/src/amd/vpelib/src/core/multi_pipe_segmentation.c new file mode 100644 index 00000000000..84833d27721 --- /dev/null +++ b/src/amd/vpelib/src/core/multi_pipe_segmentation.c @@ -0,0 +1,2119 @@ +/* Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "vpe_assert.h" +#include "vpe_priv.h" +#include "common.h" +#include "multi_pipe_segmentation.h" +#include "vpe20_resource.h" + +#define MPS_INITIAL_SECTION_SIZE 2 + +/* ===== START HELPER FUNCTIONS =============================================================== */ + +static inline int32_t get_section_width(const struct vpe_mps_section *section) +{ + return section->end_x - section->start_x; +} + +static bool is_value_in_range(int32_t value, int32_t start, int32_t end) +{ + return (value >= start) && (value <= end); +} + +// Return amount of rect that exists horizontally between two x coordinates +static uint32_t get_rect_width_in_range( + const struct vpe_rect *rect, int32_t left_x, int32_t right_x) +{ + if (rect->x <= left_x && (rect->x + (int32_t)rect->width) >= right_x) + return right_x - left_x; + + bool left_edge_inside = is_value_in_range(rect->x, left_x, right_x); + bool right_edge_inside = is_value_in_range(rect->x + (int32_t)rect->width, left_x, right_x); + uint32_t stride; + + if (left_edge_inside && right_edge_inside) + stride = rect->width; + else if (left_edge_inside) + stride = right_x - rect->x; + else if (right_edge_inside) + stride = (rect->x + rect->width) - left_x; + else + stride = 0; + + return stride; +} + +// Limit total segment width to keep dst rect within its max width +// (which will be limited by keeping src rect within max seg width) +static uint32_t change_right_seg_edge_to_limit_dst_rect_width( + const struct vpe_rect *rect, int32_t seg_left_x, int32_t seg_right_x, uint32_t max_dst_stride) +{ + bool left_edge_inside = is_value_in_range(rect->x, seg_left_x, seg_right_x); + + uint32_t stride = get_rect_width_in_range(rect, seg_left_x, seg_right_x); + int32_t new_seg_right_x = seg_right_x; + + // NOTE: the case where rect isn't within this segment is handled by get_rect_width_in_range() + if (stride > max_dst_stride) { + if (left_edge_inside) { + new_seg_right_x = rect->x + max_dst_stride; + } else { + new_seg_right_x = seg_left_x + max_dst_stride; + } + VPE_ASSERT(new_seg_right_x < seg_right_x); // Sanity check that we removed from total width + } + return new_seg_right_x; +} + +static uint16_t get_num_rects_at_x( + int32_t x, const struct vpe_rect *dst_rects, uint16_t num_input_streams) +{ + uint16_t num_rects = 0; + + for (int i = 0; i < num_input_streams; i++) + if ((x >= dst_rects[i].x) && (x < (int32_t)(dst_rects[i].x + dst_rects[i].width))) + num_rects++; + + return num_rects; +} + +// return total number of rects that exist within the same recout_align block as this x coordinate +// ex. if x = 21 and recout_align = 16, return all rects with any pixels in x e [16, 32) +static uint16_t get_num_rects_at_x_recout_align( + int32_t x, const struct vpe_rect *dst_rects, uint16_t num_input_streams, uint32_t recout_align) +{ + if (recout_align == VPE_NO_ALIGNMENT) + return get_num_rects_at_x(x, dst_rects, num_input_streams); + + int32_t lower_bound = recout_align * (x / recout_align); + int32_t upper_bound = lower_bound + recout_align; + + uint16_t num_rects = 0; + + for (int i = 0; i < num_input_streams; i++) + if (get_rect_width_in_range(&dst_rects[i], lower_bound, upper_bound) != 0) + num_rects++; + + return num_rects; +} + +// Helper func to determine when one section ends and the next one starts - checks number of streams +// at x and if its not equal to the number in the current section, updates next_section_start +static void check_num_rects_at_x_and_update_next_section_x(uint16_t prev_section_num_streams, + int32_t x, const struct vpe_rect *dst_rects, uint16_t num_input_streams, + uint32_t recout_width_alignment, int32_t *next_section_start) +{ + uint16_t next_x_num_rects; + + next_x_num_rects = + get_num_rects_at_x_recout_align(x, dst_rects, num_input_streams, recout_width_alignment); + + if (next_x_num_rects != prev_section_num_streams) + *next_section_start = min(*next_section_start, x); +} + +// Pass in end x of the last section, and how many streams were in it. If start_x == combined_dst.x, +// calculate number of streams at start_x, then find run with that value +static uint32_t calculate_next_section_start(int32_t start_x, uint16_t prev_section_num_streams, + const struct vpe_rect *dst_rects, const struct vpe_rect *combined_dst, + uint16_t num_input_streams, uint32_t recout_width_alignment) +{ + int32_t next_section_start = combined_dst->x + combined_dst->width; + + // To find end of this section (i.e. next x value where we go from one/no streams to multiple, + // or vice versa) check left and right edge of every input rect, and set next_section_start to + // smallest x where num_streams(x) != prev_section_num_streams + for (int i = 0; i < num_input_streams; i++) { + if (recout_width_alignment == VPE_NO_ALIGNMENT) { + // If unaligned, we can just check the left and right edges of each stream + if (dst_rects[i].x > start_x) + check_num_rects_at_x_and_update_next_section_x(prev_section_num_streams, + dst_rects[i].x, dst_rects, num_input_streams, recout_width_alignment, + &next_section_start); + + if (dst_rects[i].x + (int32_t)dst_rects[i].width > start_x) + check_num_rects_at_x_and_update_next_section_x(prev_section_num_streams, + dst_rects[i].x + dst_rects[i].width, dst_rects, num_input_streams, + recout_width_alignment, &next_section_start); + } else { + // If aligned, we need to take the left and right edge of each stream, then check the + // closest aligned x value below, at, and above that edge + int32_t dst_x_floor = + recout_width_alignment * (dst_rects[i].x / recout_width_alignment); + int32_t dst_x_before = dst_x_floor - recout_width_alignment; + int32_t dst_x_ceil = dst_x_floor + recout_width_alignment; + int32_t dst_width_floor = + recout_width_alignment * + ((dst_rects[i].x + dst_rects[i].width) / recout_width_alignment); + int32_t dst_width_before = dst_width_floor - recout_width_alignment; + int32_t dst_width_ceil = dst_width_floor + recout_width_alignment; + + if (dst_x_floor > start_x) + check_num_rects_at_x_and_update_next_section_x(prev_section_num_streams, + dst_x_floor, dst_rects, num_input_streams, recout_width_alignment, + &next_section_start); + + if (dst_x_before > start_x) + check_num_rects_at_x_and_update_next_section_x(prev_section_num_streams, + dst_x_before, dst_rects, num_input_streams, recout_width_alignment, + &next_section_start); + + if (dst_x_ceil > start_x) + check_num_rects_at_x_and_update_next_section_x(prev_section_num_streams, dst_x_ceil, + dst_rects, num_input_streams, recout_width_alignment, &next_section_start); + + if (dst_width_floor > start_x) + check_num_rects_at_x_and_update_next_section_x(prev_section_num_streams, + dst_width_floor, dst_rects, num_input_streams, recout_width_alignment, + &next_section_start); + + if (dst_width_before > start_x) + check_num_rects_at_x_and_update_next_section_x(prev_section_num_streams, + dst_width_before, dst_rects, num_input_streams, recout_width_alignment, + &next_section_start); + + if (dst_width_ceil > start_x) + check_num_rects_at_x_and_update_next_section_x(prev_section_num_streams, + dst_width_ceil, dst_rects, num_input_streams, recout_width_alignment, + &next_section_start); + } + } + + return next_section_start; +} + +static uint32_t get_minimum_seg_size(bool prev_section, const uint32_t recout_width_alignment) +{ + return prev_section ? VPE_MIN_VIEWPORT_SIZE + : max(VPE_MIN_VIEWPORT_SIZE, recout_width_alignment); +} + +static uint32_t get_optimal_seg_size( + struct vpe_mps_section *section, uint32_t min_seg_size, uint32_t recout_width_alignment) +{ + uint32_t optimal_seg_size = 0; + if (section->num_streams < 2) + optimal_seg_size = max(OPTIMAL_MIN_PERFORMACE_MODE_SIZE, min_seg_size); + else + optimal_seg_size = min_seg_size; + + if (recout_width_alignment != VPE_NO_ALIGNMENT) + optimal_seg_size = + recout_width_alignment * int_divide_with_ceil(optimal_seg_size, recout_width_alignment); + + return optimal_seg_size; +} + +// for section[i], grab pixels from the sections to the right of it until it reaches the minimum seg +// size. If the section to the right is too small, merge the two together +static void get_pixels_from_right_sections(struct vpe_vector *section_vector, int i, + uint32_t minimum_seg_size, bool *rerun_optimization, const uint32_t recout_width_alignment) +{ + struct vpe_mps_section *section = vpe_vector_get(section_vector, i); + struct vpe_mps_section *next_section = vpe_vector_get(section_vector, i + 1); + + if (get_section_width(section) >= (int32_t)minimum_seg_size) + return; // already at minimum size (or larger + + // if section has more streams than next_section - next_section efficiency will decrease. take + // as few pixels as we can + uint32_t pixels_required = minimum_seg_size - get_section_width(section); + uint16_t num_sections_to_erase = 0; + + while (get_section_width(section) < (int32_t)minimum_seg_size && next_section != NULL) { + uint32_t next_section_width = get_section_width(next_section); + if (next_section->num_streams > section->num_streams) { + // if next section has more streams, we need to combine the two sections + section->num_streams = next_section->num_streams; + section->end_x = next_section->end_x; + + num_sections_to_erase++; + *rerun_optimization = true; + break; + } else { + // if next section is a higher-efficiency section (aka less streams) only take as many + // pixels as required + uint32_t minimum_next_section_size = + pixels_required + + get_minimum_seg_size((uint16_t)(i + 1 + num_sections_to_erase) == + (uint16_t)(section_vector->num_elements - 1), + recout_width_alignment); + if (next_section_width >= minimum_next_section_size) { + section->end_x += pixels_required; + next_section->start_x += pixels_required; + + if (next_section_width == pixels_required) { + num_sections_to_erase++; + } + break; + } else { + section->end_x = next_section->end_x; + pixels_required -= next_section_width; + num_sections_to_erase++; + next_section = vpe_vector_get(section_vector, i + 1 + num_sections_to_erase); + } + } + } + if (pixels_required != 0) + *rerun_optimization = true; + + vpe_vector_erase(section_vector, i + 1, num_sections_to_erase); +} + +// return number of sections removed, as caller will need to update its indexing variable +static uint16_t get_pixels_from_left_sections(struct vpe_vector *section_vector, int i, + uint32_t minimum_seg_size, const uint32_t recout_width_alignment) +{ + struct vpe_mps_section *section = vpe_vector_get(section_vector, i); + struct vpe_mps_section *prev_section = vpe_vector_get(section_vector, i - 1); + + uint16_t num_sections_to_erase = 0; + uint32_t pixels_required = minimum_seg_size - get_section_width(section); + + while ((get_section_width(section) < (int32_t)minimum_seg_size) && (prev_section != NULL)) { + uint32_t prev_section_width = prev_section->end_x - prev_section->start_x; + if (prev_section->num_streams > section->num_streams) { + // at this point just need to combine the two sections + section->num_streams = prev_section->num_streams; + section->start_x = prev_section->start_x; + num_sections_to_erase++; + break; + } else { + uint32_t minimum_prev_section_size_to_give_pixels = + pixels_required + get_minimum_seg_size(false, recout_width_alignment); + if (prev_section_width >= minimum_prev_section_size_to_give_pixels) { + section->start_x -= pixels_required; + prev_section->end_x -= pixels_required; + + if (prev_section_width == pixels_required) + num_sections_to_erase++; + break; + } else { + section->start_x = prev_section->start_x; + pixels_required -= prev_section_width; + num_sections_to_erase++; + prev_section = vpe_vector_get(section_vector, i - 1 - num_sections_to_erase); + } + } + } + vpe_vector_erase(section_vector, i - num_sections_to_erase, num_sections_to_erase); + return num_sections_to_erase; +} + +static void fill_mps_cmd_packet(struct vpe_priv *vpe_priv, struct vpe_mps_ctx *mps_ctx, + const struct vpe_rect *dst_rects, struct vpe_mps_command *command, int32_t seg_left_x, + int32_t seg_right_x, uint16_t num_input_streams) +{ + uint8_t inputs_added = 0; + + for (uint16_t i = 0; i < num_input_streams; i++) { + if (get_rect_width_in_range(&dst_rects[i], seg_left_x, seg_right_x) != 0) { + command->mps_idx[command->num_inputs] = (int16_t)i; + command->stream_idx[command->num_inputs] = mps_ctx->stream_idx[i]; + command->start_x[command->num_inputs] = seg_left_x; + command->end_x[command->num_inputs] = seg_right_x; + command->is_bg_gen[command->num_inputs] = false; + command->num_inputs++; + inputs_added++; + } + } + if (inputs_added == 0) { + command->mps_idx[command->num_inputs] = -1; + command->stream_idx[command->num_inputs] = 0; + command->start_x[command->num_inputs] = seg_left_x; + command->end_x[command->num_inputs] = seg_right_x; + command->is_bg_gen[command->num_inputs] = true; + command->num_inputs++; + } +} + +static uint16_t get_num_streams_in_segment(const struct vpe_rect *dst_rects, + uint16_t num_input_streams, int32_t seg_left_x, int32_t seg_right_x) +{ + uint16_t num_streams_in_segment = 0; + for (int i = 0; i < num_input_streams; i++) { + if (get_rect_width_in_range(&dst_rects[i], seg_left_x, seg_right_x) != 0) { + num_streams_in_segment++; + } + } + return num_streams_in_segment; +} + +static enum vpe_status align_seg_right_x( + int32_t seg_left_x, int32_t *seg_right_x, uint32_t recout_width_alignment) +{ + enum vpe_status status = VPE_STATUS_OK; + + if (recout_width_alignment != VPE_NO_ALIGNMENT) { + // use int division to floor seg_width to a multiple of required alignment width + uint32_t seg_width = *seg_right_x - seg_left_x; + uint32_t new_seg_width = recout_width_alignment * (seg_width / recout_width_alignment); + if (new_seg_width != seg_width) { + status = VPE_STATUS_REPEAT_ITEM; // If we need to adjust seg, re-check that all + // contraints are met again + *seg_right_x = seg_left_x + new_seg_width; + } + } + + return status; +} + +static enum vpe_status enforce_minimum_viewport_size_for_rect_in_section( + const struct vpe_rect *dst_rects, double *scaling_ratios, uint32_t recout_width_alignment, + struct vpe_vector *section_vector, uint16_t num_inputs) +{ + uint16_t i, section_idx; + int32_t dst_in_range; + int32_t src_in_range; + enum vpe_status status = VPE_STATUS_REPEAT_ITEM; + bool is_last_section; + + while (status == VPE_STATUS_REPEAT_ITEM) { + status = VPE_STATUS_OK; + for (section_idx = 0; section_idx < section_vector->num_elements; section_idx++) { + struct vpe_mps_section *section = vpe_vector_get(section_vector, section_idx); + struct vpe_mps_section *next_section = vpe_vector_get(section_vector, section_idx + 1); + + is_last_section = ((int16_t)section_idx == (int16_t)(section_vector->num_elements - 1)); + + for (i = 0; i < num_inputs; i++) { + dst_in_range = + get_rect_width_in_range(&dst_rects[i], section->start_x, section->end_x); + + if (dst_in_range == 0) + continue; + + src_in_range = (int32_t)((double)dst_in_range / scaling_ratios[i]); + + if (is_last_section) { + // Remove all of this stream from this segment if either src or dst rect too + // small + if ((dst_in_range < VPE_MIN_VIEWPORT_SIZE) || + (src_in_range < VPE_MIN_VIEWPORT_SIZE)) { + VPE_ASSERT(false); + status = VPE_STATUS_ERROR; // Error: we haven't left enough source rect + break; + } + } else { + bool left_edge_inside = + is_value_in_range(dst_rects[i].x, section->start_x, section->end_x); + bool right_edge_inside = + is_value_in_range(dst_rects[i].x + (int32_t)dst_rects[i].width, + section->start_x, section->end_x); + + // Remove all of this stream from this segment if either src or dst rect too + // small + if ((dst_in_range < VPE_MIN_VIEWPORT_SIZE) || + (src_in_range < VPE_MIN_VIEWPORT_SIZE)) { + status = VPE_STATUS_REPEAT_ITEM; + + if (right_edge_inside) { + continue; // rects that originate from the last section should be dealt + // with by that section + } + + if (!right_edge_inside) { + if (next_section->num_streams > section->num_streams) { + int32_t pixels_to_give = dst_in_range; + if (recout_width_alignment != VPE_NO_ALIGNMENT) { + pixels_to_give = + recout_width_alignment * + int_divide_with_ceil(dst_in_range, recout_width_alignment); + VPE_ASSERT(get_section_width(section) >= pixels_to_give); + } + + if (pixels_to_give == get_section_width(section)) { + next_section->start_x = section->start_x; + vpe_vector_erase(section_vector, section_idx, 1); + section_idx--; + } else { + section->end_x -= pixels_to_give; + next_section->start_x -= pixels_to_give; + } + } else { // this section has more streams than next one + int32_t pixels_required = max(VPE_MIN_VIEWPORT_SIZE - dst_in_range, + (int32_t)(scaling_ratios[i] * + (double)(VPE_MIN_VIEWPORT_SIZE - src_in_range))); + bool rerun_optimization = false; + if (recout_width_alignment != VPE_NO_ALIGNMENT) + pixels_required = recout_width_alignment * + int_divide_with_ceil( + pixels_required, recout_width_alignment); + + get_pixels_from_right_sections(section_vector, section_idx, + get_section_width(section) + pixels_required, + &rerun_optimization, recout_width_alignment); + } + } + } + + if (status != VPE_STATUS_ERROR && !right_edge_inside) { + // Now check how much remains for the next segment + dst_in_range = dst_rects[i].width + dst_rects[i].x - next_section->start_x; + src_in_range = (int32_t)((double)dst_in_range / scaling_ratios[i]); + + if ((dst_in_range < VPE_MIN_VIEWPORT_SIZE) || + (src_in_range < VPE_MIN_VIEWPORT_SIZE)) { + if (next_section->num_streams > section->num_streams) { + int32_t pixels_to_give = max(VPE_MIN_VIEWPORT_SIZE - dst_in_range, + (int32_t)(scaling_ratios[i] * + (double)(VPE_MIN_VIEWPORT_SIZE - src_in_range))); + if (recout_width_alignment != VPE_NO_ALIGNMENT) { + pixels_to_give = + recout_width_alignment * + int_divide_with_ceil(dst_in_range, recout_width_alignment); + VPE_ASSERT(get_section_width(section) >= pixels_to_give); + } + + if (pixels_to_give >= get_section_width(section)) { + next_section->start_x = section->start_x; + vpe_vector_erase(section_vector, section_idx, 1); + section_idx--; + } else { + section->end_x -= pixels_to_give; + next_section->start_x -= pixels_to_give; + } + } else { // this section has more streams than next one + uint32_t pixels_required = dst_in_range; + bool rerun_optimization = false; + if (recout_width_alignment != VPE_NO_ALIGNMENT) + pixels_required = recout_width_alignment * + int_divide_with_ceil( + pixels_required, recout_width_alignment); + + get_pixels_from_right_sections(section_vector, section_idx, + get_section_width(section) + pixels_required, + &rerun_optimization, recout_width_alignment); + } + } + } + } + } + } + } + + return status; +} + +static enum vpe_status enforce_minimum_viewport_size_for_rect_in_seg( + const struct vpe_rect *dst_rects, double *scaling_ratios, uint16_t i, int32_t seg_left_x, + int32_t *seg_right_x, uint32_t recout_width_alignment, bool is_last_seg) +{ + uint32_t dst_in_range = get_rect_width_in_range(&dst_rects[i], seg_left_x, *seg_right_x); + enum vpe_status status = VPE_STATUS_OK; + uint32_t src_in_range; + + if (dst_in_range == 0) + return status; + + src_in_range = (uint32_t)((double)dst_in_range / scaling_ratios[i]); + + if (is_last_seg) { + // Remove all of this stream from this segment if either src or dst rect too small + if (dst_in_range < VPE_MIN_VIEWPORT_SIZE || src_in_range < VPE_MIN_VIEWPORT_SIZE) { + VPE_ASSERT(false); + status = VPE_STATUS_ERROR; // Error: we haven't left enough source rect + } + } else { + bool left_edge_inside = is_value_in_range(dst_rects[i].x, seg_left_x, *seg_right_x); + bool right_edge_inside = is_value_in_range( + dst_rects[i].x + (int32_t)dst_rects[i].width, seg_left_x, *seg_right_x); + + // Remove all of this stream from this segment if either src or dst rect too small + if (dst_in_range < VPE_MIN_VIEWPORT_SIZE || src_in_range < VPE_MIN_VIEWPORT_SIZE) { + if (!left_edge_inside) { + VPE_ASSERT(false); + status = VPE_STATUS_ERROR; // If left edge not inside, we won't be able to remove + } + if (!right_edge_inside) { + if (recout_width_alignment == VPE_NO_ALIGNMENT) { + *seg_right_x -= dst_in_range; + } else { + *seg_right_x -= recout_width_alignment * + int_divide_with_ceil(dst_in_range, recout_width_alignment); + } + } else { + if (recout_width_alignment == VPE_NO_ALIGNMENT) { + *seg_right_x = dst_rects[i].x; + } else { + *seg_right_x = + dst_rects[i].x * (uint32_t)(dst_rects[i].x / recout_width_alignment); + } + } + if (status != VPE_STATUS_ERROR) + status = VPE_STATUS_REPEAT_ITEM; // If we need to adjust seg, re-check that all + // contraints are met again + } + + if (status != VPE_STATUS_ERROR && !right_edge_inside) { + // Now check how much remains for the next segment + dst_in_range = dst_rects[i].width + dst_rects[i].x - *seg_right_x; + src_in_range = (uint32_t)((double)dst_in_range / scaling_ratios[i]); + + if (dst_in_range < VPE_MIN_VIEWPORT_SIZE) { + *seg_right_x -= max(recout_width_alignment, (VPE_MIN_VIEWPORT_SIZE - dst_in_range)); + status = VPE_STATUS_REPEAT_ITEM; // If we need to adjust seg, re-check that all + // contraints are met again + } else if (src_in_range < VPE_MIN_VIEWPORT_SIZE) { + *seg_right_x -= max(recout_width_alignment, + (uint32_t)((double)(VPE_MIN_VIEWPORT_SIZE - src_in_range) * scaling_ratios[i])); + status = VPE_STATUS_REPEAT_ITEM; // If we need to adjust seg, re-check that all + // contraints are met again + } + } + } + + return status; +} + +static enum vpe_status limit_stream_count_in_seg_to_section_num_streams( + struct vpe_mps_section *section, const struct vpe_rect *dst_rects, int32_t seg_left_x, + int32_t *seg_right_x, uint16_t num_input_streams) +{ + int16_t stream_to_remove = -1; + int32_t remove_stream_start_x = 0; + enum vpe_status status = VPE_STATUS_OK; + + while (get_num_streams_in_segment(dst_rects, num_input_streams, seg_left_x, *seg_right_x) > + section->num_streams) { + status = VPE_STATUS_REPEAT_ITEM; + for (int16_t i = 0; i < num_input_streams; i++) { + if (get_rect_width_in_range(&dst_rects[i], seg_left_x, *seg_right_x) != 0) { + if (stream_to_remove == -1) { + stream_to_remove = i; + remove_stream_start_x = dst_rects[i].x; + } else if (dst_rects[i].x > remove_stream_start_x) { + stream_to_remove = i; + remove_stream_start_x = dst_rects[i].x; + } + } + } + + if (stream_to_remove == -1 || dst_rects[stream_to_remove].x <= seg_left_x || + dst_rects[stream_to_remove].x >= *seg_right_x) { + VPE_ASSERT(false); + status = VPE_STATUS_ERROR; + break; + } + *seg_right_x = dst_rects[stream_to_remove].x; + } + + return status; +} + +// See if current segment can be added to the last command, or if a new command is required +static bool mps_is_new_command_required(struct vpe_priv *vpe_priv, struct vpe_mps_ctx *mps_ctx, + struct vpe_mps_section *section, const struct vpe_rect *dst_rects, int32_t seg_left_x, + int32_t seg_right_x, uint16_t num_input_streams) +{ + // FROD limits the number of backends and blending requires all frontends to be in sync + bool create_new_command = + ((section->num_streams > 1) || (section->command_vector->num_elements == 0) || + vpe_priv->output_ctx.frod_param.enable_frod); + if (!create_new_command) { + // Check if this segment can be added to the last command + struct vpe_mps_command *last_command = + vpe_vector_get(section->command_vector, section->command_vector->num_elements - 1); + uint16_t lut3d_count = 0; + + if (last_command->num_inputs >= vpe_priv->pub.caps->resource_caps.num_dpp) + create_new_command = true; + + for (int i = 0; i < num_input_streams; i++) + if (get_rect_width_in_range(&dst_rects[i], seg_left_x, seg_right_x) != 0) { + if ((vpe_priv->stream_ctx[mps_ctx->stream_idx[i]].stream.tm_params.enable_3dlut) || + (vpe_priv->stream_ctx[mps_ctx->stream_idx[i]].stream.tm_params.UID != 0)) { + lut3d_count++; + } + } + + for (int i = 0; i < last_command->num_inputs; i++) { + if (last_command->is_bg_gen[i] == false) { + if ((vpe_priv->stream_ctx[last_command->stream_idx[i]] + .stream.tm_params.enable_3dlut) || + (vpe_priv->stream_ctx[last_command->stream_idx[i]].stream.tm_params.UID != 0)) { + lut3d_count++; + } + } + } + + if (lut3d_count > vpe_priv->pub.caps->resource_caps.num_mpc_3dlut) { + create_new_command = true; + } + } + + return create_new_command; +} + +static enum vpe_status mps_segmentation_algo(struct vpe_priv *vpe_priv, struct vpe_mps_ctx *mps_ctx, + struct vpe_mps_input *input_params, uint32_t *max_dst_width_per_stream, double *scaling_ratios, + struct vpe_mps_section *section) +{ + struct vpe_rect dst_rects[MAX_INPUT_PIPE]; + + for (int i = 0; i < mps_ctx->num_streams; i++) + dst_rects[i] = input_params->mps_stream_ctx[i].dst_rect; + + // command_vector should be null because we need to clear the section_vector before we start + if (section->command_vector == NULL) + section->command_vector = vpe_vector_create(vpe_priv, sizeof(struct vpe_mps_command), 2); + + int32_t seg_left_x = section->start_x; + int32_t seg_right_x; + + while (seg_left_x < section->end_x) { + // Start by setting seg to maximum width + seg_right_x = min(seg_left_x + (int32_t)input_params->max_seg_width, section->end_x); + + // Limit total seg width to keep src rects within max seg width - can happen w/ downscaling + for (int i = 0; i < input_params->num_inputs; i++) { + seg_right_x = change_right_seg_edge_to_limit_dst_rect_width( + &dst_rects[i], seg_left_x, seg_right_x, max_dst_width_per_stream[i]); + } + + // Determine if alignment is required for segment width and adjust + bool adjustment_required; + do { + adjustment_required = false; + + for (uint16_t i = 0; i < input_params->num_inputs; i++) { + bool is_last_seg = (seg_right_x == section->end_x); + if (!is_last_seg) + if (align_seg_right_x(seg_left_x, &seg_right_x, + input_params->recout_width_alignment) == VPE_STATUS_REPEAT_ITEM) + adjustment_required = true; + + // We need to ensure that there's enough dst/src rect in the current segment and + // enough left for the next one If not, cut off some more from this segment to + // remove some from this one/add some to the next one + if (enforce_minimum_viewport_size_for_rect_in_seg(dst_rects, scaling_ratios, i, + seg_left_x, &seg_right_x, input_params->recout_width_alignment, + is_last_seg) == VPE_STATUS_REPEAT_ITEM) + adjustment_required = true; + } + + // Need to make sure each segment has as many stream as this section allows to correctly + // build command ex. if we have a section with 2 stream that don't overlap, then its a 1 + // stream section (i.e. performance mode section) + // in this case we need to limit this section to only contain 1 stream + if (limit_stream_count_in_seg_to_section_num_streams(section, dst_rects, seg_left_x, + &seg_right_x, input_params->num_inputs) == VPE_STATUS_REPEAT_ITEM) + adjustment_required = true; + } while (adjustment_required); + + // When blending we need every segment to be a new command + // When not blending, we can combine segments into one command (perf mode style) if no HW + // limitations + bool create_new_command = mps_is_new_command_required(vpe_priv, mps_ctx, section, dst_rects, + seg_left_x, seg_right_x, input_params->num_inputs); + + if (create_new_command) { + struct vpe_mps_command new_command = {0}; + fill_mps_cmd_packet(vpe_priv, mps_ctx, dst_rects, &new_command, seg_left_x, seg_right_x, + input_params->num_inputs); + vpe_vector_push(section->command_vector, &new_command); + } else { + struct vpe_mps_command *last_command = + vpe_vector_get(section->command_vector, section->command_vector->num_elements - 1); + fill_mps_cmd_packet(vpe_priv, mps_ctx, dst_rects, last_command, seg_left_x, seg_right_x, + input_params->num_inputs); + } + + // Update how many segments each stream has. + // Segment width is calculated later after some further optimizations + for (int i = 0; i < input_params->num_inputs; i++) { + uint32_t width_in_seg = get_rect_width_in_range(&dst_rects[i], seg_left_x, seg_right_x); + if (width_in_seg != 0) { + mps_ctx->segment_count[i]++; + } + } + seg_left_x = seg_right_x; + } + return VPE_STATUS_OK; +} + +static enum vpe_status mps_create_initial_sections(const struct vpe_rect *dst_rects, + const struct vpe_rect *combined_dst, uint16_t num_input_streams, + uint32_t recout_width_alignment, struct vpe_vector *section_vector) +{ + // Move left to right across combined dst rect, split into areas of zero/single segs or multi + // segs, then call correct seg algo on them + int32_t section_start_x = combined_dst->x; + int32_t section_end_x; + int16_t num_stream_in_current_section; + + while (section_start_x < combined_dst->x + (int32_t)combined_dst->width) { + num_stream_in_current_section = get_num_rects_at_x_recout_align( + section_start_x, dst_rects, num_input_streams, recout_width_alignment); + section_end_x = calculate_next_section_start(section_start_x, num_stream_in_current_section, + dst_rects, combined_dst, num_input_streams, recout_width_alignment); + + if (section_end_x - section_start_x <= 0) { // Sanity check + VPE_ASSERT(false); + return VPE_STATUS_ERROR; + } + + struct vpe_mps_section new_section = {0}; + new_section.start_x = section_start_x; + new_section.end_x = section_end_x; + new_section.num_streams = num_stream_in_current_section; + + if (section_vector->capacity > section_vector->num_elements) { + struct vpe_mps_section *preexisting_section = + vpe_vector_get(section_vector, section_vector->num_elements); + if (preexisting_section != NULL) + if (preexisting_section->command_vector != NULL) + new_section.command_vector = preexisting_section->command_vector; + } + + vpe_vector_push(section_vector, &new_section); + + section_start_x = section_end_x; + } + + return VPE_STATUS_OK; +} + +static enum vpe_status mps_check_empty(struct vpe_vector *section_vector) +{ + for (int i = 0; i < (int)(section_vector->num_elements - 1); i++) { + struct vpe_mps_section *section = vpe_vector_get(section_vector, i); + + if (section->start_x >= section->end_x) { + // vpe_vector_erase(section_vector, i, 1); + // i--; + VPE_ASSERT(false); // This shouldn't happen, means something went wrong earlier + return VPE_STATUS_ERROR; + } + } + + return VPE_STATUS_OK; +} + +// The point of this function is essentially to combine sections that are handled the same +// i.e. combine background only sections and 1 stream sections, as both are segmented the same way +// (performance mode style) +static enum vpe_status mps_combine_single_zero_stream_sections(struct vpe_vector *section_vector) +{ + bool rerun_optimization = false; + + for (int i = 0; i < (int)(section_vector->num_elements - 1); i++) { + struct vpe_mps_section *section = vpe_vector_get(section_vector, i); + struct vpe_mps_section *next_section = vpe_vector_get(section_vector, i + 1); + + // < 2 to combine 1 stream and 0 stream sections + if (section->num_streams < 2 && next_section->num_streams < 2) { + section->end_x = next_section->end_x; + section->num_streams = max(section->num_streams, next_section->num_streams); + vpe_vector_erase(section_vector, i + 1, 1); + + i--; // re-run check on this section, as this one and next one will have changed. + } + } + + return VPE_STATUS_OK; +} + +static enum vpe_status mps_merge_sections_under_optimal_size(struct vpe_vector *section_vector, + uint32_t max_seg_width, const uint32_t recout_width_alignment) +{ + bool rerun_optimization = false; + + for (uint16_t i = 0; i < (uint16_t)section_vector->num_elements; i++) { + struct vpe_mps_section *section = vpe_vector_get(section_vector, i); + + uint32_t width = get_section_width(section); + uint32_t minimum_seg_size = + get_minimum_seg_size(i == (section_vector->num_elements - 1), recout_width_alignment); + uint32_t optimal_seg_size = + get_optimal_seg_size(section, minimum_seg_size, recout_width_alignment); + + if (width < optimal_seg_size) { + struct vpe_mps_section *next_section = vpe_vector_get(section_vector, i + 1); + struct vpe_mps_section *prev_section = vpe_vector_get(section_vector, i - 1); + + if (width < minimum_seg_size) + rerun_optimization = true; + + if (next_section == NULL && prev_section == NULL) { + if (width < minimum_seg_size) { + VPE_ASSERT(false); + return VPE_STATUS_ERROR; + } else { + break; + } + } else if (prev_section == NULL) { // first section + if (next_section->num_streams >= section->num_streams) { + section->end_x = next_section->end_x; + section->num_streams = next_section->num_streams; + + vpe_vector_erase(section_vector, i + 1, 1); + } else { + uint32_t pixels_required = optimal_seg_size - width; + uint32_t minimum_next_section_size = get_minimum_seg_size( + (uint16_t)(i + 1) == (uint16_t)(section_vector->num_elements - 1), + recout_width_alignment); + uint32_t optimal_next_section_size = get_optimal_seg_size( + next_section, minimum_next_section_size, recout_width_alignment); + + if ((uint32_t)get_section_width(next_section) > + optimal_next_section_size + pixels_required) + get_pixels_from_right_sections(section_vector, i, optimal_seg_size, + &rerun_optimization, recout_width_alignment); + else if (width < minimum_seg_size) + get_pixels_from_right_sections(section_vector, i, minimum_seg_size, + &rerun_optimization, recout_width_alignment); + } + } else if (next_section == NULL) { + if (prev_section->num_streams >= section->num_streams) { + prev_section->end_x = section->end_x; + prev_section->num_streams = + max(section->num_streams, prev_section->num_streams); + + vpe_vector_erase(section_vector, i, 1); + i--; // If we erase a previous vector, need to update i to match the new + // indexing. + } else { + // if section has more streams than prev_section - prev_section efficiency will + // decrease. take as few pixels as we can + uint32_t pixels_required = optimal_seg_size - width; + uint32_t optimal_prev_section_size = get_optimal_seg_size(prev_section, + get_minimum_seg_size(false, recout_width_alignment), + recout_width_alignment); + + if ((uint32_t)get_section_width(prev_section) > + optimal_prev_section_size + pixels_required) { + rerun_optimization = true; + i -= get_pixels_from_left_sections( + section_vector, i, optimal_seg_size, recout_width_alignment); + } else if (width < minimum_seg_size) { + rerun_optimization = true; + i -= get_pixels_from_left_sections( + section_vector, i, minimum_seg_size, recout_width_alignment); + } else { + continue; // if section is under opt seg size but last section can't handle + // it, just skip + } + } + + } else { + // Merge this section with whichever nearby section has more (or most, if + // impossible) streams + if (prev_section->num_streams == next_section->num_streams || + (prev_section->num_streams < 2 && next_section->num_streams < 2)) { + if (prev_section->num_streams > section->num_streams) { + prev_section->end_x = next_section->end_x; + prev_section->num_streams = + max(prev_section->num_streams, next_section->num_streams); + + vpe_vector_erase(section_vector, i, 2); + i--; + } else { + // Attempt to grab pixels from the next sections. If there's not enough, + // consume all, and let this optimization section re-run, using the + // prev_section algo next time. + + uint32_t pixels_required = optimal_seg_size - width; + uint32_t optimal_next_section_size = get_optimal_seg_size(next_section, + get_minimum_seg_size((i + 1) == (int)(section_vector->num_elements - 1), + recout_width_alignment), + recout_width_alignment); + + if ((uint32_t)get_section_width(next_section) > + optimal_next_section_size + pixels_required) + get_pixels_from_right_sections(section_vector, i, optimal_seg_size, + &rerun_optimization, recout_width_alignment); + else if (width < minimum_seg_size) + get_pixels_from_right_sections(section_vector, i, minimum_seg_size, + &rerun_optimization, recout_width_alignment); + } + } else { + // This shouldn't happen, as we should've merged sections with the same number + // of streams (or 0 and 1) earlier This will change with 3 pipe support + VPE_ASSERT(false); + return VPE_STATUS_ERROR; + } + } + } + } + + return rerun_optimization ? VPE_STATUS_REPEAT_ITEM : VPE_STATUS_OK; +} + +static enum vpe_status mps_align_sections( + struct vpe_vector *section_vector, const uint32_t recout_width_alignment) +{ + bool rerun_optimization = false; + + if (recout_width_alignment != VPE_NO_ALIGNMENT) { + // num_elements-1 because last section doesn't need to be aligned + for (int i = 0; i < (int)(section_vector->num_elements - 1); i++) { + struct vpe_mps_section *section = vpe_vector_get(section_vector, i); + uint32_t width = get_section_width(section); + + if ((width % recout_width_alignment) != 0) { + struct vpe_mps_section *next_section = vpe_vector_get(section_vector, i + 1); + VPE_ASSERT(next_section->num_streams != section->num_streams); // Sanity check + + // Whichever section has more streams in it will 'take' pixels from the other + // segment Need to do this as a section with 1 stream can be incorporated into the 2 + // stream algo, but reverse is not true (cannot run perf mode segmentation on + // multi-stream section) + if (next_section->num_streams > section->num_streams) { + next_section->start_x -= (width % recout_width_alignment); + section->end_x -= (width % recout_width_alignment); + + if (get_section_width(section) <= 0) { + VPE_ASSERT(get_section_width(section) == 0); // Sanity check + vpe_vector_erase(section_vector, i, 1); + i--; + rerun_optimization = true; + } + } else { + int32_t pixels_required = + recout_width_alignment - (width % recout_width_alignment); + + // edge case for 2nd last section - if final section doesnt have enough, just + // merge the two + if (i == (int)(section_vector->num_elements - 2)) { + // for 2nd last section, next section == final_section + if (get_section_width(next_section) < pixels_required) + pixels_required = get_section_width(next_section); + } + + next_section->start_x += pixels_required; + section->end_x += pixels_required; + + if (get_section_width(next_section) <= 0) { + VPE_ASSERT(get_section_width(next_section) == 0); // Sanity check + vpe_vector_erase(section_vector, i + 1, 1); + rerun_optimization = true; + } + } + } + } + } + + return rerun_optimization ? VPE_STATUS_REPEAT_ITEM : VPE_STATUS_OK; +} + +static struct vpe_rect get_combined_dst_rect( + const struct vpe_rect *dst_rect, uint16_t num_input_streams) +{ + if (num_input_streams < 2) { + VPE_ASSERT(false); + return (struct vpe_rect){0}; + } + + struct vpe_rect new_rect = dst_rect[0]; + + for (int i = 1; i < num_input_streams; i++) { + new_rect.x = min(new_rect.x, dst_rect[i].x); + new_rect.y = min(new_rect.y, dst_rect[i].y); + new_rect.width = + max(new_rect.x + new_rect.width, dst_rect[i].x + dst_rect[i].width) - new_rect.x; + new_rect.height = + max(new_rect.y + new_rect.height, dst_rect[i].y + dst_rect[i].height) - new_rect.y; + } + + return new_rect; +} + +// find the furthest left x coordinate we can include +static int32_t get_leftmost_legal_x(struct vpe_mps_ctx *mps_ctx, const struct vpe_rect *dst_rects, + struct vpe_mps_command *cmd, uint16_t input_idx, uint32_t recout_alignment) +{ + // if we're in the first input, we can't take any more pixels from the left + // it should never happen + if (input_idx == 0) { + ASSERT(false); + return cmd->start_x[0]; + } + + int32_t leftmost_legal_x = cmd->start_x[max(1, input_idx) - 1]; + int32_t next_leftmost_legal_x = leftmost_legal_x; // used if input has no stream ex. bg gen + + // step 1: check if we are limited by any other streams (only 1 stream per input) + for (int i = 0; i < mps_ctx->num_streams; i++) { + if ((mps_ctx->stream_idx[i] == cmd->stream_idx[input_idx]) && + (cmd->mps_idx[input_idx] != -1)) { + continue; // if stream is already part of this input, its not an issue + } + + if (dst_rects[i].x < cmd->start_x[input_idx]) { + if (dst_rects[i].x + (int32_t)dst_rects[i].width > leftmost_legal_x) { + next_leftmost_legal_x = leftmost_legal_x; + leftmost_legal_x = dst_rects[i].x + dst_rects[i].width; + } + } + } + + if (cmd->is_bg_gen[input_idx]) + leftmost_legal_x = next_leftmost_legal_x; + + leftmost_legal_x = max(leftmost_legal_x, cmd->start_x[0]); + + if (leftmost_legal_x < cmd->start_x[input_idx - 1]) + leftmost_legal_x = cmd->start_x[input_idx - 1]; + + if (recout_alignment != VPE_NO_ALIGNMENT) + leftmost_legal_x = + recout_alignment * ((leftmost_legal_x + recout_alignment - 1) / recout_alignment); + + // step 2: check if taking this many pixels would cause issues in the last input (rect too + // small) + if (cmd->is_bg_gen[input_idx - 1] == false) { + for (int i = 0; i < mps_ctx->num_streams; i++) { + if (mps_ctx->stream_idx[i] != cmd->stream_idx[input_idx - 1]) + continue; + + uint32_t rect_width_in_range = get_rect_width_in_range( + &dst_rects[i], cmd->start_x[input_idx - 1], leftmost_legal_x); + if (rect_width_in_range < VPE_MIN_VIEWPORT_SIZE) { + if (recout_alignment == VPE_NO_ALIGNMENT) + leftmost_legal_x += VPE_MIN_VIEWPORT_SIZE - rect_width_in_range; + else + leftmost_legal_x += recout_alignment; + + rect_width_in_range = get_rect_width_in_range( + &dst_rects[i], cmd->start_x[input_idx - 1], leftmost_legal_x); + if (rect_width_in_range < VPE_MIN_VIEWPORT_SIZE) { + VPE_ASSERT(false); // this should never happen + return cmd->start_x[input_idx]; + } + } + break; + } + } + + return leftmost_legal_x; +} + +static uint16_t max_num_pipes_for_perf_mode(struct vpe_priv *vpe_priv, struct vpe_mps_command *cmd) +{ + uint16_t available_pipes = (uint16_t)vpe_priv->pub.caps->resource_caps.num_dpp; + + if (vpe_priv->output_ctx.frod_param.enable_frod) + available_pipes = 1; + + if (vpe_priv->stream_ctx[cmd->stream_idx[0]].stream.tm_params.enable_3dlut) { + uint16_t num_3dlut = (uint16_t)min(0xFFFF, vpe_priv->pub.caps->resource_caps.num_mpc_3dlut); + + available_pipes = + min((uint16_t)vpe_priv->pub.caps->resource_caps.num_mpc_3dlut, available_pipes); + } + + return available_pipes; +} + +// try to even out the width of the segments in this command +// only valid for 0/1 stream sections +static void get_pixels_from_previous_input(struct vpe_mps_ctx *mps_ctx, + const struct vpe_rect *dst_rects, struct vpe_mps_command *cmd, uint16_t input_idx, + int32_t pixels_requested, bool *rerun_optimization, uint32_t recout_alignment) +{ + if (input_idx < 1 || input_idx >= cmd->num_inputs) { + VPE_ASSERT(false); + return; + } + + // check that the region we're planning on grabbing pixels from is continuous with this one + if (cmd->start_x[input_idx] != cmd->end_x[input_idx - 1]) + return; + + int32_t ideal_new_x = cmd->start_x[input_idx] - pixels_requested; + int32_t leftmost_legal_x = + get_leftmost_legal_x(mps_ctx, dst_rects, cmd, input_idx, recout_alignment); + int32_t new_x = cmd->start_x[input_idx]; + + if (recout_alignment != VPE_NO_ALIGNMENT) + ideal_new_x = recout_alignment * ((ideal_new_x + recout_alignment - 1) / recout_alignment); + + if (leftmost_legal_x >= cmd->start_x[input_idx] || ideal_new_x >= cmd->start_x[input_idx]) { + if (leftmost_legal_x > cmd->start_x[input_idx] || ideal_new_x > cmd->start_x[input_idx]) + VPE_ASSERT(false); // this should never happen + + return; + } + + new_x = max(ideal_new_x, leftmost_legal_x); + + cmd->start_x[input_idx] = new_x; + cmd->end_x[input_idx - 1] = new_x; +} + +static void divide_single_stream_cmd_perf_mode_style(struct vpe_priv *vpe_priv, + struct vpe_mps_ctx *mps_ctx, struct vpe_mps_command *cmd, uint32_t recout_alignment, + const struct vpe_rect *dst_rects) +{ + if (cmd->num_inputs == 0) { + ASSERT(false); + return; + } + + uint16_t max_pipes = max_num_pipes_for_perf_mode(vpe_priv, cmd); + int32_t end_x = cmd->end_x[cmd->num_inputs - 1]; + + if (max_pipes < 2) + return; + + if (end_x - cmd->start_x[0] > OPTIMAL_MIN_PERFORMACE_MODE_SIZE) { + // Make this section run 'performance mode' style. + // Will need to adjust with multi-section single-command optimization + // (ex. can this extra pipe be better used to render a stream from another section?) + + int32_t ideal_size = (end_x - cmd->start_x[0]) / max_pipes; + uint16_t new_stream_idx = cmd->stream_idx[0]; + int16_t mps_stream_idx = cmd->mps_idx[0]; + + int16_t input_idx; + + int32_t extra_pixels = 0; + // after evenly distributing the largest amount of pixels to each input as + // possible (while remaining in multiples of recout_alignment, if using alignment) + + // ex if recout_align = 2, MAX_PIPE = 3, and cmd_width = 28, distribute evenly among pipes + // ideal_size = 8, pipe width = (8, 8, 8) + 4 remaining. extra_pixels_post_alignment = 4 + + // we then take the amount remaining in extra_pixels and distribute round robin style in + // multiples of recout_align so pipe width = (8, 8, 8) + 4 extra -> (10, 8, 8) + 2 extra -> + // (10, 10, 8) + + // for non-aligned cases add 1 ex. MAX_PIPE = 3, and cmd_width = 14 => ideal size = 14/3 = 4 + // distribute evenly among pipes pipe width = (4, 4, 4) + 2 extra => (5, 5, 4) + + VPE_ASSERT(ideal_size != 0); // sanity check incase above if statement changes + + if (recout_alignment != VPE_NO_ALIGNMENT) + ideal_size = recout_alignment * (ideal_size / recout_alignment); + + extra_pixels = (end_x - cmd->start_x[0]) - (ideal_size * max_pipes); + + if (mps_stream_idx >= 0) + mps_ctx->segment_count[mps_stream_idx] += (max_pipes - cmd->num_inputs); + + for (input_idx = 0; input_idx < max_pipes; input_idx++) { + if (input_idx != 0) + cmd->start_x[input_idx] = cmd->end_x[input_idx - 1]; + + cmd->end_x[input_idx] = cmd->start_x[input_idx] + ideal_size; + + if (extra_pixels > 0) { + if (recout_alignment == VPE_NO_ALIGNMENT) { + cmd->end_x[input_idx]++; + extra_pixels--; + } else { + cmd->end_x[input_idx] += recout_alignment; + extra_pixels -= recout_alignment; + } + } + + if (input_idx == max_pipes - 1) + VPE_ASSERT(end_x == cmd->end_x[input_idx]); // sanity check, should be same + + if (mps_stream_idx >= 0) { + if (get_rect_width_in_range(&dst_rects[mps_stream_idx], cmd->start_x[input_idx], + cmd->end_x[input_idx]) > 0) { + cmd->stream_idx[input_idx] = new_stream_idx; + cmd->mps_idx[input_idx] = mps_stream_idx; + } else { + cmd->stream_idx[input_idx] = 0; + cmd->is_bg_gen[input_idx] = true; + cmd->mps_idx[input_idx] = -1; + mps_ctx->segment_count[mps_stream_idx]--; + } + } else { + // Need this else case as most inputs will not be initialized yet + cmd->stream_idx[input_idx] = 0; + cmd->is_bg_gen[input_idx] = true; + cmd->mps_idx[input_idx] = -1; + } + } + + cmd->num_inputs = max_pipes; + } +} + +// Attempt to even out width of segments in a command +static void even_out_segment_widths_in_cmd(struct vpe_mps_ctx *mps_ctx, struct vpe_mps_command *cmd, + const struct vpe_rect *dst_rects, uint32_t recout_alignment) +{ + int32_t cmd_start_x = 0; + int32_t cmd_end_x = 0; + uint16_t input_idx; + + for (input_idx = 0; input_idx < cmd->num_inputs; input_idx++) { + if (input_idx == 0 || cmd->start_x[input_idx] < cmd_start_x) + cmd_start_x = cmd->start_x[input_idx]; + + if (input_idx == 0 || cmd->end_x[input_idx] > cmd_end_x) + cmd_end_x = cmd->end_x[input_idx]; + + // all segs need to be next to each other to be able to transfer pixels between them + if (input_idx != 0) + if ((cmd->end_x[input_idx - 1] != cmd->start_x[input_idx]) && + (cmd->end_x[input_idx] != cmd->start_x[input_idx - 1])) + return; + } + + int32_t ideal_seg_width = (cmd_end_x - cmd_start_x) / cmd->num_inputs; + int32_t pixels_requested; + bool run_optimization; + + // Sanity check: make sure cmd is valid + if ((cmd->num_inputs > MAX_INPUT_PIPE) || (cmd->num_inputs < 2)) { + VPE_ASSERT(false); + return; + } + + do { + run_optimization = false; + + for (input_idx = cmd->num_inputs - 1; input_idx > 0; input_idx--) { + // leftmost segs are already max size, so can't modify starting from there + // rightmost seg will be unoptimized (likely too small), so start there and work + // back + pixels_requested = ideal_seg_width - (cmd->end_x[input_idx] - cmd->start_x[input_idx]); + + if (pixels_requested > 8) + // we need to gain or lose some pixels from this input. to avoid overadjustment, + // don't adjust if an insignificant of adjustment is required + get_pixels_from_previous_input(mps_ctx, dst_rects, cmd, input_idx, pixels_requested, + &run_optimization, recout_alignment); + } + } while (run_optimization); +} + +// Check if there are empty inputs available for this command that can be used +static bool is_perf_mode_possible(struct vpe_priv *vpe_priv, struct vpe_mps_command *cmd) +{ + // First check if there are any free inputs + if (cmd->num_inputs >= vpe_priv->pub.caps->resource_caps.num_dpp) { + return false; + } + + // Next check that all inputs are the same stream + for (uint16_t i = 1; (i < cmd->num_inputs) && (i < MAX_INPUT_PIPE); i++) { + if ((cmd->stream_idx[i] != cmd->stream_idx[0]) && (cmd->is_bg_gen[i] == false)) { + return false; + } + } + + return true; +} + +// Attempt to even out width of segments in each command a section +// This is to improve efficiency of cmd by balancing/maximizing pipe usage +static void optimize_segments_in_section(struct vpe_priv *vpe_priv, struct vpe_mps_ctx *mps_ctx, + struct vpe_mps_section *section, const struct vpe_rect *dst_rects, uint32_t recout_alignment) +{ + if (section->num_streams < 2) { + int16_t cmd_idx; + for (cmd_idx = 0; cmd_idx < (uint16_t)(section->command_vector->num_elements); cmd_idx++) { + struct vpe_mps_command *cmd = vpe_vector_get(section->command_vector, cmd_idx); + + // NOTE: this will need to be adjusted with multi-section single-command optimization + if (is_perf_mode_possible(vpe_priv, cmd)) { + divide_single_stream_cmd_perf_mode_style( + vpe_priv, mps_ctx, cmd, recout_alignment, dst_rects); + } else { + // if command has multiple inputs (all from one stream + bg), attempt to even out + // the width of the segments + even_out_segment_widths_in_cmd(mps_ctx, cmd, dst_rects, recout_alignment); + } + } + } +} + +static enum vpe_status calculate_segment_widths( + struct vpe_mps_ctx *mps_ctx, const struct vpe_rect *dst_rects) +{ + // track seg_idx for each command. We already have total number of segs for each stream, + // but need a separate variable to count up from 0 to TOTAL_NUM_SEG + uint16_t stream_segment_idx[MAX_INPUT_PIPE] = {0}; + + uint16_t section_idx, cmd_idx, input_idx; + for (section_idx = 0; section_idx < (uint16_t)mps_ctx->section_vector->num_elements; + section_idx++) { + struct vpe_mps_section *section = vpe_vector_get(mps_ctx->section_vector, section_idx); + + for (cmd_idx = 0; cmd_idx < (uint16_t)section->command_vector->num_elements; cmd_idx++) { + struct vpe_mps_command *cmd = vpe_vector_get(section->command_vector, cmd_idx); + + for (input_idx = 0; input_idx < cmd->num_inputs; input_idx++) { + uint16_t mps_idx = cmd->mps_idx[input_idx]; + if (cmd->is_bg_gen[input_idx] == false) { + uint32_t width = get_rect_width_in_range( + &dst_rects[mps_idx], cmd->start_x[input_idx], cmd->end_x[input_idx]); + + if (width == 0) { + VPE_ASSERT(false); + return VPE_STATUS_ERROR; + } + + cmd->seg_idx[input_idx] = stream_segment_idx[mps_idx]++; + vpe_vector_push(mps_ctx->segment_widths[mps_idx], &width); + } + } + } + } + + for (int i = 0; i < mps_ctx->num_streams; i++) { + // make sure we've been correctly tracking number of segments so far + if (mps_ctx->segment_count[i] != mps_ctx->segment_widths[i]->num_elements) { + VPE_ASSERT(false); + return VPE_STATUS_ERROR; + } + } + + return VPE_STATUS_OK; +} + +// mps dst_viewports need to cover total area covered, i.e. stream + background +// adjust recout and dst_viewport to do so (even required for non-bg gen streams, as blending MPCCs +// need to match) +static void mps_calculate_dst_viewport_and_active(struct stream_ctx *stream_ctx, + struct scaler_data *scaler_data, struct vpe_rect *target_rect, int32_t seg_start_x, + int32_t seg_end_x, struct spl_opp_adjust *opp_recout_adjust) +{ + struct vpe_priv *vpe_priv = stream_ctx->vpe_priv; + + int32_t stream_start_x = stream_ctx->stream.scaling_info.dst_rect.x; + int32_t stream_end_x = + stream_ctx->stream.scaling_info.dst_rect.x + stream_ctx->stream.scaling_info.dst_rect.width; + + scaler_data->recout.x = (seg_start_x >= stream_start_x) ? 0 : (stream_start_x - seg_start_x); + scaler_data->recout.y = (target_rect->y >= stream_ctx->stream.scaling_info.dst_rect.y) + ? 0 + : (stream_ctx->stream.scaling_info.dst_rect.y - target_rect->y); + scaler_data->dst_viewport.x = seg_start_x; + scaler_data->dst_viewport.width = seg_end_x - seg_start_x; + scaler_data->dst_viewport.y = target_rect->y; + scaler_data->dst_viewport.height = target_rect->height; + + vpe20_update_recout_dst_viewport(scaler_data, vpe_priv->output_ctx.surface.format, + opp_recout_adjust, (vpe_priv->init.debug.opp_background_gen == 1)); +} + +static void fill_background_cmd_info_input(struct vpe_priv *vpe_priv, struct vpe_rect *viewport, + struct vpe_cmd_info *cmd_info, uint16_t input_idx) +{ + uint16_t bg_index = vpe_priv->resource.get_bg_stream_idx(vpe_priv); + struct scaler_data *scaler_data = &(cmd_info->inputs[input_idx].scaler_data); + struct stream_ctx *stream_ctx = &(vpe_priv->stream_ctx[bg_index]); + + vpe20_fill_bg_cmd_scaler_data(stream_ctx, viewport, scaler_data); + + // background takes stream_idx 0 as its input + cmd_info->inputs[input_idx].stream_idx = 0; + + cmd_info->outputs[input_idx].dst_viewport = scaler_data->dst_viewport; + cmd_info->outputs[input_idx].dst_viewport_c = scaler_data->dst_viewport_c; +} + +// generate cmd_info for blending case aka. section.num_streams > 1 +static enum vpe_status fill_mps_blending_cmd_info(struct vpe_priv *vpe_priv, + struct vpe_mps_ctx *mps_ctx, struct vpe_mps_command *command, uint16_t *num_cmds) +{ + struct vpe_cmd_info cmd_info = {0}; + uint16_t mps_idx, input_idx, cmd_info_input_idx, seg_idx; + enum vpe_status status = VPE_STATUS_OK; + + // number used by countdown field, shared by whole MPS op + *num_cmds -= 1; + + cmd_info.num_inputs = command->num_inputs; + cmd_info.cd = (uint8_t)(*num_cmds); + cmd_info.lut3d_type = LUT3D_TYPE_NONE; + cmd_info.ops = VPE_CMD_OPS_BLENDING; + cmd_info.insert_start_csync = false; + cmd_info.insert_end_csync = false; + + mps_idx = 0; + + struct fmt_boundary_mode output_boundary_mode = {0}; // Initialize all to BOUNDARY_REPEAT + struct spl_opp_adjust output_opp_adjust = { + 0}; // for entire output, start by assuming no seam then add as needed + + for (input_idx = 0; input_idx < command->num_inputs; input_idx++) { + seg_idx = command->seg_idx[input_idx]; + struct stream_ctx *stream_ctx = &vpe_priv->stream_ctx[command->stream_idx[input_idx]]; + struct segment_ctx *segment_ctx = &stream_ctx->segment_ctx[seg_idx]; + + if (segment_ctx->boundary_mode.left == FMT_SUBSAMPLING_BOUNDARY_EXTRA) + output_boundary_mode.left = FMT_SUBSAMPLING_BOUNDARY_EXTRA; + if (segment_ctx->boundary_mode.right == FMT_SUBSAMPLING_BOUNDARY_EXTRA) + output_boundary_mode.right = FMT_SUBSAMPLING_BOUNDARY_EXTRA; + if (segment_ctx->boundary_mode.top == FMT_SUBSAMPLING_BOUNDARY_EXTRA) + output_boundary_mode.top = FMT_SUBSAMPLING_BOUNDARY_EXTRA; + if (segment_ctx->boundary_mode.bottom == FMT_SUBSAMPLING_BOUNDARY_EXTRA) + output_boundary_mode.bottom = FMT_SUBSAMPLING_BOUNDARY_EXTRA; + + // how many pixels (absolute value) are required on each side of this stream + // aka seg_left/right_seam will always be positive values + int seg_left_seam = + -segment_ctx->opp_recout_adjust + .x; // opp_recout_adjust.x will always be -ve or 0, we want absolute + int seg_right_seam = + segment_ctx->opp_recout_adjust.width + segment_ctx->opp_recout_adjust.x; + + // how many pixels (absolute value) are required on each side for whole segment (all + // streams) aka out_left/right_seam will always be positive values + int out_left_seam = + -output_opp_adjust.x; // opp_recout_adjust.x will always be -ve or 0, we want absolute + int out_right_seam = output_opp_adjust.width + output_opp_adjust.x; + + // keep increasing size of output_opp_adjust until it covers all required seams + if (seg_left_seam > out_left_seam && seg_right_seam > out_left_seam) { + output_opp_adjust = segment_ctx->opp_recout_adjust; + } else if (seg_left_seam > out_left_seam) { + output_opp_adjust.width += seg_left_seam - out_left_seam; + output_opp_adjust.x = -seg_left_seam; + } else if (seg_right_seam > out_right_seam) { + output_opp_adjust.width += seg_right_seam - out_right_seam; + } + } + cmd_info.outputs[0].boundary_mode = output_boundary_mode; + cmd_info.outputs[0].opp_recout_adjust = output_opp_adjust; + + if (vpe_priv->output_ctx.frod_param.enable_frod) { + cmd_info.frod_param.enable_frod = vpe_priv->output_ctx.frod_param.enable_frod; + cmd_info.num_outputs = FROD_NUM_OUTPUTS; + } else { + cmd_info.num_outputs = 1; + } + for (input_idx = 0; input_idx < command->num_inputs; input_idx++) { + + cmd_info_input_idx = command->num_inputs - input_idx - 1; + // mps command packet packs smallest->larget stream idx (0 means bottom stream) + // but blending command expects other way (pipe 0 is topmost pipe) + + if (command->is_bg_gen[input_idx]) + VPE_ASSERT(false); // sanity check: shouldn't be background gen in a multi_stream cmd + // bg gen should be handled by the bottom-most stream in blending + + mps_idx = command->mps_idx[input_idx]; + seg_idx = command->seg_idx[input_idx]; + + struct stream_ctx *stream_ctx = &vpe_priv->stream_ctx[command->stream_idx[input_idx]]; + struct segment_ctx *segment_ctx = &stream_ctx->segment_ctx[seg_idx]; + + cmd_info.lut3d_type = vpe_get_stream_lut3d_type(stream_ctx); + + cmd_info.inputs[cmd_info_input_idx].stream_idx = command->stream_idx[input_idx]; + + struct scaler_data *scaler_data = &segment_ctx->scaler_data; + struct vpe_rect *target_rect = &vpe_priv->output_ctx.target_rect; + + // Adjust dst_viewport and recout to match whole segment + mps_calculate_dst_viewport_and_active(stream_ctx, scaler_data, target_rect, + command->start_x[input_idx], command->end_x[input_idx], + &segment_ctx->opp_recout_adjust); + + int additional_left_seam_required = segment_ctx->opp_recout_adjust.x - output_opp_adjust.x; + int additional_right_seam_required = + (output_opp_adjust.x + output_opp_adjust.width) - + (segment_ctx->opp_recout_adjust.x + segment_ctx->opp_recout_adjust.width); + + if (additional_left_seam_required > 0) { + scaler_data->recout.x += additional_left_seam_required; + scaler_data->dscl_prog_data.recout.x += additional_left_seam_required; + scaler_data->dscl_prog_data.mpc_size.width += additional_left_seam_required; + } + + if (additional_right_seam_required > 0) + scaler_data->dscl_prog_data.mpc_size.width += additional_right_seam_required; + + memcpy(&(cmd_info.inputs[cmd_info_input_idx].scaler_data), scaler_data, + sizeof(struct scaler_data)); + + if (input_idx != 0) { + // sanity check to ensure all MPC sizes are still the same after the OPP adjust + if (scaler_data->dscl_prog_data.mpc_size.width != + cmd_info.inputs[0].scaler_data.dscl_prog_data.mpc_size.width || + scaler_data->dscl_prog_data.mpc_size.height != + cmd_info.inputs[0].scaler_data.dscl_prog_data.mpc_size.height) { + VPE_ASSERT(false); + status = VPE_STATUS_ERROR; + break; + } + } + } + + cmd_info.outputs[0].dst_viewport = cmd_info.inputs[0].scaler_data.dst_viewport; + cmd_info.outputs[0].dst_viewport_c = cmd_info.inputs[0].scaler_data.dst_viewport_c; + + if (status == VPE_STATUS_OK) + vpe_vector_push(vpe_priv->vpe_cmd_vector, &cmd_info); + + return status; +} + +// generate command for single stream case (standard compositing or performance mode) +static enum vpe_status fill_mps_performance_cmd_info(struct vpe_priv *vpe_priv, + struct vpe_mps_ctx *mps_ctx, struct vpe_mps_command *command, uint16_t *num_cmds) +{ + struct vpe_cmd_info cmd_info = {0}; + uint16_t mps_idx, input_idx, seg_idx; + + // number used by countdown field, shared by whole MPS op + *num_cmds -= 1; + + cmd_info.num_inputs = command->num_inputs; + cmd_info.cd = (uint8_t)(*num_cmds); + cmd_info.lut3d_type = LUT3D_TYPE_NONE; + cmd_info.ops = VPE_CMD_OPS_COMPOSITING; + cmd_info.insert_start_csync = false; + cmd_info.insert_end_csync = false; + + if (vpe_priv->output_ctx.frod_param.enable_frod) { + VPE_ASSERT(command->num_inputs == 1); // only 1 input allowed for FROD + cmd_info.frod_param.enable_frod = vpe_priv->output_ctx.frod_param.enable_frod; + cmd_info.num_outputs = FROD_NUM_OUTPUTS; + } else { + cmd_info.num_outputs = command->num_inputs; + } + + mps_idx = 0; + for (input_idx = 0; input_idx < command->num_inputs; input_idx++) { + if (command->is_bg_gen[input_idx]) { + struct stream_ctx *stream_ctx = &vpe_priv->stream_ctx[0]; + struct vpe_rect viewport = { + .x = command->start_x[input_idx], + .y = vpe_priv->output_ctx.target_rect.y, + .width = command->end_x[input_idx] - command->start_x[input_idx], + .height = vpe_priv->output_ctx.target_rect.height, + }; + fill_background_cmd_info_input(vpe_priv, &viewport, &cmd_info, input_idx); + } else { + + mps_idx = command->mps_idx[input_idx]; + seg_idx = command->seg_idx[input_idx]; + struct stream_ctx *stream_ctx = &vpe_priv->stream_ctx[command->stream_idx[input_idx]]; + struct segment_ctx *segment_ctx = &stream_ctx->segment_ctx[seg_idx]; + + cmd_info.lut3d_type = vpe_get_stream_lut3d_type(stream_ctx); + + cmd_info.inputs[input_idx].stream_idx = command->stream_idx[input_idx]; + + // For 1 seg sections, we always need to generate background, so update dst_viewport + struct scaler_data *scaler_data = &stream_ctx->segment_ctx[seg_idx].scaler_data; + struct vpe_rect *target_rect = &vpe_priv->output_ctx.target_rect; + + // Adjust dst_viewport and recout to match whole segment + mps_calculate_dst_viewport_and_active(stream_ctx, scaler_data, target_rect, + command->start_x[input_idx], command->end_x[input_idx], + &segment_ctx->opp_recout_adjust); + + memcpy( + &(cmd_info.inputs[input_idx].scaler_data), scaler_data, sizeof(struct scaler_data)); + + cmd_info.outputs[input_idx].dst_viewport = segment_ctx->scaler_data.dst_viewport; + cmd_info.outputs[input_idx].dst_viewport_c = segment_ctx->scaler_data.dst_viewport_c; + cmd_info.outputs[input_idx].boundary_mode = segment_ctx->boundary_mode; + cmd_info.outputs[input_idx].opp_recout_adjust = segment_ctx->opp_recout_adjust; + } + } + vpe_vector_push(vpe_priv->vpe_cmd_vector, &cmd_info); + + return VPE_STATUS_OK; +} +/** + * @brief Get the total number of segments for a mps blend operation + * @param[in] combined_dst smallest rect that contains all input streams dst_rects + * @param[in] src_rects array of src rects for each input stream involved in mps + * blend + * @param[in] dst_rects array of dst rects for each input stream involved in mps + * blend + * @param[in] max_seg_width maximum width of a segment + * @param[in] recout_width_alignment alignment width for recout + * @param[in] num_input_streams number of input streams for mps blend + * @param[in/out] mps_ctx struct to store the return values (vector of segment widths + * and vector of sections) + * @return 0 if segments cannot be allocated for some reason + */ +static enum vpe_status vpe_mps_build_mps_ctx( + struct vpe_priv *vpe_priv, struct vpe_mps_input *input_params, struct vpe_mps_ctx *mps_ctx) +{ + uint32_t max_dst_width_per_stream[MAX_INPUT_PIPE]; + double scaling_ratios[MAX_INPUT_PIPE]; // ratio of dst over src rect width + struct vpe_rect combined_dst; + struct vpe_rect dst_rects[MAX_INPUT_PIPE]; + struct vpe_rect src_rects[MAX_INPUT_PIPE]; + enum vpe_status status = VPE_STATUS_OK; + + for (int i = 0; i < mps_ctx->num_streams; i++) { + dst_rects[i] = input_params->mps_stream_ctx[i].dst_rect; + src_rects[i] = input_params->mps_stream_ctx[i].src_rect; + } + + if (mps_ctx->stream_idx[0] == 0) + combined_dst = vpe_priv->output_ctx.target_rect; + else + combined_dst = get_combined_dst_rect(dst_rects, mps_ctx->num_streams); + + VPE_ASSERT(mps_ctx->num_streams <= vpe_priv->pub.caps->resource_caps.num_dpp); + + for (int i = 0; i < mps_ctx->num_streams; i++) + if (mps_ctx->segment_widths[i] == NULL) + mps_ctx->segment_widths[i] = vpe_vector_create(vpe_priv, sizeof(uint32_t), 1); + + if (mps_ctx->section_vector == NULL) + mps_ctx->section_vector = + vpe_vector_create(vpe_priv, sizeof(struct vpe_mps_section), MPS_INITIAL_SECTION_SIZE); + + // Downscaled inputs have a smaller max dst output width, as their src rect width will be + // larger and must stay within 1 segment width. Compute the max dst and src rect for them. + + for (int i = 0; i < mps_ctx->num_streams; i++) { + if (src_rects[i].width == 0) { + VPE_ASSERT(false); + status = VPE_STATUS_ERROR; + } + max_dst_width_per_stream[i] = min(input_params->max_seg_width, + dst_rects[i].width * input_params->max_seg_width / src_rects[i].width); + scaling_ratios[i] = (double)dst_rects[i].width / (double)src_rects[i].width; + } + + // MPS algo part 1 - divide combined dst rect into 'sections' ============================ + // horizontal spans that are differentiated by how many dst rects exist in that area + if (status != VPE_STATUS_ERROR) + status = mps_create_initial_sections(dst_rects, &combined_dst, mps_ctx->num_streams, + input_params->recout_width_alignment, mps_ctx->section_vector); + + // MPS algo part 2 - optimize the sections we've just generated ========================== + // 2.0 - merge conglomerate adjacent 0 and 1 stream sections ========================== + if (status != VPE_STATUS_ERROR) + status = mps_combine_single_zero_stream_sections(mps_ctx->section_vector); + + while (((status == VPE_STATUS_OK) || (status == VPE_STATUS_REPEAT_ITEM)) && + mps_ctx->section_vector->num_elements > 1) { + // note: all 2.x functions make high num_stream sections bigger and smaller num_stream + // sections smaller, so no infinite loop issues. worst case scenario largest num_streams + // section takes whole target rect + + // 2.1 - check for empty streams and delete =========================================== + // mostly a sanity check + status reset + status = mps_check_empty(mps_ctx->section_vector); + + if (status != VPE_STATUS_OK) + break; + + while ((status == VPE_STATUS_OK) || (status == VPE_STATUS_REPEAT_ITEM)) { + // keep optimizing/merging until we can't anymore + + // 2.2 - add pixels to small sections from neighboring ones until optimal minimum size + // met ================ + status = mps_merge_sections_under_optimal_size(mps_ctx->section_vector, + input_params->max_seg_width, input_params->recout_width_alignment); + + // 2.2 - ensure the rects in every section are large enough to meet min_viewport_reqs + if (status == VPE_STATUS_OK) + status = enforce_minimum_viewport_size_for_rect_in_section(dst_rects, + scaling_ratios, input_params->recout_width_alignment, mps_ctx->section_vector, + mps_ctx->num_streams); + + if (status == VPE_STATUS_OK) + break; + else if (status != VPE_STATUS_REPEAT_ITEM) + break; + } + + // only align ro recout once other requirements have been met + // Algo part 3 - Align our sections =================================================== + status = mps_align_sections(mps_ctx->section_vector, input_params->recout_width_alignment); + + if (status == VPE_STATUS_OK) + break; + } + + if (mps_ctx->section_vector->num_elements == 0) { + VPE_ASSERT(false); + status = VPE_STATUS_ERROR; + } + + // Algo part 4 - break sections into segment ================================================== + if (status == VPE_STATUS_OK) { + for (int i = 0; i < (int)(mps_ctx->section_vector->num_elements); i++) { + struct vpe_mps_section *section = vpe_vector_get(mps_ctx->section_vector, i); + status = mps_segmentation_algo( + vpe_priv, mps_ctx, input_params, max_dst_width_per_stream, scaling_ratios, section); + + if (status != VPE_STATUS_OK) + break; + + // adjust segment widths within a single command to be more even. + // This can only be done for single stream / BG sections, as blending (num_streams >= 2) + // cannot run in perf mode + // + // either width adjust (ex. seg width per pipe (300, 100, 500) -> (300, 300, 300)) + // and/or pipe count adjust (ex. seg width per pipe (1000, 0, 0) -> (333, 333, 334)) + optimize_segments_in_section( + vpe_priv, mps_ctx, section, dst_rects, input_params->recout_width_alignment); + } + + // Fill in MPS struct field segment_widths + seg_idx in commands + calculate_segment_widths(mps_ctx, dst_rects); + } + return status; +} + +/* ===== END HELPER FUNCTIONS ================================================================= */ + +enum vpe_status vpe_init_mps_ctx( + struct vpe_priv *vpe_priv, struct stream_ctx **stream_ctx, uint16_t num_streams) +{ + struct vpe_mps_ctx **mps_ctx = &stream_ctx[0]->mps_ctx; + *mps_ctx = vpe_zalloc(sizeof(struct vpe_mps_ctx)); + + if (!(*mps_ctx)) + return VPE_STATUS_NO_MEMORY; + + (*mps_ctx)->num_streams = num_streams; + for (int i = 0; i < num_streams; i++) { + stream_ctx[i]->mps_parent_stream = stream_ctx[0]; + (*mps_ctx)->stream_idx[i] = (uint16_t)stream_ctx[i]->stream_idx; + } + + return VPE_STATUS_OK; +} + +void vpe_free_mps_ctx(struct vpe_priv *vpe_priv, struct vpe_mps_ctx **mps_ctx) +{ + if (mps_ctx == NULL) + return; + + if (*mps_ctx == NULL) + return; + + if ((*mps_ctx)->section_vector != NULL) { + if ((*mps_ctx)->section_vector->element != NULL) { + // Because of deinit function, sometimes elements after num_elements can have cmd_vector + // initialized + (*mps_ctx)->section_vector->num_elements = (*mps_ctx)->section_vector->capacity; + for (int i = 0; i < (int)((*mps_ctx)->section_vector->capacity); i++) { + struct vpe_mps_section *section = vpe_vector_get((*mps_ctx)->section_vector, i); + if (section != NULL) + if (section->command_vector != NULL) + if (section->command_vector->element != NULL) + vpe_vector_free(section->command_vector); + } + vpe_vector_free((*mps_ctx)->section_vector); + (*mps_ctx)->section_vector = NULL; + } + } + + for (int i = 0; i < MAX_INPUT_PIPE; i++) { + if ((*mps_ctx)->segment_widths[i] != NULL) { + if ((*mps_ctx)->segment_widths[i]->element != NULL) { + vpe_vector_free((*mps_ctx)->segment_widths[i]); + (*mps_ctx)->segment_widths[i] = NULL; + } + } + } + + for (int i = 0; i < (*mps_ctx)->num_streams; i++) + vpe_priv->stream_ctx[(*mps_ctx)->stream_idx[i]].mps_parent_stream = NULL; + + vpe_free(*mps_ctx); + *mps_ctx = NULL; +} + +void vpe_clear_mps_ctx(struct vpe_priv *vpe_priv, struct vpe_mps_ctx *mps_ctx) +{ + for (int i = 0; i < mps_ctx->num_streams; i++) { + struct stream_ctx *stream_ctx = &vpe_priv->stream_ctx[mps_ctx->stream_idx[i]]; + if (stream_ctx != stream_ctx->mps_parent_stream) + stream_ctx->mps_parent_stream = NULL; + } + + if (mps_ctx->section_vector != NULL) { + if (mps_ctx->section_vector->element != NULL) { + for (int i = 0; i < (int)(mps_ctx->section_vector->num_elements); i++) { + struct vpe_mps_section *section = vpe_vector_get(mps_ctx->section_vector, i); + if (section->command_vector != NULL) + if (section->command_vector->element != NULL) + vpe_vector_clear(section->command_vector); + + section->end_x = 0; + section->start_x = 0; + section->num_streams = 0; + } + mps_ctx->section_vector->num_elements = 0; + } + } + + mps_ctx->num_streams = 0; + for (int i = 0; i < MAX_INPUT_PIPE; i++) { + vpe_vector_clear(mps_ctx->segment_widths[i]); + mps_ctx->stream_idx[i] = 0; + mps_ctx->segment_count[i] = 0; + } +} + +enum vpe_status vpe_fill_mps_blend_cmd_info(struct vpe_priv *vpe_priv, struct vpe_mps_ctx *mps_ctx) +{ + uint16_t section_idx, cmd_idx, cmd_count, num_cmds; + + if (mps_ctx == NULL) + return VPE_STATUS_ERROR; + else if (mps_ctx->section_vector == NULL) + return VPE_STATUS_ERROR; + + num_cmds = 0; + for (section_idx = 0; section_idx < (uint16_t)mps_ctx->section_vector->num_elements; + section_idx++) { + struct vpe_mps_section *section = vpe_vector_get(mps_ctx->section_vector, section_idx); + + if (section->command_vector == NULL) + return VPE_STATUS_ERROR; + else if (section->command_vector->element == NULL) + return VPE_STATUS_ERROR; + + num_cmds += (uint16_t)section->command_vector->num_elements; + } + + // need to generate non-blending cmds first, then blending cmds + // i.e. first run all bg commands, then 1 stream commands, then blending + for (cmd_count = 0; cmd_count <= (uint16_t)vpe_priv->pub.caps->resource_caps.num_dpp; + cmd_count++) { + for (section_idx = 0; section_idx < (uint16_t)mps_ctx->section_vector->num_elements; + section_idx++) { + struct vpe_mps_section *section = vpe_vector_get(mps_ctx->section_vector, section_idx); + + if (section->num_streams == cmd_count) { + for (cmd_idx = 0; cmd_idx < (uint16_t)section->command_vector->num_elements; + cmd_idx++) { + struct vpe_mps_command *command = + vpe_vector_get(section->command_vector, cmd_idx); + if (section->num_streams < 2 || command->num_inputs < 2) + fill_mps_performance_cmd_info(vpe_priv, mps_ctx, command, &num_cmds); + else + fill_mps_blending_cmd_info(vpe_priv, mps_ctx, command, &num_cmds); + } + } + } + } + + return VPE_STATUS_OK; +} + +// return the number of 3dluts required for MPS, which is the same as however many streams width +// 3dluts overlap in their x coordinates +static uint16_t get_num_3dlut_required( + const struct stream_ctx **mps_stream_ctx, uint16_t num_streams, uint32_t recout_width_align) +{ + uint16_t num_3dlut_required = 0; + uint16_t num_3dlut_streams = 0; + uint16_t stream_idx; + uint16_t lut_stream_idx[MAX_INPUT_PIPE] = {0}; + struct vpe_rect lut_rects[MAX_INPUT_PIPE] = {0}; + + // create array of streams containing 3dluts as setup for next loop + for (stream_idx = 0; stream_idx < num_streams; stream_idx++) { + const struct stream_ctx *stream_ctx = mps_stream_ctx[stream_idx]; + if (stream_ctx->stream.tm_params.UID != 0 || stream_ctx->stream.tm_params.enable_3dlut) { + lut_stream_idx[num_3dlut_streams] = stream_idx; + lut_rects[num_3dlut_streams] = stream_ctx->stream.scaling_info.dst_rect; + num_3dlut_streams++; + } + } + + for (stream_idx = 0; stream_idx < num_3dlut_streams; stream_idx++) { + uint16_t luts_required_at_this_x = 0; + const struct stream_ctx *stream_ctx = mps_stream_ctx[stream_idx]; + int32_t start_x = stream_ctx->stream.scaling_info.dst_rect.x; + int32_t end_x = stream_ctx->stream.scaling_info.dst_rect.x + + stream_ctx->stream.scaling_info.dst_rect.width; + + luts_required_at_this_x = get_num_rects_at_x_recout_align( + start_x, lut_rects, num_3dlut_streams, recout_width_align); + + if (luts_required_at_this_x > num_3dlut_required) + num_3dlut_required = luts_required_at_this_x; + + luts_required_at_this_x = get_num_rects_at_x_recout_align( + end_x, lut_rects, num_3dlut_streams, recout_width_align); + + if (luts_required_at_this_x > num_3dlut_required) + num_3dlut_required = luts_required_at_this_x; + } + + return num_3dlut_required; +} + +// check if we can run multi-pipe segmentation with these streams +bool vpe_is_mps_possible(struct vpe_priv *vpe_priv, struct stream_ctx **mps_stream_ctx, + uint16_t num_streams, uint32_t recout_width_alignment) +{ + uint16_t num_3dlut_required = 0; + uint16_t num_front_end_required = 0; + uint16_t stream_idx; + bool blending_required = false; + + // need to make sure our rect start value is aligned so that the alignment calulations + // used in MPS work as expected + if (mps_stream_ctx[0]->stream_idx == 0) + if (recout_width_alignment != VPE_NO_ALIGNMENT) + if (vpe_priv->output_ctx.target_rect.x % recout_width_alignment != 0) + return false; + + if (vpe_priv->num_input_streams == 0) + return false; // if no input streams fall back to bg_gen case - no MPS + + for (stream_idx = 0; stream_idx < num_streams; stream_idx++) { + struct stream_ctx *current_stream_ctx = mps_stream_ctx[stream_idx]; + if (stream_idx > 0) { + if (current_stream_ctx->stream.blend_info.blending) + blending_required = true; + + if (current_stream_ctx->stream_idx <= mps_stream_ctx[stream_idx - 1]->stream_idx) + return false; // we should also pass in streams in ascending order (0, 1, 2) + } + + if (current_stream_ctx->stream.tm_params.enable_3dlut) + num_3dlut_required++; + + num_front_end_required++; + + // for alpha combine family of ops, ensure we have enough input pipes for ALL streams + // required + if (current_stream_ctx->stream.flags.is_alpha_plane) { + bool is_bkgr_op = false; // assume only alpha combine first, then check if full bkgr + if (vpe_priv->num_streams >= + (uint32_t)current_stream_ctx->stream_idx + VPE_BKGR_STREAM_BACKGROUND_OFFSET + 1) + if (vpe_priv + ->stream_ctx[current_stream_ctx->stream_idx + + VPE_BKGR_STREAM_BACKGROUND_OFFSET] + .stream.flags.is_background_plane) + is_bkgr_op = true; + + if (stream_idx >= num_streams - 1 || (stream_idx >= num_streams - 2 && is_bkgr_op)) { + return false; + } else { + struct stream_ctx *alpha_combine_video_stream = + mps_stream_ctx[stream_idx + VPE_BKGR_STREAM_VIDEO_OFFSET]; + if (alpha_combine_video_stream->stream_idx != + current_stream_ctx->stream_idx + VPE_BKGR_STREAM_VIDEO_OFFSET) + return false; + + if (is_bkgr_op) { + struct stream_ctx *bkgr_bg_stream = + mps_stream_ctx[stream_idx + VPE_BKGR_STREAM_BACKGROUND_OFFSET]; + if (bkgr_bg_stream->stream_idx != + current_stream_ctx->stream_idx + VPE_BKGR_STREAM_BACKGROUND_OFFSET) + return false; + } + } + } + + // these virtual stream types shouldn't be included in MPS + if (current_stream_ctx->stream_type == VPE_STREAM_TYPE_BG_GEN || + current_stream_ctx->stream_type == VPE_STREAM_TYPE_DESTINATION) + return false; + } + + num_3dlut_required = + get_num_3dlut_required((const struct stream_ctx **)mps_stream_ctx, num_streams, recout_width_alignment); + + if (vpe_priv->init.debug.multi_pipe_segmentation_policy == VPE_MPS_DISABLED) + return false; + else if (vpe_priv->init.debug.multi_pipe_segmentation_policy == VPE_MPS_BLENDING_ONLY) { + if (num_streams == 1 || blending_required == false) + return false; + } + + // need to blend in MPC with generic location, so need bg gen in MPC + if (vpe_priv->init.debug.opp_background_gen == 1) + return false; + + if (num_3dlut_required > vpe_priv->pub.caps->resource_caps.num_mpc_3dlut) + return false; + + if (num_front_end_required > vpe_priv->pub.caps->resource_caps.num_dpp) + return false; + + return true; +} + +uint16_t vpe_mps_get_num_segs(struct vpe_priv *vpe_priv, struct stream_ctx *stream_ctx, + uint32_t *max_seg_width, uint32_t recout_width_alignment) +{ + uint16_t num_segs; + if (stream_ctx == stream_ctx->mps_parent_stream) { + // only parent stream runs MPS algorithm + struct vpe_mps_ctx *mps_ctx = stream_ctx->mps_ctx; + enum vpe_status status; + + struct vpe_mps_input input = {0}; + + for (int i = 0; i < mps_ctx->num_streams; i++) { + input.mps_stream_ctx[i].stream_ctx = &vpe_priv->stream_ctx[mps_ctx->stream_idx[i]]; + + struct vpe_rect stream_local_src_rect = + input.mps_stream_ctx[i].stream_ctx->stream.scaling_info.src_rect; + if (input.mps_stream_ctx[i].stream_ctx->stream.rotation == VPE_ROTATION_ANGLE_90 || + input.mps_stream_ctx[i].stream_ctx->stream.rotation == VPE_ROTATION_ANGLE_270) { + swap(stream_local_src_rect.width, stream_local_src_rect.height); + } + + input.mps_stream_ctx[i].src_rect = stream_local_src_rect; + input.mps_stream_ctx[i].dst_rect = + input.mps_stream_ctx[i].stream_ctx->stream.scaling_info.dst_rect; + } + + input.num_inputs = mps_ctx->num_streams; + input.recout_width_alignment = recout_width_alignment; + input.max_seg_width = *max_seg_width; + + status = vpe_mps_build_mps_ctx(vpe_priv, &input, mps_ctx); + + if (mps_ctx->num_streams == 0 || status != VPE_STATUS_OK) { + VPE_ASSERT(false); + return 0; + } + + num_segs = mps_ctx->segment_count[0]; + + } else { // If this is a non-parent stream for mps blend op, grab results from mps_ctx + struct vpe_mps_ctx *mps_ctx = stream_ctx->mps_parent_stream->mps_ctx; + uint16_t mps_idx = 0; + for (uint16_t i = 0; i < mps_ctx->num_streams; i++) { + if (mps_ctx->stream_idx[i] == stream_ctx->stream_idx) { + mps_idx = i; + break; + } + } + + num_segs = mps_ctx->segment_count[mps_idx]; + + if (mps_idx == 0 || num_segs != mps_ctx->segment_widths[mps_idx]->num_elements) { + VPE_ASSERT(false); + return VPE_STATUS_ERROR; + } + } + return num_segs; +} + diff --git a/src/amd/vpelib/src/core/resource.c b/src/amd/vpelib/src/core/resource.c index 11afdd8aca4..d56be8da5f8 100644 --- a/src/amd/vpelib/src/core/resource.c +++ b/src/amd/vpelib/src/core/resource.c @@ -31,6 +31,9 @@ #include "vpe11_resource.h" +#include "vpe20_resource.h" +#include "multi_pipe_segmentation.h" + static const struct vpe_debug_options debug_defaults = { .flags = {0}, .cm_in_bypass = 0, @@ -75,6 +78,10 @@ static const struct vpe_debug_options debug_defaults = { .skip_optimal_tap_check = 0, .disable_lut_caching = 0, .bypass_blndgam = 0, + .disable_performance_mode = 0, + .multi_pipe_segmentation_policy = 1, // 0: disable, 1: use for blending, 2: always use + .opp_background_gen = 0, // 0 : mpc bg gen, 1: opp bg gen + .subsampling_quality = 1, // 0 : 4/5 taps 1: 2/3 taps }; enum vpe_ip_level vpe_resource_parse_ip_version( @@ -90,6 +97,10 @@ enum vpe_ip_level vpe_resource_parse_ip_version( case VPE_VERSION(6, 1, 2): ip_level = VPE_IP_LEVEL_1_1; break; + case VPE_VERSION(2, 0, 0): + case VPE_VERSION(7, 0, 0): // to be removed when caller switches to new convention + ip_level = VPE_IP_LEVEL_2_0; + break; default: ip_level = VPE_IP_LEVEL_UNKNOWN; break; @@ -109,6 +120,9 @@ enum vpe_status vpe_construct_resource( case VPE_IP_LEVEL_1_1: status = vpe11_construct_resource(vpe_priv, res); break; + case VPE_IP_LEVEL_2_0: + status = vpe20_construct_resource(vpe_priv, res); + break; default: status = VPE_STATUS_NOT_SUPPORTED; vpe_log("invalid ip level: %d", (int)level); @@ -132,6 +146,9 @@ void vpe_destroy_resource(struct vpe_priv *vpe_priv, struct resource *res) case VPE_IP_LEVEL_1_1: vpe11_destroy_resource(vpe_priv, res); break; + case VPE_IP_LEVEL_2_0: + vpe20_destroy_resource(vpe_priv, res); + break; default: break; } @@ -276,6 +293,10 @@ static void free_stream_ctx(uint32_t num_streams, struct stream_ctx *stream_ctx) ctx->segment_ctx = NULL; } + if (ctx->mps_ctx) + if (ctx->mps_parent_stream == ctx) + vpe_free_mps_ctx(vpe_priv, &ctx->mps_ctx); + destroy_input_config_vector(ctx); } } @@ -434,6 +455,10 @@ void vpe_calculate_scaling_ratios(struct scaler_data *scl_data, struct vpe_rect scl_data->ratios.vert_c.value /= 2; } + if (vpe_is_yuv422(format)) { + scl_data->ratios.horz_c.value /= 2; + } + scl_data->ratios.horz = vpe_fixpt_truncate(scl_data->ratios.horz, 19); scl_data->ratios.vert = vpe_fixpt_truncate(scl_data->ratios.vert, 19); scl_data->ratios.horz_c = vpe_fixpt_truncate(scl_data->ratios.horz_c, 19); @@ -549,6 +574,10 @@ static enum vpe_status calculate_inits_and_viewports(struct segment_ctx *segment struct fixed31_32 init_adj_h = vpe_fixpt_zero; struct fixed31_32 init_adj_v = vpe_fixpt_zero; + if (vpe_is_yuv422(data->format)) { + vpc_h_div = 2; + } + get_vp_scan_direction(stream_ctx->stream.rotation, stream_ctx->stream.horizontal_mirror, &orthogonal_rotation, &flip_vert_scan_dir, &flip_horz_scan_dir); @@ -613,6 +642,8 @@ enum lut3d_type vpe_get_stream_lut3d_type(struct stream_ctx *stream_ctx) // for Fast Load Enable/Disable if ((stream_ctx->stream.tm_params.UID == 0) || (!stream_ctx->stream.tm_params.enable_3dlut)) { lut3d = LUT3D_TYPE_NONE; + } else if (stream_ctx->stream.tm_params.lut_type != VPE_LUT_TYPE_CPU) { + lut3d = LUT3D_TYPE_GPU; } else { lut3d = LUT3D_TYPE_CPU; } @@ -631,9 +662,14 @@ bool vpe_should_generate_cmd_info(struct stream_ctx *stream_ctx) { enum vpe_stream_type stream_type = stream_ctx->stream_type; + if (stream_ctx->mps_parent_stream != NULL && stream_ctx->mps_parent_stream != stream_ctx) + return false; // don't generate cmd info for non-parent stream in mps blending + // all cmd info for whole MPS op will be generated by parent stream + switch (stream_type) { case VPE_STREAM_TYPE_INPUT: case VPE_STREAM_TYPE_BG_GEN: + case VPE_STREAM_TYPE_BKGR_ALPHA: return true; default: /* destination-as-input virtual stream does not need a new cmd_info, @@ -897,6 +933,15 @@ void vpe_backend_config_callback( uint32_t vpe_get_recout_width_alignment(const struct vpe_build_param *params) { uint16_t recout_alignment; + bool dst_subsampled; + + dst_subsampled = vpe_is_subsampled_format(params->dst_surface.format); + + if (params->frod_param.enable_frod == true) + recout_alignment = VPE_FROD_ALIGNMENT; + else if (dst_subsampled == true) + recout_alignment = VPE_SUBSAMPLED_OUT_ALIGNMENT; + else recout_alignment = VPE_NO_ALIGNMENT; return recout_alignment; @@ -908,6 +953,52 @@ bool vpe_rec_is_equal(struct vpe_rect rec1, struct vpe_rect rec2) rec1.height == rec2.height); } +bool vpe_is_zero_rect(struct vpe_rect *rect) +{ + return (rect->width <= 0 || rect->height <= 0); +} + +bool vpe_is_valid_vp(struct vpe_rect *src_rect, struct vpe_rect *dst_rect) +{ + return (src_rect->width >= VPE_MIN_VIEWPORT_SIZE && src_rect->height >= VPE_MIN_VIEWPORT_SIZE && + dst_rect->width >= VPE_MIN_VIEWPORT_SIZE && dst_rect->height >= VPE_MIN_VIEWPORT_SIZE); +} + +bool vpe_is_scaling_factor_supported(struct vpe_priv *vpe_priv, struct vpe_rect *src_rect, + struct vpe_rect *dst_rect, enum vpe_rotation_angle rotation) +{ + bool ort_rotated = (rotation == VPE_ROTATION_ANGLE_90 || rotation == VPE_ROTATION_ANGLE_270); + const uint32_t max_upscale_factor = vpe_priv->pub.caps->plane_caps.max_upscale_factor; + const uint32_t max_downscale_factor = vpe_priv->pub.caps->plane_caps.max_downscale_factor; + uint32_t factor; + uint32_t src_width = ort_rotated ? src_rect->height : src_rect->width; + uint32_t src_height = ort_rotated ? src_rect->width : src_rect->height; + + // horizontal factor + factor = (uint32_t)vpe_fixpt_ceil(vpe_fixpt_from_fraction((1000 * dst_rect->width), src_width)); + if (factor > max_upscale_factor || factor < max_downscale_factor) + return false; + + // vertical factor + factor = + (uint32_t)vpe_fixpt_ceil(vpe_fixpt_from_fraction((1000 * dst_rect->height), src_height)); + if (factor > max_upscale_factor || factor < max_downscale_factor) + return false; + + return true; +} + +struct stream_ctx *vpe_get_virtual_stream( + struct vpe_priv *vpe_priv, enum vpe_stream_type stream_type) +{ + for (uint32_t i = 0; i < vpe_priv->num_virtual_streams; i++) { + if (vpe_priv->stream_ctx[i + vpe_priv->num_input_streams].stream_type == stream_type) { + return &(vpe_priv->stream_ctx[i + vpe_priv->num_input_streams]); + } + } + return NULL; +} + const struct vpe_caps *vpe_get_capability(enum vpe_ip_level ip_level) { const struct vpe_caps *caps; @@ -918,6 +1009,9 @@ const struct vpe_caps *vpe_get_capability(enum vpe_ip_level ip_level) case VPE_IP_LEVEL_1_1: caps = vpe11_get_capability(); break; + case VPE_IP_LEVEL_2_0: + caps = vpe20_get_capability(); + break; default: caps = NULL; @@ -934,6 +1028,9 @@ void vpe_setup_check_funcs(struct vpe_check_support_funcs *funcs, enum vpe_ip_le case VPE_IP_LEVEL_1_1: vpe11_setup_check_funcs(funcs); break; + case VPE_IP_LEVEL_2_0: + vpe20_setup_check_funcs(funcs); + break; default: break; } diff --git a/src/amd/vpelib/src/core/shaper_builder.c b/src/amd/vpelib/src/core/shaper_builder.c index d0735e3fdf6..2c495e4beaf 100644 --- a/src/amd/vpelib/src/core/shaper_builder.c +++ b/src/amd/vpelib/src/core/shaper_builder.c @@ -36,6 +36,18 @@ struct shaper_setup_out { int end_base_fixed_0_14; }; +enum vpe_shaper_index_mode vpe_get_shaper_index_mode( + uint32_t is_dma, enum lut_dimension lut_dim, enum lut_dimension lut_container_dim) +{ + // unitialized lut_container_dim will be treated as 33 dimension + if (is_dma && (lut_dim == LUT_DIM_17) && + ((lut_container_dim == LUT_DIM_33) || (lut_container_dim == LUT_DIM_INVALID))) { + return SHAPER_INDEX_MODE_17IN33LUT; + } else { + return SHAPER_INDEX_MODE_DEFAULT; + } +} + static unsigned int vpe_computer_shaper_pq_14u(double x, struct fixed31_32 normalized_factor) { unsigned output_fixpt_14u = 0x3fff; @@ -216,6 +228,11 @@ enum vpe_status vpe_build_shaper(const struct vpe_shaper_setup_in *shaper_in, else if (!calculate_shaper_properties_variable_hdr_mult(shaper_in, &shaper_params)) goto release; + if (shaper_in->index_mode == SHAPER_INDEX_MODE_17IN33LUT) { + normalized_factor = vpe_fixpt_mul_int(normalized_factor, 2); + d_norm /= 2; + shaper_params.end_base_fixed_0_14 /= 2; + } exp = shaper_params.exp_begin_raw; num_exp = shaper_params.exp_end_raw - shaper_params.exp_begin_raw + 1; diff --git a/src/amd/vpelib/src/core/vpe_spl_translation.c b/src/amd/vpelib/src/core/vpe_spl_translation.c new file mode 100644 index 00000000000..41f0765330d --- /dev/null +++ b/src/amd/vpelib/src/core/vpe_spl_translation.c @@ -0,0 +1,679 @@ +/* Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include "vpe_spl_translation.h" +#include "color.h" +#include "vpe_hw_types.h" +#include "common.h" + +const struct spl_sharpness_range SHARPNESS_RANGE = { + 0, 1750, 750, // SDR RGB Min, Max, Mid + 0, 3500, 1500, // SDR YUV Min, Max, Mid + 0, 2750, 1500 // HDR RGB Min, Max, Mid +}; + +static void spl_rect_to_vpe_rect(struct spl_rect *spl_rect, struct vpe_rect *vpe_rect) +{ + vpe_rect->height = spl_rect->height; + vpe_rect->width = spl_rect->width; + vpe_rect->x = spl_rect->x; + vpe_rect->y = spl_rect->y; +} + +static void vpe_rect_to_spl_rect(struct vpe_rect *vpe_rect, struct spl_rect *spl_rect) +{ + spl_rect->height = vpe_rect->height; + spl_rect->width = vpe_rect->width; + spl_rect->x = vpe_rect->x; + spl_rect->y = vpe_rect->y; +} + +struct spl_rotation_mirror_map { + enum spl_rotation_angle rotation; + bool h_mirror; +}; + +static struct spl_rotation_mirror_map spl_scan_map[] = { + {SPL_ROTATION_ANGLE_0, false}, + {SPL_ROTATION_ANGLE_270, false}, + {SPL_ROTATION_ANGLE_180, false}, + {SPL_ROTATION_ANGLE_90, false}, + {SPL_ROTATION_ANGLE_0, true}, + {SPL_ROTATION_ANGLE_270, true}, + {SPL_ROTATION_ANGLE_180, true}, + {SPL_ROTATION_ANGLE_90, true}, +}; + +static void get_spl_rotation( + enum vpe_scan_direction scan_dir, enum spl_rotation_angle *spl_angle, bool *spl_h_mirror) +{ + // VPE and DCN HW rotate in opposite directions. + // 90 degree rotation in VPE corresponds to 270 degree rotation in DCN, + // and vice versa. + *spl_angle = spl_scan_map[scan_dir].rotation; + *spl_h_mirror = spl_scan_map[scan_dir].h_mirror; +} + +static enum chroma_cositing get_spl_cositing(enum vpe_chroma_cositing cositing) +{ + switch (cositing) { + case VPE_CHROMA_COSITING_NONE: + return CHROMA_COSITING_NONE; + case VPE_CHROMA_COSITING_LEFT: + return CHROMA_COSITING_LEFT; + case VPE_CHROMA_COSITING_TOPLEFT: + return CHROMA_COSITING_TOPLEFT; + default: + VPE_ASSERT(false); + return CHROMA_COSITING_NONE; + } +} + +static enum spl_pixel_format get_spl_format(enum vpe_surface_pixel_format fmt) +{ + // 8/10/16 bit differences in formats does not affect SPL + switch (fmt) { + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB565: + return SPL_PIXEL_FORMAT_RGB565; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_R8: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_R16: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_UNORM: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616_UNORM: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_SNORM: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616_SNORM: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_RGB: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB: + return SPL_PIXEL_FORMAT_ARGB8888; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102: + return SPL_PIXEL_FORMAT_ARGB2101010; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB_FLOAT: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE: + return SPL_PIXEL_FORMAT_FP16; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + return SPL_PIXEL_FORMAT_420BPP8; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCbCr: + return SPL_PIXEL_FORMAT_420BPP10; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_CbYCrY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbCr: + return SPL_PIXEL_FORMAT_422BPP8; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CbYCrY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CbYCrY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbCr: + return SPL_PIXEL_FORMAT_422BPP10; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrCbYA8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_YCrCbA8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_YCbCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ALPHA_THRU_LUMA: + return SPL_PIXEL_FORMAT_444BPP8; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb12121212: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA12121212: + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_YCbCr: + return SPL_PIXEL_FORMAT_444BPP10; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XRGB8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: + case VPE_SURFACE_PIXEL_FORMAT_INVALID: + return SPL_PIXEL_FORMAT_UNKNOWN; + default: + VPE_ASSERT(false); + return SPL_PIXEL_FORMAT_INVALID; + } +} + +static enum spl_transfer_func_type get_spl_tf_type(enum transfer_func_type tf_type) +{ + switch (tf_type) { + case TF_TYPE_PREDEFINED: + return SPL_TF_TYPE_PREDEFINED; + case TF_TYPE_DISTRIBUTED_POINTS: + return SPL_TF_TYPE_DISTRIBUTED_POINTS; + case TF_TYPE_BYPASS: + return SPL_TF_TYPE_BYPASS; + case TF_TYPE_HWPWL: + return SPL_TF_TYPE_HWPWL; + default: + VPE_ASSERT(false); + return SPL_TF_TYPE_PREDEFINED; + } +} + +static enum spl_transfer_func_predefined get_spl_tf(enum color_transfer_func tf) +{ + switch (tf) { + case TRANSFER_FUNC_SRGB: + return SPL_TRANSFER_FUNCTION_SRGB; + case TRANSFER_FUNC_BT709: + return SPL_TRANSFER_FUNCTION_BT709; + case TRANSFER_FUNC_BT1886: + return SPL_TRANSFER_FUNCTION_GAMMA24; + case TRANSFER_FUNC_PQ2084: + return SPL_TRANSFER_FUNCTION_PQ; + case TRANSFER_FUNC_LINEAR: + return SPL_TRANSFER_FUNCTION_LINEAR; + case TRANSFER_FUNC_NORMALIZED_PQ: + return SPL_TRANSFER_FUNCTION_UNITY; + case TRANSFER_FUNC_HLG: + return SPL_TRANSFER_FUNCTION_HLG; + default: + VPE_ASSERT(false); + return SPL_TRANSFER_FUNCTION_SRGB; + } +} + +static enum spl_color_space get_spl_cs(enum color_space cs) +{ + switch (cs) { + case COLOR_SPACE_SRGB: + case COLOR_SPACE_YCBCR_JFIF: + case COLOR_SPACE_RGB_JFIF: + return SPL_COLOR_SPACE_SRGB; + case COLOR_SPACE_SRGB_LIMITED: + return SPL_COLOR_SPACE_SRGB_LIMITED; + case COLOR_SPACE_MSREF_SCRGB: + return SPL_COLOR_SPACE_MSREF_SCRGB; + case COLOR_SPACE_YCBCR601: + case COLOR_SPACE_RGB601: + return SPL_COLOR_SPACE_YCBCR601; + case COLOR_SPACE_RGB601_LIMITED: + case COLOR_SPACE_YCBCR601_LIMITED: + return SPL_COLOR_SPACE_YCBCR601_LIMITED; + case COLOR_SPACE_YCBCR709: + return SPL_COLOR_SPACE_YCBCR709; + case COLOR_SPACE_YCBCR709_LIMITED: + return SPL_COLOR_SPACE_YCBCR709_LIMITED; + case COLOR_SPACE_2020_RGB_FULLRANGE: + return SPL_COLOR_SPACE_2020_RGB_FULLRANGE; + case COLOR_SPACE_2020_RGB_LIMITEDRANGE: + return SPL_COLOR_SPACE_2020_RGB_LIMITEDRANGE; + case COLOR_SPACE_2020_YCBCR: + case COLOR_SPACE_2020_YCBCR_LIMITED: + return SPL_COLOR_SPACE_2020_YCBCR; + default: + VPE_ASSERT(false); + return SPL_COLOR_SPACE_UNKNOWN; + } +} + +static struct fixed31_32 spl_int_frac_to_fixpt( + uint32_t int_part, uint32_t frac_part, uint32_t shift_frac) +{ + struct fixed31_32 fixed_pt = vpe_fixpt_zero; + fixed_pt = vpe_fixpt_from_int(int_part); + fixed_pt.value += (frac_part >> shift_frac); + return fixed_pt; +} + +static struct fixed31_32 spl_ratio_to_fixpt(uint32_t ratio_u3d19) +{ + uint32_t int_part; + uint32_t frac_part; + struct fixed31_32 fixed_pt = vpe_fixpt_zero; + ratio_u3d19 = ratio_u3d19 >> 5; + frac_part = ratio_u3d19 & 0x7FFFF; + int_part = (ratio_u3d19 >> 19) & 0x7; + + fixed_pt = spl_int_frac_to_fixpt(int_part, frac_part, 0); + return fixed_pt; +} + +static struct fixed31_32 spl_init_to_fixpt( + uint32_t int_part, uint32_t frac_part, uint32_t shift_frac) +{ + return spl_int_frac_to_fixpt(int_part, frac_part, 5); +} + +static void set_clip_rect( + struct spl_rect *spl_clip_rect, struct vpe_rect dst_rect, struct vpe_rect clipped_dst_rect) +{ + spl_clip_rect->x = clipped_dst_rect.x - dst_rect.x; + spl_clip_rect->y = clipped_dst_rect.y - dst_rect.y; + spl_clip_rect->width = clipped_dst_rect.width; + spl_clip_rect->height = clipped_dst_rect.height; +} + +void vpe_spl_scl_to_vpe_scl(struct spl_out *spl_out, struct scaler_data *vpe_scl_data) +{ + + // taps + vpe_scl_data->taps.v_taps = spl_out->dscl_prog_data->taps.v_taps + 1; + vpe_scl_data->taps.h_taps = spl_out->dscl_prog_data->taps.h_taps + 1; + vpe_scl_data->taps.h_taps_c = spl_out->dscl_prog_data->taps.h_taps_c + 1; + vpe_scl_data->taps.v_taps_c = spl_out->dscl_prog_data->taps.v_taps_c + 1; + // viewport + spl_rect_to_vpe_rect(&spl_out->dscl_prog_data->viewport, &vpe_scl_data->viewport); + spl_rect_to_vpe_rect(&spl_out->dscl_prog_data->viewport_c, &vpe_scl_data->viewport_c); + // recout + spl_rect_to_vpe_rect(&spl_out->dscl_prog_data->recout, &vpe_scl_data->recout); + // ratios + vpe_scl_data->ratios.horz = spl_ratio_to_fixpt(spl_out->dscl_prog_data->ratios.h_scale_ratio); + vpe_scl_data->ratios.vert = spl_ratio_to_fixpt(spl_out->dscl_prog_data->ratios.v_scale_ratio); + vpe_scl_data->ratios.horz_c = + spl_ratio_to_fixpt(spl_out->dscl_prog_data->ratios.h_scale_ratio_c); + vpe_scl_data->ratios.vert_c = + spl_ratio_to_fixpt(spl_out->dscl_prog_data->ratios.v_scale_ratio_c); + // inits + vpe_scl_data->inits.h = spl_init_to_fixpt(spl_out->dscl_prog_data->init.h_filter_init_int, + spl_out->dscl_prog_data->init.h_filter_init_frac, 5); + vpe_scl_data->inits.v = spl_init_to_fixpt(spl_out->dscl_prog_data->init.v_filter_init_int, + spl_out->dscl_prog_data->init.v_filter_init_frac, 5); + vpe_scl_data->inits.h_c = spl_init_to_fixpt(spl_out->dscl_prog_data->init.h_filter_init_int_c, + spl_out->dscl_prog_data->init.h_filter_init_frac_c, 5); + vpe_scl_data->inits.v_c = spl_init_to_fixpt(spl_out->dscl_prog_data->init.v_filter_init_int_c, + spl_out->dscl_prog_data->init.v_filter_init_frac_c, 5); +} + +struct vp_scan_direction { + bool orthogonal_rotation; + bool flip_horz_scan_dir; + bool flip_vert_scan_dir; +}; + +static const struct vp_scan_direction + vp_scan_direction[VPE_ROTATION_ANGLE_COUNT][2][2] = + { + { + // VPE_ROTATION_ANGLE_0 + [false] = + { + // h_mirror = false + [false] = {false, false, false}, + [true] = {false, false, true}, + }, + [true] = + { + // h_mirror = true + [false] = {false, true, false}, + [true] = {false, true, true}, + }, + }, + { + // VPE_ROTATION_ANGLE_90 + [false] = + { + [false] = {true, false, true}, + [true] = {true, true, true}, + }, + [true] = + { + [false] = {true, false, false}, + [true] = {true, true, false}, + }, + }, + { + // VPE_ROTATION_ANGLE_180 + [false] = + { + [false] = {false, true, true}, + [true] = {false, true, false}, + }, + [true] = + { + [false] = {false, false, true}, + [true] = {false, false, false}, + }, + }, + { + // VPE_ROTATION_ANGLE_270 + [false] = + { + [false] = {true, true, false}, + [true] = {true, false, false}, + }, + [true] = + { + [false] = {true, true, true}, + [true] = {true, false, true}, + }, + }, +}; + +void vpe_get_vp_scan_direction(enum vpe_rotation_angle degree, bool h_mirror, bool v_mirror, + bool *orthogonal_rotation, bool *flip_horz_scan_dir, bool *flip_vert_scan_dir) +{ + struct vp_scan_direction res = vp_scan_direction[degree][h_mirror][v_mirror]; + + *orthogonal_rotation = res.orthogonal_rotation; + *flip_vert_scan_dir = res.flip_vert_scan_dir; + *flip_horz_scan_dir = res.flip_horz_scan_dir; +} + +static void determine_opp_recout_adjust(struct spl_in *spl_input, struct stream_ctx *stream_ctx, + struct output_ctx *output_ctx, const struct vpe_rect *clipped_src_rect, + const struct vpe_rect *clipped_dst_rect) +{ + struct vpe_caps *caps = stream_ctx->vpe_priv->pub.caps; + struct opp *opp = stream_ctx->vpe_priv->resource.opp[0]; + struct fmt_extra_pixel_info extra_info; + bool dst_subsampled = vpe_is_subsampled_format(output_ctx->surface.format); + + memset(&spl_input->basic_in.opp_recout_adjust, 0, sizeof(struct spl_opp_adjust)); + + opp->funcs->get_fmt_extra_pixel(output_ctx->surface.format, + stream_ctx->vpe_priv->init.debug.subsampling_quality, + (enum chroma_cositing)output_ctx->surface.cs.cositing, &extra_info); + + if (dst_subsampled) { + bool orthogonal, flip_horz, flip_vert; + + struct vpe_scaling_info *scaling_info = &stream_ctx->stream.scaling_info; + struct vpe_rect surf_src = *clipped_src_rect; + struct fixed31_32 h_ratio, temp; + int32_t offset; + + vpe_get_vp_scan_direction(stream_ctx->stream.rotation, stream_ctx->stream.horizontal_mirror, + stream_ctx->stream.vertical_mirror, &orthogonal, &flip_horz, &flip_vert); + + if (orthogonal) { + swap(surf_src.width, surf_src.height); + } + h_ratio = vpe_fixpt_from_fraction(surf_src.width, clipped_dst_rect->width); + + // see if the LEFT most needs more for output boundary handling, left needs 2 extra + temp = vpe_fixpt_mul_int(h_ratio, extra_info.left_pixels); + offset = (int32_t)vpe_fixpt_floor(temp); + + // default is REPEAT - destination stream is set manually beforehand + if (stream_ctx->stream_type != VPE_STREAM_TYPE_DESTINATION) { + stream_ctx->left = FMT_SUBSAMPLING_BOUNDARY_REPEAT; + stream_ctx->right = FMT_SUBSAMPLING_BOUNDARY_REPEAT; + } + + if (offset != 0) { + if (orthogonal) { + if (flip_vert) { + // i.e. left is at the bottom, check if it is out of bound + if ((clipped_src_rect->y + clipped_src_rect->height + offset) <= + (scaling_info->src_rect.y + scaling_info->src_rect.height)) { + /* can not directly modify the clipped_src_rect and clipped_dst_rect as it + * will break the recout alignment partitioning in spl becoz it assumes + * clipped_dst_rect is the same after opp */ + spl_input->basic_in.opp_recout_adjust.width += extra_info.left_pixels; + spl_input->basic_in.opp_recout_adjust.x -= extra_info.left_pixels; + stream_ctx->left = FMT_SUBSAMPLING_BOUNDARY_EXTRA; + } + } else { + // i.e. left is at the top, check if it is out of bound + if ((clipped_src_rect->y - scaling_info->src_rect.y) >= offset) { + spl_input->basic_in.opp_recout_adjust.width += extra_info.left_pixels; + spl_input->basic_in.opp_recout_adjust.x -= extra_info.left_pixels; + stream_ctx->left = FMT_SUBSAMPLING_BOUNDARY_EXTRA; + } + } + } else { + if (!flip_horz) { + if ((clipped_src_rect->x - scaling_info->src_rect.x) >= offset) { + spl_input->basic_in.opp_recout_adjust.width += extra_info.left_pixels; + spl_input->basic_in.opp_recout_adjust.x -= extra_info.left_pixels; + stream_ctx->left = FMT_SUBSAMPLING_BOUNDARY_EXTRA; + } + } else { + // right is left instead + if ((clipped_src_rect->x + clipped_src_rect->width + offset) <= + (scaling_info->src_rect.x + scaling_info->src_rect.width)) { + spl_input->basic_in.opp_recout_adjust.width += extra_info.left_pixels; + spl_input->basic_in.opp_recout_adjust.x -= extra_info.left_pixels; + stream_ctx->left = FMT_SUBSAMPLING_BOUNDARY_EXTRA; + } + } + } + } + + // see if the RIGHT most needs more for output boundary handling, right needs 1 extra + temp = vpe_fixpt_mul_int(h_ratio, extra_info.right_pixels); + offset = vpe_fixpt_floor(temp); + + if (offset != 0) { + if (orthogonal) { + if (flip_vert) { + // right is at the top + if ((clipped_src_rect->y - scaling_info->src_rect.y) >= offset) { + spl_input->basic_in.opp_recout_adjust.width += extra_info.right_pixels; + stream_ctx->right = FMT_SUBSAMPLING_BOUNDARY_EXTRA; + } + } else { + // right is at the bottom + if ((clipped_src_rect->y + clipped_src_rect->height + offset) <= + (scaling_info->src_rect.y + scaling_info->src_rect.height)) { + spl_input->basic_in.opp_recout_adjust.width += extra_info.right_pixels; + stream_ctx->left = FMT_SUBSAMPLING_BOUNDARY_EXTRA; + } + } + } else { + if (!flip_horz) { + if ((clipped_src_rect->x + clipped_src_rect->width + offset) <= + (scaling_info->src_rect.x + scaling_info->src_rect.width)) { + spl_input->basic_in.opp_recout_adjust.width += extra_info.right_pixels; + stream_ctx->right = FMT_SUBSAMPLING_BOUNDARY_EXTRA; + } + } else { + // left is right instead + if ((clipped_src_rect->x - scaling_info->src_rect.x) >= offset) { + spl_input->basic_in.opp_recout_adjust.width += extra_info.right_pixels; + stream_ctx->right = FMT_SUBSAMPLING_BOUNDARY_EXTRA; + } + } + } + } + } else { + stream_ctx->right = FMT_SUBSAMPLING_BOUNDARY_REPEAT; + stream_ctx->left = FMT_SUBSAMPLING_BOUNDARY_REPEAT; + } +} + +void vpe_init_spl_in( + struct spl_in *spl_input, struct stream_ctx *stream_ctx, struct output_ctx *output_ctx) +{ + enum color_space in_cs, out_cs; + enum color_transfer_func in_tf, out_tf; + + struct vpe_rect clipped_src_rect; + struct vpe_rect clipped_dst_rect; + + struct vpe_scaling_info *scaling_info = &stream_ctx->stream.scaling_info; + + vpe_color_get_color_space_and_tf(&stream_ctx->stream.surface_info.cs, &in_cs, &in_tf); + vpe_color_get_color_space_and_tf( + &stream_ctx->vpe_priv->output_ctx.surface.cs, &out_cs, &out_tf); + + /** Since the active values just set the mpc_size in SPL and vpelib calculates the mpc_size + * for each segment after the SPL call for segmentation, the active values does not affect the + * segmentation. Therefore, zero is set for the initialization to avoid NAN assignement. + * + * in vpe, we do not have mpc combine output from multiple input streams + * as such, we could not specify all output-related rect to use final coordinates, + * all output related rects are relative to the {0, 0 , dst_width, dst_height} only + */ + spl_input->h_active = 0; + spl_input->v_active = 0; + + // BASIC_OUT + clipped_src_rect = scaling_info->src_rect; + clipped_dst_rect = scaling_info->dst_rect; + + vpe_clip_stream(&clipped_src_rect, &clipped_dst_rect, &output_ctx->target_rect); + + determine_opp_recout_adjust( + spl_input, stream_ctx, output_ctx, &clipped_src_rect, &clipped_dst_rect); + + // struct spl_size output_size; // Output Size + spl_input->basic_out.output_size.width = scaling_info->dst_rect.width; + spl_input->basic_out.output_size.height = scaling_info->dst_rect.height; + + // do not have 2-stages scaling concept in usage, set basic_out src_rect = dst_rect + spl_input->basic_out.src_rect.x = 0; + spl_input->basic_out.src_rect.y = 0; + spl_input->basic_out.src_rect.width = scaling_info->dst_rect.width; + spl_input->basic_out.src_rect.height = scaling_info->dst_rect.height; + spl_input->basic_out.dst_rect = spl_input->basic_out.src_rect; + + // int odm_combine_factor; // deprecated + spl_input->basic_out.odm_combine_factor = 1; + spl_input->basic_out.alpha_en = stream_ctx->per_pixel_alpha; + + // BASIC_IN + // enum spl_pixel_format format; // Pixel Format + spl_input->basic_in.format = get_spl_format(stream_ctx->stream.surface_info.format); + // enum chroma_cositing cositing; /* Chroma Subsampling Offset */ + spl_input->basic_in.cositing = get_spl_cositing(stream_ctx->stream.surface_info.cs.cositing); + if (stream_ctx->stream.lut_compound.enabled) { + // In 3DLUT compound case, cs is "custom" with no cositing info + // It is provided separately via lut_compound.chroma_cositing + spl_input->basic_in.cositing = + get_spl_cositing(stream_ctx->stream.lut_compound.upsampled_chroma_input); + } else if (vpe_is_yuv422(stream_ctx->stream.surface_info.format)) { + // Force TOPLEFT cositing for 422 as other cositing modes have vertical adjustment + spl_input->basic_in.cositing = CHROMA_COSITING_TOPLEFT; + } + // struct spl_rect src_rect; // Source rect + vpe_rect_to_spl_rect(&scaling_info->src_rect, &spl_input->basic_in.src_rect); + + // struct spl_rect dst_rect; // Destination Rect + // spl shall only know the relative location of the output. + // the final absolute destination rect is adjusted in calculate_dst_viewport_and_active + spl_input->basic_in.dst_rect.x = 0; + spl_input->basic_in.dst_rect.y = 0; + spl_input->basic_in.dst_rect.width = scaling_info->dst_rect.width; + spl_input->basic_in.dst_rect.height = scaling_info->dst_rect.height; + + // enum spl_rotation_angle rotation; // Rotation + // bool horizontal_mirror; // Horizontal mirror + get_spl_rotation(vpe_get_scan_direction(stream_ctx->stream.rotation, + stream_ctx->stream.horizontal_mirror, stream_ctx->stream.vertical_mirror), + &spl_input->basic_in.rotation, &spl_input->basic_in.horizontal_mirror); + + // int mpc_num_h_slices; // MPC Horizontal Combine Factor (number of segments/horizintal slices) + spl_input->basic_in.num_h_slices_recout_width_align.use_recout_width_aligned = false; + spl_input->basic_in.num_h_slices_recout_width_align.num_slices_recout_width.mpc_num_h_slices = + stream_ctx->num_segments; + // enum spl_transfer_func_type tf_type; /* Transfer function type */ + spl_input->basic_in.tf_type = SPL_TF_TYPE_DISTRIBUTED_POINTS; + // enum spl_transfer_func_predefined tf_predefined_type; /* Transfer function predefined type */ + spl_input->basic_in.tf_predefined_type = get_spl_tf(in_tf); + // enum spl_color_space color_space; // Color Space + spl_input->basic_in.color_space = get_spl_cs(in_cs); + // unsigned int max_luminance; // Max Luminance + spl_input->basic_in.max_luminance = 80; + // struct spl_rect clip_rect; // Clip rect + set_clip_rect(&spl_input->basic_in.clip_rect, scaling_info->dst_rect, clipped_dst_rect); + // int odm_slice_index; // ODM Slice Index using get_odm_split_index + spl_input->odm_slice_index = 0; + // struct spl_taps scaling_quality; // Explicit Scaling Quality + spl_input->scaling_quality.v_taps = scaling_info->taps.v_taps; + spl_input->scaling_quality.h_taps = scaling_info->taps.h_taps; + spl_input->scaling_quality.v_taps_c = scaling_info->taps.v_taps_c; + spl_input->scaling_quality.h_taps_c = scaling_info->taps.h_taps_c; + spl_input->scaling_quality.integer_scaling = false; + spl_input->is_hdr_on = vpe_is_HDR(out_tf); + spl_input->adaptive_sharpness.enable = scaling_info->adaptive_sharpeness.enable; + spl_input->adaptive_sharpness.sharpness_level = + scaling_info->adaptive_sharpeness.sharpness_level; + spl_input->adaptive_sharpness.sharpness_range = SHARPNESS_RANGE; // to be passed by the caller + spl_input->sharpen_policy = SHARPEN_ALWAYS; + spl_input->disable_easf = !scaling_info->enable_easf; + spl_input->prefer_easf = scaling_info->prefer_easf; + + if (vpe_is_subsampled_format(stream_ctx->stream.surface_info.format)) { + spl_input->min_viewport_size = 2; + } else { + spl_input->min_viewport_size = 1; + } +} + +void vpe_scl_to_dscl_bg(struct scaler_data *scl_data) +{ + // struct spl_rect recout; + vpe_rect_to_spl_rect(&scl_data->recout, &scl_data->dscl_prog_data.recout); + // struct mpc_size mpc_size; + scl_data->dscl_prog_data.mpc_size.width = scl_data->h_active; + scl_data->dscl_prog_data.mpc_size.height = scl_data->v_active; + + // struct ratio ratios; + scl_data->dscl_prog_data.ratios.h_scale_ratio = vpe_fixpt_u3d19(scl_data->ratios.horz) << 5; + scl_data->dscl_prog_data.ratios.v_scale_ratio = vpe_fixpt_u3d19(scl_data->ratios.vert) << 5; + scl_data->dscl_prog_data.ratios.h_scale_ratio_c = vpe_fixpt_u3d19(scl_data->ratios.horz_c) << 5; + scl_data->dscl_prog_data.ratios.v_scale_ratio_c = vpe_fixpt_u3d19(scl_data->ratios.vert_c) << 5; + + // struct init init; + scl_data->dscl_prog_data.init.h_filter_init_frac = vpe_fixpt_u0d19(scl_data->inits.h) << 5; + scl_data->dscl_prog_data.init.h_filter_init_int = vpe_fixpt_floor(scl_data->inits.h); + scl_data->dscl_prog_data.init.h_filter_init_frac_c = vpe_fixpt_u0d19(scl_data->inits.h_c) << 5; + scl_data->dscl_prog_data.init.h_filter_init_int_c = vpe_fixpt_floor(scl_data->inits.h_c); + scl_data->dscl_prog_data.init.v_filter_init_frac = vpe_fixpt_u0d19(scl_data->inits.v) << 5; + scl_data->dscl_prog_data.init.v_filter_init_int = vpe_fixpt_floor(scl_data->inits.v); + scl_data->dscl_prog_data.init.v_filter_init_frac_c = vpe_fixpt_u0d19(scl_data->inits.v_c) << 5; + scl_data->dscl_prog_data.init.v_filter_init_int_c = vpe_fixpt_floor(scl_data->inits.v_c); + + // struct spl_taps taps; // TAPS - set based on scl_data.taps + scl_data->dscl_prog_data.taps.h_taps = scl_data->taps.h_taps - 1; + scl_data->dscl_prog_data.taps.v_taps = scl_data->taps.v_taps - 1; + scl_data->dscl_prog_data.taps.h_taps_c = scl_data->taps.h_taps_c - 1; + scl_data->dscl_prog_data.taps.v_taps_c = scl_data->taps.v_taps_c - 1; + + // struct spl_rect viewport; + vpe_rect_to_spl_rect(&scl_data->viewport, &scl_data->dscl_prog_data.viewport); + // struct spl_rect viewport_c; + vpe_rect_to_spl_rect(&scl_data->viewport_c, &scl_data->dscl_prog_data.viewport_c); +} diff --git a/src/amd/vpelib/src/core/vpe_visual_confirm.c b/src/amd/vpelib/src/core/vpe_visual_confirm.c index cf8b2407e51..074dd925b74 100644 --- a/src/amd/vpelib/src/core/vpe_visual_confirm.c +++ b/src/amd/vpelib/src/core/vpe_visual_confirm.c @@ -66,6 +66,8 @@ static uint16_t vpe_get_visual_confirm_total_seg_count( uint16_t stream_idx; struct stream_ctx *stream_ctx; uint32_t alignment = vpe_get_recout_width_alignment(params); + struct vpe_cmd_info *cmd_info; + uint16_t cmd_idx; if (vpe_priv->init.debug.visual_confirm_params.input_format) { for (stream_idx = 0; stream_idx < (uint16_t)vpe_priv->num_streams; stream_idx++) { @@ -81,9 +83,59 @@ static uint16_t vpe_get_visual_confirm_total_seg_count( get_visual_confirm_segs_count(max_seg_width, params->target_rect.width, alignment); } + if (vpe_priv->init.debug.visual_confirm_params.pipe_idx) { + cmd_info = vpe_priv->vpe_cmd_vector->element; + for (cmd_idx = 0; cmd_idx < (uint16_t)vpe_priv->vpe_cmd_vector->num_elements; cmd_idx++) { + total_visual_confirm_segs += cmd_info->num_inputs; + cmd_info++; + } + } + return total_visual_confirm_segs; } +static void generate_pipe_segments(struct vpe_priv *vpe_priv, const struct vpe_build_param *params, + struct vpe_rect *current_gap, uint32_t max_seg_width) +{ + uint16_t cmd_idx, input_idx, seg_cnt; + struct vpe_cmd_info *cmd_info; + struct vpe_rect visual_confirm_rect; + uint32_t recout_alignment = vpe_get_recout_width_alignment(params); + + if (vpe_priv->init.debug.visual_confirm_params.pipe_idx && + params->target_rect.height > 3 * VISUAL_CONFIRM_HEIGHT) { + cmd_info = vpe_priv->vpe_cmd_vector->element; + for (cmd_idx = 0; cmd_idx < (uint16_t)vpe_priv->vpe_cmd_vector->num_elements; cmd_idx++) { + if (cmd_info->ops == VPE_CMD_OPS_BG_VSCF_INPUT || + cmd_info->ops == VPE_CMD_OPS_BG_VSCF_OUTPUT || + cmd_info->ops == VPE_CMD_OPS_BG_VSCF_PIPE0 || + cmd_info->ops == VPE_CMD_OPS_BG_VSCF_PIPE1) { + cmd_info++; + continue; + } + for (input_idx = 0; input_idx < cmd_info->num_inputs; input_idx++) { + visual_confirm_rect = cmd_info->inputs[input_idx].scaler_data.dst_viewport; + visual_confirm_rect.height = VISUAL_CONFIRM_HEIGHT; + visual_confirm_rect.y += 2 * VISUAL_CONFIRM_HEIGHT; + seg_cnt = get_visual_confirm_segs_count( + max_seg_width, visual_confirm_rect.width, recout_alignment); + vpe_full_bg_gaps(current_gap, &visual_confirm_rect, recout_alignment, seg_cnt); + if (input_idx == 0) { + vpe_priv->resource.create_bg_segments( + vpe_priv, current_gap, seg_cnt, VPE_CMD_OPS_BG_VSCF_PIPE0); + } else if (input_idx == 1) { + vpe_priv->resource.create_bg_segments( + vpe_priv, current_gap, seg_cnt, VPE_CMD_OPS_BG_VSCF_PIPE1); + } else { + VPE_ASSERT(0); + } + current_gap += seg_cnt; + } + cmd_info++; + } + } +} + struct vpe_color vpe_get_visual_confirm_color(struct vpe_priv *vpe_priv, enum vpe_surface_pixel_format format, struct vpe_color_space cs, enum color_space output_cs, struct transfer_func *output_tf, enum vpe_surface_pixel_format output_format, bool enable_3dlut) @@ -99,6 +151,7 @@ struct vpe_color vpe_get_visual_confirm_color(struct vpe_priv *vpe_priv, switch (format) { case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ALPHA_THRU_LUMA: // YUV420 8bit: Green visual_confirm_color.rgba.r = 0.0; visual_confirm_color.rgba.g = 1.0; @@ -165,6 +218,121 @@ struct vpe_color vpe_get_visual_confirm_color(struct vpe_priv *vpe_priv, visual_confirm_color.rgba.g = 0.65f; visual_confirm_color.rgba.b = 0.0; break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_420_12bpc_YCbCr: + // P016 : Dark Green + visual_confirm_color.rgba.r = 0.0; + visual_confirm_color.rgba.g = 0.35f; + visual_confirm_color.rgba.b = 0.0; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_UNORM: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616_UNORM: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_SNORM: + case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616_SNORM: + // RGB16 and variants: Blue + visual_confirm_color.rgba.r = 0.0; + visual_confirm_color.rgba.g = 0.0; + visual_confirm_color.rgba.b = 1.0; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_R8: + // Monochrome 8 bit: Silver + visual_confirm_color.rgba.r = 0.753f; + visual_confirm_color.rgba.g = 0.753f; + visual_confirm_color.rgba.b = 0.753f; + break; + + case VPE_SURFACE_PIXEL_FORMAT_GRPH_R16: + // Monochrome 16 bit: Dim Gray + visual_confirm_color.rgba.r = 0.412f; + visual_confirm_color.rgba.g = 0.412f; + visual_confirm_color.rgba.b = 0.412f; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_YCbCr: + // YUY2: Misty Rose + visual_confirm_color.rgba.r = 0.412f; + visual_confirm_color.rgba.g = 0.894f; + visual_confirm_color.rgba.b = 0.882f; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_CbYCrY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_10bpc_YCbCr: + // Y210: Salmon + visual_confirm_color.rgba.r = 0.412f; + visual_confirm_color.rgba.g = 0.627f; + visual_confirm_color.rgba.b = 0.478f; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrYCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbYCr: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CrYCbY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_CbYCrY: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCrCb: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_422_12bpc_YCbCr: + // Y216: Maroon + visual_confirm_color.rgba.r = 0.5; + visual_confirm_color.rgba.g = 0.0; + visual_confirm_color.rgba.b = 0.0; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrCbYA8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_YCrCbA8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA8888: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888: + // AYUV: Aqua Marine + visual_confirm_color.rgba.r = 0.5; + visual_confirm_color.rgba.g = 1.0; + visual_confirm_color.rgba.b = 0.8f; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: + // Y410: Dark Cyan + visual_confirm_color.rgba.r = 0.0; + visual_confirm_color.rgba.g = 0.5; + visual_confirm_color.rgba.b = 0.5; + break; + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb12121212: + case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA12121212: + // Y416: Navy + visual_confirm_color.rgba.r = 0.0; + visual_confirm_color.rgba.g = 0.0; + visual_confirm_color.rgba.b = 0.5; + break; + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_RGB: + // Planar RGB8: Lavender + visual_confirm_color.rgba.r = 0.9f; + visual_confirm_color.rgba.g = 0.9f; + visual_confirm_color.rgba.b = 0.98f; + break; + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_YCbCr: + // Planar YCbCr8: Chocolate + visual_confirm_color.rgba.r = 0.824f; + visual_confirm_color.rgba.g = 0.412f; + visual_confirm_color.rgba.b = 0.118f; + break; + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_RGB: + // Planar RGB16: Rosy Brown + visual_confirm_color.rgba.r = 0.737f; + visual_confirm_color.rgba.g = 0.56f; + visual_confirm_color.rgba.b = 0.56f; + break; + case VPE_SURFACE_PIXEL_FORMAT_PLANAR_16bpc_YCbCr: + // Planar YCbCr16: Saddle Brown + visual_confirm_color.rgba.r = 0.545f; + visual_confirm_color.rgba.g = 0.271f; + visual_confirm_color.rgba.b = 0.075f; + break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE: + // RGBE: Olive + visual_confirm_color.rgba.r = 0.5; + visual_confirm_color.rgba.g = 0.5; + visual_confirm_color.rgba.b = 0.0; + break; default: break; } @@ -236,6 +404,8 @@ enum vpe_status vpe_create_visual_confirm_segs( current_gap += seg_cnt; } + generate_pipe_segments(vpe_priv, params, current_gap, max_seg_width); + if (visual_confirm_gaps != NULL) { vpe_free(visual_confirm_gaps); visual_confirm_gaps = NULL; diff --git a/src/amd/vpelib/src/core/vpelib.c b/src/amd/vpelib/src/core/vpelib.c index c184d7bd6e4..38e2a4814c8 100644 --- a/src/amd/vpelib/src/core/vpelib.c +++ b/src/amd/vpelib/src/core/vpelib.c @@ -40,6 +40,7 @@ #include #include #include +#include "multi_pipe_segmentation.h" static void dummy_sys_event(enum vpe_event_id eventId, ...) { @@ -135,6 +136,11 @@ static void override_debug_option( if (user_debug->flags.disable_performance_mode) debug->disable_performance_mode = user_debug->disable_performance_mode; + if (user_debug->flags.subsampling_quality) + debug->subsampling_quality = user_debug->subsampling_quality; + + if (user_debug->flags.disable_3dlut_fl) + debug->disable_3dlut_fl = user_debug->disable_3dlut_fl; } static void verify_collaboration_mode(struct vpe_priv *vpe_priv) @@ -189,6 +195,9 @@ static void free_output_ctx(struct vpe_priv *vpe_priv) vpe_free(vpe_priv->output_ctx.output_tf); vpe_priv->output_ctx.output_tf = NULL; + if (vpe_priv->output_ctx.out_csc_matrix) + vpe_free(vpe_priv->output_ctx.out_csc_matrix); + vpe_priv->output_ctx.out_csc_matrix = NULL; destroy_output_config_vector(vpe_priv); } @@ -295,6 +304,8 @@ struct vpe *vpe_create(const struct vpe_init_data *params) vpe_priv->scale_yuv_matrix = true; vpe_priv->collaborate_sync_index = 0; + if (vpe_priv->init.debug.disable_3dlut_fl) /* disable DMA 3D LUT support for debugging */ + vpe_priv->pub.caps->color_caps.mpc.dma_3d_lut = 0; return &vpe_priv->pub; } @@ -333,6 +344,81 @@ void vpe_destroy(struct vpe **vpe) *vpe = NULL; } +/***************************************************************************************** + * populate_destination_stream + * populate destination stream for multi-pass blending + * struct vpe* vpe + * [input] vpe context + * const struct vpe_build_param* param + * [input] original parameter from caller + * struct struct vpe_stream_ctx* stream_ctx + * [input/output] caller provided vpe_stream_ctx struct to populate + *****************************************************************************************/ +static enum vpe_status populate_destination_stream( + struct vpe_priv *vpe_priv, const struct vpe_build_param *param, struct stream_ctx *stream_ctx) +{ + struct vpe_surface_info *surface_info; + struct vpe_scaling_info *scaling_info; + struct vpe_scaling_filter_coeffs *polyphaseCoeffs; + struct vpe_stream *stream; + struct output_ctx *output_ctx; + + if (!param || !stream_ctx) + return VPE_STATUS_ERROR; + + stream = &stream_ctx->stream; + output_ctx = &vpe_priv->output_ctx; + stream_ctx->stream_type = VPE_STREAM_TYPE_DESTINATION; + + // set output surface as our destination input + surface_info = &stream->surface_info; + scaling_info = &stream->scaling_info; + polyphaseCoeffs = &stream->polyphase_scaling_coeffs; + + memcpy(&stream->surface_info, &output_ctx->surface, sizeof(struct vpe_surface_info)); + + stream_ctx->cs = output_ctx->cs; + + scaling_info->src_rect.x = param->target_rect.x; + scaling_info->src_rect.y = param->target_rect.y; + scaling_info->src_rect.width = param->target_rect.width; + scaling_info->src_rect.height = param->target_rect.height; + scaling_info->dst_rect.x = param->target_rect.x; + scaling_info->dst_rect.y = param->target_rect.y; + scaling_info->dst_rect.width = param->target_rect.width; + scaling_info->dst_rect.height = param->target_rect.height; + scaling_info->taps.v_taps = 0; + scaling_info->taps.h_taps = 0; + scaling_info->taps.v_taps_c = 0; + scaling_info->taps.h_taps_c = 0; + + polyphaseCoeffs->taps = scaling_info->taps; + polyphaseCoeffs->nb_phases = 64; + + stream->blend_info.blending = false; + stream->blend_info.pre_multiplied_alpha = false; + stream->blend_info.global_alpha = true; + stream->blend_info.global_alpha_value = 1.0f; + + stream->color_adj.brightness = 0.0f; + stream->color_adj.contrast = 1.0f; + stream->color_adj.hue = 0.0f; + stream->color_adj.saturation = 1.0f; + stream->rotation = VPE_ROTATION_ANGLE_0; + stream->horizontal_mirror = false; + stream->vertical_mirror = false; + stream->enable_luma_key = false; + stream->lower_luma_bound = 0; + stream->upper_luma_bound = 0; + stream->hdr_metadata = output_ctx->hdr_metadata; + + stream->flags.hdr_metadata = 1; + stream->flags.geometric_scaling = 0; + stream->use_external_scaling_coeffs = false; + + return VPE_STATUS_OK; +} + /***************************************************************************************** * populate_bg_stream * populate virtual stream for background output only @@ -423,12 +509,21 @@ static enum vpe_status populate_bg_stream(struct vpe_priv *vpe_priv, const struc static uint32_t get_required_virtual_stream_count(struct vpe_priv *vpe_priv, const struct vpe_build_param *param) { uint32_t result = 0; + uint32_t i; // Check for zero-input background stream // Normally we result++ instead of returning, but bg_color_fill_only removes other streams (and therefore other features) if (param->num_streams == 0 || vpe_priv->init.debug.bg_color_fill_only) return 1; + // Check for destination stream for multi-pass blending + for (i = 1; i < param->num_streams; i++) { + if (param->streams[i].blend_info.blending) { + result++; + break; + } + } + return result; } @@ -444,6 +539,46 @@ static enum vpe_status populate_input_streams(struct vpe_priv *vpe_priv, const s for (i = 0; i < vpe_priv->num_input_streams; i++) { stream_ctx = &stream_ctx_base[i]; stream_ctx->stream_type = VPE_STREAM_TYPE_INPUT; + // BGR feature streams + if (param->streams[i].flags.is_alpha_combine) { + // Stream is part of bg replace feature + + if (!vpe_has_per_pixel_alpha(vpe_priv->output_ctx.surface.format)) { + // Output surface must support alpha if we are doing bg replace + return VPE_STATUS_PARAM_CHECK_ERROR; + } + + if (param->streams[i].flags.is_alpha_plane) { + if (param->streams[i].surface_info.format != + VPE_SURFACE_PIXEL_FORMAT_VIDEO_ALPHA_THRU_LUMA) + return VPE_STATUS_PARAM_CHECK_ERROR; + stream_ctx->stream_type = VPE_STREAM_TYPE_BKGR_ALPHA; + if (vpe_priv->num_input_streams <= i + 2) + // Sanity check: Check we pass in enough planes for bg replace (this + 2) + return VPE_STATUS_PARAM_CHECK_ERROR; + else if (param->streams[i + VPE_BKGR_STREAM_VIDEO_OFFSET].flags.is_alpha_combine == + 0 || + param->streams[i + VPE_BKGR_STREAM_BACKGROUND_OFFSET] + .flags.is_background_plane == 0) + // Sanity check: Check we pass in video stream next + return VPE_STATUS_PARAM_CHECK_ERROR; + } else if (param->streams[i].flags.is_background_plane) { + stream_ctx->stream_type = VPE_STREAM_TYPE_BKGR_BACKGROUND; + if (i < 2) + return VPE_STATUS_PARAM_CHECK_ERROR; + else if (param->streams[i - VPE_BKGR_STREAM_BACKGROUND_OFFSET] + .flags.is_alpha_plane == false || + param->streams[i - VPE_BKGR_STREAM_VIDEO_OFFSET].flags.is_alpha_combine == + false) + // Sanity check: Ensure two previous streams are part of BGR op + return VPE_STATUS_PARAM_CHECK_ERROR; + } else { + stream_ctx->stream_type = VPE_STREAM_TYPE_BKGR_VIDEO; + } + } + if (vpe_validate_hist_collection(¶m->streams[i]) == false) { + return VPE_INVALID_HISTOGRAM_SELECTION; + } stream_ctx->stream_idx = (int32_t)i; stream_ctx->per_pixel_alpha = @@ -462,6 +597,13 @@ static enum vpe_status populate_input_streams(struct vpe_priv *vpe_priv, const s stream_ctx->flip_horizonal_output = false; memcpy(&stream_ctx->stream, ¶m->streams[i], sizeof(struct vpe_stream)); + if (stream_ctx->stream_type == VPE_STREAM_TYPE_BKGR_ALPHA) { + stream_ctx->stream.blend_info.blending = true; + stream_ctx->per_pixel_alpha = true; + } else if (stream_ctx->stream_type == VPE_STREAM_TYPE_BKGR_BACKGROUND) { + stream_ctx->stream.blend_info.blending = true; + stream_ctx->per_pixel_alpha = true; + } } return result; @@ -473,6 +615,7 @@ static enum vpe_status populate_virtual_streams(struct vpe_priv* vpe_priv, const uint32_t virtual_stream_idx = 0; struct stream_ctx *stream_ctx; bool input_h_mirror, output_h_mirror; + uint32_t i; vpe_priv->resource.check_h_mirror_support(&input_h_mirror, &output_h_mirror); @@ -484,6 +627,18 @@ static enum vpe_status populate_virtual_streams(struct vpe_priv* vpe_priv, const result = populate_bg_stream(vpe_priv, param, &stream_ctx_base[virtual_stream_idx++]); } + if (result != VPE_STATUS_OK) + return result; + + // Destination stream for multi-pass blending + for (i = 1; i < param->num_streams; i++) { + if (param->streams[i].blend_info.blending) { + result = populate_destination_stream( + vpe_priv, param, &stream_ctx_base[virtual_stream_idx++]); + break; + } + } + if (result != VPE_STATUS_OK) return result; @@ -564,6 +719,10 @@ enum vpe_status vpe_check_support( vpe_log("fail alplha fill check. status %d\n", (int)status); } } + for (i = 0; i < param->num_streams; i++) + if (vpe_priv->stream_ctx != NULL) + if (vpe_priv->stream_ctx[i].mps_ctx) + vpe_clear_mps_ctx(vpe_priv, vpe_priv->stream_ctx[i].mps_ctx); if (status == VPE_STATUS_OK) { // output checking - check per asic support @@ -594,6 +753,19 @@ enum vpe_status vpe_check_support( break; } + // input checking - check 3dlut compound support + status = vpe_check_3dlut_compound(vpe, ¶m->streams[i], param); + if (status != VPE_STATUS_OK) { + vpe_log("fail 3dlut support check. status %d\n", (int)status); + break; + } + // histogram support check + status = vpe_check_histogram_support(vpe, ¶m->streams[i]); + if (status != VPE_STATUS_OK) { + vpe_log("fail histogram support check. status %d\n", (int)status); + break; + } + } } if (status == VPE_STATUS_OK) { @@ -610,6 +782,17 @@ enum vpe_status vpe_check_support( vpe_vector_clear(vpe_priv->vpe_cmd_vector); output_ctx->clamping_params = vpe_priv->init.debug.clamping_params; } + if (status == VPE_STATUS_OK && param->frod_param.enable_frod) { + if (vpe->caps->frod_support) { + status = vpe_priv->resource.populate_frod_param(vpe_priv, param); + if (status != VPE_STATUS_OK) { + vpe_log("fail frod support check. status %d\n", (int)status); + } + } else { + status = VPE_STATUS_FROD_NOT_SUPPORTED; + vpe_log("fail frod support check. status %d\n", (int)status); + } + } if (status == VPE_STATUS_OK) { status = populate_input_streams(vpe_priv, param, vpe_priv->stream_ctx); diff --git a/src/amd/vpelib/src/imported/SPL/Makefile b/src/amd/vpelib/src/imported/SPL/Makefile new file mode 100644 index 00000000000..5e3e4aa1382 --- /dev/null +++ b/src/amd/vpelib/src/imported/SPL/Makefile @@ -0,0 +1,33 @@ +# +# Copyright 2017 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# +# Makefile for the 'spl' sub-component of DAL. +# It provides the scaling library interface. + +SPL = dc_spl.o dc_spl_scl_filters.o dc_spl_scl_easf_filters.o dc_spl_isharp_filters.o dc_spl_filters.o spl_fixpt31_32.o spl_custom_float.o + +AMD_DAL_SPL = $(addprefix $(AMDDALPATH)/dc/sspl/,$(SPL)) + +AMD_DISPLAY_FILES += $(AMD_DAL_SPL) + + + diff --git a/src/amd/vpelib/src/imported/SPL/dc_spl.c b/src/amd/vpelib/src/imported/SPL/dc_spl.c new file mode 100644 index 00000000000..25485bf2474 --- /dev/null +++ b/src/amd/vpelib/src/imported/SPL/dc_spl.c @@ -0,0 +1,2176 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2024 Advanced Micro Devices, Inc. + +#include "dc_spl.h" +#include "dc_spl_scl_easf_filters.h" +#include "dc_spl_isharp_filters.h" +#include "spl_debug.h" + +#define IDENTITY_RATIO(ratio) (SPL_NAMESPACE(spl_fixpt_u3d19(ratio)) == (1 << 19)) +#define MIN_VIEWPORT_SIZE 12 + +static bool spl_is_yuv420(enum spl_pixel_format format) +{ + if ((format >= SPL_PIXEL_FORMAT_420BPP8) && + (format <= SPL_PIXEL_FORMAT_420BPP10)) + return true; + + return false; +} + +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) +static bool spl_is_yuv422(enum spl_pixel_format format) +{ + if ((format >= SPL_PIXEL_FORMAT_422BPP8) && + (format <= SPL_PIXEL_FORMAT_422BPP12)) + return true; + + return false; +} + +#endif +static bool spl_is_rgb8(enum spl_pixel_format format) +{ + if (format == SPL_PIXEL_FORMAT_ARGB8888) + return true; + + return false; +} + +static bool spl_is_video_format(enum spl_pixel_format format) +{ + if (format >= SPL_PIXEL_FORMAT_VIDEO_BEGIN + && format <= SPL_PIXEL_FORMAT_VIDEO_END) + return true; + else + return false; +} + +static bool spl_is_subsampled_format(enum spl_pixel_format format) +{ + if (format >= SPL_PIXEL_FORMAT_SUBSAMPLED_BEGIN + && format <= SPL_PIXEL_FORMAT_SUBSAMPLED_END) + return true; + else + return false; +} + +static struct spl_rect intersect_rec(const struct spl_rect *r0, const struct spl_rect *r1) +{ + struct spl_rect rec; + int r0_x_end = r0->x + r0->width; + int r1_x_end = r1->x + r1->width; + int r0_y_end = r0->y + r0->height; + int r1_y_end = r1->y + r1->height; + + rec.x = r0->x > r1->x ? r0->x : r1->x; + rec.width = r0_x_end > r1_x_end ? r1_x_end - rec.x : r0_x_end - rec.x; + rec.y = r0->y > r1->y ? r0->y : r1->y; + rec.height = r0_y_end > r1_y_end ? r1_y_end - rec.y : r0_y_end - rec.y; + + /* in case that there is no intersection */ + if (rec.width < 0 || rec.height < 0) + memset(&rec, 0, sizeof(rec)); + + return rec; +} + +static struct spl_rect shift_rec(const struct spl_rect *rec_in, int x, int y) +{ + struct spl_rect rec_out = *rec_in; + + rec_out.x += x; + rec_out.y += y; + + return rec_out; +} + +static void spl_opp_adjust_rect(struct spl_rect *rec, const struct spl_opp_adjust *adjust) +{ + if ((rec->x + adjust->x) >= 0) + rec->x += adjust->x; + + if ((rec->y + adjust->y) >= 0) + rec->y += adjust->y; + + if ((rec->width + adjust->width) >= 1) + rec->width += adjust->width; + + if ((rec->height + adjust->height) >= 1) + rec->height += adjust->height; +} + +static struct spl_rect calculate_plane_rec_in_timing_active( + struct spl_in *spl_in, + const struct spl_rect *rec_in) +{ + /* + * The following diagram shows an example where we map a 1920x1200 + * desktop to a 2560x1440 timing with a plane rect in the middle + * of the screen. To map a plane rect from Stream Source to Timing + * Active space, we first multiply stream scaling ratios (i.e 2304/1920 + * horizontal and 1440/1200 vertical) to the plane's x and y, then + * we add stream destination offsets (i.e 128 horizontal, 0 vertical). + * This will give us a plane rect's position in Timing Active. However + * we have to remove the fractional. The rule is that we find left/right + * and top/bottom positions and round the value to the adjacent integer. + * + * Stream Source Space + * ------------ + * __________________________________________________ + * |Stream Source (1920 x 1200) ^ | + * | y | + * | <------- w --------|> | + * | __________________V | + * |<-- x -->|Plane//////////////| ^ | + * | |(pre scale)////////| | | + * | |///////////////////| | | + * | |///////////////////| h | + * | |///////////////////| | | + * | |///////////////////| | | + * | |///////////////////| V | + * | | + * | | + * |__________________________________________________| + * + * + * Timing Active Space + * --------------------------------- + * + * Timing Active (2560 x 1440) + * __________________________________________________ + * |*****| Stteam Destination (2304 x 1440) |*****| + * |*****| |*****| + * |<128>| |*****| + * |*****| __________________ |*****| + * |*****| |Plane/////////////| |*****| + * |*****| |(post scale)//////| |*****| + * |*****| |//////////////////| |*****| + * |*****| |//////////////////| |*****| + * |*****| |//////////////////| |*****| + * |*****| |//////////////////| |*****| + * |*****| |*****| + * |*****| |*****| + * |*****| |*****| + * |*****|______________________________________|*****| + * + * So the resulting formulas are shown below: + * + * recout_x = 128 + round(plane_x * 2304 / 1920) + * recout_w = 128 + round((plane_x + plane_w) * 2304 / 1920) - recout_x + * recout_y = 0 + round(plane_y * 1440 / 1200) + * recout_h = 0 + round((plane_y + plane_h) * 1440 / 1200) - recout_y + * + * NOTE: fixed point division is not error free. To reduce errors + * introduced by fixed point division, we divide only after + * multiplication is complete. + */ + const struct spl_rect *stream_src = &spl_in->basic_out.src_rect; + const struct spl_rect *stream_dst = &spl_in->basic_out.dst_rect; + struct spl_rect rec_out = {0}; + struct spl_fixed31_32 temp; + + + temp = SPL_NAMESPACE(spl_fixpt_from_fraction( + rec_in->x * (long long)stream_dst->width, + stream_src->width)); + rec_out.x = stream_dst->x + spl_fixpt_round(temp); + + temp = SPL_NAMESPACE(spl_fixpt_from_fraction( + (rec_in->x + rec_in->width) * (long long)stream_dst->width, + stream_src->width)); + rec_out.width = stream_dst->x + spl_fixpt_round(temp) - rec_out.x; + + temp = SPL_NAMESPACE(spl_fixpt_from_fraction( + rec_in->y * (long long)stream_dst->height, + stream_src->height)); + rec_out.y = stream_dst->y + spl_fixpt_round(temp); + + temp = SPL_NAMESPACE(spl_fixpt_from_fraction( + (rec_in->y + rec_in->height) * (long long)stream_dst->height, + stream_src->height)); + rec_out.height = stream_dst->y + spl_fixpt_round(temp) - rec_out.y; + + return rec_out; +} + +static struct spl_rect calculate_mpc_slice_in_timing_active( + struct spl_in *spl_in, + struct spl_rect *plane_clip_rec) +{ + bool use_recout_width_aligned = + spl_in->basic_in.num_h_slices_recout_width_align.use_recout_width_aligned; + int mpc_slice_count = + spl_in->basic_in.num_h_slices_recout_width_align.num_slices_recout_width.mpc_num_h_slices; + int recout_width_align = + spl_in->basic_in.num_h_slices_recout_width_align.num_slices_recout_width.mpc_recout_width_align; + int mpc_slice_idx = spl_in->basic_in.mpc_h_slice_index; + int epimo = mpc_slice_count - plane_clip_rec->width % mpc_slice_count - 1; + struct spl_rect mpc_rec; + + if (spl_in->basic_in.custom_width != 0) { + mpc_rec.width = spl_in->basic_in.custom_width; + mpc_rec.x = spl_in->basic_in.custom_x; + mpc_rec.height = plane_clip_rec->height; + mpc_rec.y = plane_clip_rec->y; + } else if (use_recout_width_aligned) { + mpc_rec.width = recout_width_align; + if ((mpc_rec.width * (mpc_slice_idx + 1)) > plane_clip_rec->width) { + mpc_rec.width = plane_clip_rec->width % recout_width_align; + mpc_rec.x = plane_clip_rec->x + recout_width_align * mpc_slice_idx; + } else + mpc_rec.x = plane_clip_rec->x + mpc_rec.width * mpc_slice_idx; + mpc_rec.height = plane_clip_rec->height; + mpc_rec.y = plane_clip_rec->y; + + } else { + mpc_rec.width = plane_clip_rec->width / mpc_slice_count; + mpc_rec.x = plane_clip_rec->x + mpc_rec.width * mpc_slice_idx; + mpc_rec.height = plane_clip_rec->height; + mpc_rec.y = plane_clip_rec->y; + } + SPL_ASSERT(mpc_slice_count == 1 || + spl_in->basic_out.view_format != SPL_VIEW_3D_SIDE_BY_SIDE || + mpc_rec.width % 2 == 0); + + /* extra pixels in the division remainder need to go to pipes after + * the extra pixel index minus one(epimo) defined here as: + */ + if ((use_recout_width_aligned == false) && + mpc_slice_idx > epimo && spl_in->basic_in.custom_width == 0) { + mpc_rec.x += mpc_slice_idx - epimo - 1; + mpc_rec.width += 1; + } + + if (spl_in->basic_out.view_format == SPL_VIEW_3D_TOP_AND_BOTTOM) { + SPL_ASSERT(mpc_rec.height % 2 == 0); + mpc_rec.height /= 2; + } + return mpc_rec; +} + +static struct spl_rect calculate_odm_slice_in_timing_active(struct spl_in *spl_in) +{ + int odm_slice_count = spl_in->basic_out.odm_combine_factor; + int odm_slice_idx = spl_in->odm_slice_index; + bool is_last_odm_slice = (odm_slice_idx + 1) == odm_slice_count; + int h_active = spl_in->basic_out.output_size.width; + int v_active = spl_in->basic_out.output_size.height; + int odm_slice_width; + struct spl_rect odm_rec; + + if (spl_in->basic_out.odm_combine_factor > 0) { + odm_slice_width = h_active / odm_slice_count; + /* + * deprecated, caller must pass in odm slice rect i.e OPP input + * rect in timing active for the new interface. + */ + if (spl_in->basic_out.use_two_pixels_per_container && (odm_slice_width % 2)) + odm_slice_width++; + + odm_rec.x = odm_slice_width * odm_slice_idx; + odm_rec.width = is_last_odm_slice ? + /* last slice width is the reminder of h_active */ + h_active - odm_slice_width * (odm_slice_count - 1) : + /* odm slice width is the floor of h_active / count */ + odm_slice_width; + odm_rec.y = 0; + odm_rec.height = v_active; + + return odm_rec; + } + + return spl_in->basic_out.odm_slice_rect; +} + +static void spl_calculate_recout(struct spl_in *spl_in, struct spl_scratch *spl_scratch, struct spl_out *spl_out) +{ + (void)spl_out; + /* + * A plane clip represents the desired plane size and position in Stream + * Source Space. Stream Source is the destination where all planes are + * blended (i.e. positioned, scaled and overlaid). It is a canvas where + * all planes associated with the current stream are drawn together. + * After Stream Source is completed, we will further scale and + * reposition the entire canvas of the stream source to Stream + * Destination in Timing Active Space. This could be due to display + * overscan adjustment where we will need to rescale and reposition all + * the planes so they can fit into a TV with overscan or downscale + * upscale features such as GPU scaling or VSR. + * + * This two step blending is a virtual procedure in software. In + * hardware there is no such thing as Stream Source. all planes are + * blended once in Timing Active Space. Software virtualizes a Stream + * Source space to decouple the math complicity so scaling param + * calculation focuses on one step at a time. + * + * In the following two diagrams, user applied 10% overscan adjustment + * so the Stream Source needs to be scaled down a little before mapping + * to Timing Active Space. As a result the Plane Clip is also scaled + * down by the same ratio, Plane Clip position (i.e. x and y) with + * respect to Stream Source is also scaled down. To map it in Timing + * Active Space additional x and y offsets from Stream Destination are + * added to Plane Clip as well. + * + * Stream Source Space + * ------------ + * __________________________________________________ + * |Stream Source (3840 x 2160) ^ | + * | y | + * | | | + * | __________________V | + * |<-- x -->|Plane Clip/////////| | + * | |(pre scale)////////| | + * | |///////////////////| | + * | |///////////////////| | + * | |///////////////////| | + * | |///////////////////| | + * | |///////////////////| | + * | | + * | | + * |__________________________________________________| + * + * + * Timing Active Space (3840 x 2160) + * --------------------------------- + * + * Timing Active + * __________________________________________________ + * | y_____________________________________________ | + * |x |Stream Destination (3456 x 1944) | | + * | | | | + * | | __________________ | | + * | | |Plane Clip////////| | | + * | | |(post scale)//////| | | + * | | |//////////////////| | | + * | | |//////////////////| | | + * | | |//////////////////| | | + * | | |//////////////////| | | + * | | | | + * | | | | + * | |____________________________________________| | + * |__________________________________________________| + * + * + * In Timing Active Space a plane clip could be further sliced into + * pieces called MPC slices. Each Pipe Context is responsible for + * processing only one MPC slice so the plane processing workload can be + * distributed to multiple DPP Pipes. MPC slices could be blended + * together to a single ODM slice. Each ODM slice is responsible for + * processing a portion of Timing Active divided horizontally so the + * output pixel processing workload can be distributed to multiple OPP + * pipes. All ODM slices are mapped together in ODM block so all MPC + * slices belong to different ODM slices could be pieced together to + * form a single image in Timing Active. MPC slices must belong to + * single ODM slice. If an MPC slice goes across ODM slice boundary, it + * needs to be divided into two MPC slices one for each ODM slice. + * + * In the following diagram the output pixel processing workload is + * divided horizontally into two ODM slices one for each OPP blend tree. + * OPP0 blend tree is responsible for processing left half of Timing + * Active, while OPP2 blend tree is responsible for processing right + * half. + * + * The plane has two MPC slices. However since the right MPC slice goes + * across ODM boundary, two DPP pipes are needed one for each OPP blend + * tree. (i.e. DPP1 for OPP0 blend tree and DPP2 for OPP2 blend tree). + * + * Assuming that we have a Pipe Context associated with OPP0 and DPP1 + * working on processing the plane in the diagram. We want to know the + * width and height of the shaded rectangle and its relative position + * with respect to the ODM slice0. This is called the recout of the pipe + * context. + * + * Planes can be at arbitrary size and position and there could be an + * arbitrary number of MPC and ODM slices. The algorithm needs to take + * all scenarios into account. + * + * Timing Active Space (3840 x 2160) + * --------------------------------- + * + * Timing Active + * __________________________________________________ + * |OPP0(ODM slice0)^ |OPP2(ODM slice1) | + * | y | | + * | | <- w -> | + * | _____V________|____ | + * | |DPP0 ^ |DPP1 |DPP2| | + * |<------ x |-----|->|/////| | | + * | | | |/////| | | + * | | h |/////| | | + * | | | |/////| | | + * | |_____V__|/////|____| | + * | | | + * | | | + * | | | + * |_________________________|________________________| + * + * + */ + struct spl_rect plane_clip; + struct spl_rect mpc_slice_of_plane_clip; + struct spl_rect odm_slice; + struct spl_rect overlapping_area; + + plane_clip = calculate_plane_rec_in_timing_active(spl_in, + &spl_in->basic_in.clip_rect); + /* guard plane clip from drawing beyond stream dst here */ + plane_clip = intersect_rec(&plane_clip, + &spl_in->basic_out.dst_rect); + mpc_slice_of_plane_clip = calculate_mpc_slice_in_timing_active( + spl_in, &plane_clip); + odm_slice = calculate_odm_slice_in_timing_active(spl_in); + overlapping_area = intersect_rec(&mpc_slice_of_plane_clip, &odm_slice); + + if (overlapping_area.height > 0 && + overlapping_area.width > 0) { + /* shift the overlapping area so it is with respect to current + * ODM slice's position + */ + spl_scratch->scl_data.recout = shift_rec( + &overlapping_area, + -odm_slice.x, -odm_slice.y); + spl_scratch->scl_data.recout.height -= + spl_in->debug.visual_confirm_base_offset; + spl_scratch->scl_data.recout.height -= + spl_in->debug.visual_confirm_dpp_offset; + } else + /* if there is no overlap, zero recout */ + memset(&spl_scratch->scl_data.recout, 0, + sizeof(struct spl_rect)); +} + +/* Calculate scaling ratios */ +static void spl_calculate_scaling_ratios(struct spl_in *spl_in, + struct spl_scratch *spl_scratch, + struct spl_out *spl_out) +{ + (void)spl_out; + const int in_w = spl_in->basic_out.src_rect.width; + const int in_h = spl_in->basic_out.src_rect.height; + const int out_w = spl_in->basic_out.dst_rect.width; + const int out_h = spl_in->basic_out.dst_rect.height; + struct spl_rect surf_src = spl_in->basic_in.src_rect; + + /*Swap surf_src height and width since scaling ratios are in recout rotation*/ + if (spl_in->basic_in.rotation == SPL_ROTATION_ANGLE_90 || + spl_in->basic_in.rotation == SPL_ROTATION_ANGLE_270) + spl_swap(surf_src.height, surf_src.width); + + spl_scratch->scl_data.ratios.horz = SPL_NAMESPACE(spl_fixpt_from_fraction( + surf_src.width, + spl_in->basic_in.dst_rect.width)); + spl_scratch->scl_data.ratios.vert = SPL_NAMESPACE(spl_fixpt_from_fraction( + surf_src.height, + spl_in->basic_in.dst_rect.height)); + + if (spl_in->basic_out.view_format == SPL_VIEW_3D_SIDE_BY_SIDE) + spl_scratch->scl_data.ratios.horz.value *= 2; + else if (spl_in->basic_out.view_format == SPL_VIEW_3D_TOP_AND_BOTTOM) + spl_scratch->scl_data.ratios.vert.value *= 2; + + spl_scratch->scl_data.ratios.vert.value = spl_div64_s64( + spl_scratch->scl_data.ratios.vert.value * in_h, out_h); + spl_scratch->scl_data.ratios.horz.value = spl_div64_s64( + spl_scratch->scl_data.ratios.horz.value * in_w, out_w); + + spl_scratch->scl_data.ratios.horz_c = spl_scratch->scl_data.ratios.horz; + spl_scratch->scl_data.ratios.vert_c = spl_scratch->scl_data.ratios.vert; + + if (spl_is_yuv420(spl_in->basic_in.format)) { + spl_scratch->scl_data.ratios.horz_c.value /= 2; + spl_scratch->scl_data.ratios.vert_c.value /= 2; +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) + } else if (spl_is_yuv422(spl_in->basic_in.format)) { + if (spl_in->basic_in.rotation == SPL_ROTATION_ANGLE_90 || + spl_in->basic_in.rotation == SPL_ROTATION_ANGLE_270) + spl_scratch->scl_data.ratios.vert_c.value /= 2; + else + spl_scratch->scl_data.ratios.horz_c.value /= 2; + } +#else + } +#endif + spl_scratch->scl_data.ratios.horz = spl_fixpt_truncate( + spl_scratch->scl_data.ratios.horz, 19); + spl_scratch->scl_data.ratios.vert = spl_fixpt_truncate( + spl_scratch->scl_data.ratios.vert, 19); + spl_scratch->scl_data.ratios.horz_c = spl_fixpt_truncate( + spl_scratch->scl_data.ratios.horz_c, 19); + spl_scratch->scl_data.ratios.vert_c = spl_fixpt_truncate( + spl_scratch->scl_data.ratios.vert_c, 19); + + /* + * Coefficient table and some registers are different based on ratio + * that is output/input. Currently we calculate input/output + * Store 1/ratio in recip_ratio for those lookups + */ + spl_scratch->scl_data.recip_ratios.horz = SPL_NAMESPACE(spl_fixpt_recip( + spl_scratch->scl_data.ratios.horz)); + spl_scratch->scl_data.recip_ratios.vert = SPL_NAMESPACE(spl_fixpt_recip( + spl_scratch->scl_data.ratios.vert)); + spl_scratch->scl_data.recip_ratios.horz_c = SPL_NAMESPACE(spl_fixpt_recip( + spl_scratch->scl_data.ratios.horz_c)); + spl_scratch->scl_data.recip_ratios.vert_c = SPL_NAMESPACE(spl_fixpt_recip( + spl_scratch->scl_data.ratios.vert_c)); +} + +/* Calculate Viewport size */ +static void spl_calculate_viewport_size(struct spl_in *spl_in, struct spl_scratch *spl_scratch) +{ + spl_scratch->scl_data.viewport.width = spl_fixpt_ceil(spl_fixpt_mul_int(spl_scratch->scl_data.ratios.horz, + spl_scratch->scl_data.recout.width)); + spl_scratch->scl_data.viewport.height = spl_fixpt_ceil(spl_fixpt_mul_int(spl_scratch->scl_data.ratios.vert, + spl_scratch->scl_data.recout.height)); + spl_scratch->scl_data.viewport_c.width = spl_fixpt_ceil(spl_fixpt_mul_int(spl_scratch->scl_data.ratios.horz_c, + spl_scratch->scl_data.recout.width)); + spl_scratch->scl_data.viewport_c.height = spl_fixpt_ceil(spl_fixpt_mul_int(spl_scratch->scl_data.ratios.vert_c, + spl_scratch->scl_data.recout.height)); + if (spl_in->basic_in.rotation == SPL_ROTATION_ANGLE_90 || + spl_in->basic_in.rotation == SPL_ROTATION_ANGLE_270) { + spl_swap(spl_scratch->scl_data.viewport.width, spl_scratch->scl_data.viewport.height); + spl_swap(spl_scratch->scl_data.viewport_c.width, spl_scratch->scl_data.viewport_c.height); + } +} + +static void spl_get_vp_scan_direction(enum spl_rotation_angle rotation, + bool horizontal_mirror, + bool *orthogonal_rotation, + bool *flip_vert_scan_dir, + bool *flip_horz_scan_dir) +{ + *orthogonal_rotation = false; + *flip_vert_scan_dir = false; + *flip_horz_scan_dir = false; + if (rotation == SPL_ROTATION_ANGLE_180) { + *flip_vert_scan_dir = true; + *flip_horz_scan_dir = true; + } else if (rotation == SPL_ROTATION_ANGLE_90) { + *orthogonal_rotation = true; + *flip_horz_scan_dir = true; + } else if (rotation == SPL_ROTATION_ANGLE_270) { + *orthogonal_rotation = true; + *flip_vert_scan_dir = true; + } + + if (horizontal_mirror) + *flip_horz_scan_dir = !*flip_horz_scan_dir; +} + +/* + * We completely calculate vp offset, size and inits here based entirely on scaling + * ratios and recout for pixel perfect pipe combine. + */ +static void spl_calculate_init_and_vp(bool flip_scan_dir, + int recout_offset_within_recout_full, + int recout_size, + int src_size, + int taps, + struct spl_fixed31_32 ratio, + struct spl_fixed31_32 init_adj, + struct spl_fixed31_32 *init, + int *vp_offset, + int *vp_size) +{ + struct spl_fixed31_32 temp; + int int_part; + + /* + * First of the taps starts sampling pixel number corresponding to recout + * pixel 1. Next recout pixel samples int part of and so on. + * All following calculations are based on this logic. + * + * Init calculated according to formula: + * init = (scaling_ratio + number_of_taps + 1) / 2 + * init_bot = init + scaling_ratio + * to get pixel perfect combine add the fraction from calculating vp offset + */ + temp = spl_fixpt_mul_int(ratio, recout_offset_within_recout_full); + *vp_offset = spl_fixpt_floor(temp); + temp.value &= 0xffffffff; + *init = spl_fixpt_add(spl_fixpt_div_int(spl_fixpt_add_int(ratio, taps + 1), 2), temp); + *init = spl_fixpt_add(*init, init_adj); + *init = spl_fixpt_truncate(*init, 19); + + /* + * If viewport has non 0 offset and there are more taps than covered by init then + * we should decrease the offset and increase init so we are never sampling + * outside of viewport. + */ + int_part = spl_fixpt_floor(*init); + if (int_part < taps) { + int_part = taps - int_part; + if (int_part > *vp_offset) + int_part = *vp_offset; + *vp_offset -= int_part; + *init = spl_fixpt_add_int(*init, int_part); + } + /* + * If taps are sampling outside of viewport at end of recout and there are more pixels + * available in the surface we should increase the viewport size, regardless set vp to + * only what is used. + */ + temp = spl_fixpt_add(*init, spl_fixpt_mul_int(ratio, recout_size - 1)); + *vp_size = spl_fixpt_floor(temp); + if (*vp_size + *vp_offset > src_size) + *vp_size = src_size - *vp_offset; + + /* We did all the math assuming we are scanning same direction as display does, + * however mirror/rotation changes how vp scans vs how it is offset. If scan direction + * is flipped we simply need to calculate offset from the other side of plane. + * Note that outside of viewport all scaling hardware works in recout space. + */ + if (flip_scan_dir) + *vp_offset = src_size - *vp_offset - *vp_size; +} + +/*Calculate inits and viewport */ +static void spl_calculate_inits_and_viewports(struct spl_in *spl_in, + struct spl_scratch *spl_scratch) +{ + struct spl_rect src = spl_in->basic_in.src_rect; + struct spl_rect recout_dst_in_active_timing; + struct spl_rect recout_clip_in_active_timing; + struct spl_rect recout_clip_in_recout_dst; + struct spl_rect overlap_in_active_timing; + struct spl_rect odm_slice = calculate_odm_slice_in_timing_active(spl_in); +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) + int vp_hc_div = spl_is_subsampled_format(spl_in->basic_in.format) ? 2 : 1; + int vp_vc_div = spl_is_yuv420(spl_in->basic_in.format) ? 2 : 1; +#else + int vpc_div = spl_is_subsampled_format(spl_in->basic_in.format) ? 2 : 1; +#endif + bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir; + struct spl_fixed31_32 init_adj_h = spl_fixpt_zero; + struct spl_fixed31_32 init_adj_v = spl_fixpt_zero; + + recout_clip_in_active_timing = shift_rec( + &spl_scratch->scl_data.recout, odm_slice.x, odm_slice.y); + recout_dst_in_active_timing = calculate_plane_rec_in_timing_active( + spl_in, &spl_in->basic_in.dst_rect); + overlap_in_active_timing = intersect_rec(&recout_clip_in_active_timing, + &recout_dst_in_active_timing); + if (overlap_in_active_timing.width > 0 && + overlap_in_active_timing.height > 0) + recout_clip_in_recout_dst = shift_rec(&overlap_in_active_timing, + -recout_dst_in_active_timing.x, + -recout_dst_in_active_timing.y); + else + memset(&recout_clip_in_recout_dst, 0, sizeof(struct spl_rect)); + /* + * Work in recout rotation since that requires less transformations + */ + spl_get_vp_scan_direction( + spl_in->basic_in.rotation, + spl_in->basic_in.horizontal_mirror, + &orthogonal_rotation, + &flip_vert_scan_dir, + &flip_horz_scan_dir); + + if (spl_is_subsampled_format(spl_in->basic_in.format)) { + /* this gives the direction of the cositing (negative will move + * left, right otherwise) + */ + int h_sign = flip_horz_scan_dir ? -1 : 1; + int v_sign = flip_vert_scan_dir ? -1 : 1; + + switch (spl_in->basic_in.cositing) { + case CHROMA_COSITING_TOPLEFT: + init_adj_h = SPL_NAMESPACE(spl_fixpt_from_fraction(h_sign, 4)); + init_adj_v = SPL_NAMESPACE(spl_fixpt_from_fraction(v_sign, 4)); + break; + case CHROMA_COSITING_LEFT: + init_adj_h = SPL_NAMESPACE(spl_fixpt_from_fraction(h_sign, 4)); + init_adj_v = spl_fixpt_zero; + break; + case CHROMA_COSITING_NONE: + default: + init_adj_h = spl_fixpt_zero; + init_adj_v = spl_fixpt_zero; + break; + } + } + + if (orthogonal_rotation) { + spl_swap(src.width, src.height); + spl_swap(flip_vert_scan_dir, flip_horz_scan_dir); +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) + spl_swap(vp_hc_div, vp_vc_div); +#endif + spl_swap(init_adj_h, init_adj_v); + } + + spl_calculate_init_and_vp( + flip_horz_scan_dir, + recout_clip_in_recout_dst.x, + spl_scratch->scl_data.recout.width, + src.width, + spl_scratch->scl_data.taps.h_taps, + spl_scratch->scl_data.ratios.horz, + spl_fixpt_zero, + &spl_scratch->scl_data.inits.h, + &spl_scratch->scl_data.viewport.x, + &spl_scratch->scl_data.viewport.width); + spl_calculate_init_and_vp( + flip_horz_scan_dir, + recout_clip_in_recout_dst.x, + spl_scratch->scl_data.recout.width, +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) + src.width / vp_hc_div, +#else + src.width / vpc_div, +#endif + spl_scratch->scl_data.taps.h_taps_c, + spl_scratch->scl_data.ratios.horz_c, + init_adj_h, + &spl_scratch->scl_data.inits.h_c, + &spl_scratch->scl_data.viewport_c.x, + &spl_scratch->scl_data.viewport_c.width); + spl_calculate_init_and_vp( + flip_vert_scan_dir, + recout_clip_in_recout_dst.y, + spl_scratch->scl_data.recout.height, + src.height, + spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.ratios.vert, + spl_fixpt_zero, + &spl_scratch->scl_data.inits.v, + &spl_scratch->scl_data.viewport.y, + &spl_scratch->scl_data.viewport.height); + spl_calculate_init_and_vp( + flip_vert_scan_dir, + recout_clip_in_recout_dst.y, + spl_scratch->scl_data.recout.height, +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) + src.height / vp_vc_div, +#else + src.height / vpc_div, +#endif + spl_scratch->scl_data.taps.v_taps_c, + spl_scratch->scl_data.ratios.vert_c, + init_adj_v, + &spl_scratch->scl_data.inits.v_c, + &spl_scratch->scl_data.viewport_c.y, + &spl_scratch->scl_data.viewport_c.height); + if (orthogonal_rotation) { + spl_swap(spl_scratch->scl_data.viewport.x, spl_scratch->scl_data.viewport.y); + spl_swap(spl_scratch->scl_data.viewport.width, spl_scratch->scl_data.viewport.height); + spl_swap(spl_scratch->scl_data.viewport_c.x, spl_scratch->scl_data.viewport_c.y); + spl_swap(spl_scratch->scl_data.viewport_c.width, spl_scratch->scl_data.viewport_c.height); +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) + spl_swap(vp_hc_div, vp_vc_div); +#endif + } + spl_scratch->scl_data.viewport.x += src.x; + spl_scratch->scl_data.viewport.y += src.y; +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) + SPL_ASSERT(src.x % vp_hc_div == 0 && src.y % vp_vc_div == 0); + spl_scratch->scl_data.viewport_c.x += src.x / vp_hc_div; + spl_scratch->scl_data.viewport_c.y += src.y / vp_vc_div; +#else + SPL_ASSERT(src.x % vpc_div == 0 && src.y % vpc_div == 0); + spl_scratch->scl_data.viewport_c.x += src.x / vpc_div; + spl_scratch->scl_data.viewport_c.y += src.y / vpc_div; +#endif +} + +static void spl_handle_3d_recout(struct spl_in *spl_in, struct spl_rect *recout) +{ + /* + * Handle side by side and top bottom 3d recout offsets after vp calculation + * since 3d is special and needs to calculate vp as if there is no recout offset + * This may break with rotation, good thing we aren't mixing hw rotation and 3d + */ + if (spl_in->basic_in.mpc_h_slice_index) { + SPL_ASSERT(spl_in->basic_in.rotation == SPL_ROTATION_ANGLE_0 || + (spl_in->basic_out.view_format != SPL_VIEW_3D_TOP_AND_BOTTOM && + spl_in->basic_out.view_format != SPL_VIEW_3D_SIDE_BY_SIDE)); + if (spl_in->basic_out.view_format == SPL_VIEW_3D_TOP_AND_BOTTOM) + recout->y += recout->height; + else if (spl_in->basic_out.view_format == SPL_VIEW_3D_SIDE_BY_SIDE) + recout->x += recout->width; + } +} + +static void spl_clamp_viewport(struct spl_rect *viewport, int min_viewport_size) +{ + if (min_viewport_size == 0) + min_viewport_size = MIN_VIEWPORT_SIZE; + /* Clamp minimum viewport size */ + if (viewport->height < min_viewport_size) + viewport->height = min_viewport_size; + if (viewport->width < min_viewport_size) + viewport->width = min_viewport_size; +} + +static enum scl_mode spl_get_dscl_mode(const struct spl_in *spl_in, + const struct spl_scaler_data *data, + bool enable_isharp, bool enable_easf) +{ + (void)enable_easf; + const long long one = spl_fixpt_one.value; + enum spl_pixel_format pixel_format = spl_in->basic_in.format; + + /* Bypass if ratio is 1:1 with no ISHARP or force scale on */ + if (data->ratios.horz.value == one + && data->ratios.vert.value == one + && data->ratios.horz_c.value == one + && data->ratios.vert_c.value == one + && !spl_in->basic_out.always_scale + && !enable_isharp) + return SCL_MODE_SCALING_444_BYPASS; + + if (!spl_is_subsampled_format(pixel_format)) { + if (spl_is_video_format(pixel_format)) + return SCL_MODE_SCALING_444_YCBCR_ENABLE; + else + return SCL_MODE_SCALING_444_RGB_ENABLE; + } + + /* + * Bypass YUV if Y is 1:1 with no ISHARP + * Do not bypass UV at 1:1 for cositing to be applied + */ + if (!enable_isharp) { + if (data->ratios.horz.value == one && data->ratios.vert.value == one && !spl_in->basic_out.always_scale) + return SCL_MODE_SCALING_420_LUMA_BYPASS; + } + + return SCL_MODE_SCALING_420_YCBCR_ENABLE; +} + +static void spl_choose_lls_policy(enum spl_pixel_format format, + enum linear_light_scaling *lls_pref) +{ + if (spl_is_subsampled_format(format)) + *lls_pref = LLS_PREF_NO; + else /* RGB or YUV444 */ + *lls_pref = LLS_PREF_YES; +} + +/* Enable EASF ?*/ +static bool enable_easf(struct spl_in *spl_in, struct spl_scratch *spl_scratch) +{ + int vratio = 0; + int hratio = 0; + bool skip_easf = false; + + if (spl_in->disable_easf) + skip_easf = true; + + vratio = spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert); + hratio = spl_fixpt_ceil(spl_scratch->scl_data.ratios.horz); + + /* + * No EASF support for downscaling > 2:1 + * EASF support for upscaling or downscaling up to 2:1 + */ + if ((vratio > 2) || (hratio > 2)) + skip_easf = true; + + /* + * If lls_pref is LLS_PREF_DONT_CARE, then use pixel format + * to determine whether to use LINEAR or NONLINEAR scaling + */ + if (spl_in->lls_pref == LLS_PREF_DONT_CARE) + spl_choose_lls_policy(spl_in->basic_in.format, + &spl_in->lls_pref); + + /* Check for linear scaling or EASF preferred */ + if (spl_in->lls_pref != LLS_PREF_YES && !spl_in->prefer_easf) + skip_easf = true; + + return skip_easf; +} + +/* Check if video is in fullscreen mode */ +static bool spl_is_video_fullscreen(struct spl_in *spl_in) +{ + if (spl_is_video_format(spl_in->basic_in.format) && spl_in->is_fullscreen) + return true; + return false; +} + +static bool spl_get_isharp_en(struct spl_in *spl_in, + struct spl_scratch *spl_scratch) +{ + bool enable_isharp = false; + int vratio = 0; + int hratio = 0; + struct spl_taps taps = spl_scratch->scl_data.taps; + bool fullscreen = spl_is_video_fullscreen(spl_in); + + /* Return if adaptive sharpness is disabled */ + if (spl_in->adaptive_sharpness.enable == false) + return enable_isharp; + + vratio = spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert); + hratio = spl_fixpt_ceil(spl_scratch->scl_data.ratios.horz); + + /* No iSHARP support for downscaling */ + if (vratio > 1 || hratio > 1) + return enable_isharp; + + // Scaling is up to 1:1 (no scaling) or upscaling + + /* + * Apply sharpness to RGB and YUV (NV12/P010) + * surfaces based on policy setting + */ + if (!spl_is_video_format(spl_in->basic_in.format) && + (spl_in->sharpen_policy == SHARPEN_YUV)) + return enable_isharp; + else if ((spl_is_video_format(spl_in->basic_in.format) && !fullscreen) && + (spl_in->sharpen_policy == SHARPEN_RGB_FULLSCREEN_YUV)) + return enable_isharp; + else if (!spl_in->is_fullscreen && + spl_in->sharpen_policy == SHARPEN_FULLSCREEN_ALL) + return enable_isharp; + + /* + * Apply sharpness if supports horizontal taps 4,6 AND + * vertical taps 3, 4, 6 + */ + if ((taps.h_taps == 4 || taps.h_taps == 6) && + (taps.v_taps == 3 || taps.v_taps == 4 || taps.v_taps == 6)) + enable_isharp = true; + + return enable_isharp; +} + +/* Calculate number of tap with adaptive scaling off */ +static void spl_get_taps_non_adaptive_scaler( + struct spl_scratch *spl_scratch, + const struct spl_taps *in_taps, +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) + bool is_horz_subsampled, + bool is_vert_subsampled) +#else + bool is_subsampled) +#endif +{ + bool check_max_downscale = false; + + if (in_taps->h_taps == 0) { + if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.horz) > 1) + spl_scratch->scl_data.taps.h_taps = spl_min(2 * spl_fixpt_ceil( + spl_scratch->scl_data.ratios.horz), 8); + else + spl_scratch->scl_data.taps.h_taps = 4; + } else + spl_scratch->scl_data.taps.h_taps = in_taps->h_taps; + + if (in_taps->v_taps == 0) { + if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert) > 1) + spl_scratch->scl_data.taps.v_taps = spl_min(2 * spl_fixpt_ceil( + spl_scratch->scl_data.ratios.vert), 8); + else + spl_scratch->scl_data.taps.v_taps = 4; + } else + spl_scratch->scl_data.taps.v_taps = in_taps->v_taps; + + if (in_taps->v_taps_c == 0) { + if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert_c) > 1) + spl_scratch->scl_data.taps.v_taps_c = spl_min(2 * spl_fixpt_ceil( + spl_scratch->scl_data.ratios.vert_c), 8); + else + spl_scratch->scl_data.taps.v_taps_c = 4; + } else + spl_scratch->scl_data.taps.v_taps_c = in_taps->v_taps_c; + + if (in_taps->h_taps_c == 0) { + if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.horz_c) > 1) + spl_scratch->scl_data.taps.h_taps_c = spl_min(2 * spl_fixpt_ceil( + spl_scratch->scl_data.ratios.horz_c), 8); + else + spl_scratch->scl_data.taps.h_taps_c = 4; + } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1) + /* Only 1 and even h_taps_c are supported by hw */ + spl_scratch->scl_data.taps.h_taps_c = in_taps->h_taps_c - 1; + else + spl_scratch->scl_data.taps.h_taps_c = in_taps->h_taps_c; + + + /* + * Max downscale supported is 6.0x. Add ASSERT to catch if go beyond that + */ + check_max_downscale = spl_fixpt_le(spl_scratch->scl_data.ratios.horz, + SPL_NAMESPACE(spl_fixpt_from_fraction(6, 1))); + SPL_ASSERT(check_max_downscale); + check_max_downscale = spl_fixpt_le(spl_scratch->scl_data.ratios.vert, + SPL_NAMESPACE(spl_fixpt_from_fraction(6, 1))); + SPL_ASSERT(check_max_downscale); + check_max_downscale = spl_fixpt_le(spl_scratch->scl_data.ratios.horz_c, + SPL_NAMESPACE(spl_fixpt_from_fraction(6, 1))); + SPL_ASSERT(check_max_downscale); + check_max_downscale = spl_fixpt_le(spl_scratch->scl_data.ratios.vert_c, + SPL_NAMESPACE(spl_fixpt_from_fraction(6, 1))); + SPL_ASSERT(check_max_downscale); + + + if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz)) + spl_scratch->scl_data.taps.h_taps = 1; + if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert)) + spl_scratch->scl_data.taps.v_taps = 1; +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) + if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz_c) && !is_horz_subsampled) + spl_scratch->scl_data.taps.h_taps_c = 1; + if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert_c) && !is_vert_subsampled) + spl_scratch->scl_data.taps.v_taps_c = 1; +#else + if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz_c) && !is_subsampled) + spl_scratch->scl_data.taps.h_taps_c = 1; + if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert_c) && !is_subsampled) + spl_scratch->scl_data.taps.v_taps_c = 1; + +#endif +} + +/* Calculate optimal number of taps */ +static bool spl_get_optimal_number_of_taps( + int max_downscale_src_width, struct spl_in *spl_in, struct spl_scratch *spl_scratch, + const struct spl_taps *in_taps, bool *enable_easf_v, bool *enable_easf_h, + bool *enable_isharp) +{ + int num_part_y, num_part_c; + unsigned int max_taps_y, max_taps_c; + unsigned int min_taps_y, min_taps_c; + enum lb_memory_config lb_config; + bool skip_easf = false; +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) + bool is_horz_subsampled = spl_is_subsampled_format(spl_in->basic_in.format); + bool is_vert_subsampled = spl_is_yuv420(spl_in->basic_in.format); +#else + bool is_subsampled = spl_is_subsampled_format(spl_in->basic_in.format); +#endif + + if (spl_scratch->scl_data.viewport.width > spl_scratch->scl_data.h_active && + max_downscale_src_width != 0 && + spl_scratch->scl_data.viewport.width > max_downscale_src_width) { +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) + spl_get_taps_non_adaptive_scaler(spl_scratch, in_taps, is_horz_subsampled, is_vert_subsampled); +#else + spl_get_taps_non_adaptive_scaler(spl_scratch, in_taps, is_subsampled); +#endif + *enable_easf_v = false; + *enable_easf_h = false; + *enable_isharp = false; + return false; + } + + /* Disable adaptive scaler and sharpener when integer scaling is enabled */ + if (spl_in->scaling_quality.integer_scaling) { +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) + spl_get_taps_non_adaptive_scaler(spl_scratch, in_taps, is_horz_subsampled, is_vert_subsampled); +#else + spl_get_taps_non_adaptive_scaler(spl_scratch, in_taps, is_subsampled); +#endif + *enable_easf_v = false; + *enable_easf_h = false; + *enable_isharp = false; + return true; + } + + /* Check if we are using EASF or not */ + skip_easf = enable_easf(spl_in, spl_scratch); + + /* + * Set default taps if none are provided + * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling + * taps = 4 for upscaling + */ + if (skip_easf) { +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) + spl_get_taps_non_adaptive_scaler(spl_scratch, in_taps, is_horz_subsampled, is_vert_subsampled); +#else + spl_get_taps_non_adaptive_scaler(spl_scratch, in_taps, is_subsampled); +#endif + } + else { + if (spl_is_video_format(spl_in->basic_in.format)) { + spl_scratch->scl_data.taps.h_taps = 6; + spl_scratch->scl_data.taps.v_taps = 6; + spl_scratch->scl_data.taps.h_taps_c = 4; + spl_scratch->scl_data.taps.v_taps_c = 4; + } else { /* RGB */ + spl_scratch->scl_data.taps.h_taps = 6; + spl_scratch->scl_data.taps.v_taps = 6; + spl_scratch->scl_data.taps.h_taps_c = 6; + spl_scratch->scl_data.taps.v_taps_c = 6; + } + + /* Override mode: keep EASF enabled but use input taps if valid */ + if (spl_in->override_easf) { + spl_scratch->scl_data.taps.h_taps = (in_taps->h_taps != 0) ? in_taps->h_taps : spl_scratch->scl_data.taps.h_taps; + spl_scratch->scl_data.taps.v_taps = (in_taps->v_taps != 0) ? in_taps->v_taps : spl_scratch->scl_data.taps.v_taps; + spl_scratch->scl_data.taps.h_taps_c = (in_taps->h_taps_c != 0) ? in_taps->h_taps_c : spl_scratch->scl_data.taps.h_taps_c; + spl_scratch->scl_data.taps.v_taps_c = (in_taps->v_taps_c != 0) ? in_taps->v_taps_c : spl_scratch->scl_data.taps.v_taps_c; + + if ((spl_scratch->scl_data.taps.h_taps > 6) || (spl_scratch->scl_data.taps.v_taps > 6)) + skip_easf = true; + if ((spl_scratch->scl_data.taps.h_taps > 1) && (spl_scratch->scl_data.taps.h_taps % 2)) + spl_scratch->scl_data.taps.h_taps--; + if ((spl_scratch->scl_data.taps.h_taps_c > 1) && (spl_scratch->scl_data.taps.h_taps_c % 2)) + spl_scratch->scl_data.taps.h_taps_c--; + } + } + + /*Ensure we can support the requested number of vtaps*/ + min_taps_y = spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert); + min_taps_c = spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert_c); + + /* Use LB_MEMORY_CONFIG_3 for 4:2:0 */ + if (spl_is_yuv420(spl_in->basic_in.format)) + lb_config = LB_MEMORY_CONFIG_3; + else + lb_config = LB_MEMORY_CONFIG_0; + // Determine max vtap support by calculating how much line buffer can fit + spl_in->callbacks.spl_calc_lb_num_partitions(spl_in->basic_out.alpha_en, &spl_scratch->scl_data, + lb_config, &num_part_y, &num_part_c); + /* MAX_V_TAPS = MIN (NUM_LINES - MAX(CEILING(V_RATIO,1)-2, 0), 8) */ + if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert) > 2) + if ((spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert) - 2) > num_part_y) + max_taps_y = 0; + else + max_taps_y = num_part_y - (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert) - 2); + else + max_taps_y = num_part_y; + + if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert_c) > 2) + if ((spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert_c) - 2) > num_part_c) + max_taps_c = 0; + else + max_taps_c = num_part_c - (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert_c) - 2); + else + max_taps_c = num_part_c; + + if (max_taps_y < min_taps_y) + return false; + else if (max_taps_c < min_taps_c) + return false; + + if (spl_scratch->scl_data.taps.v_taps > max_taps_y) + spl_scratch->scl_data.taps.v_taps = max_taps_y; + + if (spl_scratch->scl_data.taps.v_taps_c > max_taps_c) + spl_scratch->scl_data.taps.v_taps_c = max_taps_c; + + if (!skip_easf) { + /* + * RGB ( L + NL ) and Linear HDR support 6x6, 6x4, 6x3, 4x4, 4x3 + * NL YUV420 only supports 6x6, 6x4 for Y and 4x4 for UV + * + * If LB does not support 3, 4, or 6 taps, then disable EASF_V + * and only enable EASF_H. So for RGB, support 6x2, 4x2 + * and for NL YUV420, support 6x2 for Y and 4x2 for UV + * + * All other cases, have to disable EASF_V and EASF_H + * + * If optimal no of taps is 5, then set it to 4 + * If optimal no of taps is 7 or 8, then fine since max tap is 6 + * + */ + if (spl_scratch->scl_data.taps.v_taps == 5) + spl_scratch->scl_data.taps.v_taps = 4; + + if (spl_scratch->scl_data.taps.v_taps_c == 5) + spl_scratch->scl_data.taps.v_taps_c = 4; + + if (spl_scratch->scl_data.taps.h_taps == 5) + spl_scratch->scl_data.taps.h_taps = 4; + + if (spl_scratch->scl_data.taps.h_taps_c == 5) + spl_scratch->scl_data.taps.h_taps_c = 4; + + if (spl_is_video_format(spl_in->basic_in.format)) { + if (spl_scratch->scl_data.taps.h_taps <= 4) { + *enable_easf_v = false; + *enable_easf_h = false; + } else if (spl_scratch->scl_data.taps.v_taps <= 3) { + *enable_easf_v = false; + *enable_easf_h = true; + } else { + *enable_easf_v = true; + *enable_easf_h = true; + } + SPL_ASSERT((spl_scratch->scl_data.taps.v_taps > 1) && + (spl_scratch->scl_data.taps.v_taps_c > 1)); + } else { /* RGB */ + if (spl_scratch->scl_data.taps.h_taps <= 3) { + *enable_easf_v = false; + *enable_easf_h = false; + } else if (spl_scratch->scl_data.taps.v_taps < 3) { + *enable_easf_v = false; + *enable_easf_h = true; + } else { + *enable_easf_v = true; + *enable_easf_h = true; + } + SPL_ASSERT(spl_scratch->scl_data.taps.v_taps > 1); + } + } else { + *enable_easf_v = false; + *enable_easf_h = false; + } // end of if prefer_easf + + /* Sharpener requires scaler to be enabled, including for 1:1 + * Check if ISHARP can be enabled + * If ISHARP is not enabled, set taps to 1 if ratio is 1:1 + * except for chroma taps. Keep previous taps so it can + * handle cositing + */ + + *enable_isharp = spl_get_isharp_en(spl_in, spl_scratch); + if (!*enable_isharp && !spl_in->basic_out.always_scale) { + if ((IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz)) && + (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert))) { + spl_scratch->scl_data.taps.h_taps = 1; + spl_scratch->scl_data.taps.v_taps = 1; +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) + if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz_c) && !is_horz_subsampled) + spl_scratch->scl_data.taps.h_taps_c = 1; + + if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert_c) && !is_vert_subsampled) + spl_scratch->scl_data.taps.v_taps_c = 1; +#else + if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz_c) && !is_subsampled) + spl_scratch->scl_data.taps.h_taps_c = 1; + + if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert_c) && !is_subsampled) + spl_scratch->scl_data.taps.v_taps_c = 1; + +#endif + + *enable_easf_v = false; + *enable_easf_h = false; + } else { + if ((!*enable_easf_h) && + (IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz))) + spl_scratch->scl_data.taps.h_taps = 1; + + if ((!*enable_easf_v) && + (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert))) + spl_scratch->scl_data.taps.v_taps = 1; + +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) + if ((!*enable_easf_h) && !is_horz_subsampled && + (IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz_c))) + spl_scratch->scl_data.taps.h_taps_c = 1; + + if ((!*enable_easf_v) && !is_vert_subsampled && + (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert_c))) + spl_scratch->scl_data.taps.v_taps_c = 1; +#else + if ((!*enable_easf_h) && !is_subsampled && + (IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz_c))) + spl_scratch->scl_data.taps.h_taps_c = 1; + + if ((!*enable_easf_v) && !is_subsampled && + (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert_c))) + spl_scratch->scl_data.taps.v_taps_c = 1; +#endif + + } + } + return true; +} + +static void spl_set_black_color_data(enum spl_pixel_format format, + struct scl_black_color *scl_black_color) +{ + bool ycbcr = spl_is_video_format(format); + if (ycbcr) { + scl_black_color->offset_rgb_y = BLACK_OFFSET_RGB_Y; + scl_black_color->offset_rgb_cbcr = BLACK_OFFSET_CBCR; + } else { + scl_black_color->offset_rgb_y = 0x0; + scl_black_color->offset_rgb_cbcr = 0x0; + } +} + +static void spl_set_manual_ratio_init_data(struct dscl_prog_data *dscl_prog_data, + const struct spl_scaler_data *scl_data) +{ + struct spl_fixed31_32 bot; + + dscl_prog_data->ratios.h_scale_ratio = SPL_NAMESPACE(spl_fixpt_u3d19( + scl_data->ratios.horz)) << 5; + dscl_prog_data->ratios.v_scale_ratio = SPL_NAMESPACE(spl_fixpt_u3d19( + scl_data->ratios.vert)) << 5; + dscl_prog_data->ratios.h_scale_ratio_c = SPL_NAMESPACE(spl_fixpt_u3d19( + scl_data->ratios.horz_c)) << 5; + dscl_prog_data->ratios.v_scale_ratio_c = SPL_NAMESPACE(spl_fixpt_u3d19( + scl_data->ratios.vert_c)) << 5; + /* + * 0.24 format for fraction, first five bits zeroed + */ + dscl_prog_data->init.h_filter_init_frac = + SPL_NAMESPACE(spl_fixpt_u0d19(scl_data->inits.h)) << 5; + dscl_prog_data->init.h_filter_init_int = + spl_fixpt_floor(scl_data->inits.h); + dscl_prog_data->init.h_filter_init_frac_c = + SPL_NAMESPACE(spl_fixpt_u0d19(scl_data->inits.h_c)) << 5; + dscl_prog_data->init.h_filter_init_int_c = + spl_fixpt_floor(scl_data->inits.h_c); + dscl_prog_data->init.v_filter_init_frac = + SPL_NAMESPACE(spl_fixpt_u0d19(scl_data->inits.v)) << 5; + dscl_prog_data->init.v_filter_init_int = + spl_fixpt_floor(scl_data->inits.v); + dscl_prog_data->init.v_filter_init_frac_c = + SPL_NAMESPACE(spl_fixpt_u0d19(scl_data->inits.v_c)) << 5; + dscl_prog_data->init.v_filter_init_int_c = + spl_fixpt_floor(scl_data->inits.v_c); + + bot = spl_fixpt_add(scl_data->inits.v, scl_data->ratios.vert); + dscl_prog_data->init.v_filter_init_bot_frac = SPL_NAMESPACE(spl_fixpt_u0d19(bot)) << 5; + dscl_prog_data->init.v_filter_init_bot_int = spl_fixpt_floor(bot); + bot = spl_fixpt_add(scl_data->inits.v_c, scl_data->ratios.vert_c); + dscl_prog_data->init.v_filter_init_bot_frac_c = SPL_NAMESPACE(spl_fixpt_u0d19(bot)) << 5; + dscl_prog_data->init.v_filter_init_bot_int_c = spl_fixpt_floor(bot); +} + +static void spl_set_taps_data(struct dscl_prog_data *dscl_prog_data, + const struct spl_scaler_data *scl_data) +{ + dscl_prog_data->taps.v_taps = scl_data->taps.v_taps - 1; + dscl_prog_data->taps.h_taps = scl_data->taps.h_taps - 1; + dscl_prog_data->taps.v_taps_c = scl_data->taps.v_taps_c - 1; + dscl_prog_data->taps.h_taps_c = scl_data->taps.h_taps_c - 1; +} + +/* Populate dscl prog data structure from scaler data calculated by SPL */ +static void spl_set_dscl_prog_data(struct spl_in *spl_in, struct spl_scratch *spl_scratch, + struct spl_out *spl_out, bool enable_easf_v, bool enable_easf_h, bool enable_isharp) +{ + struct dscl_prog_data *dscl_prog_data = spl_out->dscl_prog_data; + + const struct spl_scaler_data *data = &spl_scratch->scl_data; + + struct scl_black_color *scl_black_color = &dscl_prog_data->scl_black_color; + + bool enable_easf = enable_easf_v || enable_easf_h; + + // Set values for recout + dscl_prog_data->recout = spl_scratch->scl_data.recout; + // Set values for MPC Size + dscl_prog_data->mpc_size.width = spl_scratch->scl_data.h_active; + dscl_prog_data->mpc_size.height = spl_scratch->scl_data.v_active; + + // SCL_MODE - Set SCL_MODE data + dscl_prog_data->dscl_mode = spl_get_dscl_mode(spl_in, data, enable_isharp, + enable_easf); + + // SCL_BLACK_COLOR + spl_set_black_color_data(spl_in->basic_in.format, scl_black_color); + + /* Manually calculate scale ratio and init values */ + spl_set_manual_ratio_init_data(dscl_prog_data, data); + + // Set HTaps/VTaps + spl_set_taps_data(dscl_prog_data, data); + // Set viewport + dscl_prog_data->viewport = spl_scratch->scl_data.viewport; + // Set viewport_c + dscl_prog_data->viewport_c = spl_scratch->scl_data.viewport_c; + // Set filters data + SPL_NAMESPACE(spl_set_filters_data(dscl_prog_data, data, enable_easf_v, enable_easf_h)); +} + +/* Calculate C0-C3 coefficients based on HDR_mult */ +static void spl_calculate_c0_c3_hdr(struct dscl_prog_data *dscl_prog_data, uint32_t sdr_white_level_nits) +{ + struct spl_fixed31_32 hdr_mult, c0_mult, c1_mult, c2_mult; + struct spl_fixed31_32 c0_calc, c1_calc, c2_calc; + struct spl_custom_float_format fmt; + uint32_t hdr_multx100_int; + + if ((sdr_white_level_nits >= 80) && (sdr_white_level_nits <= 480)) + hdr_multx100_int = sdr_white_level_nits * 100 / 80; + else + hdr_multx100_int = 100; /* default for 80 nits otherwise */ + + hdr_mult = SPL_NAMESPACE(spl_fixpt_from_fraction((long long)hdr_multx100_int, 100LL)); + c0_mult = SPL_NAMESPACE(spl_fixpt_from_fraction(2126LL, 10000LL)); + c1_mult = SPL_NAMESPACE(spl_fixpt_from_fraction(7152LL, 10000LL)); + c2_mult = SPL_NAMESPACE(spl_fixpt_from_fraction(722LL, 10000LL)); + + c0_calc = SPL_NAMESPACE(spl_fixpt_mul(hdr_mult, SPL_NAMESPACE(spl_fixpt_mul(c0_mult, + SPL_NAMESPACE(spl_fixpt_from_fraction(16384LL, 125LL)))))); + c1_calc = SPL_NAMESPACE(spl_fixpt_mul(hdr_mult, SPL_NAMESPACE(spl_fixpt_mul(c1_mult, + SPL_NAMESPACE(spl_fixpt_from_fraction(16384LL, 125LL)))))); + c2_calc = SPL_NAMESPACE(spl_fixpt_mul(hdr_mult, SPL_NAMESPACE(spl_fixpt_mul(c2_mult, + SPL_NAMESPACE(spl_fixpt_from_fraction(16384LL, 125LL)))))); + + fmt.exponenta_bits = 5; + fmt.mantissa_bits = 10; + fmt.sign = true; + + // fp1.5.10, C0 coefficient (LN_rec709: HDR_MULT * 0.212600 * 2^14/125) + SPL_NAMESPACE(spl_convert_to_custom_float_format(c0_calc, &fmt, + &dscl_prog_data->easf_matrix_c0)); + // fp1.5.10, C1 coefficient (LN_rec709: HDR_MULT * 0.715200 * 2^14/125) + SPL_NAMESPACE(spl_convert_to_custom_float_format(c1_calc, &fmt, + &dscl_prog_data->easf_matrix_c1)); + // fp1.5.10, C2 coefficient (LN_rec709: HDR_MULT * 0.072200 * 2^14/125) + SPL_NAMESPACE(spl_convert_to_custom_float_format(c2_calc, &fmt, + &dscl_prog_data->easf_matrix_c2)); + dscl_prog_data->easf_matrix_c3 = 0x0; // fp1.5.10, C3 coefficient +} + +/* Set EASF data */ +static void spl_set_easf_data(struct spl_scratch *spl_scratch, struct spl_out *spl_out, bool enable_easf_v, + bool enable_easf_h, enum linear_light_scaling lls_pref, + enum spl_pixel_format format, enum system_setup setup, + uint32_t sdr_white_level_nits) +{ + struct dscl_prog_data *dscl_prog_data = spl_out->dscl_prog_data; + if (enable_easf_v) { + dscl_prog_data->easf_v_en = true; + dscl_prog_data->easf_v_ring = 0; + dscl_prog_data->easf_v_sharp_factor = 1; + dscl_prog_data->easf_v_bf1_en = 1; // 1-bit, BF1 calculation enable, 0=disable, 1=enable + dscl_prog_data->easf_v_bf2_mode = 0xF; // 4-bit, BF2 calculation mode + /* 2-bit, BF3 chroma mode correction calculation mode */ + dscl_prog_data->easf_v_bf3_mode = SPL_NAMESPACE(spl_get_v_bf3_mode( + spl_scratch->scl_data.recip_ratios.vert)); + /* FP1.5.10 [ minCoef ]*/ + dscl_prog_data->easf_v_ringest_3tap_dntilt_uptilt = + SPL_NAMESPACE(spl_get_3tap_dntilt_uptilt_offset(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert)); + /* FP1.5.10 [ upTiltMaxVal ]*/ + dscl_prog_data->easf_v_ringest_3tap_uptilt_max = + SPL_NAMESPACE(spl_get_3tap_uptilt_maxval(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert)); + /* FP1.5.10 [ dnTiltSlope ]*/ + dscl_prog_data->easf_v_ringest_3tap_dntilt_slope = + SPL_NAMESPACE(spl_get_3tap_dntilt_slope(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert)); + /* FP1.5.10 [ upTilt1Slope ]*/ + dscl_prog_data->easf_v_ringest_3tap_uptilt1_slope = + SPL_NAMESPACE(spl_get_3tap_uptilt1_slope(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert)); + /* FP1.5.10 [ upTilt2Slope ]*/ + dscl_prog_data->easf_v_ringest_3tap_uptilt2_slope = + SPL_NAMESPACE(spl_get_3tap_uptilt2_slope(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert)); + /* FP1.5.10 [ upTilt2Offset ]*/ + dscl_prog_data->easf_v_ringest_3tap_uptilt2_offset = + SPL_NAMESPACE(spl_get_3tap_uptilt2_offset(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert)); + /* FP1.5.10; (2.0) Ring reducer gain for 4 or 6-tap mode [H_REDUCER_GAIN4] */ + dscl_prog_data->easf_v_ringest_eventap_reduceg1 = + SPL_NAMESPACE(spl_get_reducer_gain4(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert)); + /* FP1.5.10; (2.5) Ring reducer gain for 6-tap mode [V_REDUCER_GAIN6] */ + dscl_prog_data->easf_v_ringest_eventap_reduceg2 = + SPL_NAMESPACE(spl_get_reducer_gain6(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert)); + /* FP1.5.10; (-0.135742) Ring gain for 6-tap set to -139/1024 */ + dscl_prog_data->easf_v_ringest_eventap_gain1 = + SPL_NAMESPACE(spl_get_gainRing4(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert)); + /* FP1.5.10; (-0.024414) Ring gain for 6-tap set to -25/1024 */ + dscl_prog_data->easf_v_ringest_eventap_gain2 = + SPL_NAMESPACE(spl_get_gainRing6(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert)); + dscl_prog_data->easf_v_bf_maxa = 63; //Vertical Max BF value A in U0.6 format.Selected if V_FCNTL == 0 + dscl_prog_data->easf_v_bf_maxb = 63; //Vertical Max BF value A in U0.6 format.Selected if V_FCNTL == 1 + dscl_prog_data->easf_v_bf_mina = 0; //Vertical Min BF value A in U0.6 format.Selected if V_FCNTL == 0 + dscl_prog_data->easf_v_bf_minb = 0; //Vertical Min BF value A in U0.6 format.Selected if V_FCNTL == 1 + if (lls_pref == LLS_PREF_YES) { + dscl_prog_data->easf_v_bf2_flat1_gain = 4; // U1.3, BF2 Flat1 Gain control + dscl_prog_data->easf_v_bf2_flat2_gain = 8; // U4.0, BF2 Flat2 Gain control + dscl_prog_data->easf_v_bf2_roc_gain = 4; // U2.2, Rate Of Change control + + dscl_prog_data->easf_v_bf1_pwl_in_seg0 = 0x600; // S0.10, BF1 PWL Segment 0 = -512 + dscl_prog_data->easf_v_bf1_pwl_base_seg0 = 0; // U0.6, BF1 Base PWL Segment 0 + dscl_prog_data->easf_v_bf1_pwl_slope_seg0 = 3; // S7.3, BF1 Slope PWL Segment 0 + dscl_prog_data->easf_v_bf1_pwl_in_seg1 = 0x7EC; // S0.10, BF1 PWL Segment 1 = -20 + dscl_prog_data->easf_v_bf1_pwl_base_seg1 = 12; // U0.6, BF1 Base PWL Segment 1 + dscl_prog_data->easf_v_bf1_pwl_slope_seg1 = 326; // S7.3, BF1 Slope PWL Segment 1 + dscl_prog_data->easf_v_bf1_pwl_in_seg2 = 0; // S0.10, BF1 PWL Segment 2 + dscl_prog_data->easf_v_bf1_pwl_base_seg2 = 63; // U0.6, BF1 Base PWL Segment 2 + dscl_prog_data->easf_v_bf1_pwl_slope_seg2 = 0; // S7.3, BF1 Slope PWL Segment 2 + dscl_prog_data->easf_v_bf1_pwl_in_seg3 = 16; // S0.10, BF1 PWL Segment 3 + dscl_prog_data->easf_v_bf1_pwl_base_seg3 = 63; // U0.6, BF1 Base PWL Segment 3 + dscl_prog_data->easf_v_bf1_pwl_slope_seg3 = 0x7C8; // S7.3, BF1 Slope PWL Segment 3 = -56 + dscl_prog_data->easf_v_bf1_pwl_in_seg4 = 32; // S0.10, BF1 PWL Segment 4 + dscl_prog_data->easf_v_bf1_pwl_base_seg4 = 56; // U0.6, BF1 Base PWL Segment 4 + dscl_prog_data->easf_v_bf1_pwl_slope_seg4 = 0x7D0; // S7.3, BF1 Slope PWL Segment 4 = -48 + dscl_prog_data->easf_v_bf1_pwl_in_seg5 = 48; // S0.10, BF1 PWL Segment 5 + dscl_prog_data->easf_v_bf1_pwl_base_seg5 = 50; // U0.6, BF1 Base PWL Segment 5 + dscl_prog_data->easf_v_bf1_pwl_slope_seg5 = 0x710; // S7.3, BF1 Slope PWL Segment 5 = -240 + dscl_prog_data->easf_v_bf1_pwl_in_seg6 = 64; // S0.10, BF1 PWL Segment 6 + dscl_prog_data->easf_v_bf1_pwl_base_seg6 = 20; // U0.6, BF1 Base PWL Segment 6 + dscl_prog_data->easf_v_bf1_pwl_slope_seg6 = 0x760; // S7.3, BF1 Slope PWL Segment 6 = -160 + dscl_prog_data->easf_v_bf1_pwl_in_seg7 = 80; // S0.10, BF1 PWL Segment 7 + dscl_prog_data->easf_v_bf1_pwl_base_seg7 = 0; // U0.6, BF1 Base PWL Segment 7 + + dscl_prog_data->easf_v_bf3_pwl_in_set0 = 0x000; // FP0.6.6, BF3 Input value PWL Segment 0 + dscl_prog_data->easf_v_bf3_pwl_base_set0 = 63; // S0.6, BF3 Base PWL Segment 0 + dscl_prog_data->easf_v_bf3_pwl_slope_set0 = 0x12C5; // FP1.6.6, BF3 Slope PWL Segment 0 + dscl_prog_data->easf_v_bf3_pwl_in_set1 = + 0x0B37; // FP0.6.6, BF3 Input value PWL Segment 1 (0.0078125 * 125^3) + dscl_prog_data->easf_v_bf3_pwl_base_set1 = 62; // S0.6, BF3 Base PWL Segment 1 + dscl_prog_data->easf_v_bf3_pwl_slope_set1 = + 0x13B8; // FP1.6.6, BF3 Slope PWL Segment 1 + dscl_prog_data->easf_v_bf3_pwl_in_set2 = + 0x0BB7; // FP0.6.6, BF3 Input value PWL Segment 2 (0.03125 * 125^3) + dscl_prog_data->easf_v_bf3_pwl_base_set2 = 20; // S0.6, BF3 Base PWL Segment 2 + dscl_prog_data->easf_v_bf3_pwl_slope_set2 = + 0x1356; // FP1.6.6, BF3 Slope PWL Segment 2 + dscl_prog_data->easf_v_bf3_pwl_in_set3 = + 0x0BF7; // FP0.6.6, BF3 Input value PWL Segment 3 (0.0625 * 125^3) + dscl_prog_data->easf_v_bf3_pwl_base_set3 = 0; // S0.6, BF3 Base PWL Segment 3 + dscl_prog_data->easf_v_bf3_pwl_slope_set3 = + 0x136B; // FP1.6.6, BF3 Slope PWL Segment 3 + dscl_prog_data->easf_v_bf3_pwl_in_set4 = + 0x0C37; // FP0.6.6, BF3 Input value PWL Segment 4 (0.125 * 125^3) + dscl_prog_data->easf_v_bf3_pwl_base_set4 = 0x4E; // S0.6, BF3 Base PWL Segment 4 = -50 + dscl_prog_data->easf_v_bf3_pwl_slope_set4 = + 0x1200; // FP1.6.6, BF3 Slope PWL Segment 4 + dscl_prog_data->easf_v_bf3_pwl_in_set5 = + 0x0CF7; // FP0.6.6, BF3 Input value PWL Segment 5 (1.0 * 125^3) + dscl_prog_data->easf_v_bf3_pwl_base_set5 = 0x41; // S0.6, BF3 Base PWL Segment 5 = -63 + } else { + dscl_prog_data->easf_v_bf2_flat1_gain = 13; // U1.3, BF2 Flat1 Gain control + dscl_prog_data->easf_v_bf2_flat2_gain = 15; // U4.0, BF2 Flat2 Gain control + dscl_prog_data->easf_v_bf2_roc_gain = 14; // U2.2, Rate Of Change control + + dscl_prog_data->easf_v_bf1_pwl_in_seg0 = 0x440; // S0.10, BF1 PWL Segment 0 = -960 + dscl_prog_data->easf_v_bf1_pwl_base_seg0 = 0; // U0.6, BF1 Base PWL Segment 0 + dscl_prog_data->easf_v_bf1_pwl_slope_seg0 = 2; // S7.3, BF1 Slope PWL Segment 0 + dscl_prog_data->easf_v_bf1_pwl_in_seg1 = 0x7C4; // S0.10, BF1 PWL Segment 1 = -60 + dscl_prog_data->easf_v_bf1_pwl_base_seg1 = 12; // U0.6, BF1 Base PWL Segment 1 + dscl_prog_data->easf_v_bf1_pwl_slope_seg1 = 109; // S7.3, BF1 Slope PWL Segment 1 + dscl_prog_data->easf_v_bf1_pwl_in_seg2 = 0; // S0.10, BF1 PWL Segment 2 + dscl_prog_data->easf_v_bf1_pwl_base_seg2 = 63; // U0.6, BF1 Base PWL Segment 2 + dscl_prog_data->easf_v_bf1_pwl_slope_seg2 = 0; // S7.3, BF1 Slope PWL Segment 2 + dscl_prog_data->easf_v_bf1_pwl_in_seg3 = 48; // S0.10, BF1 PWL Segment 3 + dscl_prog_data->easf_v_bf1_pwl_base_seg3 = 63; // U0.6, BF1 Base PWL Segment 3 + dscl_prog_data->easf_v_bf1_pwl_slope_seg3 = 0x7ED; // S7.3, BF1 Slope PWL Segment 3 = -19 + dscl_prog_data->easf_v_bf1_pwl_in_seg4 = 96; // S0.10, BF1 PWL Segment 4 + dscl_prog_data->easf_v_bf1_pwl_base_seg4 = 56; // U0.6, BF1 Base PWL Segment 4 + dscl_prog_data->easf_v_bf1_pwl_slope_seg4 = 0x7F0; // S7.3, BF1 Slope PWL Segment 4 = -16 + dscl_prog_data->easf_v_bf1_pwl_in_seg5 = 144; // S0.10, BF1 PWL Segment 5 + dscl_prog_data->easf_v_bf1_pwl_base_seg5 = 50; // U0.6, BF1 Base PWL Segment 5 + dscl_prog_data->easf_v_bf1_pwl_slope_seg5 = 0x7B0; // S7.3, BF1 Slope PWL Segment 5 = -80 + dscl_prog_data->easf_v_bf1_pwl_in_seg6 = 192; // S0.10, BF1 PWL Segment 6 + dscl_prog_data->easf_v_bf1_pwl_base_seg6 = 20; // U0.6, BF1 Base PWL Segment 6 + dscl_prog_data->easf_v_bf1_pwl_slope_seg6 = 0x7CB; // S7.3, BF1 Slope PWL Segment 6 = -53 + dscl_prog_data->easf_v_bf1_pwl_in_seg7 = 240; // S0.10, BF1 PWL Segment 7 + dscl_prog_data->easf_v_bf1_pwl_base_seg7 = 0; // U0.6, BF1 Base PWL Segment 7 + + dscl_prog_data->easf_v_bf3_pwl_in_set0 = 0x000; // FP0.6.6, BF3 Input value PWL Segment 0 + dscl_prog_data->easf_v_bf3_pwl_base_set0 = 63; // S0.6, BF3 Base PWL Segment 0 + dscl_prog_data->easf_v_bf3_pwl_slope_set0 = 0x0000; // FP1.6.6, BF3 Slope PWL Segment 0 + dscl_prog_data->easf_v_bf3_pwl_in_set1 = + 0x06C0; // FP0.6.6, BF3 Input value PWL Segment 1 (0.0625) + dscl_prog_data->easf_v_bf3_pwl_base_set1 = 63; // S0.6, BF3 Base PWL Segment 1 + dscl_prog_data->easf_v_bf3_pwl_slope_set1 = 0x1896; // FP1.6.6, BF3 Slope PWL Segment 1 + dscl_prog_data->easf_v_bf3_pwl_in_set2 = + 0x0700; // FP0.6.6, BF3 Input value PWL Segment 2 (0.125) + dscl_prog_data->easf_v_bf3_pwl_base_set2 = 20; // S0.6, BF3 Base PWL Segment 2 + dscl_prog_data->easf_v_bf3_pwl_slope_set2 = 0x1810; // FP1.6.6, BF3 Slope PWL Segment 2 + dscl_prog_data->easf_v_bf3_pwl_in_set3 = + 0x0740; // FP0.6.6, BF3 Input value PWL Segment 3 (0.25) + dscl_prog_data->easf_v_bf3_pwl_base_set3 = 0; // S0.6, BF3 Base PWL Segment 3 + dscl_prog_data->easf_v_bf3_pwl_slope_set3 = + 0x1878; // FP1.6.6, BF3 Slope PWL Segment 3 + dscl_prog_data->easf_v_bf3_pwl_in_set4 = + 0x0761; // FP0.6.6, BF3 Input value PWL Segment 4 (0.375) + dscl_prog_data->easf_v_bf3_pwl_base_set4 = 0x44; // S0.6, BF3 Base PWL Segment 4 = -60 + dscl_prog_data->easf_v_bf3_pwl_slope_set4 = 0x1760; // FP1.6.6, BF3 Slope PWL Segment 4 + dscl_prog_data->easf_v_bf3_pwl_in_set5 = + 0x0780; // FP0.6.6, BF3 Input value PWL Segment 5 (0.5) + dscl_prog_data->easf_v_bf3_pwl_base_set5 = 0x41; // S0.6, BF3 Base PWL Segment 5 = -63 + } + } else + dscl_prog_data->easf_v_en = false; + + if (enable_easf_h) { + dscl_prog_data->easf_h_en = true; + dscl_prog_data->easf_h_ring = 0; + dscl_prog_data->easf_h_sharp_factor = 1; + dscl_prog_data->easf_h_bf1_en = + 1; // 1-bit, BF1 calculation enable, 0=disable, 1=enable + dscl_prog_data->easf_h_bf2_mode = + 0xF; // 4-bit, BF2 calculation mode + /* 2-bit, BF3 chroma mode correction calculation mode */ + dscl_prog_data->easf_h_bf3_mode = SPL_NAMESPACE(spl_get_h_bf3_mode( + spl_scratch->scl_data.recip_ratios.horz)); + /* FP1.5.10; (2.0) Ring reducer gain for 4 or 6-tap mode [H_REDUCER_GAIN4] */ + dscl_prog_data->easf_h_ringest_eventap_reduceg1 = + SPL_NAMESPACE(spl_get_reducer_gain4(spl_scratch->scl_data.taps.h_taps, + spl_scratch->scl_data.recip_ratios.horz)); + /* FP1.5.10; (2.5) Ring reducer gain for 6-tap mode [V_REDUCER_GAIN6] */ + dscl_prog_data->easf_h_ringest_eventap_reduceg2 = + SPL_NAMESPACE(spl_get_reducer_gain6(spl_scratch->scl_data.taps.h_taps, + spl_scratch->scl_data.recip_ratios.horz)); + /* FP1.5.10; (-0.135742) Ring gain for 6-tap set to -139/1024 */ + dscl_prog_data->easf_h_ringest_eventap_gain1 = + SPL_NAMESPACE(spl_get_gainRing4(spl_scratch->scl_data.taps.h_taps, + spl_scratch->scl_data.recip_ratios.horz)); + /* FP1.5.10; (-0.024414) Ring gain for 6-tap set to -25/1024 */ + dscl_prog_data->easf_h_ringest_eventap_gain2 = + SPL_NAMESPACE(spl_get_gainRing6(spl_scratch->scl_data.taps.h_taps, + spl_scratch->scl_data.recip_ratios.horz)); + dscl_prog_data->easf_h_bf_maxa = 63; //Horz Max BF value A in U0.6 format.Selected if H_FCNTL==0 + dscl_prog_data->easf_h_bf_maxb = 63; //Horz Max BF value B in U0.6 format.Selected if H_FCNTL==1 + dscl_prog_data->easf_h_bf_mina = 0; //Horz Min BF value B in U0.6 format.Selected if H_FCNTL==0 + dscl_prog_data->easf_h_bf_minb = 0; //Horz Min BF value B in U0.6 format.Selected if H_FCNTL==1 + if (lls_pref == LLS_PREF_YES) { + dscl_prog_data->easf_h_bf2_flat1_gain = 4; // U1.3, BF2 Flat1 Gain control + dscl_prog_data->easf_h_bf2_flat2_gain = 8; // U4.0, BF2 Flat2 Gain control + dscl_prog_data->easf_h_bf2_roc_gain = 4; // U2.2, Rate Of Change control + + dscl_prog_data->easf_h_bf1_pwl_in_seg0 = 0x600; // S0.10, BF1 PWL Segment 0 = -512 + dscl_prog_data->easf_h_bf1_pwl_base_seg0 = 0; // U0.6, BF1 Base PWL Segment 0 + dscl_prog_data->easf_h_bf1_pwl_slope_seg0 = 3; // S7.3, BF1 Slope PWL Segment 0 + dscl_prog_data->easf_h_bf1_pwl_in_seg1 = 0x7EC; // S0.10, BF1 PWL Segment 1 = -20 + dscl_prog_data->easf_h_bf1_pwl_base_seg1 = 12; // U0.6, BF1 Base PWL Segment 1 + dscl_prog_data->easf_h_bf1_pwl_slope_seg1 = 326; // S7.3, BF1 Slope PWL Segment 1 + dscl_prog_data->easf_h_bf1_pwl_in_seg2 = 0; // S0.10, BF1 PWL Segment 2 + dscl_prog_data->easf_h_bf1_pwl_base_seg2 = 63; // U0.6, BF1 Base PWL Segment 2 + dscl_prog_data->easf_h_bf1_pwl_slope_seg2 = 0; // S7.3, BF1 Slope PWL Segment 2 + dscl_prog_data->easf_h_bf1_pwl_in_seg3 = 16; // S0.10, BF1 PWL Segment 3 + dscl_prog_data->easf_h_bf1_pwl_base_seg3 = 63; // U0.6, BF1 Base PWL Segment 3 + dscl_prog_data->easf_h_bf1_pwl_slope_seg3 = 0x7C8; // S7.3, BF1 Slope PWL Segment 3 = -56 + dscl_prog_data->easf_h_bf1_pwl_in_seg4 = 32; // S0.10, BF1 PWL Segment 4 + dscl_prog_data->easf_h_bf1_pwl_base_seg4 = 56; // U0.6, BF1 Base PWL Segment 4 + dscl_prog_data->easf_h_bf1_pwl_slope_seg4 = 0x7D0; // S7.3, BF1 Slope PWL Segment 4 = -48 + dscl_prog_data->easf_h_bf1_pwl_in_seg5 = 48; // S0.10, BF1 PWL Segment 5 + dscl_prog_data->easf_h_bf1_pwl_base_seg5 = 50; // U0.6, BF1 Base PWL Segment 5 + dscl_prog_data->easf_h_bf1_pwl_slope_seg5 = 0x710; // S7.3, BF1 Slope PWL Segment 5 = -240 + dscl_prog_data->easf_h_bf1_pwl_in_seg6 = 64; // S0.10, BF1 PWL Segment 6 + dscl_prog_data->easf_h_bf1_pwl_base_seg6 = 20; // U0.6, BF1 Base PWL Segment 6 + dscl_prog_data->easf_h_bf1_pwl_slope_seg6 = 0x760; // S7.3, BF1 Slope PWL Segment 6 = -160 + dscl_prog_data->easf_h_bf1_pwl_in_seg7 = 80; // S0.10, BF1 PWL Segment 7 + dscl_prog_data->easf_h_bf1_pwl_base_seg7 = 0; // U0.6, BF1 Base PWL Segment 7 + + dscl_prog_data->easf_h_bf3_pwl_in_set0 = 0x000; // FP0.6.6, BF3 Input value PWL Segment 0 + dscl_prog_data->easf_h_bf3_pwl_base_set0 = 63; // S0.6, BF3 Base PWL Segment 0 + dscl_prog_data->easf_h_bf3_pwl_slope_set0 = 0x12C5; // FP1.6.6, BF3 Slope PWL Segment 0 + dscl_prog_data->easf_h_bf3_pwl_in_set1 = + 0x0B37; // FP0.6.6, BF3 Input value PWL Segment 1 (0.0078125 * 125^3) + dscl_prog_data->easf_h_bf3_pwl_base_set1 = 62; // S0.6, BF3 Base PWL Segment 1 + dscl_prog_data->easf_h_bf3_pwl_slope_set1 = 0x13B8; // FP1.6.6, BF3 Slope PWL Segment 1 + dscl_prog_data->easf_h_bf3_pwl_in_set2 = + 0x0BB7; // FP0.6.6, BF3 Input value PWL Segment 2 (0.03125 * 125^3) + dscl_prog_data->easf_h_bf3_pwl_base_set2 = 20; // S0.6, BF3 Base PWL Segment 2 + dscl_prog_data->easf_h_bf3_pwl_slope_set2 = 0x1356; // FP1.6.6, BF3 Slope PWL Segment 2 + dscl_prog_data->easf_h_bf3_pwl_in_set3 = + 0x0BF7; // FP0.6.6, BF3 Input value PWL Segment 3 (0.0625 * 125^3) + dscl_prog_data->easf_h_bf3_pwl_base_set3 = 0; // S0.6, BF3 Base PWL Segment 3 + dscl_prog_data->easf_h_bf3_pwl_slope_set3 = 0x136B; // FP1.6.6, BF3 Slope PWL Segment 3 + dscl_prog_data->easf_h_bf3_pwl_in_set4 = + 0x0C37; // FP0.6.6, BF3 Input value PWL Segment 4 (0.125 * 125^3) + dscl_prog_data->easf_h_bf3_pwl_base_set4 = 0x4E; // S0.6, BF3 Base PWL Segment 4 = -50 + dscl_prog_data->easf_h_bf3_pwl_slope_set4 = 0x1200; // FP1.6.6, BF3 Slope PWL Segment 4 + dscl_prog_data->easf_h_bf3_pwl_in_set5 = + 0x0CF7; // FP0.6.6, BF3 Input value PWL Segment 5 (1.0 * 125^3) + dscl_prog_data->easf_h_bf3_pwl_base_set5 = 0x41; // S0.6, BF3 Base PWL Segment 5 = -63 + } else { + dscl_prog_data->easf_h_bf2_flat1_gain = 13; // U1.3, BF2 Flat1 Gain control + dscl_prog_data->easf_h_bf2_flat2_gain = 15; // U4.0, BF2 Flat2 Gain control + dscl_prog_data->easf_h_bf2_roc_gain = 14; // U2.2, Rate Of Change control + + dscl_prog_data->easf_h_bf1_pwl_in_seg0 = 0x440; // S0.10, BF1 PWL Segment 0 = -960 + dscl_prog_data->easf_h_bf1_pwl_base_seg0 = 0; // U0.6, BF1 Base PWL Segment 0 + dscl_prog_data->easf_h_bf1_pwl_slope_seg0 = 2; // S7.3, BF1 Slope PWL Segment 0 + dscl_prog_data->easf_h_bf1_pwl_in_seg1 = 0x7C4; // S0.10, BF1 PWL Segment 1 = -60 + dscl_prog_data->easf_h_bf1_pwl_base_seg1 = 12; // U0.6, BF1 Base PWL Segment 1 + dscl_prog_data->easf_h_bf1_pwl_slope_seg1 = 109; // S7.3, BF1 Slope PWL Segment 1 + dscl_prog_data->easf_h_bf1_pwl_in_seg2 = 0; // S0.10, BF1 PWL Segment 2 + dscl_prog_data->easf_h_bf1_pwl_base_seg2 = 63; // U0.6, BF1 Base PWL Segment 2 + dscl_prog_data->easf_h_bf1_pwl_slope_seg2 = 0; // S7.3, BF1 Slope PWL Segment 2 + dscl_prog_data->easf_h_bf1_pwl_in_seg3 = 48; // S0.10, BF1 PWL Segment 3 + dscl_prog_data->easf_h_bf1_pwl_base_seg3 = 63; // U0.6, BF1 Base PWL Segment 3 + dscl_prog_data->easf_h_bf1_pwl_slope_seg3 = 0x7ED; // S7.3, BF1 Slope PWL Segment 3 = -19 + dscl_prog_data->easf_h_bf1_pwl_in_seg4 = 96; // S0.10, BF1 PWL Segment 4 + dscl_prog_data->easf_h_bf1_pwl_base_seg4 = 56; // U0.6, BF1 Base PWL Segment 4 + dscl_prog_data->easf_h_bf1_pwl_slope_seg4 = 0x7F0; // S7.3, BF1 Slope PWL Segment 4 = -16 + dscl_prog_data->easf_h_bf1_pwl_in_seg5 = 144; // S0.10, BF1 PWL Segment 5 + dscl_prog_data->easf_h_bf1_pwl_base_seg5 = 50; // U0.6, BF1 Base PWL Segment 5 + dscl_prog_data->easf_h_bf1_pwl_slope_seg5 = 0x7B0; // S7.3, BF1 Slope PWL Segment 5 = -80 + dscl_prog_data->easf_h_bf1_pwl_in_seg6 = 192; // S0.10, BF1 PWL Segment 6 + dscl_prog_data->easf_h_bf1_pwl_base_seg6 = 20; // U0.6, BF1 Base PWL Segment 6 + dscl_prog_data->easf_h_bf1_pwl_slope_seg6 = 0x7CB; // S7.3, BF1 Slope PWL Segment 6 = -53 + dscl_prog_data->easf_h_bf1_pwl_in_seg7 = 240; // S0.10, BF1 PWL Segment 7 + dscl_prog_data->easf_h_bf1_pwl_base_seg7 = 0; // U0.6, BF1 Base PWL Segment 7 + + dscl_prog_data->easf_h_bf3_pwl_in_set0 = 0x000; // FP0.6.6, BF3 Input value PWL Segment 0 + dscl_prog_data->easf_h_bf3_pwl_base_set0 = 63; // S0.6, BF3 Base PWL Segment 0 + dscl_prog_data->easf_h_bf3_pwl_slope_set0 = 0x0000; // FP1.6.6, BF3 Slope PWL Segment 0 + dscl_prog_data->easf_h_bf3_pwl_in_set1 = + 0x06C0; // FP0.6.6, BF3 Input value PWL Segment 1 (0.0625) + dscl_prog_data->easf_h_bf3_pwl_base_set1 = 63; // S0.6, BF3 Base PWL Segment 1 + dscl_prog_data->easf_h_bf3_pwl_slope_set1 = 0x1896; // FP1.6.6, BF3 Slope PWL Segment 1 + dscl_prog_data->easf_h_bf3_pwl_in_set2 = + 0x0700; // FP0.6.6, BF3 Input value PWL Segment 2 (0.125) + dscl_prog_data->easf_h_bf3_pwl_base_set2 = 20; // S0.6, BF3 Base PWL Segment 2 + dscl_prog_data->easf_h_bf3_pwl_slope_set2 = 0x1810; // FP1.6.6, BF3 Slope PWL Segment 2 + dscl_prog_data->easf_h_bf3_pwl_in_set3 = + 0x0740; // FP0.6.6, BF3 Input value PWL Segment 3 (0.25) + dscl_prog_data->easf_h_bf3_pwl_base_set3 = 0; // S0.6, BF3 Base PWL Segment 3 + dscl_prog_data->easf_h_bf3_pwl_slope_set3 = 0x1878; // FP1.6.6, BF3 Slope PWL Segment 3 + dscl_prog_data->easf_h_bf3_pwl_in_set4 = + 0x0761; // FP0.6.6, BF3 Input value PWL Segment 4 (0.375) + dscl_prog_data->easf_h_bf3_pwl_base_set4 = 0x44; // S0.6, BF3 Base PWL Segment 4 = -60 + dscl_prog_data->easf_h_bf3_pwl_slope_set4 = 0x1760; // FP1.6.6, BF3 Slope PWL Segment 4 + dscl_prog_data->easf_h_bf3_pwl_in_set5 = + 0x0780; // FP0.6.6, BF3 Input value PWL Segment 5 (0.5) + dscl_prog_data->easf_h_bf3_pwl_base_set5 = 0x41; // S0.6, BF3 Base PWL Segment 5 = -63 + } // if (lls_pref == LLS_PREF_YES) + } else + dscl_prog_data->easf_h_en = false; + + if (lls_pref == LLS_PREF_YES) { + dscl_prog_data->easf_ltonl_en = 1; // Linear input + if ((setup == HDR_L) && (spl_is_rgb8(format))) { + /* Calculate C0-C3 coefficients based on HDR multiplier */ + spl_calculate_c0_c3_hdr(dscl_prog_data, sdr_white_level_nits); + } else { // HDR_L ( DWM ) and SDR_L + dscl_prog_data->easf_matrix_c0 = + 0x4EF7; // fp1.5.10, C0 coefficient (LN_rec709: 0.2126 * (2^14)/125 = 27.86590720) + dscl_prog_data->easf_matrix_c1 = + 0x55DC; // fp1.5.10, C1 coefficient (LN_rec709: 0.7152 * (2^14)/125 = 93.74269440) + dscl_prog_data->easf_matrix_c2 = + 0x48BB; // fp1.5.10, C2 coefficient (LN_rec709: 0.0722 * (2^14)/125 = 9.46339840) + dscl_prog_data->easf_matrix_c3 = + 0x0; // fp1.5.10, C3 coefficient + } + } else { + dscl_prog_data->easf_ltonl_en = 0; // Non-Linear input + dscl_prog_data->easf_matrix_c0 = + 0x3434; // fp1.5.10, C0 coefficient (LN_BT2020: 0.262695312500000) + dscl_prog_data->easf_matrix_c1 = + 0x396D; // fp1.5.10, C1 coefficient (LN_BT2020: 0.678222656250000) + dscl_prog_data->easf_matrix_c2 = + 0x2B97; // fp1.5.10, C2 coefficient (LN_BT2020: 0.059295654296875) + dscl_prog_data->easf_matrix_c3 = + 0x0; // fp1.5.10, C3 coefficient + } + + if (spl_is_subsampled_format(format)) { /* TODO: 0 = RGB, 1 = YUV */ + dscl_prog_data->easf_matrix_mode = 1; + /* + * 2-bit, BF3 chroma mode correction calculation mode + * Needs to be disabled for YUV420 mode + * Override lookup value + */ + dscl_prog_data->easf_v_bf3_mode = 0; + dscl_prog_data->easf_h_bf3_mode = 0; + } else + dscl_prog_data->easf_matrix_mode = 0; + +} + +/*Set isharp noise detection */ +static void spl_set_isharp_noise_det_mode(struct dscl_prog_data *dscl_prog_data, + const struct spl_scaler_data *data) +{ + // ISHARP_NOISEDET_MODE + // 0: 3x5 as VxH + // 1: 4x5 as VxH + // 2: + // 3: 5x5 as VxH + if (data->taps.v_taps == 6) + dscl_prog_data->isharp_noise_det.mode = 3; + else if (data->taps.v_taps == 4) + dscl_prog_data->isharp_noise_det.mode = 1; + else if (data->taps.v_taps == 3) + dscl_prog_data->isharp_noise_det.mode = 0; +}; +/* Set Sharpener data */ +static void spl_set_isharp_data(struct dscl_prog_data *dscl_prog_data, + struct adaptive_sharpness adp_sharpness, bool enable_isharp, + enum linear_light_scaling lls_pref, enum spl_pixel_format format, + const struct spl_scaler_data *data, struct spl_fixed31_32 ratio, + enum system_setup setup, enum scale_to_sharpness_policy scale_to_sharpness_policy) +{ + (void)format; + /* Turn off sharpener if not required */ + if (!enable_isharp) { + dscl_prog_data->isharp_en = 0; + return; + } + + SPL_NAMESPACE(spl_build_isharp_1dlut_from_reference_curve(ratio, setup, adp_sharpness, + scale_to_sharpness_policy)); + memcpy(dscl_prog_data->isharp_delta, SPL_NAMESPACE(spl_get_pregen_filter_isharp_1D_lut(setup)), + sizeof(uint32_t) * ISHARP_LUT_TABLE_SIZE); + dscl_prog_data->sharpness_level = adp_sharpness.sharpness_level; + + dscl_prog_data->isharp_en = 1; // ISHARP_EN + // Set ISHARP_NOISEDET_MODE if htaps = 6-tap + if (data->taps.h_taps == 6) { + dscl_prog_data->isharp_noise_det.enable = 1; /* ISHARP_NOISEDET_EN */ + spl_set_isharp_noise_det_mode(dscl_prog_data, data); /* ISHARP_NOISEDET_MODE */ + } else + dscl_prog_data->isharp_noise_det.enable = 0; // ISHARP_NOISEDET_EN + // Program noise detection threshold + dscl_prog_data->isharp_noise_det.uthreshold = 24; // ISHARP_NOISEDET_UTHRE + dscl_prog_data->isharp_noise_det.dthreshold = 4; // ISHARP_NOISEDET_DTHRE + // Program noise detection gain + dscl_prog_data->isharp_noise_det.pwl_start_in = 3; // ISHARP_NOISEDET_PWL_START_IN + dscl_prog_data->isharp_noise_det.pwl_end_in = 13; // ISHARP_NOISEDET_PWL_END_IN + dscl_prog_data->isharp_noise_det.pwl_slope = 1623; // ISHARP_NOISEDET_PWL_SLOPE + + if (lls_pref == LLS_PREF_NO) /* ISHARP_FMT_MODE */ + dscl_prog_data->isharp_fmt.mode = 1; + else + dscl_prog_data->isharp_fmt.mode = 0; + + dscl_prog_data->isharp_fmt.norm = 0x3C00; // ISHARP_FMT_NORM + dscl_prog_data->isharp_lba.mode = 0; // ISHARP_LBA_MODE + + if (setup == SDR_L) { + // ISHARP_LBA_PWL_SEG0: ISHARP Local Brightness Adjustment PWL Segment 0 + dscl_prog_data->isharp_lba.in_seg[0] = 0; // ISHARP LBA PWL for Seg 0. INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[0] = 0; // ISHARP LBA PWL for Seg 0. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[0] = 62; // ISHARP LBA for Seg 0. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG1: ISHARP LBA PWL Segment 1 + dscl_prog_data->isharp_lba.in_seg[1] = 130; // ISHARP LBA PWL for Seg 1. INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[1] = 63; // ISHARP LBA PWL for Seg 1. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[1] = 0; // ISHARP LBA for Seg 1. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG2: ISHARP LBA PWL Segment 2 + dscl_prog_data->isharp_lba.in_seg[2] = 450; // ISHARP LBA PWL for Seg 2. INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[2] = 63; // ISHARP LBA PWL for Seg 2. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[2] = 0x18D; // ISHARP LBA for Seg 2. SLOPE value in S5.3 format = -115 + // ISHARP_LBA_PWL_SEG3: ISHARP LBA PWL Segment 3 + dscl_prog_data->isharp_lba.in_seg[3] = 520; // ISHARP LBA PWL for Seg 3.INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[3] = 0; // ISHARP LBA PWL for Seg 3. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[3] = 0; // ISHARP LBA for Seg 3. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG4: ISHARP LBA PWL Segment 4 + dscl_prog_data->isharp_lba.in_seg[4] = 520; // ISHARP LBA PWL for Seg 4.INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[4] = 0; // ISHARP LBA PWL for Seg 4. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[4] = 0; // ISHARP LBA for Seg 4. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG5: ISHARP LBA PWL Segment 5 + dscl_prog_data->isharp_lba.in_seg[5] = 520; // ISHARP LBA PWL for Seg 5.INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[5] = 0; // ISHARP LBA PWL for Seg 5. BASE value in U0.6 format + } else if (setup == HDR_L) { + // ISHARP_LBA_PWL_SEG0: ISHARP Local Brightness Adjustment PWL Segment 0 + dscl_prog_data->isharp_lba.in_seg[0] = 0; // ISHARP LBA PWL for Seg 0. INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[0] = 0; // ISHARP LBA PWL for Seg 0. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[0] = 32; // ISHARP LBA for Seg 0. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG1: ISHARP LBA PWL Segment 1 + dscl_prog_data->isharp_lba.in_seg[1] = 254; // ISHARP LBA PWL for Seg 1. INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[1] = 63; // ISHARP LBA PWL for Seg 1. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[1] = 0; // ISHARP LBA for Seg 1. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG2: ISHARP LBA PWL Segment 2 + dscl_prog_data->isharp_lba.in_seg[2] = 559; // ISHARP LBA PWL for Seg 2. INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[2] = 63; // ISHARP LBA PWL for Seg 2. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[2] = 0x10C; // ISHARP LBA for Seg 2. SLOPE value in S5.3 format = -244 + // ISHARP_LBA_PWL_SEG3: ISHARP LBA PWL Segment 3 + dscl_prog_data->isharp_lba.in_seg[3] = 592; // ISHARP LBA PWL for Seg 3.INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[3] = 0; // ISHARP LBA PWL for Seg 3. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[3] = 0; // ISHARP LBA for Seg 3. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG4: ISHARP LBA PWL Segment 4 + dscl_prog_data->isharp_lba.in_seg[4] = 1023; // ISHARP LBA PWL for Seg 4.INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[4] = 0; // ISHARP LBA PWL for Seg 4. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[4] = 0; // ISHARP LBA for Seg 4. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG5: ISHARP LBA PWL Segment 5 + dscl_prog_data->isharp_lba.in_seg[5] = 1023; // ISHARP LBA PWL for Seg 5.INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[5] = 0; // ISHARP LBA PWL for Seg 5. BASE value in U0.6 format + } else { + // ISHARP_LBA_PWL_SEG0: ISHARP Local Brightness Adjustment PWL Segment 0 + dscl_prog_data->isharp_lba.in_seg[0] = 0; // ISHARP LBA PWL for Seg 0. INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[0] = 0; // ISHARP LBA PWL for Seg 0. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[0] = 40; // ISHARP LBA for Seg 0. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG1: ISHARP LBA PWL Segment 1 + dscl_prog_data->isharp_lba.in_seg[1] = 204; // ISHARP LBA PWL for Seg 1. INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[1] = 63; // ISHARP LBA PWL for Seg 1. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[1] = 0; // ISHARP LBA for Seg 1. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG2: ISHARP LBA PWL Segment 2 + dscl_prog_data->isharp_lba.in_seg[2] = 818; // ISHARP LBA PWL for Seg 2. INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[2] = 63; // ISHARP LBA PWL for Seg 2. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[2] = 0x1D9; // ISHARP LBA for Seg 2. SLOPE value in S5.3 format = -39 + // ISHARP_LBA_PWL_SEG3: ISHARP LBA PWL Segment 3 + dscl_prog_data->isharp_lba.in_seg[3] = 1023; // ISHARP LBA PWL for Seg 3.INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[3] = 0; // ISHARP LBA PWL for Seg 3. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[3] = 0; // ISHARP LBA for Seg 3. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG4: ISHARP LBA PWL Segment 4 + dscl_prog_data->isharp_lba.in_seg[4] = 1023; // ISHARP LBA PWL for Seg 4.INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[4] = 0; // ISHARP LBA PWL for Seg 4. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[4] = 0; // ISHARP LBA for Seg 4. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG5: ISHARP LBA PWL Segment 5 + dscl_prog_data->isharp_lba.in_seg[5] = 1023; // ISHARP LBA PWL for Seg 5.INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[5] = 0; // ISHARP LBA PWL for Seg 5. BASE value in U0.6 format + } + + // Program the nldelta soft clip values + if (lls_pref == LLS_PREF_YES) { + dscl_prog_data->isharp_nldelta_sclip.enable_p = 0; /* ISHARP_NLDELTA_SCLIP_EN_P */ + dscl_prog_data->isharp_nldelta_sclip.pivot_p = 0; /* ISHARP_NLDELTA_SCLIP_PIVOT_P */ + dscl_prog_data->isharp_nldelta_sclip.slope_p = 0; /* ISHARP_NLDELTA_SCLIP_SLOPE_P */ + dscl_prog_data->isharp_nldelta_sclip.enable_n = 1; /* ISHARP_NLDELTA_SCLIP_EN_N */ + dscl_prog_data->isharp_nldelta_sclip.pivot_n = 71; /* ISHARP_NLDELTA_SCLIP_PIVOT_N */ + dscl_prog_data->isharp_nldelta_sclip.slope_n = 16; /* ISHARP_NLDELTA_SCLIP_SLOPE_N */ + } else { + dscl_prog_data->isharp_nldelta_sclip.enable_p = 1; /* ISHARP_NLDELTA_SCLIP_EN_P */ + dscl_prog_data->isharp_nldelta_sclip.pivot_p = 70; /* ISHARP_NLDELTA_SCLIP_PIVOT_P */ + dscl_prog_data->isharp_nldelta_sclip.slope_p = 24; /* ISHARP_NLDELTA_SCLIP_SLOPE_P */ + dscl_prog_data->isharp_nldelta_sclip.enable_n = 1; /* ISHARP_NLDELTA_SCLIP_EN_N */ + dscl_prog_data->isharp_nldelta_sclip.pivot_n = 70; /* ISHARP_NLDELTA_SCLIP_PIVOT_N */ + dscl_prog_data->isharp_nldelta_sclip.slope_n = 24; /* ISHARP_NLDELTA_SCLIP_SLOPE_N */ + } + + // Set the values as per lookup table + SPL_NAMESPACE(spl_set_blur_scale_data(dscl_prog_data, data)); +} +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) + +static void determine_upsp_values(struct spl_in *spl_in, struct dscl_prog_data *dscl_prog_data) +{ + dscl_prog_data->upsp_mode = spl_in->upsp_mode; + + if (dscl_prog_data->upsp_mode == UPSP_BYPASS) { //Set all UPSP register fields to 0 if bypass + dscl_prog_data->upsp_v_num_taps = UPSP_2_TAPS; + dscl_prog_data->upsp_h_num_taps = UPSP_2_TAPS; + dscl_prog_data->upsp_boundary_mode = UPSP_BOUNDARY_BLACK; + dscl_prog_data->upsp_v_init_int = 0x0; + dscl_prog_data->upsp_v_init_frac = 0x0; + dscl_prog_data->upsp_v_coef_tap0_p0 = 0x0; + dscl_prog_data->upsp_v_coef_tap1_p0 = 0x0; + dscl_prog_data->upsp_v_coef_tap2_p0 = 0x0; + dscl_prog_data->upsp_v_coef_tap3_p0 = 0x0; + dscl_prog_data->upsp_v_coef_tap0_p1 = 0x0; + dscl_prog_data->upsp_v_coef_tap1_p1 = 0x0; + dscl_prog_data->upsp_v_coef_tap2_p1 = 0x0; + dscl_prog_data->upsp_v_coef_tap3_p1 = 0x0; + dscl_prog_data->upsp_h_init_int = 0x0; + dscl_prog_data->upsp_h_init_frac = 0x0; + dscl_prog_data->upsp_h_coef_tap0_p0 = 0x0; + dscl_prog_data->upsp_h_coef_tap1_p0 = 0x0; + dscl_prog_data->upsp_h_coef_tap2_p0 = 0x0; + dscl_prog_data->upsp_h_coef_tap3_p0 = 0x0; + dscl_prog_data->upsp_h_coef_tap0_p1 = 0x0; + dscl_prog_data->upsp_h_coef_tap1_p1 = 0x0; + dscl_prog_data->upsp_h_coef_tap2_p1 = 0x0; + dscl_prog_data->upsp_h_coef_tap3_p1 = 0x0; + dscl_prog_data->upsp_clamp_max = 0x0; + dscl_prog_data->upsp_clamp_min = 0x0; + } else { + dscl_prog_data->upsp_v_num_taps = UPSP_4_TAPS; + dscl_prog_data->upsp_h_num_taps = UPSP_4_TAPS; + dscl_prog_data->upsp_boundary_mode = UPSP_BOUNDARY_EDGE; + dscl_prog_data->upsp_clamp_max = 0xFFF;//4095 + dscl_prog_data->upsp_clamp_min = 0x0; + + if (spl_in->basic_in.cositing == CHROMA_COSITING_TOPLEFT) { //Vertical Subsampling: Co-sited + if (dscl_prog_data->upsp_v_num_taps == UPSP_4_TAPS) { + dscl_prog_data->upsp_v_init_int = 0x3; + dscl_prog_data->upsp_v_init_frac = 0x0; + dscl_prog_data->upsp_v_coef_tap0_p0 = 0x00; + dscl_prog_data->upsp_v_coef_tap1_p0 = 0x40; + dscl_prog_data->upsp_v_coef_tap2_p0 = 0x00; + dscl_prog_data->upsp_v_coef_tap3_p0 = 0x00; + dscl_prog_data->upsp_v_coef_tap0_p1 = 0xFC; + dscl_prog_data->upsp_v_coef_tap1_p1 = 0x24; + dscl_prog_data->upsp_v_coef_tap2_p1 = 0x24; + dscl_prog_data->upsp_v_coef_tap3_p1 = 0xFC; + } else { //2 taps + dscl_prog_data->upsp_v_init_int = 0x2; + dscl_prog_data->upsp_v_init_frac = 0x0; + dscl_prog_data->upsp_v_coef_tap0_p0 = 0x40; + dscl_prog_data->upsp_v_coef_tap1_p0 = 0x00; + dscl_prog_data->upsp_v_coef_tap2_p0 = 0x00; + dscl_prog_data->upsp_v_coef_tap3_p0 = 0x00; + dscl_prog_data->upsp_v_coef_tap0_p1 = 0x20; + dscl_prog_data->upsp_v_coef_tap1_p1 = 0x20; + dscl_prog_data->upsp_v_coef_tap2_p1 = 0x00; + dscl_prog_data->upsp_v_coef_tap3_p1 = 0x00; + } + } else { //Vertical Subsampling: Interstitial + if (dscl_prog_data->upsp_v_num_taps == UPSP_4_TAPS) { + dscl_prog_data->upsp_v_init_int = 0x2; + dscl_prog_data->upsp_v_init_frac = 0x1; + dscl_prog_data->upsp_v_coef_tap0_p0 = 0xFB; + dscl_prog_data->upsp_v_coef_tap1_p0 = 0x2F; + dscl_prog_data->upsp_v_coef_tap2_p0 = 0x19; + dscl_prog_data->upsp_v_coef_tap3_p0 = 0xFD; + dscl_prog_data->upsp_v_coef_tap0_p1 = 0xFD; + dscl_prog_data->upsp_v_coef_tap1_p1 = 0x19; + dscl_prog_data->upsp_v_coef_tap2_p1 = 0x2F; + dscl_prog_data->upsp_v_coef_tap3_p1 = 0xFB; + } else { //2 taps + dscl_prog_data->upsp_v_init_int = 0x1; + dscl_prog_data->upsp_v_init_frac = 0x1; + dscl_prog_data->upsp_v_coef_tap0_p0 = 0x28; + dscl_prog_data->upsp_v_coef_tap1_p0 = 0x18; + dscl_prog_data->upsp_v_coef_tap2_p0 = 0x00; + dscl_prog_data->upsp_v_coef_tap3_p0 = 0x00; + dscl_prog_data->upsp_v_coef_tap0_p1 = 0x18; + dscl_prog_data->upsp_v_coef_tap1_p1 = 0x28; + dscl_prog_data->upsp_v_coef_tap2_p1 = 0x00; + dscl_prog_data->upsp_v_coef_tap3_p1 = 0x00; + } + } + if (spl_in->basic_in.cositing == CHROMA_COSITING_LEFT || spl_in->basic_in.cositing == CHROMA_COSITING_TOPLEFT) { //Horizontal Subsampling: Co-sited + if (dscl_prog_data->upsp_h_num_taps == UPSP_4_TAPS) { + dscl_prog_data->upsp_h_init_int = 0x3; + dscl_prog_data->upsp_h_init_frac = 0x0; + dscl_prog_data->upsp_h_coef_tap0_p0 = 0x00; + dscl_prog_data->upsp_h_coef_tap1_p0 = 0x40; + dscl_prog_data->upsp_h_coef_tap2_p0 = 0x00; + dscl_prog_data->upsp_h_coef_tap3_p0 = 0x00; + dscl_prog_data->upsp_h_coef_tap0_p1 = 0xFC; + dscl_prog_data->upsp_h_coef_tap1_p1 = 0x24; + dscl_prog_data->upsp_h_coef_tap2_p1 = 0x24; + dscl_prog_data->upsp_h_coef_tap3_p1 = 0xFC; + } else { //2 taps + dscl_prog_data->upsp_h_init_int = 0x2; + dscl_prog_data->upsp_h_init_frac = 0x0; + dscl_prog_data->upsp_h_coef_tap0_p0 = 0x40; + dscl_prog_data->upsp_h_coef_tap1_p0 = 0x00; + dscl_prog_data->upsp_h_coef_tap2_p0 = 0x00; + dscl_prog_data->upsp_h_coef_tap3_p0 = 0x00; + dscl_prog_data->upsp_h_coef_tap0_p1 = 0x20; + dscl_prog_data->upsp_h_coef_tap1_p1 = 0x20; + dscl_prog_data->upsp_h_coef_tap2_p1 = 0x00; + dscl_prog_data->upsp_h_coef_tap3_p1 = 0x00; + } + } else { //Horizontal Subsampling: Interstitial + if (dscl_prog_data->upsp_h_num_taps == UPSP_4_TAPS) { + dscl_prog_data->upsp_h_init_int = 0x2; + dscl_prog_data->upsp_h_init_frac = 0x1; + dscl_prog_data->upsp_h_coef_tap0_p0 = 0xFB; + dscl_prog_data->upsp_h_coef_tap1_p0 = 0x2F; + dscl_prog_data->upsp_h_coef_tap2_p0 = 0x19; + dscl_prog_data->upsp_h_coef_tap3_p0 = 0xFD; + dscl_prog_data->upsp_h_coef_tap0_p1 = 0xFD; + dscl_prog_data->upsp_h_coef_tap1_p1 = 0x19; + dscl_prog_data->upsp_h_coef_tap2_p1 = 0x2F; + dscl_prog_data->upsp_h_coef_tap3_p1 = 0xFB; + } else { //2 taps + dscl_prog_data->upsp_h_init_int = 0x1; + dscl_prog_data->upsp_h_init_frac = 0x1; + dscl_prog_data->upsp_h_coef_tap0_p0 = 0x28; + dscl_prog_data->upsp_h_coef_tap1_p0 = 0x18; + dscl_prog_data->upsp_h_coef_tap2_p0 = 0x00; + dscl_prog_data->upsp_h_coef_tap3_p0 = 0x00; + dscl_prog_data->upsp_h_coef_tap0_p1 = 0x18; + dscl_prog_data->upsp_h_coef_tap1_p1 = 0x28; + dscl_prog_data->upsp_h_coef_tap2_p1 = 0x00; + dscl_prog_data->upsp_h_coef_tap3_p1 = 0x00; + } + } + } +} +#endif + +/* Calculate recout, scaling ratio, and viewport, then get optimal number of taps */ +static bool spl_calculate_number_of_taps(struct spl_in *spl_in, struct spl_scratch *spl_scratch, struct spl_out *spl_out, + bool *enable_easf_v, bool *enable_easf_h, bool *enable_isharp) +{ + bool res = false; + + memset(spl_scratch, 0, sizeof(struct spl_scratch)); + spl_scratch->scl_data.h_active = spl_in->h_active; + spl_scratch->scl_data.v_active = spl_in->v_active; + + // All SPL calls + /* recout calculation */ + /* depends on h_active */ + spl_calculate_recout(spl_in, spl_scratch, spl_out); + /* depends on pixel format */ + spl_calculate_scaling_ratios(spl_in, spl_scratch, spl_out); + /* Adjust recout for opp if needed */ + spl_opp_adjust_rect(&spl_scratch->scl_data.recout, &spl_in->basic_in.opp_recout_adjust); + /* depends on scaling ratios and recout, does not calculate offset yet */ + spl_calculate_viewport_size(spl_in, spl_scratch); + + res = spl_get_optimal_number_of_taps( + spl_in->basic_out.max_downscale_src_width, spl_in, + spl_scratch, &spl_in->scaling_quality, enable_easf_v, + enable_easf_h, enable_isharp); + return res; +} + +/* Calculate scaler parameters */ +bool SPL_NAMESPACE(spl_calculate_scaler_params(struct spl_in *spl_in, struct spl_out *spl_out)) +{ + bool res = false; + bool enable_easf_v = false; + bool enable_easf_h = false; + int vratio = 0; + int hratio = 0; + struct spl_scratch spl_scratch; + struct spl_fixed31_32 isharp_scale_ratio; + enum system_setup setup; + bool enable_isharp = false; + const struct spl_scaler_data *data = &spl_scratch.scl_data; +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) + + determine_upsp_values(spl_in, spl_out->dscl_prog_data); +#endif + + res = spl_calculate_number_of_taps(spl_in, &spl_scratch, spl_out, + &enable_easf_v, &enable_easf_h, &enable_isharp); + + /* + * Depends on recout, scaling ratios, h_active and taps + * May need to re-check lb size after this in some obscure scenario + */ + if (res) + spl_calculate_inits_and_viewports(spl_in, &spl_scratch); + // Handle 3d recout + spl_handle_3d_recout(spl_in, &spl_scratch.scl_data.recout); + // Clamp + spl_clamp_viewport(&spl_scratch.scl_data.viewport, spl_in->min_viewport_size); + + // Save all calculated parameters in dscl_prog_data structure to program hw registers + spl_set_dscl_prog_data(spl_in, &spl_scratch, spl_out, enable_easf_v, enable_easf_h, enable_isharp); + + if (!res) + return res; + + if (spl_in->lls_pref == LLS_PREF_YES) { + if (spl_in->is_hdr_on) + setup = HDR_L; + else + setup = SDR_L; + } else { + if (spl_in->is_hdr_on) + setup = HDR_NL; + else + setup = SDR_NL; + } + + // Set EASF + spl_set_easf_data(&spl_scratch, spl_out, enable_easf_v, enable_easf_h, spl_in->lls_pref, + spl_in->basic_in.format, setup, spl_in->sdr_white_level_nits); + + // Set iSHARP + vratio = spl_fixpt_ceil(spl_scratch.scl_data.ratios.vert); + hratio = spl_fixpt_ceil(spl_scratch.scl_data.ratios.horz); + if (vratio <= hratio) + isharp_scale_ratio = spl_scratch.scl_data.recip_ratios.vert; + else + isharp_scale_ratio = spl_scratch.scl_data.recip_ratios.horz; + + spl_set_isharp_data(spl_out->dscl_prog_data, spl_in->adaptive_sharpness, enable_isharp, + spl_in->lls_pref, spl_in->basic_in.format, data, isharp_scale_ratio, setup, + spl_in->debug.scale_to_sharpness_policy); + + return res; +} + +/* External interface to get number of taps only */ +bool SPL_NAMESPACE(spl_get_number_of_taps(struct spl_in *spl_in, struct spl_out *spl_out)) +{ + bool res = false; + bool enable_easf_v = false; + bool enable_easf_h = false; + bool enable_isharp = false; + struct spl_scratch spl_scratch; + struct dscl_prog_data *dscl_prog_data = spl_out->dscl_prog_data; + const struct spl_scaler_data *data = &spl_scratch.scl_data; + + res = spl_calculate_number_of_taps(spl_in, &spl_scratch, spl_out, + &enable_easf_v, &enable_easf_h, &enable_isharp); + spl_set_taps_data(dscl_prog_data, data); + return res; +} diff --git a/src/amd/vpelib/src/imported/SPL/dc_spl.h b/src/amd/vpelib/src/imported/SPL/dc_spl.h new file mode 100644 index 00000000000..db813260dfc --- /dev/null +++ b/src/amd/vpelib/src/imported/SPL/dc_spl.h @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2024 Advanced Micro Devices, Inc. + +#ifndef __DC_SPL_H__ +#define __DC_SPL_H__ + +#include "dc_spl_types.h" +#define BLACK_OFFSET_RGB_Y 0x0 +#define BLACK_OFFSET_CBCR 0x8000 + +#ifdef __cplusplus +extern "C" { +#endif + +/* SPL interfaces */ + +bool SPL_NAMESPACE(spl_calculate_scaler_params(struct spl_in *spl_in, struct spl_out *spl_out)); + +bool SPL_NAMESPACE(spl_get_number_of_taps(struct spl_in *spl_in, struct spl_out *spl_out)); + +#ifdef __cplusplus +} +#endif + +#endif /* __DC_SPL_H__ */ diff --git a/src/amd/vpelib/src/imported/SPL/dc_spl_filters.c b/src/amd/vpelib/src/imported/SPL/dc_spl_filters.c new file mode 100644 index 00000000000..088aba3c00a --- /dev/null +++ b/src/amd/vpelib/src/imported/SPL/dc_spl_filters.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2024 Advanced Micro Devices, Inc. + +#include "dc_spl_filters.h" + +void SPL_NAMESPACE(convert_filter_s1_10_to_s1_12(const uint16_t *s1_10_filter, + uint16_t *s1_12_filter, int num_taps)) +{ + int num_entries = NUM_PHASES_COEFF * num_taps; + int i; + + for (i = 0; i < num_entries; i++) + *(s1_12_filter + i) = *(s1_10_filter + i) * 4; +} diff --git a/src/amd/vpelib/src/imported/SPL/dc_spl_filters.h b/src/amd/vpelib/src/imported/SPL/dc_spl_filters.h new file mode 100644 index 00000000000..f3ee51c42bf --- /dev/null +++ b/src/amd/vpelib/src/imported/SPL/dc_spl_filters.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ + +/* Copyright 2024 Advanced Micro Devices, Inc. */ + +#ifndef __DC_SPL_FILTERS_H__ +#define __DC_SPL_FILTERS_H__ + +#include "dc_spl_types.h" + +#define NUM_PHASES_COEFF 33 + +void SPL_NAMESPACE(convert_filter_s1_10_to_s1_12(const uint16_t *s1_10_filter, + uint16_t *s1_12_filter, int num_taps)); + +#endif /* __DC_SPL_FILTERS_H__ */ diff --git a/src/amd/vpelib/src/imported/SPL/dc_spl_isharp_filters.c b/src/amd/vpelib/src/imported/SPL/dc_spl_isharp_filters.c new file mode 100644 index 00000000000..a75ab23b072 --- /dev/null +++ b/src/amd/vpelib/src/imported/SPL/dc_spl_isharp_filters.c @@ -0,0 +1,554 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2024 Advanced Micro Devices, Inc. + +#include "spl_debug.h" +#include "dc_spl_filters.h" +#include "dc_spl_isharp_filters.h" + +//======================================== +// Delta Gain 1DLUT +// LUT content is packed as 4-bytes into one DWORD/entry +// A_start = 0.000000 +// A_end = 10.000000 +// A_gain = 3.000000 +// B_start = 11.000000 +// B_end = 127.000000 +// C_start = 40.000000 +// C_end = 127.000000 +//======================================== +static const uint32_t filter_isharp_1D_lut_3p0x[ISHARP_LUT_TABLE_SIZE] = { +0x03010000, +0x0F0B0805, +0x211E1813, +0x2B292624, +0x3533302E, +0x3E3C3A37, +0x46444240, +0x4D4B4A48, +0x5352504F, +0x59575655, +0x5D5C5B5A, +0x61605F5E, +0x64646362, +0x66666565, +0x68686767, +0x68686868, +0x68686868, +0x67676868, +0x65656666, +0x62636464, +0x5E5F6061, +0x5A5B5C5D, +0x55565759, +0x4F505253, +0x484A4B4D, +0x40424446, +0x373A3C3E, +0x2E303335, +0x2426292B, +0x191B1E21, +0x0D101316, +0x0003060A, +}; + +// Blur and scale coefficients +//======================================================== +// gen_BlurScale_coeffs.m +// 25-Apr-2022 +// 4 +// 64 +// Blur & Scale LPF +// S1.10 +//======================================================== +static const uint16_t filter_isharp_bs_4tap_in_6_64p[198] = { +0x0000, 0x00E5, 0x0237, 0x00E4, 0x0000, 0x0000, +0x0000, 0x00DE, 0x0237, 0x00EB, 0x0000, 0x0000, +0x0000, 0x00D7, 0x0236, 0x00F2, 0x0001, 0x0000, +0x0000, 0x00D0, 0x0235, 0x00FA, 0x0001, 0x0000, +0x0000, 0x00C9, 0x0234, 0x0101, 0x0002, 0x0000, +0x0000, 0x00C2, 0x0233, 0x0108, 0x0003, 0x0000, +0x0000, 0x00BB, 0x0232, 0x0110, 0x0003, 0x0000, +0x0000, 0x00B5, 0x0230, 0x0117, 0x0004, 0x0000, +0x0000, 0x00AE, 0x022E, 0x011F, 0x0005, 0x0000, +0x0000, 0x00A8, 0x022C, 0x0126, 0x0006, 0x0000, +0x0000, 0x00A2, 0x022A, 0x012D, 0x0007, 0x0000, +0x0000, 0x009C, 0x0228, 0x0134, 0x0008, 0x0000, +0x0000, 0x0096, 0x0225, 0x013C, 0x0009, 0x0000, +0x0000, 0x0090, 0x0222, 0x0143, 0x000B, 0x0000, +0x0000, 0x008A, 0x021F, 0x014B, 0x000C, 0x0000, +0x0000, 0x0085, 0x021C, 0x0151, 0x000E, 0x0000, +0x0000, 0x007F, 0x0218, 0x015A, 0x000F, 0x0000, +0x0000, 0x007A, 0x0215, 0x0160, 0x0011, 0x0000, +0x0000, 0x0074, 0x0211, 0x0168, 0x0013, 0x0000, +0x0000, 0x006F, 0x020D, 0x016F, 0x0015, 0x0000, +0x0000, 0x006A, 0x0209, 0x0176, 0x0017, 0x0000, +0x0000, 0x0065, 0x0204, 0x017E, 0x0019, 0x0000, +0x0000, 0x0060, 0x0200, 0x0185, 0x001B, 0x0000, +0x0000, 0x005C, 0x01FB, 0x018C, 0x001D, 0x0000, +0x0000, 0x0057, 0x01F6, 0x0193, 0x0020, 0x0000, +0x0000, 0x0053, 0x01F1, 0x019A, 0x0022, 0x0000, +0x0000, 0x004E, 0x01EC, 0x01A1, 0x0025, 0x0000, +0x0000, 0x004A, 0x01E6, 0x01A8, 0x0028, 0x0000, +0x0000, 0x0046, 0x01E1, 0x01AF, 0x002A, 0x0000, +0x0000, 0x0042, 0x01DB, 0x01B6, 0x002D, 0x0000, +0x0000, 0x003F, 0x01D5, 0x01BB, 0x0031, 0x0000, +0x0000, 0x003B, 0x01CF, 0x01C2, 0x0034, 0x0000, +0x0000, 0x0037, 0x01C9, 0x01C9, 0x0037, 0x0000 +}; +//======================================================== +// gen_BlurScale_coeffs.m +// 25-Apr-2022 +// 4 +// 64 +// Blur & Scale LPF +// S1.10 +//======================================================== +static const uint16_t filter_isharp_bs_4tap_64p[132] = { +0x00E5, 0x0237, 0x00E4, 0x0000, +0x00DE, 0x0237, 0x00EB, 0x0000, +0x00D7, 0x0236, 0x00F2, 0x0001, +0x00D0, 0x0235, 0x00FA, 0x0001, +0x00C9, 0x0234, 0x0101, 0x0002, +0x00C2, 0x0233, 0x0108, 0x0003, +0x00BB, 0x0232, 0x0110, 0x0003, +0x00B5, 0x0230, 0x0117, 0x0004, +0x00AE, 0x022E, 0x011F, 0x0005, +0x00A8, 0x022C, 0x0126, 0x0006, +0x00A2, 0x022A, 0x012D, 0x0007, +0x009C, 0x0228, 0x0134, 0x0008, +0x0096, 0x0225, 0x013C, 0x0009, +0x0090, 0x0222, 0x0143, 0x000B, +0x008A, 0x021F, 0x014B, 0x000C, +0x0085, 0x021C, 0x0151, 0x000E, +0x007F, 0x0218, 0x015A, 0x000F, +0x007A, 0x0215, 0x0160, 0x0011, +0x0074, 0x0211, 0x0168, 0x0013, +0x006F, 0x020D, 0x016F, 0x0015, +0x006A, 0x0209, 0x0176, 0x0017, +0x0065, 0x0204, 0x017E, 0x0019, +0x0060, 0x0200, 0x0185, 0x001B, +0x005C, 0x01FB, 0x018C, 0x001D, +0x0057, 0x01F6, 0x0193, 0x0020, +0x0053, 0x01F1, 0x019A, 0x0022, +0x004E, 0x01EC, 0x01A1, 0x0025, +0x004A, 0x01E6, 0x01A8, 0x0028, +0x0046, 0x01E1, 0x01AF, 0x002A, +0x0042, 0x01DB, 0x01B6, 0x002D, +0x003F, 0x01D5, 0x01BB, 0x0031, +0x003B, 0x01CF, 0x01C2, 0x0034, +0x0037, 0x01C9, 0x01C9, 0x0037, +}; +//======================================================== +// gen_BlurScale_coeffs.m +// 09-Jun-2022 +// 3 +// 64 +// Blur & Scale LPF +// S1.10 +//======================================================== +static const uint16_t filter_isharp_bs_3tap_64p[99] = { +0x0200, 0x0200, 0x0000, +0x01F6, 0x0206, 0x0004, +0x01EC, 0x020B, 0x0009, +0x01E2, 0x0211, 0x000D, +0x01D8, 0x0216, 0x0012, +0x01CE, 0x021C, 0x0016, +0x01C4, 0x0221, 0x001B, +0x01BA, 0x0226, 0x0020, +0x01B0, 0x022A, 0x0026, +0x01A6, 0x022F, 0x002B, +0x019C, 0x0233, 0x0031, +0x0192, 0x0238, 0x0036, +0x0188, 0x023C, 0x003C, +0x017E, 0x0240, 0x0042, +0x0174, 0x0244, 0x0048, +0x016A, 0x0248, 0x004E, +0x0161, 0x024A, 0x0055, +0x0157, 0x024E, 0x005B, +0x014D, 0x0251, 0x0062, +0x0144, 0x0253, 0x0069, +0x013A, 0x0256, 0x0070, +0x0131, 0x0258, 0x0077, +0x0127, 0x025B, 0x007E, +0x011E, 0x025C, 0x0086, +0x0115, 0x025E, 0x008D, +0x010B, 0x0260, 0x0095, +0x0102, 0x0262, 0x009C, +0x00F9, 0x0263, 0x00A4, +0x00F0, 0x0264, 0x00AC, +0x00E7, 0x0265, 0x00B4, +0x00DF, 0x0264, 0x00BD, +0x00D6, 0x0265, 0x00C5, +0x00CD, 0x0266, 0x00CD, +}; + +/* Converted Blur & Scale coeff tables from S1.10 to S1.12 */ +static const uint16_t filter_isharp_bs_4tap_in_6_64p_s1_12[198] = { +0x0000, 0x0394, 0x08dc, 0x0390, 0x0000, 0x0000, +0x0000, 0x0378, 0x08dc, 0x03ac, 0x0000, 0x0000, +0x0000, 0x035c, 0x08d8, 0x03c8, 0x0004, 0x0000, +0x0000, 0x0340, 0x08d4, 0x03e8, 0x0004, 0x0000, +0x0000, 0x0324, 0x08d0, 0x0404, 0x0008, 0x0000, +0x0000, 0x0308, 0x08cc, 0x0420, 0x000c, 0x0000, +0x0000, 0x02ec, 0x08c8, 0x0440, 0x000c, 0x0000, +0x0000, 0x02d4, 0x08c0, 0x045c, 0x0010, 0x0000, +0x0000, 0x02b8, 0x08b8, 0x047c, 0x0014, 0x0000, +0x0000, 0x02a0, 0x08b0, 0x0498, 0x0018, 0x0000, +0x0000, 0x0288, 0x08a8, 0x04b4, 0x001c, 0x0000, +0x0000, 0x0270, 0x08a0, 0x04d0, 0x0020, 0x0000, +0x0000, 0x0258, 0x0894, 0x04f0, 0x0024, 0x0000, +0x0000, 0x0240, 0x0888, 0x050c, 0x002c, 0x0000, +0x0000, 0x0228, 0x087c, 0x052c, 0x0030, 0x0000, +0x0000, 0x0214, 0x0870, 0x0544, 0x0038, 0x0000, +0x0000, 0x01fc, 0x0860, 0x0568, 0x003c, 0x0000, +0x0000, 0x01e8, 0x0854, 0x0580, 0x0044, 0x0000, +0x0000, 0x01d0, 0x0844, 0x05a0, 0x004c, 0x0000, +0x0000, 0x01bc, 0x0834, 0x05bc, 0x0054, 0x0000, +0x0000, 0x01a8, 0x0824, 0x05d8, 0x005c, 0x0000, +0x0000, 0x0194, 0x0810, 0x05f8, 0x0064, 0x0000, +0x0000, 0x0180, 0x0800, 0x0614, 0x006c, 0x0000, +0x0000, 0x0170, 0x07ec, 0x0630, 0x0074, 0x0000, +0x0000, 0x015c, 0x07d8, 0x064c, 0x0080, 0x0000, +0x0000, 0x014c, 0x07c4, 0x0668, 0x0088, 0x0000, +0x0000, 0x0138, 0x07b0, 0x0684, 0x0094, 0x0000, +0x0000, 0x0128, 0x0798, 0x06a0, 0x00a0, 0x0000, +0x0000, 0x0118, 0x0784, 0x06bc, 0x00a8, 0x0000, +0x0000, 0x0108, 0x076c, 0x06d8, 0x00b4, 0x0000, +0x0000, 0x00fc, 0x0754, 0x06ec, 0x00c4, 0x0000, +0x0000, 0x00ec, 0x073c, 0x0708, 0x00d0, 0x0000, +0x0000, 0x00dc, 0x0724, 0x0724, 0x00dc, 0x0000, +}; + +static const uint16_t filter_isharp_bs_4tap_64p_s1_12[132] = { +0x0394, 0x08dc, 0x0390, 0x0000, +0x0378, 0x08dc, 0x03ac, 0x0000, +0x035c, 0x08d8, 0x03c8, 0x0004, +0x0340, 0x08d4, 0x03e8, 0x0004, +0x0324, 0x08d0, 0x0404, 0x0008, +0x0308, 0x08cc, 0x0420, 0x000c, +0x02ec, 0x08c8, 0x0440, 0x000c, +0x02d4, 0x08c0, 0x045c, 0x0010, +0x02b8, 0x08b8, 0x047c, 0x0014, +0x02a0, 0x08b0, 0x0498, 0x0018, +0x0288, 0x08a8, 0x04b4, 0x001c, +0x0270, 0x08a0, 0x04d0, 0x0020, +0x0258, 0x0894, 0x04f0, 0x0024, +0x0240, 0x0888, 0x050c, 0x002c, +0x0228, 0x087c, 0x052c, 0x0030, +0x0214, 0x0870, 0x0544, 0x0038, +0x01fc, 0x0860, 0x0568, 0x003c, +0x01e8, 0x0854, 0x0580, 0x0044, +0x01d0, 0x0844, 0x05a0, 0x004c, +0x01bc, 0x0834, 0x05bc, 0x0054, +0x01a8, 0x0824, 0x05d8, 0x005c, +0x0194, 0x0810, 0x05f8, 0x0064, +0x0180, 0x0800, 0x0614, 0x006c, +0x0170, 0x07ec, 0x0630, 0x0074, +0x015c, 0x07d8, 0x064c, 0x0080, +0x014c, 0x07c4, 0x0668, 0x0088, +0x0138, 0x07b0, 0x0684, 0x0094, +0x0128, 0x0798, 0x06a0, 0x00a0, +0x0118, 0x0784, 0x06bc, 0x00a8, +0x0108, 0x076c, 0x06d8, 0x00b4, +0x00fc, 0x0754, 0x06ec, 0x00c4, +0x00ec, 0x073c, 0x0708, 0x00d0, +0x00dc, 0x0724, 0x0724, 0x00dc, +}; + +static const uint16_t filter_isharp_bs_3tap_64p_s1_12[99] = { +0x0800, 0x0800, 0x0000, +0x07d8, 0x0818, 0x0010, +0x07b0, 0x082c, 0x0024, +0x0788, 0x0844, 0x0034, +0x0760, 0x0858, 0x0048, +0x0738, 0x0870, 0x0058, +0x0710, 0x0884, 0x006c, +0x06e8, 0x0898, 0x0080, +0x06c0, 0x08a8, 0x0098, +0x0698, 0x08bc, 0x00ac, +0x0670, 0x08cc, 0x00c4, +0x0648, 0x08e0, 0x00d8, +0x0620, 0x08f0, 0x00f0, +0x05f8, 0x0900, 0x0108, +0x05d0, 0x0910, 0x0120, +0x05a8, 0x0920, 0x0138, +0x0584, 0x0928, 0x0154, +0x055c, 0x0938, 0x016c, +0x0534, 0x0944, 0x0188, +0x0510, 0x094c, 0x01a4, +0x04e8, 0x0958, 0x01c0, +0x04c4, 0x0960, 0x01dc, +0x049c, 0x096c, 0x01f8, +0x0478, 0x0970, 0x0218, +0x0454, 0x0978, 0x0234, +0x042c, 0x0980, 0x0254, +0x0408, 0x0988, 0x0270, +0x03e4, 0x098c, 0x0290, +0x03c0, 0x0990, 0x02b0, +0x039c, 0x0994, 0x02d0, +0x037c, 0x0990, 0x02f4, +0x0358, 0x0994, 0x0314, +0x0334, 0x0998, 0x0334, +}; + +/* Pre-generated 1DLUT for given setup and sharpness level */ +static struct isharp_1D_lut_pregen filter_isharp_1D_lut_pregen[NUM_SHARPNESS_SETUPS] = { + { + 0, 0, + { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + } + }, + { + 0, 0, + { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + } + }, + { + 0, 0, + { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + } + }, + { + 0, 0, + { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + } + }, +}; + +static struct scale_ratio_to_sharpness_level_adj sharpness_level_adj[NUM_SHARPNESS_ADJ_LEVELS] = { + {1125, 1000, 0}, + {11, 10, 1}, + {1075, 1000, 2}, + {105, 100, 3}, + {1025, 1000, 4}, + {1, 1, 5}, +}; + +static unsigned int spl_calculate_sharpness_level_adj(struct spl_fixed31_32 ratio) +{ + int j; + struct spl_fixed31_32 ratio_level; + struct scale_ratio_to_sharpness_level_adj *lookup_ptr; + unsigned int sharpness_level_down_adj; + + /* + * Adjust sharpness level based on current scaling ratio + * + * We have 5 discrete scaling ratios which we will use to adjust the + * sharpness level down by 1 as we pass each ratio. The ratios + * are + * + * 1.125 upscale and higher - no adj + * 1.100 - under 1.125 - adj level down 1 + * 1.075 - under 1.100 - adj level down 2 + * 1.050 - under 1.075 - adj level down 3 + * 1.025 - under 1.050 - adj level down 4 + * 1.000 - under 1.025 - adj level down 5 + * + */ + j = 0; + sharpness_level_down_adj = 0; + lookup_ptr = sharpness_level_adj; + while (j < NUM_SHARPNESS_ADJ_LEVELS) { + ratio_level = SPL_NAMESPACE(spl_fixpt_from_fraction(lookup_ptr->ratio_numer, + lookup_ptr->ratio_denom)); + if (ratio.value >= ratio_level.value) { + sharpness_level_down_adj = lookup_ptr->level_down_adj; + break; + } + lookup_ptr++; + j++; + } + return sharpness_level_down_adj; +} + +static unsigned int spl_calculate_sharpness_level(struct spl_fixed31_32 ratio, + unsigned int discrete_sharpness_level, enum system_setup setup, + struct spl_sharpness_range sharpness_range, + enum scale_to_sharpness_policy scale_to_sharpness_policy) +{ + unsigned int sharpness_level = 0; + unsigned int sharpness_level_down_adj = 0; + + int min_sharpness, max_sharpness, mid_sharpness; + + /* + * Adjust sharpness level if policy requires we adjust it based on + * scale ratio. Based on scale ratio, we may adjust the sharpness + * level down by a certain number of steps. We will not select + * a sharpness value of 0 so the lowest sharpness level will be + * 0 or 1 depending on what the min_sharpness is + * + * If the policy is no required, this code maybe removed at a later + * date + */ + switch (setup) { + + case HDR_L: + min_sharpness = sharpness_range.hdr_rgb_min; + max_sharpness = sharpness_range.hdr_rgb_max; + mid_sharpness = sharpness_range.hdr_rgb_mid; + if (scale_to_sharpness_policy == SCALE_TO_SHARPNESS_ADJ_ALL) + sharpness_level_down_adj = spl_calculate_sharpness_level_adj(ratio); + break; + case HDR_NL: + /* currently no use case, use Non-linear SDR values for now */ + case SDR_NL: + min_sharpness = sharpness_range.sdr_yuv_min; + max_sharpness = sharpness_range.sdr_yuv_max; + mid_sharpness = sharpness_range.sdr_yuv_mid; + if (scale_to_sharpness_policy >= SCALE_TO_SHARPNESS_ADJ_YUV) + sharpness_level_down_adj = spl_calculate_sharpness_level_adj(ratio); + break; + case SDR_L: + default: + min_sharpness = sharpness_range.sdr_rgb_min; + max_sharpness = sharpness_range.sdr_rgb_max; + mid_sharpness = sharpness_range.sdr_rgb_mid; + if (scale_to_sharpness_policy == SCALE_TO_SHARPNESS_ADJ_ALL) + sharpness_level_down_adj = spl_calculate_sharpness_level_adj(ratio); + break; + } + + if ((min_sharpness == 0) && (sharpness_level_down_adj >= discrete_sharpness_level)) + discrete_sharpness_level = 1; + else if (sharpness_level_down_adj >= discrete_sharpness_level) + discrete_sharpness_level = 0; + else + discrete_sharpness_level -= sharpness_level_down_adj; + + int lower_half_step_size = (mid_sharpness - min_sharpness) / 5; + int upper_half_step_size = (max_sharpness - mid_sharpness) / 5; + + // lower half linear approximation + if (discrete_sharpness_level < 5) + sharpness_level = min_sharpness + (lower_half_step_size * discrete_sharpness_level); + // upper half linear approximation + else + sharpness_level = mid_sharpness + (upper_half_step_size * (discrete_sharpness_level - 5)); + + return sharpness_level; +} + +void SPL_NAMESPACE(spl_build_isharp_1dlut_from_reference_curve( + struct spl_fixed31_32 ratio, enum system_setup setup, + struct adaptive_sharpness sharpness, enum scale_to_sharpness_policy scale_to_sharpness_policy)) +{ + uint8_t *byte_ptr_1dlut_src, *byte_ptr_1dlut_dst; + struct spl_fixed31_32 sharp_base, sharp_calc, sharp_level; + int j; + int size_1dlut; + int sharp_calc_int; + uint32_t filter_pregen_store[ISHARP_LUT_TABLE_SIZE]; + + /* Custom sharpnessX1000 value */ + unsigned int sharpnessX1000 = spl_calculate_sharpness_level(ratio, + sharpness.sharpness_level, setup, + sharpness.sharpness_range, scale_to_sharpness_policy); + sharp_level = SPL_NAMESPACE(spl_fixpt_from_fraction(sharpnessX1000, 1000)); + + /* + * Check if pregen 1dlut table is already precalculated + * If numer/denom is different, then recalculate + */ + if ((filter_isharp_1D_lut_pregen[setup].sharpness_numer == sharpnessX1000) && + (filter_isharp_1D_lut_pregen[setup].sharpness_denom == 1000)) + return; + + /* + * Calculate LUT_128_gained with this equation: + * + * LUT_128_gained[i] = (uint8)(0.5 + min(255,(double)(LUT_128[i])*sharpLevel/iGain)) + * where LUT_128[i] is contents of 3p0x isharp 1dlut + * where sharpLevel is desired sharpness level + * where iGain is base sharpness level 3.0 + * where LUT_128_gained[i] is adjusted 1dlut value based on desired sharpness level + */ + byte_ptr_1dlut_src = (uint8_t *)filter_isharp_1D_lut_3p0x; + byte_ptr_1dlut_dst = (uint8_t *)filter_pregen_store; + size_1dlut = sizeof(filter_isharp_1D_lut_3p0x); + memset(byte_ptr_1dlut_dst, 0, size_1dlut); + for (j = 0; j < size_1dlut; j++) { + sharp_base = spl_fixpt_from_int((int)*byte_ptr_1dlut_src); + sharp_calc = SPL_NAMESPACE(spl_fixpt_mul(sharp_base, sharp_level)); + sharp_calc = spl_fixpt_div(sharp_calc, spl_fixpt_from_int(3)); + sharp_calc = spl_fixpt_min(spl_fixpt_from_int(255), sharp_calc); + sharp_calc = spl_fixpt_add(sharp_calc, + SPL_NAMESPACE(spl_fixpt_from_fraction(1, 2))); + sharp_calc_int = spl_fixpt_floor(sharp_calc); + /* Clamp it at 0x7F so it doesn't wrap */ + if (sharp_calc_int > 127) + sharp_calc_int = 127; + *byte_ptr_1dlut_dst = (uint8_t)sharp_calc_int; + + byte_ptr_1dlut_src++; + byte_ptr_1dlut_dst++; + } + + /* Update 1dlut table and sharpness level */ + memcpy((void *)filter_isharp_1D_lut_pregen[setup].value, (void *)filter_pregen_store, size_1dlut); + filter_isharp_1D_lut_pregen[setup].sharpness_numer = sharpnessX1000; + filter_isharp_1D_lut_pregen[setup].sharpness_denom = 1000; +} + +uint32_t *SPL_NAMESPACE(spl_get_pregen_filter_isharp_1D_lut(enum system_setup setup)) +{ + return filter_isharp_1D_lut_pregen[setup].value; +} + +const uint16_t *SPL_NAMESPACE(spl_dscl_get_blur_scale_coeffs_64p(int taps)) +{ + if (taps == 3) + return filter_isharp_bs_3tap_64p_s1_12; + else if (taps == 4) + return filter_isharp_bs_4tap_64p_s1_12; + else if (taps == 6) + return filter_isharp_bs_4tap_in_6_64p_s1_12; + else { + /* should never happen, bug */ + SPL_BREAK_TO_DEBUGGER(); + return NULL; + } +} + +const uint16_t *SPL_NAMESPACE(spl_dscl_get_blur_scale_coeffs_64p_s1_10(int taps)) +{ + if (taps == 3) + return filter_isharp_bs_3tap_64p; + else if (taps == 4) + return filter_isharp_bs_4tap_64p; + else if (taps == 6) + return filter_isharp_bs_4tap_in_6_64p; + else { + /* should never happen, bug */ + SPL_BREAK_TO_DEBUGGER(); + return NULL; + } +} + +void SPL_NAMESPACE(spl_set_blur_scale_data(struct dscl_prog_data *dscl_prog_data, + const struct spl_scaler_data *data)) +{ + dscl_prog_data->filter_blur_scale_h = + SPL_NAMESPACE(spl_dscl_get_blur_scale_coeffs_64p(data->taps.h_taps)); + + dscl_prog_data->filter_blur_scale_v = + SPL_NAMESPACE(spl_dscl_get_blur_scale_coeffs_64p(data->taps.v_taps)); +} diff --git a/src/amd/vpelib/src/imported/SPL/dc_spl_isharp_filters.h b/src/amd/vpelib/src/imported/SPL/dc_spl_isharp_filters.h new file mode 100644 index 00000000000..d4082d4969e --- /dev/null +++ b/src/amd/vpelib/src/imported/SPL/dc_spl_isharp_filters.h @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2024 Advanced Micro Devices, Inc. + +#ifndef __DC_SPL_ISHARP_FILTERS_H__ +#define __DC_SPL_ISHARP_FILTERS_H__ + +#include "dc_spl_types.h" + +#define NUM_SHARPNESS_ADJ_LEVELS 6 +struct scale_ratio_to_sharpness_level_adj { + unsigned int ratio_numer; + unsigned int ratio_denom; + unsigned int level_down_adj; /* adjust sharpness level down */ +}; + +struct isharp_1D_lut_pregen { + unsigned int sharpness_numer; + unsigned int sharpness_denom; + uint32_t value[ISHARP_LUT_TABLE_SIZE]; +}; + +enum system_setup { + SDR_NL = 0, + SDR_L, + HDR_NL, + HDR_L, + NUM_SHARPNESS_SETUPS +}; + +void SPL_NAMESPACE(spl_set_blur_scale_data(struct dscl_prog_data *dscl_prog_data, + const struct spl_scaler_data *data)); + +void SPL_NAMESPACE(spl_build_isharp_1dlut_from_reference_curve( + struct spl_fixed31_32 ratio, enum system_setup setup, + struct adaptive_sharpness sharpness, + enum scale_to_sharpness_policy scale_to_sharpness_policy)); +uint32_t *SPL_NAMESPACE(spl_get_pregen_filter_isharp_1D_lut(enum system_setup setup)); + +// public API +const uint16_t *SPL_NAMESPACE(spl_dscl_get_blur_scale_coeffs_64p(int taps)); +const uint16_t *SPL_NAMESPACE(spl_dscl_get_blur_scale_coeffs_64p_s1_10(int taps)); + +#endif /* __DC_SPL_ISHARP_FILTERS_H__ */ diff --git a/src/amd/vpelib/src/imported/SPL/dc_spl_scl_easf_filters.c b/src/amd/vpelib/src/imported/SPL/dc_spl_scl_easf_filters.c new file mode 100644 index 00000000000..de16ee58607 --- /dev/null +++ b/src/amd/vpelib/src/imported/SPL/dc_spl_scl_easf_filters.c @@ -0,0 +1,2589 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2024 Advanced Micro Devices, Inc. + +#include "spl_debug.h" +#include "dc_spl_filters.h" +#include "dc_spl_scl_filters.h" +#include "dc_spl_scl_easf_filters.h" + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 3t_64p_LanczosEd_p_0.3_p_10qb_ +// 3 +// 64 +// input/output = 0.300000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_3tap_64p_ratio_0_30[99] = { + 0x0200, 0x0200, 0x0000, + 0x01F6, 0x0206, 0x0004, + 0x01EC, 0x020B, 0x0009, + 0x01E2, 0x0211, 0x000D, + 0x01D8, 0x0216, 0x0012, + 0x01CE, 0x021C, 0x0016, + 0x01C4, 0x0221, 0x001B, + 0x01BA, 0x0226, 0x0020, + 0x01B0, 0x022A, 0x0026, + 0x01A6, 0x022F, 0x002B, + 0x019C, 0x0233, 0x0031, + 0x0192, 0x0238, 0x0036, + 0x0188, 0x023C, 0x003C, + 0x017E, 0x0240, 0x0042, + 0x0174, 0x0244, 0x0048, + 0x016A, 0x0248, 0x004E, + 0x0161, 0x024A, 0x0055, + 0x0157, 0x024E, 0x005B, + 0x014D, 0x0251, 0x0062, + 0x0144, 0x0253, 0x0069, + 0x013A, 0x0256, 0x0070, + 0x0131, 0x0258, 0x0077, + 0x0127, 0x025B, 0x007E, + 0x011E, 0x025C, 0x0086, + 0x0115, 0x025E, 0x008D, + 0x010B, 0x0260, 0x0095, + 0x0102, 0x0262, 0x009C, + 0x00F9, 0x0263, 0x00A4, + 0x00F0, 0x0264, 0x00AC, + 0x00E7, 0x0265, 0x00B4, + 0x00DF, 0x0264, 0x00BD, + 0x00D6, 0x0265, 0x00C5, + 0x00CD, 0x0266, 0x00CD, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 3t_64p_LanczosEd_p_0.4_p_10qb_ +// 3 +// 64 +// input/output = 0.400000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_3tap_64p_ratio_0_40[99] = { + 0x0200, 0x0200, 0x0000, + 0x01F6, 0x0206, 0x0004, + 0x01EB, 0x020E, 0x0007, + 0x01E1, 0x0214, 0x000B, + 0x01D7, 0x021A, 0x000F, + 0x01CD, 0x0220, 0x0013, + 0x01C2, 0x0226, 0x0018, + 0x01B8, 0x022C, 0x001C, + 0x01AE, 0x0231, 0x0021, + 0x01A3, 0x0237, 0x0026, + 0x0199, 0x023C, 0x002B, + 0x018F, 0x0240, 0x0031, + 0x0185, 0x0245, 0x0036, + 0x017A, 0x024A, 0x003C, + 0x0170, 0x024F, 0x0041, + 0x0166, 0x0253, 0x0047, + 0x015C, 0x0257, 0x004D, + 0x0152, 0x025A, 0x0054, + 0x0148, 0x025E, 0x005A, + 0x013E, 0x0261, 0x0061, + 0x0134, 0x0264, 0x0068, + 0x012B, 0x0266, 0x006F, + 0x0121, 0x0269, 0x0076, + 0x0117, 0x026C, 0x007D, + 0x010E, 0x026E, 0x0084, + 0x0104, 0x0270, 0x008C, + 0x00FB, 0x0271, 0x0094, + 0x00F2, 0x0272, 0x009C, + 0x00E9, 0x0273, 0x00A4, + 0x00E0, 0x0274, 0x00AC, + 0x00D7, 0x0275, 0x00B4, + 0x00CE, 0x0275, 0x00BD, + 0x00C5, 0x0276, 0x00C5, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 3t_64p_LanczosEd_p_0.5_p_10qb_ +// 3 +// 64 +// input/output = 0.500000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_3tap_64p_ratio_0_50[99] = { + 0x0200, 0x0200, 0x0000, + 0x01F5, 0x0209, 0x0002, + 0x01EA, 0x0211, 0x0005, + 0x01DF, 0x021A, 0x0007, + 0x01D4, 0x0222, 0x000A, + 0x01C9, 0x022A, 0x000D, + 0x01BE, 0x0232, 0x0010, + 0x01B3, 0x0239, 0x0014, + 0x01A8, 0x0241, 0x0017, + 0x019D, 0x0248, 0x001B, + 0x0192, 0x024F, 0x001F, + 0x0187, 0x0255, 0x0024, + 0x017C, 0x025C, 0x0028, + 0x0171, 0x0262, 0x002D, + 0x0166, 0x0268, 0x0032, + 0x015B, 0x026E, 0x0037, + 0x0150, 0x0273, 0x003D, + 0x0146, 0x0278, 0x0042, + 0x013B, 0x027D, 0x0048, + 0x0130, 0x0282, 0x004E, + 0x0126, 0x0286, 0x0054, + 0x011B, 0x028A, 0x005B, + 0x0111, 0x028D, 0x0062, + 0x0107, 0x0290, 0x0069, + 0x00FD, 0x0293, 0x0070, + 0x00F3, 0x0296, 0x0077, + 0x00E9, 0x0298, 0x007F, + 0x00DF, 0x029A, 0x0087, + 0x00D5, 0x029C, 0x008F, + 0x00CC, 0x029D, 0x0097, + 0x00C3, 0x029E, 0x009F, + 0x00BA, 0x029E, 0x00A8, + 0x00B1, 0x029E, 0x00B1, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 3t_64p_LanczosEd_p_0.6_p_10qb_ +// 3 +// 64 +// input/output = 0.600000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_3tap_64p_ratio_0_60[99] = { + 0x0200, 0x0200, 0x0000, + 0x01F4, 0x020B, 0x0001, + 0x01E8, 0x0216, 0x0002, + 0x01DC, 0x0221, 0x0003, + 0x01D0, 0x022B, 0x0005, + 0x01C4, 0x0235, 0x0007, + 0x01B8, 0x0240, 0x0008, + 0x01AC, 0x0249, 0x000B, + 0x01A0, 0x0253, 0x000D, + 0x0194, 0x025C, 0x0010, + 0x0188, 0x0265, 0x0013, + 0x017C, 0x026E, 0x0016, + 0x0170, 0x0277, 0x0019, + 0x0164, 0x027F, 0x001D, + 0x0158, 0x0287, 0x0021, + 0x014C, 0x028F, 0x0025, + 0x0140, 0x0297, 0x0029, + 0x0135, 0x029D, 0x002E, + 0x0129, 0x02A4, 0x0033, + 0x011D, 0x02AB, 0x0038, + 0x0112, 0x02B0, 0x003E, + 0x0107, 0x02B5, 0x0044, + 0x00FC, 0x02BA, 0x004A, + 0x00F1, 0x02BF, 0x0050, + 0x00E6, 0x02C3, 0x0057, + 0x00DB, 0x02C7, 0x005E, + 0x00D1, 0x02CA, 0x0065, + 0x00C7, 0x02CC, 0x006D, + 0x00BD, 0x02CE, 0x0075, + 0x00B3, 0x02D0, 0x007D, + 0x00A9, 0x02D2, 0x0085, + 0x00A0, 0x02D2, 0x008E, + 0x0097, 0x02D2, 0x0097, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 3t_64p_LanczosEd_p_0.7_p_10qb_ +// 3 +// 64 +// input/output = 0.700000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_3tap_64p_ratio_0_70[99] = { + 0x0200, 0x0200, 0x0000, + 0x01F3, 0x020D, 0x0000, + 0x01E5, 0x021B, 0x0000, + 0x01D8, 0x0228, 0x0000, + 0x01CB, 0x0235, 0x0000, + 0x01BD, 0x0243, 0x0000, + 0x01B0, 0x024F, 0x0001, + 0x01A2, 0x025C, 0x0002, + 0x0195, 0x0268, 0x0003, + 0x0187, 0x0275, 0x0004, + 0x017A, 0x0280, 0x0006, + 0x016D, 0x028C, 0x0007, + 0x015F, 0x0298, 0x0009, + 0x0152, 0x02A2, 0x000C, + 0x0145, 0x02AD, 0x000E, + 0x0138, 0x02B7, 0x0011, + 0x012B, 0x02C0, 0x0015, + 0x011E, 0x02CA, 0x0018, + 0x0111, 0x02D3, 0x001C, + 0x0105, 0x02DB, 0x0020, + 0x00F8, 0x02E3, 0x0025, + 0x00EC, 0x02EA, 0x002A, + 0x00E0, 0x02F1, 0x002F, + 0x00D5, 0x02F6, 0x0035, + 0x00C9, 0x02FC, 0x003B, + 0x00BE, 0x0301, 0x0041, + 0x00B3, 0x0305, 0x0048, + 0x00A8, 0x0309, 0x004F, + 0x009E, 0x030C, 0x0056, + 0x0094, 0x030E, 0x005E, + 0x008A, 0x0310, 0x0066, + 0x0081, 0x0310, 0x006F, + 0x0077, 0x0312, 0x0077, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 3t_64p_LanczosEd_p_0.8_p_10qb_ +// 3 +// 64 +// input/output = 0.800000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_3tap_64p_ratio_0_80[99] = { + 0x0200, 0x0200, 0x0000, + 0x01F1, 0x0210, 0x0FFF, + 0x01E2, 0x0220, 0x0FFE, + 0x01D2, 0x0232, 0x0FFC, + 0x01C3, 0x0241, 0x0FFC, + 0x01B4, 0x0251, 0x0FFB, + 0x01A4, 0x0262, 0x0FFA, + 0x0195, 0x0271, 0x0FFA, + 0x0186, 0x0281, 0x0FF9, + 0x0176, 0x0291, 0x0FF9, + 0x0167, 0x02A0, 0x0FF9, + 0x0158, 0x02AE, 0x0FFA, + 0x0149, 0x02BD, 0x0FFA, + 0x013A, 0x02CB, 0x0FFB, + 0x012C, 0x02D7, 0x0FFD, + 0x011D, 0x02E5, 0x0FFE, + 0x010F, 0x02F1, 0x0000, + 0x0101, 0x02FD, 0x0002, + 0x00F3, 0x0308, 0x0005, + 0x00E5, 0x0313, 0x0008, + 0x00D8, 0x031D, 0x000B, + 0x00CB, 0x0326, 0x000F, + 0x00BE, 0x032F, 0x0013, + 0x00B2, 0x0337, 0x0017, + 0x00A6, 0x033E, 0x001C, + 0x009A, 0x0345, 0x0021, + 0x008F, 0x034A, 0x0027, + 0x0084, 0x034F, 0x002D, + 0x0079, 0x0353, 0x0034, + 0x006F, 0x0356, 0x003B, + 0x0065, 0x0358, 0x0043, + 0x005C, 0x0359, 0x004B, + 0x0053, 0x035A, 0x0053, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 3t_64p_LanczosEd_p_0.9_p_10qb_ +// 3 +// 64 +// input/output = 0.900000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_3tap_64p_ratio_0_90[99] = { + 0x0200, 0x0200, 0x0000, + 0x01EE, 0x0214, 0x0FFE, + 0x01DC, 0x0228, 0x0FFC, + 0x01CA, 0x023C, 0x0FFA, + 0x01B9, 0x024F, 0x0FF8, + 0x01A7, 0x0262, 0x0FF7, + 0x0195, 0x0276, 0x0FF5, + 0x0183, 0x028A, 0x0FF3, + 0x0172, 0x029C, 0x0FF2, + 0x0160, 0x02AF, 0x0FF1, + 0x014F, 0x02C2, 0x0FEF, + 0x013E, 0x02D4, 0x0FEE, + 0x012D, 0x02E5, 0x0FEE, + 0x011C, 0x02F7, 0x0FED, + 0x010C, 0x0307, 0x0FED, + 0x00FB, 0x0318, 0x0FED, + 0x00EC, 0x0327, 0x0FED, + 0x00DC, 0x0336, 0x0FEE, + 0x00CD, 0x0344, 0x0FEF, + 0x00BE, 0x0352, 0x0FF0, + 0x00B0, 0x035E, 0x0FF2, + 0x00A2, 0x036A, 0x0FF4, + 0x0095, 0x0375, 0x0FF6, + 0x0088, 0x037F, 0x0FF9, + 0x007B, 0x0388, 0x0FFD, + 0x006F, 0x0391, 0x0000, + 0x0064, 0x0397, 0x0005, + 0x0059, 0x039D, 0x000A, + 0x004E, 0x03A3, 0x000F, + 0x0045, 0x03A6, 0x0015, + 0x003B, 0x03A9, 0x001C, + 0x0033, 0x03AA, 0x0023, + 0x002A, 0x03AC, 0x002A, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 3t_64p_LanczosEd_p_1_p_10qb_ +// 3 +// 64 +// input/output = 1.000000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_3tap_64p_ratio_1_00[99] = { + 0x0200, 0x0200, 0x0000, + 0x01EB, 0x0217, 0x0FFE, + 0x01D5, 0x022F, 0x0FFC, + 0x01C0, 0x0247, 0x0FF9, + 0x01AB, 0x025E, 0x0FF7, + 0x0196, 0x0276, 0x0FF4, + 0x0181, 0x028D, 0x0FF2, + 0x016C, 0x02A5, 0x0FEF, + 0x0158, 0x02BB, 0x0FED, + 0x0144, 0x02D1, 0x0FEB, + 0x0130, 0x02E8, 0x0FE8, + 0x011C, 0x02FE, 0x0FE6, + 0x0109, 0x0313, 0x0FE4, + 0x00F6, 0x0328, 0x0FE2, + 0x00E4, 0x033C, 0x0FE0, + 0x00D2, 0x034F, 0x0FDF, + 0x00C0, 0x0363, 0x0FDD, + 0x00B0, 0x0374, 0x0FDC, + 0x009F, 0x0385, 0x0FDC, + 0x0090, 0x0395, 0x0FDB, + 0x0081, 0x03A4, 0x0FDB, + 0x0072, 0x03B3, 0x0FDB, + 0x0064, 0x03C0, 0x0FDC, + 0x0057, 0x03CC, 0x0FDD, + 0x004B, 0x03D6, 0x0FDF, + 0x003F, 0x03E0, 0x0FE1, + 0x0034, 0x03E8, 0x0FE4, + 0x002A, 0x03EF, 0x0FE7, + 0x0020, 0x03F5, 0x0FEB, + 0x0017, 0x03FA, 0x0FEF, + 0x000F, 0x03FD, 0x0FF4, + 0x0007, 0x03FF, 0x0FFA, + 0x0000, 0x0400, 0x0000, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 4t_64p_LanczosEd_p_0.3_p_10qb_ +// 4 +// 64 +// input/output = 0.300000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_4tap_64p_ratio_0_30[132] = { + 0x0104, 0x01F8, 0x0104, 0x0000, + 0x00FE, 0x01F7, 0x010A, 0x0001, + 0x00F8, 0x01F6, 0x010F, 0x0003, + 0x00F2, 0x01F5, 0x0114, 0x0005, + 0x00EB, 0x01F4, 0x011B, 0x0006, + 0x00E5, 0x01F3, 0x0120, 0x0008, + 0x00DF, 0x01F2, 0x0125, 0x000A, + 0x00DA, 0x01F0, 0x012A, 0x000C, + 0x00D4, 0x01EE, 0x0130, 0x000E, + 0x00CE, 0x01ED, 0x0135, 0x0010, + 0x00C8, 0x01EB, 0x013A, 0x0013, + 0x00C2, 0x01E9, 0x0140, 0x0015, + 0x00BD, 0x01E7, 0x0145, 0x0017, + 0x00B7, 0x01E5, 0x014A, 0x001A, + 0x00B1, 0x01E2, 0x0151, 0x001C, + 0x00AC, 0x01E0, 0x0155, 0x001F, + 0x00A7, 0x01DD, 0x015A, 0x0022, + 0x00A1, 0x01DB, 0x015F, 0x0025, + 0x009C, 0x01D8, 0x0165, 0x0027, + 0x0097, 0x01D5, 0x016A, 0x002A, + 0x0092, 0x01D2, 0x016E, 0x002E, + 0x008C, 0x01CF, 0x0174, 0x0031, + 0x0087, 0x01CC, 0x0179, 0x0034, + 0x0083, 0x01C9, 0x017D, 0x0037, + 0x007E, 0x01C5, 0x0182, 0x003B, + 0x0079, 0x01C2, 0x0187, 0x003E, + 0x0074, 0x01BE, 0x018C, 0x0042, + 0x0070, 0x01BA, 0x0190, 0x0046, + 0x006B, 0x01B7, 0x0195, 0x0049, + 0x0066, 0x01B3, 0x019A, 0x004D, + 0x0062, 0x01AF, 0x019E, 0x0051, + 0x005E, 0x01AB, 0x01A2, 0x0055, + 0x005A, 0x01A6, 0x01A6, 0x005A, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 4t_64p_LanczosEd_p_0.4_p_10qb_ +// 4 +// 64 +// input/output = 0.400000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_4tap_64p_ratio_0_40[132] = { + 0x00FB, 0x0209, 0x00FC, 0x0000, + 0x00F5, 0x0209, 0x0101, 0x0001, + 0x00EE, 0x0208, 0x0108, 0x0002, + 0x00E8, 0x0207, 0x010E, 0x0003, + 0x00E2, 0x0206, 0x0114, 0x0004, + 0x00DB, 0x0205, 0x011A, 0x0006, + 0x00D5, 0x0204, 0x0120, 0x0007, + 0x00CF, 0x0203, 0x0125, 0x0009, + 0x00C9, 0x0201, 0x012C, 0x000A, + 0x00C3, 0x01FF, 0x0132, 0x000C, + 0x00BD, 0x01FD, 0x0138, 0x000E, + 0x00B7, 0x01FB, 0x013E, 0x0010, + 0x00B1, 0x01F9, 0x0144, 0x0012, + 0x00AC, 0x01F7, 0x0149, 0x0014, + 0x00A6, 0x01F4, 0x0150, 0x0016, + 0x00A0, 0x01F2, 0x0156, 0x0018, + 0x009B, 0x01EF, 0x015C, 0x001A, + 0x0095, 0x01EC, 0x0162, 0x001D, + 0x0090, 0x01E9, 0x0168, 0x001F, + 0x008B, 0x01E6, 0x016D, 0x0022, + 0x0085, 0x01E3, 0x0173, 0x0025, + 0x0080, 0x01DF, 0x0179, 0x0028, + 0x007B, 0x01DC, 0x017E, 0x002B, + 0x0076, 0x01D8, 0x0184, 0x002E, + 0x0071, 0x01D4, 0x018A, 0x0031, + 0x006D, 0x01D1, 0x018E, 0x0034, + 0x0068, 0x01CD, 0x0193, 0x0038, + 0x0063, 0x01C8, 0x019A, 0x003B, + 0x005F, 0x01C4, 0x019E, 0x003F, + 0x005B, 0x01C0, 0x01A3, 0x0042, + 0x0056, 0x01BB, 0x01A9, 0x0046, + 0x0052, 0x01B7, 0x01AD, 0x004A, + 0x004E, 0x01B2, 0x01B2, 0x004E, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 4t_64p_LanczosEd_p_0.5_p_10qb_ +// 4 +// 64 +// input/output = 0.500000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_4tap_64p_ratio_0_50[132] = { + 0x00E5, 0x0236, 0x00E5, 0x0000, + 0x00DE, 0x0235, 0x00ED, 0x0000, + 0x00D7, 0x0235, 0x00F4, 0x0000, + 0x00D0, 0x0235, 0x00FB, 0x0000, + 0x00C9, 0x0234, 0x0102, 0x0001, + 0x00C2, 0x0233, 0x010A, 0x0001, + 0x00BC, 0x0232, 0x0111, 0x0001, + 0x00B5, 0x0230, 0x0119, 0x0002, + 0x00AE, 0x022F, 0x0121, 0x0002, + 0x00A8, 0x022D, 0x0128, 0x0003, + 0x00A2, 0x022B, 0x012F, 0x0004, + 0x009B, 0x0229, 0x0137, 0x0005, + 0x0095, 0x0226, 0x013F, 0x0006, + 0x008F, 0x0224, 0x0146, 0x0007, + 0x0089, 0x0221, 0x014E, 0x0008, + 0x0083, 0x021E, 0x0155, 0x000A, + 0x007E, 0x021B, 0x015C, 0x000B, + 0x0078, 0x0217, 0x0164, 0x000D, + 0x0072, 0x0213, 0x016D, 0x000E, + 0x006D, 0x0210, 0x0173, 0x0010, + 0x0068, 0x020C, 0x017A, 0x0012, + 0x0063, 0x0207, 0x0182, 0x0014, + 0x005E, 0x0203, 0x0189, 0x0016, + 0x0059, 0x01FE, 0x0191, 0x0018, + 0x0054, 0x01F9, 0x0198, 0x001B, + 0x0050, 0x01F4, 0x019F, 0x001D, + 0x004B, 0x01EF, 0x01A6, 0x0020, + 0x0047, 0x01EA, 0x01AC, 0x0023, + 0x0043, 0x01E4, 0x01B3, 0x0026, + 0x003F, 0x01DF, 0x01B9, 0x0029, + 0x003B, 0x01D9, 0x01C0, 0x002C, + 0x0037, 0x01D3, 0x01C6, 0x0030, + 0x0033, 0x01CD, 0x01CD, 0x0033, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 4t_64p_LanczosEd_p_0.6_p_10qb_ +// 4 +// 64 +// input/output = 0.600000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_4tap_64p_ratio_0_60[132] = { + 0x00C8, 0x026F, 0x00C9, 0x0000, + 0x00C0, 0x0270, 0x00D1, 0x0FFF, + 0x00B8, 0x0270, 0x00D9, 0x0FFF, + 0x00B1, 0x0270, 0x00E1, 0x0FFE, + 0x00A9, 0x026F, 0x00EB, 0x0FFD, + 0x00A2, 0x026E, 0x00F3, 0x0FFD, + 0x009A, 0x026D, 0x00FD, 0x0FFC, + 0x0093, 0x026C, 0x0105, 0x0FFC, + 0x008C, 0x026A, 0x010F, 0x0FFB, + 0x0085, 0x0268, 0x0118, 0x0FFB, + 0x007E, 0x0265, 0x0122, 0x0FFB, + 0x0078, 0x0263, 0x012A, 0x0FFB, + 0x0071, 0x0260, 0x0134, 0x0FFB, + 0x006B, 0x025C, 0x013E, 0x0FFB, + 0x0065, 0x0259, 0x0147, 0x0FFB, + 0x005F, 0x0255, 0x0151, 0x0FFB, + 0x0059, 0x0251, 0x015A, 0x0FFC, + 0x0054, 0x024D, 0x0163, 0x0FFC, + 0x004E, 0x0248, 0x016D, 0x0FFD, + 0x0049, 0x0243, 0x0176, 0x0FFE, + 0x0044, 0x023E, 0x017F, 0x0FFF, + 0x003F, 0x0238, 0x0189, 0x0000, + 0x003A, 0x0232, 0x0193, 0x0001, + 0x0036, 0x022C, 0x019C, 0x0002, + 0x0031, 0x0226, 0x01A5, 0x0004, + 0x002D, 0x021F, 0x01AF, 0x0005, + 0x0029, 0x0218, 0x01B8, 0x0007, + 0x0025, 0x0211, 0x01C1, 0x0009, + 0x0022, 0x020A, 0x01C9, 0x000B, + 0x001E, 0x0203, 0x01D2, 0x000D, + 0x001B, 0x01FB, 0x01DA, 0x0010, + 0x0018, 0x01F3, 0x01E3, 0x0012, + 0x0015, 0x01EB, 0x01EB, 0x0015, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 4t_64p_LanczosEd_p_0.7_p_10qb_ +// 4 +// 64 +// input/output = 0.700000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_4tap_64p_ratio_0_70[132] = { + 0x00A3, 0x02B9, 0x00A4, 0x0000, + 0x009A, 0x02BA, 0x00AD, 0x0FFF, + 0x0092, 0x02BA, 0x00B6, 0x0FFE, + 0x0089, 0x02BA, 0x00C1, 0x0FFC, + 0x0081, 0x02B9, 0x00CB, 0x0FFB, + 0x0079, 0x02B8, 0x00D5, 0x0FFA, + 0x0071, 0x02B7, 0x00DF, 0x0FF9, + 0x0069, 0x02B5, 0x00EA, 0x0FF8, + 0x0062, 0x02B3, 0x00F4, 0x0FF7, + 0x005B, 0x02B0, 0x00FF, 0x0FF6, + 0x0054, 0x02AD, 0x010B, 0x0FF4, + 0x004D, 0x02A9, 0x0117, 0x0FF3, + 0x0046, 0x02A5, 0x0123, 0x0FF2, + 0x0040, 0x02A1, 0x012D, 0x0FF2, + 0x003A, 0x029C, 0x0139, 0x0FF1, + 0x0034, 0x0297, 0x0145, 0x0FF0, + 0x002F, 0x0292, 0x0150, 0x0FEF, + 0x0029, 0x028C, 0x015C, 0x0FEF, + 0x0024, 0x0285, 0x0169, 0x0FEE, + 0x001F, 0x027F, 0x0174, 0x0FEE, + 0x001B, 0x0278, 0x017F, 0x0FEE, + 0x0016, 0x0270, 0x018D, 0x0FED, + 0x0012, 0x0268, 0x0199, 0x0FED, + 0x000E, 0x0260, 0x01A4, 0x0FEE, + 0x000B, 0x0258, 0x01AF, 0x0FEE, + 0x0007, 0x024F, 0x01BC, 0x0FEE, + 0x0004, 0x0246, 0x01C7, 0x0FEF, + 0x0001, 0x023D, 0x01D3, 0x0FEF, + 0x0FFE, 0x0233, 0x01DF, 0x0FF0, + 0x0FFC, 0x0229, 0x01EA, 0x0FF1, + 0x0FFA, 0x021F, 0x01F4, 0x0FF3, + 0x0FF8, 0x0215, 0x01FF, 0x0FF4, + 0x0FF6, 0x020A, 0x020A, 0x0FF6, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 4t_64p_LanczosEd_p_0.8_p_10qb_ +// 4 +// 64 +// input/output = 0.800000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_4tap_64p_ratio_0_80[132] = { + 0x0075, 0x0315, 0x0076, 0x0000, + 0x006C, 0x0316, 0x007F, 0x0FFF, + 0x0062, 0x0316, 0x008A, 0x0FFE, + 0x0059, 0x0315, 0x0096, 0x0FFC, + 0x0050, 0x0314, 0x00A1, 0x0FFB, + 0x0048, 0x0312, 0x00AD, 0x0FF9, + 0x0040, 0x0310, 0x00B8, 0x0FF8, + 0x0038, 0x030D, 0x00C5, 0x0FF6, + 0x0030, 0x030A, 0x00D1, 0x0FF5, + 0x0029, 0x0306, 0x00DE, 0x0FF3, + 0x0022, 0x0301, 0x00EB, 0x0FF2, + 0x001C, 0x02FC, 0x00F8, 0x0FF0, + 0x0015, 0x02F7, 0x0106, 0x0FEE, + 0x0010, 0x02F1, 0x0112, 0x0FED, + 0x000A, 0x02EA, 0x0121, 0x0FEB, + 0x0005, 0x02E3, 0x012F, 0x0FE9, + 0x0000, 0x02DB, 0x013D, 0x0FE8, + 0x0FFB, 0x02D3, 0x014C, 0x0FE6, + 0x0FF7, 0x02CA, 0x015A, 0x0FE5, + 0x0FF3, 0x02C1, 0x0169, 0x0FE3, + 0x0FF0, 0x02B7, 0x0177, 0x0FE2, + 0x0FEC, 0x02AD, 0x0186, 0x0FE1, + 0x0FE9, 0x02A2, 0x0196, 0x0FDF, + 0x0FE7, 0x0297, 0x01A4, 0x0FDE, + 0x0FE4, 0x028C, 0x01B3, 0x0FDD, + 0x0FE2, 0x0280, 0x01C2, 0x0FDC, + 0x0FE0, 0x0274, 0x01D0, 0x0FDC, + 0x0FDF, 0x0268, 0x01DE, 0x0FDB, + 0x0FDD, 0x025B, 0x01EE, 0x0FDA, + 0x0FDC, 0x024E, 0x01FC, 0x0FDA, + 0x0FDB, 0x0241, 0x020A, 0x0FDA, + 0x0FDB, 0x0233, 0x0218, 0x0FDA, + 0x0FDA, 0x0226, 0x0226, 0x0FDA, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 4t_64p_LanczosEd_p_0.9_p_10qb_ +// 4 +// 64 +// input/output = 0.900000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_4tap_64p_ratio_0_90[132] = { + 0x003F, 0x0383, 0x003E, 0x0000, + 0x0034, 0x0383, 0x004A, 0x0FFF, + 0x002B, 0x0383, 0x0054, 0x0FFE, + 0x0021, 0x0381, 0x0061, 0x0FFD, + 0x0019, 0x037F, 0x006C, 0x0FFC, + 0x0010, 0x037C, 0x0079, 0x0FFB, + 0x0008, 0x0378, 0x0086, 0x0FFA, + 0x0001, 0x0374, 0x0093, 0x0FF8, + 0x0FFA, 0x036E, 0x00A1, 0x0FF7, + 0x0FF3, 0x0368, 0x00B0, 0x0FF5, + 0x0FED, 0x0361, 0x00BF, 0x0FF3, + 0x0FE8, 0x035A, 0x00CD, 0x0FF1, + 0x0FE2, 0x0352, 0x00DC, 0x0FF0, + 0x0FDE, 0x0349, 0x00EB, 0x0FEE, + 0x0FD9, 0x033F, 0x00FC, 0x0FEC, + 0x0FD5, 0x0335, 0x010D, 0x0FE9, + 0x0FD2, 0x032A, 0x011D, 0x0FE7, + 0x0FCF, 0x031E, 0x012E, 0x0FE5, + 0x0FCC, 0x0312, 0x013F, 0x0FE3, + 0x0FCA, 0x0305, 0x0150, 0x0FE1, + 0x0FC8, 0x02F8, 0x0162, 0x0FDE, + 0x0FC6, 0x02EA, 0x0174, 0x0FDC, + 0x0FC5, 0x02DC, 0x0185, 0x0FDA, + 0x0FC4, 0x02CD, 0x0197, 0x0FD8, + 0x0FC3, 0x02BE, 0x01AA, 0x0FD5, + 0x0FC3, 0x02AF, 0x01BB, 0x0FD3, + 0x0FC3, 0x029F, 0x01CD, 0x0FD1, + 0x0FC3, 0x028E, 0x01E0, 0x0FCF, + 0x0FC3, 0x027E, 0x01F2, 0x0FCD, + 0x0FC4, 0x026D, 0x0203, 0x0FCC, + 0x0FC5, 0x025C, 0x0215, 0x0FCA, + 0x0FC6, 0x024B, 0x0227, 0x0FC8, + 0x0FC7, 0x0239, 0x0239, 0x0FC7, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 4t_64p_LanczosEd_p_1_p_10qb_ +// 4 +// 64 +// input/output = 1.000000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_4tap_64p_ratio_1_00[132] = { + 0x0000, 0x0400, 0x0000, 0x0000, + 0x0FF6, 0x03FF, 0x000B, 0x0000, + 0x0FED, 0x03FE, 0x0015, 0x0000, + 0x0FE4, 0x03FB, 0x0022, 0x0FFF, + 0x0FDC, 0x03F7, 0x002E, 0x0FFF, + 0x0FD5, 0x03F2, 0x003B, 0x0FFE, + 0x0FCE, 0x03EC, 0x0048, 0x0FFE, + 0x0FC8, 0x03E5, 0x0056, 0x0FFD, + 0x0FC3, 0x03DC, 0x0065, 0x0FFC, + 0x0FBE, 0x03D3, 0x0075, 0x0FFA, + 0x0FB9, 0x03C9, 0x0085, 0x0FF9, + 0x0FB6, 0x03BE, 0x0094, 0x0FF8, + 0x0FB2, 0x03B2, 0x00A6, 0x0FF6, + 0x0FB0, 0x03A5, 0x00B7, 0x0FF4, + 0x0FAD, 0x0397, 0x00CA, 0x0FF2, + 0x0FAB, 0x0389, 0x00DC, 0x0FF0, + 0x0FAA, 0x0379, 0x00EF, 0x0FEE, + 0x0FA9, 0x0369, 0x0102, 0x0FEC, + 0x0FA9, 0x0359, 0x0115, 0x0FE9, + 0x0FA9, 0x0348, 0x0129, 0x0FE6, + 0x0FA9, 0x0336, 0x013D, 0x0FE4, + 0x0FA9, 0x0323, 0x0153, 0x0FE1, + 0x0FAA, 0x0310, 0x0168, 0x0FDE, + 0x0FAC, 0x02FD, 0x017C, 0x0FDB, + 0x0FAD, 0x02E9, 0x0192, 0x0FD8, + 0x0FAF, 0x02D5, 0x01A7, 0x0FD5, + 0x0FB1, 0x02C0, 0x01BD, 0x0FD2, + 0x0FB3, 0x02AC, 0x01D2, 0x0FCF, + 0x0FB5, 0x0296, 0x01E9, 0x0FCC, + 0x0FB8, 0x0281, 0x01FE, 0x0FC9, + 0x0FBA, 0x026C, 0x0214, 0x0FC6, + 0x0FBD, 0x0256, 0x022A, 0x0FC3, + 0x0FC0, 0x0240, 0x0240, 0x0FC0, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 02-Apr-2024 +// 6t_64p_LanczosEd_p_0.3_p_10qb_ +// 6 +// 64 +// input/output = 0.300000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_6tap_64p_ratio_0_30[198] = { + 0x004B, 0x0100, 0x0169, 0x0101, 0x004B, 0x0000, + 0x0049, 0x00FD, 0x0169, 0x0103, 0x004E, 0x0000, + 0x0047, 0x00FA, 0x0169, 0x0106, 0x0050, 0x0000, + 0x0045, 0x00F7, 0x0168, 0x0109, 0x0052, 0x0001, + 0x0043, 0x00F5, 0x0168, 0x010B, 0x0054, 0x0001, + 0x0040, 0x00F2, 0x0168, 0x010E, 0x0057, 0x0001, + 0x003E, 0x00EF, 0x0168, 0x0110, 0x0059, 0x0002, + 0x003C, 0x00EC, 0x0167, 0x0113, 0x005C, 0x0002, + 0x003A, 0x00E9, 0x0167, 0x0116, 0x005E, 0x0002, + 0x0038, 0x00E6, 0x0166, 0x0118, 0x0061, 0x0003, + 0x0036, 0x00E3, 0x0165, 0x011C, 0x0063, 0x0003, + 0x0034, 0x00E0, 0x0165, 0x011D, 0x0066, 0x0004, + 0x0033, 0x00DD, 0x0164, 0x0120, 0x0068, 0x0004, + 0x0031, 0x00DA, 0x0163, 0x0122, 0x006B, 0x0005, + 0x002F, 0x00D7, 0x0163, 0x0125, 0x006D, 0x0005, + 0x002D, 0x00D3, 0x0162, 0x0128, 0x0070, 0x0006, + 0x002B, 0x00D0, 0x0161, 0x012A, 0x0073, 0x0007, + 0x002A, 0x00CD, 0x0160, 0x012D, 0x0075, 0x0007, + 0x0028, 0x00CA, 0x015F, 0x012F, 0x0078, 0x0008, + 0x0026, 0x00C7, 0x015E, 0x0131, 0x007B, 0x0009, + 0x0025, 0x00C4, 0x015D, 0x0133, 0x007E, 0x0009, + 0x0023, 0x00C1, 0x015C, 0x0136, 0x0080, 0x000A, + 0x0022, 0x00BE, 0x015A, 0x0138, 0x0083, 0x000B, + 0x0020, 0x00BB, 0x0159, 0x013A, 0x0086, 0x000C, + 0x001F, 0x00B8, 0x0158, 0x013B, 0x0089, 0x000D, + 0x001E, 0x00B5, 0x0156, 0x013E, 0x008C, 0x000D, + 0x001C, 0x00B2, 0x0155, 0x0140, 0x008F, 0x000E, + 0x001B, 0x00AF, 0x0153, 0x0143, 0x0091, 0x000F, + 0x0019, 0x00AC, 0x0152, 0x0145, 0x0094, 0x0010, + 0x0018, 0x00A9, 0x0150, 0x0147, 0x0097, 0x0011, + 0x0017, 0x00A6, 0x014F, 0x0148, 0x009A, 0x0012, + 0x0016, 0x00A3, 0x014D, 0x0149, 0x009D, 0x0014, + 0x0015, 0x00A0, 0x014B, 0x014B, 0x00A0, 0x0015, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 02-Apr-2024 +// 6t_64p_LanczosEd_p_0.4_p_10qb_ +// 6 +// 64 +// input/output = 0.400000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_6tap_64p_ratio_0_40[198] = { + 0x0028, 0x0106, 0x01A3, 0x0107, 0x0028, 0x0000, + 0x0026, 0x0102, 0x01A3, 0x010A, 0x002B, 0x0000, + 0x0024, 0x00FE, 0x01A3, 0x010F, 0x002D, 0x0FFF, + 0x0022, 0x00FA, 0x01A3, 0x0113, 0x002F, 0x0FFF, + 0x0021, 0x00F6, 0x01A3, 0x0116, 0x0031, 0x0FFF, + 0x001F, 0x00F2, 0x01A2, 0x011B, 0x0034, 0x0FFE, + 0x001D, 0x00EE, 0x01A2, 0x011F, 0x0036, 0x0FFE, + 0x001B, 0x00EA, 0x01A1, 0x0123, 0x0039, 0x0FFE, + 0x0019, 0x00E6, 0x01A1, 0x0127, 0x003B, 0x0FFE, + 0x0018, 0x00E2, 0x01A0, 0x012A, 0x003E, 0x0FFE, + 0x0016, 0x00DE, 0x01A0, 0x012E, 0x0041, 0x0FFD, + 0x0015, 0x00DA, 0x019F, 0x0132, 0x0043, 0x0FFD, + 0x0013, 0x00D6, 0x019E, 0x0136, 0x0046, 0x0FFD, + 0x0012, 0x00D2, 0x019D, 0x0139, 0x0049, 0x0FFD, + 0x0010, 0x00CE, 0x019C, 0x013D, 0x004C, 0x0FFD, + 0x000F, 0x00CA, 0x019A, 0x0141, 0x004F, 0x0FFD, + 0x000E, 0x00C6, 0x0199, 0x0144, 0x0052, 0x0FFD, + 0x000D, 0x00C2, 0x0197, 0x0148, 0x0055, 0x0FFD, + 0x000B, 0x00BE, 0x0196, 0x014C, 0x0058, 0x0FFD, + 0x000A, 0x00BA, 0x0195, 0x014F, 0x005B, 0x0FFD, + 0x0009, 0x00B6, 0x0193, 0x0153, 0x005E, 0x0FFD, + 0x0008, 0x00B2, 0x0191, 0x0157, 0x0061, 0x0FFD, + 0x0007, 0x00AE, 0x0190, 0x015A, 0x0064, 0x0FFD, + 0x0006, 0x00AA, 0x018E, 0x015D, 0x0068, 0x0FFD, + 0x0005, 0x00A6, 0x018C, 0x0161, 0x006B, 0x0FFD, + 0x0005, 0x00A2, 0x0189, 0x0164, 0x006F, 0x0FFD, + 0x0004, 0x009E, 0x0187, 0x0167, 0x0072, 0x0FFE, + 0x0003, 0x009A, 0x0185, 0x016B, 0x0075, 0x0FFE, + 0x0002, 0x0096, 0x0183, 0x016E, 0x0079, 0x0FFE, + 0x0002, 0x0093, 0x0180, 0x016F, 0x007D, 0x0FFF, + 0x0001, 0x008F, 0x017E, 0x0173, 0x0080, 0x0FFF, + 0x0001, 0x008B, 0x017B, 0x0175, 0x0084, 0x0000, + 0x0000, 0x0087, 0x0179, 0x0179, 0x0087, 0x0000, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 02-Apr-2024 +// 6t_64p_LanczosEd_p_0.5_p_10qb_ +// 6 +// 64 +// input/output = 0.500000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_6tap_64p_ratio_0_50[198] = { + 0x0000, 0x0107, 0x01F3, 0x0106, 0x0000, 0x0000, + 0x0FFE, 0x0101, 0x01F3, 0x010D, 0x0002, 0x0FFF, + 0x0FFD, 0x00FB, 0x01F3, 0x0113, 0x0003, 0x0FFF, + 0x0FFC, 0x00F6, 0x01F3, 0x0118, 0x0005, 0x0FFE, + 0x0FFA, 0x00F0, 0x01F3, 0x011E, 0x0007, 0x0FFE, + 0x0FF9, 0x00EB, 0x01F2, 0x0124, 0x0009, 0x0FFD, + 0x0FF8, 0x00E5, 0x01F2, 0x0129, 0x000B, 0x0FFD, + 0x0FF7, 0x00E0, 0x01F1, 0x012F, 0x000D, 0x0FFC, + 0x0FF6, 0x00DA, 0x01F0, 0x0135, 0x0010, 0x0FFB, + 0x0FF5, 0x00D4, 0x01EF, 0x013B, 0x0012, 0x0FFB, + 0x0FF4, 0x00CF, 0x01EE, 0x0141, 0x0014, 0x0FFA, + 0x0FF3, 0x00C9, 0x01ED, 0x0147, 0x0017, 0x0FF9, + 0x0FF2, 0x00C4, 0x01EB, 0x014C, 0x001A, 0x0FF9, + 0x0FF1, 0x00BF, 0x01EA, 0x0152, 0x001C, 0x0FF8, + 0x0FF1, 0x00B9, 0x01E8, 0x0157, 0x001F, 0x0FF8, + 0x0FF0, 0x00B4, 0x01E6, 0x015D, 0x0022, 0x0FF7, + 0x0FF0, 0x00AE, 0x01E4, 0x0163, 0x0025, 0x0FF6, + 0x0FEF, 0x00A9, 0x01E2, 0x0168, 0x0028, 0x0FF6, + 0x0FEF, 0x00A4, 0x01DF, 0x016E, 0x002B, 0x0FF5, + 0x0FEF, 0x009F, 0x01DD, 0x0172, 0x002E, 0x0FF5, + 0x0FEE, 0x009A, 0x01DA, 0x0178, 0x0032, 0x0FF4, + 0x0FEE, 0x0094, 0x01D8, 0x017E, 0x0035, 0x0FF3, + 0x0FEE, 0x008F, 0x01D5, 0x0182, 0x0039, 0x0FF3, + 0x0FEE, 0x008A, 0x01D2, 0x0188, 0x003C, 0x0FF2, + 0x0FEE, 0x0085, 0x01CF, 0x018C, 0x0040, 0x0FF2, + 0x0FEE, 0x0081, 0x01CB, 0x0191, 0x0044, 0x0FF1, + 0x0FEE, 0x007C, 0x01C8, 0x0196, 0x0047, 0x0FF1, + 0x0FEE, 0x0077, 0x01C4, 0x019C, 0x004B, 0x0FF0, + 0x0FEE, 0x0072, 0x01C1, 0x01A0, 0x004F, 0x0FF0, + 0x0FEE, 0x006E, 0x01BD, 0x01A4, 0x0053, 0x0FF0, + 0x0FEE, 0x0069, 0x01B9, 0x01A9, 0x0058, 0x0FEF, + 0x0FEE, 0x0065, 0x01B5, 0x01AD, 0x005C, 0x0FEF, + 0x0FEF, 0x0060, 0x01B1, 0x01B1, 0x0060, 0x0FEF, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 02-Apr-2024 +// 6t_64p_LanczosEd_p_0.6_p_10qb_ +// 6 +// 64 +// input/output = 0.600000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_6tap_64p_ratio_0_60[198] = { + 0x0FD9, 0x00FB, 0x0258, 0x00FB, 0x0FD9, 0x0000, + 0x0FD9, 0x00F3, 0x0258, 0x0102, 0x0FDA, 0x0000, + 0x0FD8, 0x00EB, 0x0258, 0x010B, 0x0FDB, 0x0FFF, + 0x0FD8, 0x00E3, 0x0258, 0x0112, 0x0FDC, 0x0FFF, + 0x0FD8, 0x00DC, 0x0257, 0x011B, 0x0FDC, 0x0FFE, + 0x0FD7, 0x00D4, 0x0256, 0x0123, 0x0FDE, 0x0FFE, + 0x0FD7, 0x00CD, 0x0255, 0x012B, 0x0FDF, 0x0FFD, + 0x0FD7, 0x00C5, 0x0254, 0x0133, 0x0FE0, 0x0FFD, + 0x0FD7, 0x00BE, 0x0252, 0x013C, 0x0FE1, 0x0FFC, + 0x0FD7, 0x00B6, 0x0251, 0x0143, 0x0FE3, 0x0FFC, + 0x0FD8, 0x00AF, 0x024F, 0x014B, 0x0FE4, 0x0FFB, + 0x0FD8, 0x00A8, 0x024C, 0x0154, 0x0FE6, 0x0FFA, + 0x0FD8, 0x00A1, 0x024A, 0x015B, 0x0FE8, 0x0FFA, + 0x0FD9, 0x009A, 0x0247, 0x0163, 0x0FEA, 0x0FF9, + 0x0FD9, 0x0093, 0x0244, 0x016C, 0x0FEC, 0x0FF8, + 0x0FD9, 0x008C, 0x0241, 0x0174, 0x0FEF, 0x0FF7, + 0x0FDA, 0x0085, 0x023E, 0x017B, 0x0FF1, 0x0FF7, + 0x0FDB, 0x007F, 0x023A, 0x0183, 0x0FF3, 0x0FF6, + 0x0FDB, 0x0078, 0x0237, 0x018B, 0x0FF6, 0x0FF5, + 0x0FDC, 0x0072, 0x0233, 0x0192, 0x0FF9, 0x0FF4, + 0x0FDD, 0x006C, 0x022F, 0x0199, 0x0FFC, 0x0FF3, + 0x0FDD, 0x0065, 0x022A, 0x01A3, 0x0FFF, 0x0FF2, + 0x0FDE, 0x005F, 0x0226, 0x01AA, 0x0002, 0x0FF1, + 0x0FDF, 0x005A, 0x0221, 0x01B0, 0x0006, 0x0FF0, + 0x0FE0, 0x0054, 0x021C, 0x01B7, 0x0009, 0x0FF0, + 0x0FE1, 0x004E, 0x0217, 0x01BE, 0x000D, 0x0FEF, + 0x0FE2, 0x0048, 0x0212, 0x01C6, 0x0010, 0x0FEE, + 0x0FE3, 0x0043, 0x020C, 0x01CD, 0x0014, 0x0FED, + 0x0FE4, 0x003E, 0x0207, 0x01D3, 0x0018, 0x0FEC, + 0x0FE5, 0x0039, 0x0200, 0x01DA, 0x001D, 0x0FEB, + 0x0FE6, 0x0034, 0x01FA, 0x01E1, 0x0021, 0x0FEA, + 0x0FE7, 0x002F, 0x01F5, 0x01E7, 0x0025, 0x0FE9, + 0x0FE8, 0x002A, 0x01EE, 0x01EE, 0x002A, 0x0FE8, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 02-Apr-2024 +// 6t_64p_LanczosEd_p_0.7_p_10qb_ +// 6 +// 64 +// input/output = 0.700000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_6tap_64p_ratio_0_70[198] = { + 0x0FC0, 0x00DA, 0x02CC, 0x00DA, 0x0FC0, 0x0000, + 0x0FC1, 0x00D0, 0x02CC, 0x00E4, 0x0FBF, 0x0000, + 0x0FC2, 0x00C6, 0x02CB, 0x00EF, 0x0FBE, 0x0000, + 0x0FC3, 0x00BC, 0x02CA, 0x00F9, 0x0FBE, 0x0000, + 0x0FC4, 0x00B2, 0x02C9, 0x0104, 0x0FBD, 0x0000, + 0x0FC5, 0x00A8, 0x02C7, 0x010F, 0x0FBD, 0x0000, + 0x0FC7, 0x009F, 0x02C5, 0x0119, 0x0FBC, 0x0000, + 0x0FC8, 0x0095, 0x02C3, 0x0124, 0x0FBC, 0x0000, + 0x0FC9, 0x008C, 0x02C0, 0x012F, 0x0FBC, 0x0000, + 0x0FCB, 0x0083, 0x02BD, 0x0139, 0x0FBC, 0x0000, + 0x0FCC, 0x007A, 0x02BA, 0x0144, 0x0FBC, 0x0000, + 0x0FCE, 0x0072, 0x02B6, 0x014D, 0x0FBD, 0x0000, + 0x0FD0, 0x0069, 0x02B2, 0x0159, 0x0FBD, 0x0FFF, + 0x0FD1, 0x0061, 0x02AD, 0x0164, 0x0FBE, 0x0FFF, + 0x0FD3, 0x0059, 0x02A9, 0x016E, 0x0FBF, 0x0FFE, + 0x0FD4, 0x0051, 0x02A4, 0x017A, 0x0FBF, 0x0FFE, + 0x0FD6, 0x0049, 0x029E, 0x0184, 0x0FC1, 0x0FFE, + 0x0FD8, 0x0042, 0x0299, 0x018E, 0x0FC2, 0x0FFD, + 0x0FD9, 0x003A, 0x0293, 0x019B, 0x0FC3, 0x0FFC, + 0x0FDB, 0x0033, 0x028D, 0x01A4, 0x0FC5, 0x0FFC, + 0x0FDC, 0x002D, 0x0286, 0x01AF, 0x0FC7, 0x0FFB, + 0x0FDE, 0x0026, 0x0280, 0x01BA, 0x0FC8, 0x0FFA, + 0x0FE0, 0x001F, 0x0279, 0x01C4, 0x0FCB, 0x0FF9, + 0x0FE1, 0x0019, 0x0272, 0x01CE, 0x0FCD, 0x0FF9, + 0x0FE3, 0x0013, 0x026A, 0x01D9, 0x0FCF, 0x0FF8, + 0x0FE4, 0x000D, 0x0263, 0x01E3, 0x0FD2, 0x0FF7, + 0x0FE6, 0x0008, 0x025B, 0x01EC, 0x0FD5, 0x0FF6, + 0x0FE7, 0x0002, 0x0253, 0x01F7, 0x0FD8, 0x0FF5, + 0x0FE9, 0x0FFD, 0x024A, 0x0202, 0x0FDB, 0x0FF3, + 0x0FEA, 0x0FF8, 0x0242, 0x020B, 0x0FDF, 0x0FF2, + 0x0FEC, 0x0FF3, 0x0239, 0x0215, 0x0FE2, 0x0FF1, + 0x0FED, 0x0FEF, 0x0230, 0x021E, 0x0FE6, 0x0FF0, + 0x0FEF, 0x0FEB, 0x0226, 0x0226, 0x0FEB, 0x0FEF, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 02-Apr-2024 +// 6t_64p_LanczosEd_p_0.8_p_10qb_ +// 6 +// 64 +// input/output = 0.800000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_6tap_64p_ratio_0_80[198] = { + 0x0FBF, 0x00A1, 0x0340, 0x00A1, 0x0FBF, 0x0000, + 0x0FC1, 0x0095, 0x0340, 0x00AD, 0x0FBC, 0x0001, + 0x0FC4, 0x0089, 0x033E, 0x00BA, 0x0FBA, 0x0001, + 0x0FC6, 0x007D, 0x033D, 0x00C6, 0x0FB8, 0x0002, + 0x0FC9, 0x0072, 0x033A, 0x00D3, 0x0FB6, 0x0002, + 0x0FCC, 0x0067, 0x0338, 0x00DF, 0x0FB3, 0x0003, + 0x0FCE, 0x005C, 0x0334, 0x00EE, 0x0FB1, 0x0003, + 0x0FD1, 0x0051, 0x0331, 0x00FA, 0x0FAF, 0x0004, + 0x0FD3, 0x0047, 0x032D, 0x0108, 0x0FAD, 0x0004, + 0x0FD6, 0x003D, 0x0328, 0x0116, 0x0FAB, 0x0004, + 0x0FD8, 0x0033, 0x0323, 0x0123, 0x0FAA, 0x0005, + 0x0FDB, 0x002A, 0x031D, 0x0131, 0x0FA8, 0x0005, + 0x0FDD, 0x0021, 0x0317, 0x013F, 0x0FA7, 0x0005, + 0x0FDF, 0x0018, 0x0311, 0x014D, 0x0FA5, 0x0006, + 0x0FE2, 0x0010, 0x030A, 0x015A, 0x0FA4, 0x0006, + 0x0FE4, 0x0008, 0x0302, 0x0169, 0x0FA3, 0x0006, + 0x0FE6, 0x0000, 0x02FB, 0x0177, 0x0FA2, 0x0006, + 0x0FE8, 0x0FF9, 0x02F3, 0x0185, 0x0FA1, 0x0006, + 0x0FEB, 0x0FF1, 0x02EA, 0x0193, 0x0FA1, 0x0006, + 0x0FED, 0x0FEB, 0x02E1, 0x01A1, 0x0FA0, 0x0006, + 0x0FEE, 0x0FE4, 0x02D8, 0x01B0, 0x0FA0, 0x0006, + 0x0FF0, 0x0FDE, 0x02CE, 0x01BE, 0x0FA0, 0x0006, + 0x0FF2, 0x0FD8, 0x02C5, 0x01CB, 0x0FA0, 0x0006, + 0x0FF4, 0x0FD3, 0x02BA, 0x01D8, 0x0FA1, 0x0006, + 0x0FF6, 0x0FCD, 0x02B0, 0x01E7, 0x0FA1, 0x0005, + 0x0FF7, 0x0FC8, 0x02A5, 0x01F5, 0x0FA2, 0x0005, + 0x0FF9, 0x0FC4, 0x029A, 0x0202, 0x0FA3, 0x0004, + 0x0FFA, 0x0FC0, 0x028E, 0x0210, 0x0FA4, 0x0004, + 0x0FFB, 0x0FBC, 0x0283, 0x021D, 0x0FA6, 0x0003, + 0x0FFD, 0x0FB8, 0x0276, 0x022A, 0x0FA8, 0x0003, + 0x0FFE, 0x0FB4, 0x026B, 0x0237, 0x0FAA, 0x0002, + 0x0FFF, 0x0FB1, 0x025E, 0x0245, 0x0FAC, 0x0001, + 0x0000, 0x0FAE, 0x0252, 0x0252, 0x0FAE, 0x0000, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 02-Apr-2024 +// 6t_64p_LanczosEd_p_0.9_p_10qb_ +// 6 +// 64 +// input/output = 0.900000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_6tap_64p_ratio_0_90[198] = { + 0x0FD8, 0x0055, 0x03A7, 0x0054, 0x0FD8, 0x0000, + 0x0FDB, 0x0047, 0x03A7, 0x0063, 0x0FD4, 0x0000, + 0x0FDF, 0x003B, 0x03A5, 0x006F, 0x0FD1, 0x0001, + 0x0FE2, 0x002E, 0x03A3, 0x007E, 0x0FCD, 0x0002, + 0x0FE5, 0x0022, 0x03A0, 0x008D, 0x0FCA, 0x0002, + 0x0FE8, 0x0017, 0x039D, 0x009B, 0x0FC6, 0x0003, + 0x0FEB, 0x000C, 0x0398, 0x00AC, 0x0FC2, 0x0003, + 0x0FEE, 0x0001, 0x0394, 0x00BA, 0x0FBF, 0x0004, + 0x0FF1, 0x0FF7, 0x038E, 0x00CA, 0x0FBB, 0x0005, + 0x0FF4, 0x0FED, 0x0388, 0x00DA, 0x0FB8, 0x0005, + 0x0FF6, 0x0FE4, 0x0381, 0x00EB, 0x0FB4, 0x0006, + 0x0FF9, 0x0FDB, 0x037A, 0x00FA, 0x0FB1, 0x0007, + 0x0FFB, 0x0FD3, 0x0372, 0x010B, 0x0FAD, 0x0008, + 0x0FFD, 0x0FCB, 0x0369, 0x011D, 0x0FAA, 0x0008, + 0x0000, 0x0FC3, 0x0360, 0x012E, 0x0FA6, 0x0009, + 0x0002, 0x0FBC, 0x0356, 0x013F, 0x0FA3, 0x000A, + 0x0003, 0x0FB6, 0x034C, 0x0150, 0x0FA0, 0x000B, + 0x0005, 0x0FB0, 0x0341, 0x0162, 0x0F9D, 0x000B, + 0x0007, 0x0FAA, 0x0336, 0x0173, 0x0F9A, 0x000C, + 0x0008, 0x0FA5, 0x032A, 0x0185, 0x0F97, 0x000D, + 0x000A, 0x0FA0, 0x031E, 0x0197, 0x0F94, 0x000D, + 0x000B, 0x0F9B, 0x0311, 0x01A9, 0x0F92, 0x000E, + 0x000C, 0x0F97, 0x0303, 0x01BC, 0x0F8F, 0x000F, + 0x000D, 0x0F94, 0x02F6, 0x01CD, 0x0F8D, 0x000F, + 0x000E, 0x0F91, 0x02E8, 0x01DE, 0x0F8B, 0x0010, + 0x000F, 0x0F8E, 0x02D9, 0x01F1, 0x0F89, 0x0010, + 0x0010, 0x0F8B, 0x02CA, 0x0202, 0x0F88, 0x0011, + 0x0010, 0x0F89, 0x02BB, 0x0214, 0x0F87, 0x0011, + 0x0011, 0x0F87, 0x02AB, 0x0226, 0x0F86, 0x0011, + 0x0011, 0x0F86, 0x029C, 0x0236, 0x0F85, 0x0012, + 0x0011, 0x0F85, 0x028B, 0x0249, 0x0F84, 0x0012, + 0x0012, 0x0F84, 0x027B, 0x0259, 0x0F84, 0x0012, + 0x0012, 0x0F84, 0x026A, 0x026A, 0x0F84, 0x0012, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 02-Apr-2024 +// 6t_64p_LanczosEd_p_1_p_10qb_ +// 6 +// 64 +// input/output = 1.000000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_6tap_64p_ratio_1_00[198] = { + 0x0000, 0x0000, 0x0400, 0x0000, 0x0000, 0x0000, + 0x0003, 0x0FF3, 0x0400, 0x000D, 0x0FFD, 0x0000, + 0x0006, 0x0FE7, 0x03FE, 0x001C, 0x0FF9, 0x0000, + 0x0009, 0x0FDB, 0x03FC, 0x002B, 0x0FF5, 0x0000, + 0x000C, 0x0FD0, 0x03F9, 0x003A, 0x0FF1, 0x0000, + 0x000E, 0x0FC5, 0x03F5, 0x004A, 0x0FED, 0x0001, + 0x0011, 0x0FBB, 0x03F0, 0x005A, 0x0FE9, 0x0001, + 0x0013, 0x0FB2, 0x03EB, 0x006A, 0x0FE5, 0x0001, + 0x0015, 0x0FA9, 0x03E4, 0x007B, 0x0FE1, 0x0002, + 0x0017, 0x0FA1, 0x03DD, 0x008D, 0x0FDC, 0x0002, + 0x0018, 0x0F99, 0x03D4, 0x00A0, 0x0FD8, 0x0003, + 0x001A, 0x0F92, 0x03CB, 0x00B2, 0x0FD3, 0x0004, + 0x001B, 0x0F8C, 0x03C1, 0x00C6, 0x0FCE, 0x0004, + 0x001C, 0x0F86, 0x03B7, 0x00D9, 0x0FC9, 0x0005, + 0x001D, 0x0F80, 0x03AB, 0x00EE, 0x0FC4, 0x0006, + 0x001E, 0x0F7C, 0x039F, 0x0101, 0x0FBF, 0x0007, + 0x001F, 0x0F78, 0x0392, 0x0115, 0x0FBA, 0x0008, + 0x001F, 0x0F74, 0x0385, 0x012B, 0x0FB5, 0x0008, + 0x0020, 0x0F71, 0x0376, 0x0140, 0x0FB0, 0x0009, + 0x0020, 0x0F6E, 0x0367, 0x0155, 0x0FAB, 0x000B, + 0x0020, 0x0F6C, 0x0357, 0x016B, 0x0FA6, 0x000C, + 0x0020, 0x0F6A, 0x0347, 0x0180, 0x0FA2, 0x000D, + 0x0020, 0x0F69, 0x0336, 0x0196, 0x0F9D, 0x000E, + 0x0020, 0x0F69, 0x0325, 0x01AB, 0x0F98, 0x000F, + 0x001F, 0x0F68, 0x0313, 0x01C3, 0x0F93, 0x0010, + 0x001F, 0x0F69, 0x0300, 0x01D8, 0x0F8F, 0x0011, + 0x001E, 0x0F69, 0x02ED, 0x01EF, 0x0F8B, 0x0012, + 0x001D, 0x0F6A, 0x02D9, 0x0205, 0x0F87, 0x0014, + 0x001D, 0x0F6C, 0x02C5, 0x021A, 0x0F83, 0x0015, + 0x001C, 0x0F6E, 0x02B1, 0x0230, 0x0F7F, 0x0016, + 0x001B, 0x0F70, 0x029C, 0x0247, 0x0F7B, 0x0017, + 0x001A, 0x0F72, 0x0287, 0x025D, 0x0F78, 0x0018, + 0x0019, 0x0F75, 0x0272, 0x0272, 0x0F75, 0x0019, +}; + +/* Converted scaler coeff tables from S1.10 to S1.12 */ +static const uint16_t easf_filter_3tap_64p_ratio_0_30_s1_12[99] = { +0x0800, 0x0800, 0x0000, +0x07d8, 0x0818, 0x0010, +0x07b0, 0x082c, 0x0024, +0x0788, 0x0844, 0x0034, +0x0760, 0x0858, 0x0048, +0x0738, 0x0870, 0x0058, +0x0710, 0x0884, 0x006c, +0x06e8, 0x0898, 0x0080, +0x06c0, 0x08a8, 0x0098, +0x0698, 0x08bc, 0x00ac, +0x0670, 0x08cc, 0x00c4, +0x0648, 0x08e0, 0x00d8, +0x0620, 0x08f0, 0x00f0, +0x05f8, 0x0900, 0x0108, +0x05d0, 0x0910, 0x0120, +0x05a8, 0x0920, 0x0138, +0x0584, 0x0928, 0x0154, +0x055c, 0x0938, 0x016c, +0x0534, 0x0944, 0x0188, +0x0510, 0x094c, 0x01a4, +0x04e8, 0x0958, 0x01c0, +0x04c4, 0x0960, 0x01dc, +0x049c, 0x096c, 0x01f8, +0x0478, 0x0970, 0x0218, +0x0454, 0x0978, 0x0234, +0x042c, 0x0980, 0x0254, +0x0408, 0x0988, 0x0270, +0x03e4, 0x098c, 0x0290, +0x03c0, 0x0990, 0x02b0, +0x039c, 0x0994, 0x02d0, +0x037c, 0x0990, 0x02f4, +0x0358, 0x0994, 0x0314, +0x0334, 0x0998, 0x0334, +}; + +static const uint16_t easf_filter_3tap_64p_ratio_0_40_s1_12[99] = { +0x0800, 0x0800, 0x0000, +0x07d8, 0x0818, 0x0010, +0x07ac, 0x0838, 0x001c, +0x0784, 0x0850, 0x002c, +0x075c, 0x0868, 0x003c, +0x0734, 0x0880, 0x004c, +0x0708, 0x0898, 0x0060, +0x06e0, 0x08b0, 0x0070, +0x06b8, 0x08c4, 0x0084, +0x068c, 0x08dc, 0x0098, +0x0664, 0x08f0, 0x00ac, +0x063c, 0x0900, 0x00c4, +0x0614, 0x0914, 0x00d8, +0x05e8, 0x0928, 0x00f0, +0x05c0, 0x093c, 0x0104, +0x0598, 0x094c, 0x011c, +0x0570, 0x095c, 0x0134, +0x0548, 0x0968, 0x0150, +0x0520, 0x0978, 0x0168, +0x04f8, 0x0984, 0x0184, +0x04d0, 0x0990, 0x01a0, +0x04ac, 0x0998, 0x01bc, +0x0484, 0x09a4, 0x01d8, +0x045c, 0x09b0, 0x01f4, +0x0438, 0x09b8, 0x0210, +0x0410, 0x09c0, 0x0230, +0x03ec, 0x09c4, 0x0250, +0x03c8, 0x09c8, 0x0270, +0x03a4, 0x09cc, 0x0290, +0x0380, 0x09d0, 0x02b0, +0x035c, 0x09d4, 0x02d0, +0x0338, 0x09d4, 0x02f4, +0x0314, 0x09d8, 0x0314, +}; + +static const uint16_t easf_filter_3tap_64p_ratio_0_50_s1_12[99] = { +0x0800, 0x0800, 0x0000, +0x07d4, 0x0824, 0x0008, +0x07a8, 0x0844, 0x0014, +0x077c, 0x0868, 0x001c, +0x0750, 0x0888, 0x0028, +0x0724, 0x08a8, 0x0034, +0x06f8, 0x08c8, 0x0040, +0x06cc, 0x08e4, 0x0050, +0x06a0, 0x0904, 0x005c, +0x0674, 0x0920, 0x006c, +0x0648, 0x093c, 0x007c, +0x061c, 0x0954, 0x0090, +0x05f0, 0x0970, 0x00a0, +0x05c4, 0x0988, 0x00b4, +0x0598, 0x09a0, 0x00c8, +0x056c, 0x09b8, 0x00dc, +0x0540, 0x09cc, 0x00f4, +0x0518, 0x09e0, 0x0108, +0x04ec, 0x09f4, 0x0120, +0x04c0, 0x0a08, 0x0138, +0x0498, 0x0a18, 0x0150, +0x046c, 0x0a28, 0x016c, +0x0444, 0x0a34, 0x0188, +0x041c, 0x0a40, 0x01a4, +0x03f4, 0x0a4c, 0x01c0, +0x03cc, 0x0a58, 0x01dc, +0x03a4, 0x0a60, 0x01fc, +0x037c, 0x0a68, 0x021c, +0x0354, 0x0a70, 0x023c, +0x0330, 0x0a74, 0x025c, +0x030c, 0x0a78, 0x027c, +0x02e8, 0x0a78, 0x02a0, +0x02c4, 0x0a78, 0x02c4, +}; + +static const uint16_t easf_filter_3tap_64p_ratio_0_60_s1_12[99] = { +0x0800, 0x0800, 0x0000, +0x07d0, 0x082c, 0x0004, +0x07a0, 0x0858, 0x0008, +0x0770, 0x0884, 0x000c, +0x0740, 0x08ac, 0x0014, +0x0710, 0x08d4, 0x001c, +0x06e0, 0x0900, 0x0020, +0x06b0, 0x0924, 0x002c, +0x0680, 0x094c, 0x0034, +0x0650, 0x0970, 0x0040, +0x0620, 0x0994, 0x004c, +0x05f0, 0x09b8, 0x0058, +0x05c0, 0x09dc, 0x0064, +0x0590, 0x09fc, 0x0074, +0x0560, 0x0a1c, 0x0084, +0x0530, 0x0a3c, 0x0094, +0x0500, 0x0a5c, 0x00a4, +0x04d4, 0x0a74, 0x00b8, +0x04a4, 0x0a90, 0x00cc, +0x0474, 0x0aac, 0x00e0, +0x0448, 0x0ac0, 0x00f8, +0x041c, 0x0ad4, 0x0110, +0x03f0, 0x0ae8, 0x0128, +0x03c4, 0x0afc, 0x0140, +0x0398, 0x0b0c, 0x015c, +0x036c, 0x0b1c, 0x0178, +0x0344, 0x0b28, 0x0194, +0x031c, 0x0b30, 0x01b4, +0x02f4, 0x0b38, 0x01d4, +0x02cc, 0x0b40, 0x01f4, +0x02a4, 0x0b48, 0x0214, +0x0280, 0x0b48, 0x0238, +0x025c, 0x0b48, 0x025c, +}; + +static const uint16_t easf_filter_3tap_64p_ratio_0_70_s1_12[99] = { +0x0800, 0x0800, 0x0000, +0x07cc, 0x0834, 0x0000, +0x0794, 0x086c, 0x0000, +0x0760, 0x08a0, 0x0000, +0x072c, 0x08d4, 0x0000, +0x06f4, 0x090c, 0x0000, +0x06c0, 0x093c, 0x0004, +0x0688, 0x0970, 0x0008, +0x0654, 0x09a0, 0x000c, +0x061c, 0x09d4, 0x0010, +0x05e8, 0x0a00, 0x0018, +0x05b4, 0x0a30, 0x001c, +0x057c, 0x0a60, 0x0024, +0x0548, 0x0a88, 0x0030, +0x0514, 0x0ab4, 0x0038, +0x04e0, 0x0adc, 0x0044, +0x04ac, 0x0b00, 0x0054, +0x0478, 0x0b28, 0x0060, +0x0444, 0x0b4c, 0x0070, +0x0414, 0x0b6c, 0x0080, +0x03e0, 0x0b8c, 0x0094, +0x03b0, 0x0ba8, 0x00a8, +0x0380, 0x0bc4, 0x00bc, +0x0354, 0x0bd8, 0x00d4, +0x0324, 0x0bf0, 0x00ec, +0x02f8, 0x0c04, 0x0104, +0x02cc, 0x0c14, 0x0120, +0x02a0, 0x0c24, 0x013c, +0x0278, 0x0c30, 0x0158, +0x0250, 0x0c38, 0x0178, +0x0228, 0x0c40, 0x0198, +0x0204, 0x0c40, 0x01bc, +0x01dc, 0x0c48, 0x01dc, +}; + +static const uint16_t easf_filter_3tap_64p_ratio_0_80_s1_12[99] = { +0x0800, 0x0800, 0x0000, +0x07c4, 0x0840, 0x3ffc, +0x0788, 0x0880, 0x3ff8, +0x0748, 0x08c8, 0x3ff0, +0x070c, 0x0904, 0x3ff0, +0x06d0, 0x0944, 0x3fec, +0x0690, 0x0988, 0x3fe8, +0x0654, 0x09c4, 0x3fe8, +0x0618, 0x0a04, 0x3fe4, +0x05d8, 0x0a44, 0x3fe4, +0x059c, 0x0a80, 0x3fe4, +0x0560, 0x0ab8, 0x3fe8, +0x0524, 0x0af4, 0x3fe8, +0x04e8, 0x0b2c, 0x3fec, +0x04b0, 0x0b5c, 0x3ff4, +0x0474, 0x0b94, 0x3ff8, +0x043c, 0x0bc4, 0x0000, +0x0404, 0x0bf4, 0x0008, +0x03cc, 0x0c20, 0x0014, +0x0394, 0x0c4c, 0x0020, +0x0360, 0x0c74, 0x002c, +0x032c, 0x0c98, 0x003c, +0x02f8, 0x0cbc, 0x004c, +0x02c8, 0x0cdc, 0x005c, +0x0298, 0x0cf8, 0x0070, +0x0268, 0x0d14, 0x0084, +0x023c, 0x0d28, 0x009c, +0x0210, 0x0d3c, 0x00b4, +0x01e4, 0x0d4c, 0x00d0, +0x01bc, 0x0d58, 0x00ec, +0x0194, 0x0d60, 0x010c, +0x0170, 0x0d64, 0x012c, +0x014c, 0x0d68, 0x014c, +}; + +static const uint16_t easf_filter_3tap_64p_ratio_0_90_s1_12[99] = { +0x0800, 0x0800, 0x0000, +0x07b8, 0x0850, 0x3ff8, +0x0770, 0x08a0, 0x3ff0, +0x0728, 0x08f0, 0x3fe8, +0x06e4, 0x093c, 0x3fe0, +0x069c, 0x0988, 0x3fdc, +0x0654, 0x09d8, 0x3fd4, +0x060c, 0x0a28, 0x3fcc, +0x05c8, 0x0a70, 0x3fc8, +0x0580, 0x0abc, 0x3fc4, +0x053c, 0x0b08, 0x3fbc, +0x04f8, 0x0b50, 0x3fb8, +0x04b4, 0x0b94, 0x3fb8, +0x0470, 0x0bdc, 0x3fb4, +0x0430, 0x0c1c, 0x3fb4, +0x03ec, 0x0c60, 0x3fb4, +0x03b0, 0x0c9c, 0x3fb4, +0x0370, 0x0cd8, 0x3fb8, +0x0334, 0x0d10, 0x3fbc, +0x02f8, 0x0d48, 0x3fc0, +0x02c0, 0x0d78, 0x3fc8, +0x0288, 0x0da8, 0x3fd0, +0x0254, 0x0dd4, 0x3fd8, +0x0220, 0x0dfc, 0x3fe4, +0x01ec, 0x0e20, 0x3ff4, +0x01bc, 0x0e44, 0x0000, +0x0190, 0x0e5c, 0x0014, +0x0164, 0x0e74, 0x0028, +0x0138, 0x0e8c, 0x003c, +0x0114, 0x0e98, 0x0054, +0x00ec, 0x0ea4, 0x0070, +0x00cc, 0x0ea8, 0x008c, +0x00a8, 0x0eb0, 0x00a8, +}; + +static const uint16_t easf_filter_3tap_64p_ratio_1_00_s1_12[99] = { +0x0800, 0x0800, 0x0000, +0x07ac, 0x085c, 0x3ff8, +0x0754, 0x08bc, 0x3ff0, +0x0700, 0x091c, 0x3fe4, +0x06ac, 0x0978, 0x3fdc, +0x0658, 0x09d8, 0x3fd0, +0x0604, 0x0a34, 0x3fc8, +0x05b0, 0x0a94, 0x3fbc, +0x0560, 0x0aec, 0x3fb4, +0x0510, 0x0b44, 0x3fac, +0x04c0, 0x0ba0, 0x3fa0, +0x0470, 0x0bf8, 0x3f98, +0x0424, 0x0c4c, 0x3f90, +0x03d8, 0x0ca0, 0x3f88, +0x0390, 0x0cf0, 0x3f80, +0x0348, 0x0d3c, 0x3f7c, +0x0300, 0x0d8c, 0x3f74, +0x02c0, 0x0dd0, 0x3f70, +0x027c, 0x0e14, 0x3f70, +0x0240, 0x0e54, 0x3f6c, +0x0204, 0x0e90, 0x3f6c, +0x01c8, 0x0ecc, 0x3f6c, +0x0190, 0x0f00, 0x3f70, +0x015c, 0x0f30, 0x3f74, +0x012c, 0x0f58, 0x3f7c, +0x00fc, 0x0f80, 0x3f84, +0x00d0, 0x0fa0, 0x3f90, +0x00a8, 0x0fbc, 0x3f9c, +0x0080, 0x0fd4, 0x3fac, +0x005c, 0x0fe8, 0x3fbc, +0x003c, 0x0ff4, 0x3fd0, +0x001c, 0x0ffc, 0x3fe8, +0x0000, 0x1000, 0x0000, +}; + +static const uint16_t easf_filter_4tap_64p_ratio_0_30_s1_12[132] = { +0x0410, 0x07e0, 0x0410, 0x0000, +0x03f8, 0x07dc, 0x0428, 0x0004, +0x03e0, 0x07d8, 0x043c, 0x000c, +0x03c8, 0x07d4, 0x0450, 0x0014, +0x03ac, 0x07d0, 0x046c, 0x0018, +0x0394, 0x07cc, 0x0480, 0x0020, +0x037c, 0x07c8, 0x0494, 0x0028, +0x0368, 0x07c0, 0x04a8, 0x0030, +0x0350, 0x07b8, 0x04c0, 0x0038, +0x0338, 0x07b4, 0x04d4, 0x0040, +0x0320, 0x07ac, 0x04e8, 0x004c, +0x0308, 0x07a4, 0x0500, 0x0054, +0x02f4, 0x079c, 0x0514, 0x005c, +0x02dc, 0x0794, 0x0528, 0x0068, +0x02c4, 0x0788, 0x0544, 0x0070, +0x02b0, 0x0780, 0x0554, 0x007c, +0x029c, 0x0774, 0x0568, 0x0088, +0x0284, 0x076c, 0x057c, 0x0094, +0x0270, 0x0760, 0x0594, 0x009c, +0x025c, 0x0754, 0x05a8, 0x00a8, +0x0248, 0x0748, 0x05b8, 0x00b8, +0x0230, 0x073c, 0x05d0, 0x00c4, +0x021c, 0x0730, 0x05e4, 0x00d0, +0x020c, 0x0724, 0x05f4, 0x00dc, +0x01f8, 0x0714, 0x0608, 0x00ec, +0x01e4, 0x0708, 0x061c, 0x00f8, +0x01d0, 0x06f8, 0x0630, 0x0108, +0x01c0, 0x06e8, 0x0640, 0x0118, +0x01ac, 0x06dc, 0x0654, 0x0124, +0x0198, 0x06cc, 0x0668, 0x0134, +0x0188, 0x06bc, 0x0678, 0x0144, +0x0178, 0x06ac, 0x0688, 0x0154, +0x0168, 0x0698, 0x0698, 0x0168, +}; + +static const uint16_t easf_filter_4tap_64p_ratio_0_40_s1_12[132] = { +0x03ec, 0x0824, 0x03f0, 0x0000, +0x03d4, 0x0824, 0x0404, 0x0004, +0x03b8, 0x0820, 0x0420, 0x0008, +0x03a0, 0x081c, 0x0438, 0x000c, +0x0388, 0x0818, 0x0450, 0x0010, +0x036c, 0x0814, 0x0468, 0x0018, +0x0354, 0x0810, 0x0480, 0x001c, +0x033c, 0x080c, 0x0494, 0x0024, +0x0324, 0x0804, 0x04b0, 0x0028, +0x030c, 0x07fc, 0x04c8, 0x0030, +0x02f4, 0x07f4, 0x04e0, 0x0038, +0x02dc, 0x07ec, 0x04f8, 0x0040, +0x02c4, 0x07e4, 0x0510, 0x0048, +0x02b0, 0x07dc, 0x0524, 0x0050, +0x0298, 0x07d0, 0x0540, 0x0058, +0x0280, 0x07c8, 0x0558, 0x0060, +0x026c, 0x07bc, 0x0570, 0x0068, +0x0254, 0x07b0, 0x0588, 0x0074, +0x0240, 0x07a4, 0x05a0, 0x007c, +0x022c, 0x0798, 0x05b4, 0x0088, +0x0214, 0x078c, 0x05cc, 0x0094, +0x0200, 0x077c, 0x05e4, 0x00a0, +0x01ec, 0x0770, 0x05f8, 0x00ac, +0x01d8, 0x0760, 0x0610, 0x00b8, +0x01c4, 0x0750, 0x0628, 0x00c4, +0x01b4, 0x0744, 0x0638, 0x00d0, +0x01a0, 0x0734, 0x064c, 0x00e0, +0x018c, 0x0720, 0x0668, 0x00ec, +0x017c, 0x0710, 0x0678, 0x00fc, +0x016c, 0x0700, 0x068c, 0x0108, +0x0158, 0x06ec, 0x06a4, 0x0118, +0x0148, 0x06dc, 0x06b4, 0x0128, +0x0138, 0x06c8, 0x06c8, 0x0138, +}; + +static const uint16_t easf_filter_4tap_64p_ratio_0_50_s1_12[132] = { +0x0394, 0x08d8, 0x0394, 0x0000, +0x0378, 0x08d4, 0x03b4, 0x0000, +0x035c, 0x08d4, 0x03d0, 0x0000, +0x0340, 0x08d4, 0x03ec, 0x0000, +0x0324, 0x08d0, 0x0408, 0x0004, +0x0308, 0x08cc, 0x0428, 0x0004, +0x02f0, 0x08c8, 0x0444, 0x0004, +0x02d4, 0x08c0, 0x0464, 0x0008, +0x02b8, 0x08bc, 0x0484, 0x0008, +0x02a0, 0x08b4, 0x04a0, 0x000c, +0x0288, 0x08ac, 0x04bc, 0x0010, +0x026c, 0x08a4, 0x04dc, 0x0014, +0x0254, 0x0898, 0x04fc, 0x0018, +0x023c, 0x0890, 0x0518, 0x001c, +0x0224, 0x0884, 0x0538, 0x0020, +0x020c, 0x0878, 0x0554, 0x0028, +0x01f8, 0x086c, 0x0570, 0x002c, +0x01e0, 0x085c, 0x0590, 0x0034, +0x01c8, 0x084c, 0x05b4, 0x0038, +0x01b4, 0x0840, 0x05cc, 0x0040, +0x01a0, 0x0830, 0x05e8, 0x0048, +0x018c, 0x081c, 0x0608, 0x0050, +0x0178, 0x080c, 0x0624, 0x0058, +0x0164, 0x07f8, 0x0644, 0x0060, +0x0150, 0x07e4, 0x0660, 0x006c, +0x0140, 0x07d0, 0x067c, 0x0074, +0x012c, 0x07bc, 0x0698, 0x0080, +0x011c, 0x07a8, 0x06b0, 0x008c, +0x010c, 0x0790, 0x06cc, 0x0098, +0x00fc, 0x077c, 0x06e4, 0x00a4, +0x00ec, 0x0764, 0x0700, 0x00b0, +0x00dc, 0x074c, 0x0718, 0x00c0, +0x00cc, 0x0734, 0x0734, 0x00cc, +}; + +static const uint16_t easf_filter_4tap_64p_ratio_0_60_s1_12[132] = { +0x0320, 0x09bc, 0x0324, 0x0000, +0x0300, 0x09c0, 0x0344, 0x3ffc, +0x02e0, 0x09c0, 0x0364, 0x3ffc, +0x02c4, 0x09c0, 0x0384, 0x3ff8, +0x02a4, 0x09bc, 0x03ac, 0x3ff4, +0x0288, 0x09b8, 0x03cc, 0x3ff4, +0x0268, 0x09b4, 0x03f4, 0x3ff0, +0x024c, 0x09b0, 0x0414, 0x3ff0, +0x0230, 0x09a8, 0x043c, 0x3fec, +0x0214, 0x09a0, 0x0460, 0x3fec, +0x01f8, 0x0994, 0x0488, 0x3fec, +0x01e0, 0x098c, 0x04a8, 0x3fec, +0x01c4, 0x0980, 0x04d0, 0x3fec, +0x01ac, 0x0970, 0x04f8, 0x3fec, +0x0194, 0x0964, 0x051c, 0x3fec, +0x017c, 0x0954, 0x0544, 0x3fec, +0x0164, 0x0944, 0x0568, 0x3ff0, +0x0150, 0x0934, 0x058c, 0x3ff0, +0x0138, 0x0920, 0x05b4, 0x3ff4, +0x0124, 0x090c, 0x05d8, 0x3ff8, +0x0110, 0x08f8, 0x05fc, 0x3ffc, +0x00fc, 0x08e0, 0x0624, 0x0000, +0x00e8, 0x08c8, 0x064c, 0x0004, +0x00d8, 0x08b0, 0x0670, 0x0008, +0x00c4, 0x0898, 0x0694, 0x0010, +0x00b4, 0x087c, 0x06bc, 0x0014, +0x00a4, 0x0860, 0x06e0, 0x001c, +0x0094, 0x0844, 0x0704, 0x0024, +0x0088, 0x0828, 0x0724, 0x002c, +0x0078, 0x080c, 0x0748, 0x0034, +0x006c, 0x07ec, 0x0768, 0x0040, +0x0060, 0x07cc, 0x078c, 0x0048, +0x0054, 0x07ac, 0x07ac, 0x0054, +}; + +static const uint16_t easf_filter_4tap_64p_ratio_0_70_s1_12[132] = { +0x028c, 0x0ae4, 0x0290, 0x0000, +0x0268, 0x0ae8, 0x02b4, 0x3ffc, +0x0248, 0x0ae8, 0x02d8, 0x3ff8, +0x0224, 0x0ae8, 0x0304, 0x3ff0, +0x0204, 0x0ae4, 0x032c, 0x3fec, +0x01e4, 0x0ae0, 0x0354, 0x3fe8, +0x01c4, 0x0adc, 0x037c, 0x3fe4, +0x01a4, 0x0ad4, 0x03a8, 0x3fe0, +0x0188, 0x0acc, 0x03d0, 0x3fdc, +0x016c, 0x0ac0, 0x03fc, 0x3fd8, +0x0150, 0x0ab4, 0x042c, 0x3fd0, +0x0134, 0x0aa4, 0x045c, 0x3fcc, +0x0118, 0x0a94, 0x048c, 0x3fc8, +0x0100, 0x0a84, 0x04b4, 0x3fc8, +0x00e8, 0x0a70, 0x04e4, 0x3fc4, +0x00d0, 0x0a5c, 0x0514, 0x3fc0, +0x00bc, 0x0a48, 0x0540, 0x3fbc, +0x00a4, 0x0a30, 0x0570, 0x3fbc, +0x0090, 0x0a14, 0x05a4, 0x3fb8, +0x007c, 0x09fc, 0x05d0, 0x3fb8, +0x006c, 0x09e0, 0x05fc, 0x3fb8, +0x0058, 0x09c0, 0x0634, 0x3fb4, +0x0048, 0x09a0, 0x0664, 0x3fb4, +0x0038, 0x0980, 0x0690, 0x3fb8, +0x002c, 0x0960, 0x06bc, 0x3fb8, +0x001c, 0x093c, 0x06f0, 0x3fb8, +0x0010, 0x0918, 0x071c, 0x3fbc, +0x0004, 0x08f4, 0x074c, 0x3fbc, +0x3ff8, 0x08cc, 0x077c, 0x3fc0, +0x3ff0, 0x08a4, 0x07a8, 0x3fc4, +0x3fe8, 0x087c, 0x07d0, 0x3fcc, +0x3fe0, 0x0854, 0x07fc, 0x3fd0, +0x3fd8, 0x0828, 0x0828, 0x3fd8, +}; + +static const uint16_t easf_filter_4tap_64p_ratio_0_80_s1_12[132] = { +0x01d4, 0x0c54, 0x01d8, 0x0000, +0x01b0, 0x0c58, 0x01fc, 0x3ffc, +0x0188, 0x0c58, 0x0228, 0x3ff8, +0x0164, 0x0c54, 0x0258, 0x3ff0, +0x0140, 0x0c50, 0x0284, 0x3fec, +0x0120, 0x0c48, 0x02b4, 0x3fe4, +0x0100, 0x0c40, 0x02e0, 0x3fe0, +0x00e0, 0x0c34, 0x0314, 0x3fd8, +0x00c0, 0x0c28, 0x0344, 0x3fd4, +0x00a4, 0x0c18, 0x0378, 0x3fcc, +0x0088, 0x0c04, 0x03ac, 0x3fc8, +0x0070, 0x0bf0, 0x03e0, 0x3fc0, +0x0054, 0x0bdc, 0x0418, 0x3fb8, +0x0040, 0x0bc4, 0x0448, 0x3fb4, +0x0028, 0x0ba8, 0x0484, 0x3fac, +0x0014, 0x0b8c, 0x04bc, 0x3fa4, +0x0000, 0x0b6c, 0x04f4, 0x3fa0, +0x3fec, 0x0b4c, 0x0530, 0x3f98, +0x3fdc, 0x0b28, 0x0568, 0x3f94, +0x3fcc, 0x0b04, 0x05a4, 0x3f8c, +0x3fc0, 0x0adc, 0x05dc, 0x3f88, +0x3fb0, 0x0ab4, 0x0618, 0x3f84, +0x3fa4, 0x0a88, 0x0658, 0x3f7c, +0x3f9c, 0x0a5c, 0x0690, 0x3f78, +0x3f90, 0x0a30, 0x06cc, 0x3f74, +0x3f88, 0x0a00, 0x0708, 0x3f70, +0x3f80, 0x09d0, 0x0740, 0x3f70, +0x3f7c, 0x09a0, 0x0778, 0x3f6c, +0x3f74, 0x096c, 0x07b8, 0x3f68, +0x3f70, 0x0938, 0x07f0, 0x3f68, +0x3f6c, 0x0904, 0x0828, 0x3f68, +0x3f6c, 0x08cc, 0x0860, 0x3f68, +0x3f68, 0x0898, 0x0898, 0x3f68, +}; + +static const uint16_t easf_filter_4tap_64p_ratio_0_90_s1_12[132] = { +0x00fc, 0x0e0c, 0x00f8, 0x0000, +0x00d0, 0x0e0c, 0x0128, 0x3ffc, +0x00ac, 0x0e0c, 0x0150, 0x3ff8, +0x0084, 0x0e04, 0x0184, 0x3ff4, +0x0064, 0x0dfc, 0x01b0, 0x3ff0, +0x0040, 0x0df0, 0x01e4, 0x3fec, +0x0020, 0x0de0, 0x0218, 0x3fe8, +0x0004, 0x0dd0, 0x024c, 0x3fe0, +0x3fe8, 0x0db8, 0x0284, 0x3fdc, +0x3fcc, 0x0da0, 0x02c0, 0x3fd4, +0x3fb4, 0x0d84, 0x02fc, 0x3fcc, +0x3fa0, 0x0d68, 0x0334, 0x3fc4, +0x3f88, 0x0d48, 0x0370, 0x3fc0, +0x3f78, 0x0d24, 0x03ac, 0x3fb8, +0x3f64, 0x0cfc, 0x03f0, 0x3fb0, +0x3f54, 0x0cd4, 0x0434, 0x3fa4, +0x3f48, 0x0ca8, 0x0474, 0x3f9c, +0x3f3c, 0x0c78, 0x04b8, 0x3f94, +0x3f30, 0x0c48, 0x04fc, 0x3f8c, +0x3f28, 0x0c14, 0x0540, 0x3f84, +0x3f20, 0x0be0, 0x0588, 0x3f78, +0x3f18, 0x0ba8, 0x05d0, 0x3f70, +0x3f14, 0x0b70, 0x0614, 0x3f68, +0x3f10, 0x0b34, 0x065c, 0x3f60, +0x3f0c, 0x0af8, 0x06a8, 0x3f54, +0x3f0c, 0x0abc, 0x06ec, 0x3f4c, +0x3f0c, 0x0a7c, 0x0734, 0x3f44, +0x3f0c, 0x0a38, 0x0780, 0x3f3c, +0x3f0c, 0x09f8, 0x07c8, 0x3f34, +0x3f10, 0x09b4, 0x080c, 0x3f30, +0x3f14, 0x0970, 0x0854, 0x3f28, +0x3f18, 0x092c, 0x089c, 0x3f20, +0x3f1c, 0x08e4, 0x08e4, 0x3f1c, +}; + +static const uint16_t easf_filter_4tap_64p_ratio_1_00_s1_12[132] = { +0x0000, 0x1000, 0x0000, 0x0000, +0x3fd8, 0x0ffc, 0x002c, 0x0000, +0x3fb4, 0x0ff8, 0x0054, 0x0000, +0x3f90, 0x0fec, 0x0088, 0x3ffc, +0x3f70, 0x0fdc, 0x00b8, 0x3ffc, +0x3f54, 0x0fc8, 0x00ec, 0x3ff8, +0x3f38, 0x0fb0, 0x0120, 0x3ff8, +0x3f20, 0x0f94, 0x0158, 0x3ff4, +0x3f0c, 0x0f70, 0x0194, 0x3ff0, +0x3ef8, 0x0f4c, 0x01d4, 0x3fe8, +0x3ee4, 0x0f24, 0x0214, 0x3fe4, +0x3ed8, 0x0ef8, 0x0250, 0x3fe0, +0x3ec8, 0x0ec8, 0x0298, 0x3fd8, +0x3ec0, 0x0e94, 0x02dc, 0x3fd0, +0x3eb4, 0x0e5c, 0x0328, 0x3fc8, +0x3eac, 0x0e24, 0x0370, 0x3fc0, +0x3ea8, 0x0de4, 0x03bc, 0x3fb8, +0x3ea4, 0x0da4, 0x0408, 0x3fb0, +0x3ea4, 0x0d64, 0x0454, 0x3fa4, +0x3ea4, 0x0d20, 0x04a4, 0x3f98, +0x3ea4, 0x0cd8, 0x04f4, 0x3f90, +0x3ea4, 0x0c8c, 0x054c, 0x3f84, +0x3ea8, 0x0c40, 0x05a0, 0x3f78, +0x3eb0, 0x0bf4, 0x05f0, 0x3f6c, +0x3eb4, 0x0ba4, 0x0648, 0x3f60, +0x3ebc, 0x0b54, 0x069c, 0x3f54, +0x3ec4, 0x0b00, 0x06f4, 0x3f48, +0x3ecc, 0x0ab0, 0x0748, 0x3f3c, +0x3ed4, 0x0a58, 0x07a4, 0x3f30, +0x3ee0, 0x0a04, 0x07f8, 0x3f24, +0x3ee8, 0x09b0, 0x0850, 0x3f18, +0x3ef4, 0x0958, 0x08a8, 0x3f0c, +0x3f00, 0x0900, 0x0900, 0x3f00, +}; + +static const uint16_t easf_filter_6tap_64p_ratio_0_30_s1_12[198] = { +0x012c, 0x0400, 0x05a4, 0x0404, 0x012c, 0x0000, +0x0124, 0x03f4, 0x05a4, 0x040c, 0x0138, 0x0000, +0x011c, 0x03e8, 0x05a4, 0x0418, 0x0140, 0x0000, +0x0114, 0x03dc, 0x05a0, 0x0424, 0x0148, 0x0004, +0x010c, 0x03d4, 0x05a0, 0x042c, 0x0150, 0x0004, +0x0100, 0x03c8, 0x05a0, 0x0438, 0x015c, 0x0004, +0x00f8, 0x03bc, 0x05a0, 0x0440, 0x0164, 0x0008, +0x00f0, 0x03b0, 0x059c, 0x044c, 0x0170, 0x0008, +0x00e8, 0x03a4, 0x059c, 0x0458, 0x0178, 0x0008, +0x00e0, 0x0398, 0x0598, 0x0460, 0x0184, 0x000c, +0x00d8, 0x038c, 0x0594, 0x0470, 0x018c, 0x000c, +0x00d0, 0x0380, 0x0594, 0x0474, 0x0198, 0x0010, +0x00cc, 0x0374, 0x0590, 0x0480, 0x01a0, 0x0010, +0x00c4, 0x0368, 0x058c, 0x0488, 0x01ac, 0x0014, +0x00bc, 0x035c, 0x058c, 0x0494, 0x01b4, 0x0014, +0x00b4, 0x034c, 0x0588, 0x04a0, 0x01c0, 0x0018, +0x00ac, 0x0340, 0x0584, 0x04a8, 0x01cc, 0x001c, +0x00a8, 0x0334, 0x0580, 0x04b4, 0x01d4, 0x001c, +0x00a0, 0x0328, 0x057c, 0x04bc, 0x01e0, 0x0020, +0x0098, 0x031c, 0x0578, 0x04c4, 0x01ec, 0x0024, +0x0094, 0x0310, 0x0574, 0x04cc, 0x01f8, 0x0024, +0x008c, 0x0304, 0x0570, 0x04d8, 0x0200, 0x0028, +0x0088, 0x02f8, 0x0568, 0x04e0, 0x020c, 0x002c, +0x0080, 0x02ec, 0x0564, 0x04e8, 0x0218, 0x0030, +0x007c, 0x02e0, 0x0560, 0x04ec, 0x0224, 0x0034, +0x0078, 0x02d4, 0x0558, 0x04f8, 0x0230, 0x0034, +0x0070, 0x02c8, 0x0554, 0x0500, 0x023c, 0x0038, +0x006c, 0x02bc, 0x054c, 0x050c, 0x0244, 0x003c, +0x0064, 0x02b0, 0x0548, 0x0514, 0x0250, 0x0040, +0x0060, 0x02a4, 0x0540, 0x051c, 0x025c, 0x0044, +0x005c, 0x0298, 0x053c, 0x0520, 0x0268, 0x0048, +0x0058, 0x028c, 0x0534, 0x0524, 0x0274, 0x0050, +0x0054, 0x0280, 0x052c, 0x052c, 0x0280, 0x0054, +}; + +static const uint16_t easf_filter_6tap_64p_ratio_0_40_s1_12[198] = { +0x00a0, 0x0418, 0x068c, 0x041c, 0x00a0, 0x0000, +0x0098, 0x0408, 0x068c, 0x0428, 0x00ac, 0x0000, +0x0090, 0x03f8, 0x068c, 0x043c, 0x00b4, 0x3ffc, +0x0088, 0x03e8, 0x068c, 0x044c, 0x00bc, 0x3ffc, +0x0084, 0x03d8, 0x068c, 0x0458, 0x00c4, 0x3ffc, +0x007c, 0x03c8, 0x0688, 0x046c, 0x00d0, 0x3ff8, +0x0074, 0x03b8, 0x0688, 0x047c, 0x00d8, 0x3ff8, +0x006c, 0x03a8, 0x0684, 0x048c, 0x00e4, 0x3ff8, +0x0064, 0x0398, 0x0684, 0x049c, 0x00ec, 0x3ff8, +0x0060, 0x0388, 0x0680, 0x04a8, 0x00f8, 0x3ff8, +0x0058, 0x0378, 0x0680, 0x04b8, 0x0104, 0x3ff4, +0x0054, 0x0368, 0x067c, 0x04c8, 0x010c, 0x3ff4, +0x004c, 0x0358, 0x0678, 0x04d8, 0x0118, 0x3ff4, +0x0048, 0x0348, 0x0674, 0x04e4, 0x0124, 0x3ff4, +0x0040, 0x0338, 0x0670, 0x04f4, 0x0130, 0x3ff4, +0x003c, 0x0328, 0x0668, 0x0504, 0x013c, 0x3ff4, +0x0038, 0x0318, 0x0664, 0x0510, 0x0148, 0x3ff4, +0x0034, 0x0308, 0x065c, 0x0520, 0x0154, 0x3ff4, +0x002c, 0x02f8, 0x0658, 0x0530, 0x0160, 0x3ff4, +0x0028, 0x02e8, 0x0654, 0x053c, 0x016c, 0x3ff4, +0x0024, 0x02d8, 0x064c, 0x054c, 0x0178, 0x3ff4, +0x0020, 0x02c8, 0x0644, 0x055c, 0x0184, 0x3ff4, +0x001c, 0x02b8, 0x0640, 0x0568, 0x0190, 0x3ff4, +0x0018, 0x02a8, 0x0638, 0x0574, 0x01a0, 0x3ff4, +0x0014, 0x0298, 0x0630, 0x0584, 0x01ac, 0x3ff4, +0x0014, 0x0288, 0x0624, 0x0590, 0x01bc, 0x3ff4, +0x0010, 0x0278, 0x061c, 0x059c, 0x01c8, 0x3ff8, +0x000c, 0x0268, 0x0614, 0x05ac, 0x01d4, 0x3ff8, +0x0008, 0x0258, 0x060c, 0x05b8, 0x01e4, 0x3ff8, +0x0008, 0x024c, 0x0600, 0x05bc, 0x01f4, 0x3ffc, +0x0004, 0x023c, 0x05f8, 0x05cc, 0x0200, 0x3ffc, +0x0004, 0x022c, 0x05ec, 0x05d4, 0x0210, 0x0000, +0x0000, 0x021c, 0x05e4, 0x05e4, 0x021c, 0x0000, +}; + +static const uint16_t easf_filter_6tap_64p_ratio_0_50_s1_12[198] = { +0x0000, 0x041c, 0x07cc, 0x0418, 0x0000, 0x0000, +0x3ff8, 0x0404, 0x07cc, 0x0434, 0x0008, 0x3ffc, +0x3ff4, 0x03ec, 0x07cc, 0x044c, 0x000c, 0x3ffc, +0x3ff0, 0x03d8, 0x07cc, 0x0460, 0x0014, 0x3ff8, +0x3fe8, 0x03c0, 0x07cc, 0x0478, 0x001c, 0x3ff8, +0x3fe4, 0x03ac, 0x07c8, 0x0490, 0x0024, 0x3ff4, +0x3fe0, 0x0394, 0x07c8, 0x04a4, 0x002c, 0x3ff4, +0x3fdc, 0x0380, 0x07c4, 0x04bc, 0x0034, 0x3ff0, +0x3fd8, 0x0368, 0x07c0, 0x04d4, 0x0040, 0x3fec, +0x3fd4, 0x0350, 0x07bc, 0x04ec, 0x0048, 0x3fec, +0x3fd0, 0x033c, 0x07b8, 0x0504, 0x0050, 0x3fe8, +0x3fcc, 0x0324, 0x07b4, 0x051c, 0x005c, 0x3fe4, +0x3fc8, 0x0310, 0x07ac, 0x0530, 0x0068, 0x3fe4, +0x3fc4, 0x02fc, 0x07a8, 0x0548, 0x0070, 0x3fe0, +0x3fc4, 0x02e4, 0x07a0, 0x055c, 0x007c, 0x3fe0, +0x3fc0, 0x02d0, 0x0798, 0x0574, 0x0088, 0x3fdc, +0x3fc0, 0x02b8, 0x0790, 0x058c, 0x0094, 0x3fd8, +0x3fbc, 0x02a4, 0x0788, 0x05a0, 0x00a0, 0x3fd8, +0x3fbc, 0x0290, 0x077c, 0x05b8, 0x00ac, 0x3fd4, +0x3fbc, 0x027c, 0x0774, 0x05c8, 0x00b8, 0x3fd4, +0x3fb8, 0x0268, 0x0768, 0x05e0, 0x00c8, 0x3fd0, +0x3fb8, 0x0250, 0x0760, 0x05f8, 0x00d4, 0x3fcc, +0x3fb8, 0x023c, 0x0754, 0x0608, 0x00e4, 0x3fcc, +0x3fb8, 0x0228, 0x0748, 0x0620, 0x00f0, 0x3fc8, +0x3fb8, 0x0214, 0x073c, 0x0630, 0x0100, 0x3fc8, +0x3fb8, 0x0204, 0x072c, 0x0644, 0x0110, 0x3fc4, +0x3fb8, 0x01f0, 0x0720, 0x0658, 0x011c, 0x3fc4, +0x3fb8, 0x01dc, 0x0710, 0x0670, 0x012c, 0x3fc0, +0x3fb8, 0x01c8, 0x0704, 0x0680, 0x013c, 0x3fc0, +0x3fb8, 0x01b8, 0x06f4, 0x0690, 0x014c, 0x3fc0, +0x3fb8, 0x01a4, 0x06e4, 0x06a4, 0x0160, 0x3fbc, +0x3fb8, 0x0194, 0x06d4, 0x06b4, 0x0170, 0x3fbc, +0x3fbc, 0x0180, 0x06c4, 0x06c4, 0x0180, 0x3fbc, +}; + +static const uint16_t easf_filter_6tap_64p_ratio_0_60_s1_12[198] = { +0x3f64, 0x03ec, 0x0960, 0x03ec, 0x3f64, 0x0000, +0x3f64, 0x03cc, 0x0960, 0x0408, 0x3f68, 0x0000, +0x3f60, 0x03ac, 0x0960, 0x042c, 0x3f6c, 0x3ffc, +0x3f60, 0x038c, 0x0960, 0x0448, 0x3f70, 0x3ffc, +0x3f60, 0x0370, 0x095c, 0x046c, 0x3f70, 0x3ff8, +0x3f5c, 0x0350, 0x0958, 0x048c, 0x3f78, 0x3ff8, +0x3f5c, 0x0334, 0x0954, 0x04ac, 0x3f7c, 0x3ff4, +0x3f5c, 0x0314, 0x0950, 0x04cc, 0x3f80, 0x3ff4, +0x3f5c, 0x02f8, 0x0948, 0x04f0, 0x3f84, 0x3ff0, +0x3f5c, 0x02d8, 0x0944, 0x050c, 0x3f8c, 0x3ff0, +0x3f60, 0x02bc, 0x093c, 0x052c, 0x3f90, 0x3fec, +0x3f60, 0x02a0, 0x0930, 0x0550, 0x3f98, 0x3fe8, +0x3f60, 0x0284, 0x0928, 0x056c, 0x3fa0, 0x3fe8, +0x3f64, 0x0268, 0x091c, 0x058c, 0x3fa8, 0x3fe4, +0x3f64, 0x024c, 0x0910, 0x05b0, 0x3fb0, 0x3fe0, +0x3f64, 0x0230, 0x0904, 0x05d0, 0x3fbc, 0x3fdc, +0x3f68, 0x0214, 0x08f8, 0x05ec, 0x3fc4, 0x3fdc, +0x3f6c, 0x01fc, 0x08e8, 0x060c, 0x3fcc, 0x3fd8, +0x3f6c, 0x01e0, 0x08dc, 0x062c, 0x3fd8, 0x3fd4, +0x3f70, 0x01c8, 0x08cc, 0x0648, 0x3fe4, 0x3fd0, +0x3f74, 0x01b0, 0x08bc, 0x0664, 0x3ff0, 0x3fcc, +0x3f74, 0x0194, 0x08a8, 0x068c, 0x3ffc, 0x3fc8, +0x3f78, 0x017c, 0x0898, 0x06a8, 0x0008, 0x3fc4, +0x3f7c, 0x0168, 0x0884, 0x06c0, 0x0018, 0x3fc0, +0x3f80, 0x0150, 0x0870, 0x06dc, 0x0024, 0x3fc0, +0x3f84, 0x0138, 0x085c, 0x06f8, 0x0034, 0x3fbc, +0x3f88, 0x0120, 0x0848, 0x0718, 0x0040, 0x3fb8, +0x3f8c, 0x010c, 0x0830, 0x0734, 0x0050, 0x3fb4, +0x3f90, 0x00f8, 0x081c, 0x074c, 0x0060, 0x3fb0, +0x3f94, 0x00e4, 0x0800, 0x0768, 0x0074, 0x3fac, +0x3f98, 0x00d0, 0x07e8, 0x0784, 0x0084, 0x3fa8, +0x3f9c, 0x00bc, 0x07d4, 0x079c, 0x0094, 0x3fa4, +0x3fa0, 0x00a8, 0x07b8, 0x07b8, 0x00a8, 0x3fa0, +}; + +static const uint16_t easf_filter_6tap_64p_ratio_0_70_s1_12[198] = { +0x3f00, 0x0368, 0x0b30, 0x0368, 0x3f00, 0x0000, +0x3f04, 0x0340, 0x0b30, 0x0390, 0x3efc, 0x0000, +0x3f08, 0x0318, 0x0b2c, 0x03bc, 0x3ef8, 0x0000, +0x3f0c, 0x02f0, 0x0b28, 0x03e4, 0x3ef8, 0x0000, +0x3f10, 0x02c8, 0x0b24, 0x0410, 0x3ef4, 0x0000, +0x3f14, 0x02a0, 0x0b1c, 0x043c, 0x3ef4, 0x0000, +0x3f1c, 0x027c, 0x0b14, 0x0464, 0x3ef0, 0x0000, +0x3f20, 0x0254, 0x0b0c, 0x0490, 0x3ef0, 0x0000, +0x3f24, 0x0230, 0x0b00, 0x04bc, 0x3ef0, 0x0000, +0x3f2c, 0x020c, 0x0af4, 0x04e4, 0x3ef0, 0x0000, +0x3f30, 0x01e8, 0x0ae8, 0x0510, 0x3ef0, 0x0000, +0x3f38, 0x01c8, 0x0ad8, 0x0534, 0x3ef4, 0x0000, +0x3f40, 0x01a4, 0x0ac8, 0x0564, 0x3ef4, 0x3ffc, +0x3f44, 0x0184, 0x0ab4, 0x0590, 0x3ef8, 0x3ffc, +0x3f4c, 0x0164, 0x0aa4, 0x05b8, 0x3efc, 0x3ff8, +0x3f50, 0x0144, 0x0a90, 0x05e8, 0x3efc, 0x3ff8, +0x3f58, 0x0124, 0x0a78, 0x0610, 0x3f04, 0x3ff8, +0x3f60, 0x0108, 0x0a64, 0x0638, 0x3f08, 0x3ff4, +0x3f64, 0x00e8, 0x0a4c, 0x066c, 0x3f0c, 0x3ff0, +0x3f6c, 0x00cc, 0x0a34, 0x0690, 0x3f14, 0x3ff0, +0x3f70, 0x00b4, 0x0a18, 0x06bc, 0x3f1c, 0x3fec, +0x3f78, 0x0098, 0x0a00, 0x06e8, 0x3f20, 0x3fe8, +0x3f80, 0x007c, 0x09e4, 0x0710, 0x3f2c, 0x3fe4, +0x3f84, 0x0064, 0x09c8, 0x0738, 0x3f34, 0x3fe4, +0x3f8c, 0x004c, 0x09a8, 0x0764, 0x3f3c, 0x3fe0, +0x3f90, 0x0034, 0x098c, 0x078c, 0x3f48, 0x3fdc, +0x3f98, 0x0020, 0x096c, 0x07b0, 0x3f54, 0x3fd8, +0x3f9c, 0x0008, 0x094c, 0x07dc, 0x3f60, 0x3fd4, +0x3fa4, 0x3ff4, 0x0928, 0x0808, 0x3f6c, 0x3fcc, +0x3fa8, 0x3fe0, 0x0908, 0x082c, 0x3f7c, 0x3fc8, +0x3fb0, 0x3fcc, 0x08e4, 0x0854, 0x3f88, 0x3fc4, +0x3fb4, 0x3fbc, 0x08c0, 0x0878, 0x3f98, 0x3fc0, +0x3fbc, 0x3fac, 0x0898, 0x0898, 0x3fac, 0x3fbc, +}; + +static const uint16_t easf_filter_6tap_64p_ratio_0_80_s1_12[198] = { +0x3efc, 0x0284, 0x0d00, 0x0284, 0x3efc, 0x0000, +0x3f04, 0x0254, 0x0d00, 0x02b4, 0x3ef0, 0x0004, +0x3f10, 0x0224, 0x0cf8, 0x02e8, 0x3ee8, 0x0004, +0x3f18, 0x01f4, 0x0cf4, 0x0318, 0x3ee0, 0x0008, +0x3f24, 0x01c8, 0x0ce8, 0x034c, 0x3ed8, 0x0008, +0x3f30, 0x019c, 0x0ce0, 0x037c, 0x3ecc, 0x000c, +0x3f38, 0x0170, 0x0cd0, 0x03b8, 0x3ec4, 0x000c, +0x3f44, 0x0144, 0x0cc4, 0x03e8, 0x3ebc, 0x0010, +0x3f4c, 0x011c, 0x0cb4, 0x0420, 0x3eb4, 0x0010, +0x3f58, 0x00f4, 0x0ca0, 0x0458, 0x3eac, 0x0010, +0x3f60, 0x00cc, 0x0c8c, 0x048c, 0x3ea8, 0x0014, +0x3f6c, 0x00a8, 0x0c74, 0x04c4, 0x3ea0, 0x0014, +0x3f74, 0x0084, 0x0c5c, 0x04fc, 0x3e9c, 0x0014, +0x3f7c, 0x0060, 0x0c44, 0x0534, 0x3e94, 0x0018, +0x3f88, 0x0040, 0x0c28, 0x0568, 0x3e90, 0x0018, +0x3f90, 0x0020, 0x0c08, 0x05a4, 0x3e8c, 0x0018, +0x3f98, 0x0000, 0x0bec, 0x05dc, 0x3e88, 0x0018, +0x3fa0, 0x3fe4, 0x0bcc, 0x0614, 0x3e84, 0x0018, +0x3fac, 0x3fc4, 0x0ba8, 0x064c, 0x3e84, 0x0018, +0x3fb4, 0x3fac, 0x0b84, 0x0684, 0x3e80, 0x0018, +0x3fb8, 0x3f90, 0x0b60, 0x06c0, 0x3e80, 0x0018, +0x3fc0, 0x3f78, 0x0b38, 0x06f8, 0x3e80, 0x0018, +0x3fc8, 0x3f60, 0x0b14, 0x072c, 0x3e80, 0x0018, +0x3fd0, 0x3f4c, 0x0ae8, 0x0760, 0x3e84, 0x0018, +0x3fd8, 0x3f34, 0x0ac0, 0x079c, 0x3e84, 0x0014, +0x3fdc, 0x3f20, 0x0a94, 0x07d4, 0x3e88, 0x0014, +0x3fe4, 0x3f10, 0x0a68, 0x0808, 0x3e8c, 0x0010, +0x3fe8, 0x3f00, 0x0a38, 0x0840, 0x3e90, 0x0010, +0x3fec, 0x3ef0, 0x0a0c, 0x0874, 0x3e98, 0x000c, +0x3ff4, 0x3ee0, 0x09d8, 0x08a8, 0x3ea0, 0x000c, +0x3ff8, 0x3ed0, 0x09ac, 0x08dc, 0x3ea8, 0x0008, +0x3ffc, 0x3ec4, 0x0978, 0x0914, 0x3eb0, 0x0004, +0x0000, 0x3eb8, 0x0948, 0x0948, 0x3eb8, 0x0000, +}; + +static const uint16_t easf_filter_6tap_64p_ratio_0_90_s1_12[198] = { +0x3f60, 0x0154, 0x0e9c, 0x0150, 0x3f60, 0x0000, +0x3f6c, 0x011c, 0x0e9c, 0x018c, 0x3f50, 0x0000, +0x3f7c, 0x00ec, 0x0e94, 0x01bc, 0x3f44, 0x0004, +0x3f88, 0x00b8, 0x0e8c, 0x01f8, 0x3f34, 0x0008, +0x3f94, 0x0088, 0x0e80, 0x0234, 0x3f28, 0x0008, +0x3fa0, 0x005c, 0x0e74, 0x026c, 0x3f18, 0x000c, +0x3fac, 0x0030, 0x0e60, 0x02b0, 0x3f08, 0x000c, +0x3fb8, 0x0004, 0x0e50, 0x02e8, 0x3efc, 0x0010, +0x3fc4, 0x3fdc, 0x0e38, 0x0328, 0x3eec, 0x0014, +0x3fd0, 0x3fb4, 0x0e20, 0x0368, 0x3ee0, 0x0014, +0x3fd8, 0x3f90, 0x0e04, 0x03ac, 0x3ed0, 0x0018, +0x3fe4, 0x3f6c, 0x0de8, 0x03e8, 0x3ec4, 0x001c, +0x3fec, 0x3f4c, 0x0dc8, 0x042c, 0x3eb4, 0x0020, +0x3ff4, 0x3f2c, 0x0da4, 0x0474, 0x3ea8, 0x0020, +0x0000, 0x3f0c, 0x0d80, 0x04b8, 0x3e98, 0x0024, +0x0008, 0x3ef0, 0x0d58, 0x04fc, 0x3e8c, 0x0028, +0x000c, 0x3ed8, 0x0d30, 0x0540, 0x3e80, 0x002c, +0x0014, 0x3ec0, 0x0d04, 0x0588, 0x3e74, 0x002c, +0x001c, 0x3ea8, 0x0cd8, 0x05cc, 0x3e68, 0x0030, +0x0020, 0x3e94, 0x0ca8, 0x0614, 0x3e5c, 0x0034, +0x0028, 0x3e80, 0x0c78, 0x065c, 0x3e50, 0x0034, +0x002c, 0x3e6c, 0x0c44, 0x06a4, 0x3e48, 0x0038, +0x0030, 0x3e5c, 0x0c0c, 0x06f0, 0x3e3c, 0x003c, +0x0034, 0x3e50, 0x0bd8, 0x0734, 0x3e34, 0x003c, +0x0038, 0x3e44, 0x0ba0, 0x0778, 0x3e2c, 0x0040, +0x003c, 0x3e38, 0x0b64, 0x07c4, 0x3e24, 0x0040, +0x0040, 0x3e2c, 0x0b28, 0x0808, 0x3e20, 0x0044, +0x0040, 0x3e24, 0x0aec, 0x0850, 0x3e1c, 0x0044, +0x0044, 0x3e1c, 0x0aac, 0x0898, 0x3e18, 0x0044, +0x0044, 0x3e18, 0x0a70, 0x08d8, 0x3e14, 0x0048, +0x0044, 0x3e14, 0x0a2c, 0x0924, 0x3e10, 0x0048, +0x0048, 0x3e10, 0x09ec, 0x0964, 0x3e10, 0x0048, +0x0048, 0x3e10, 0x09a8, 0x09a8, 0x3e10, 0x0048, +}; + +static const uint16_t easf_filter_6tap_64p_ratio_1_00_s1_12[198] = { +0x0000, 0x0000, 0x1000, 0x0000, 0x0000, 0x0000, +0x000c, 0x3fcc, 0x1000, 0x0034, 0x3ff4, 0x0000, +0x0018, 0x3f9c, 0x0ff8, 0x0070, 0x3fe4, 0x0000, +0x0024, 0x3f6c, 0x0ff0, 0x00ac, 0x3fd4, 0x0000, +0x0030, 0x3f40, 0x0fe4, 0x00e8, 0x3fc4, 0x0000, +0x0038, 0x3f14, 0x0fd4, 0x0128, 0x3fb4, 0x0004, +0x0044, 0x3eec, 0x0fc0, 0x0168, 0x3fa4, 0x0004, +0x004c, 0x3ec8, 0x0fac, 0x01a8, 0x3f94, 0x0004, +0x0054, 0x3ea4, 0x0f90, 0x01ec, 0x3f84, 0x0008, +0x005c, 0x3e84, 0x0f74, 0x0234, 0x3f70, 0x0008, +0x0060, 0x3e64, 0x0f50, 0x0280, 0x3f60, 0x000c, +0x0068, 0x3e48, 0x0f2c, 0x02c8, 0x3f4c, 0x0010, +0x006c, 0x3e30, 0x0f04, 0x0318, 0x3f38, 0x0010, +0x0070, 0x3e18, 0x0edc, 0x0364, 0x3f24, 0x0014, +0x0074, 0x3e00, 0x0eac, 0x03b8, 0x3f10, 0x0018, +0x0078, 0x3df0, 0x0e7c, 0x0404, 0x3efc, 0x001c, +0x007c, 0x3de0, 0x0e48, 0x0454, 0x3ee8, 0x0020, +0x007c, 0x3dd0, 0x0e14, 0x04ac, 0x3ed4, 0x0020, +0x0080, 0x3dc4, 0x0dd8, 0x0500, 0x3ec0, 0x0024, +0x0080, 0x3db8, 0x0d9c, 0x0554, 0x3eac, 0x002c, +0x0080, 0x3db0, 0x0d5c, 0x05ac, 0x3e98, 0x0030, +0x0080, 0x3da8, 0x0d1c, 0x0600, 0x3e88, 0x0034, +0x0080, 0x3da4, 0x0cd8, 0x0658, 0x3e74, 0x0038, +0x0080, 0x3da4, 0x0c94, 0x06ac, 0x3e60, 0x003c, +0x007c, 0x3da0, 0x0c4c, 0x070c, 0x3e4c, 0x0040, +0x007c, 0x3da4, 0x0c00, 0x0760, 0x3e3c, 0x0044, +0x0078, 0x3da4, 0x0bb4, 0x07bc, 0x3e2c, 0x0048, +0x0074, 0x3da8, 0x0b64, 0x0814, 0x3e1c, 0x0050, +0x0074, 0x3db0, 0x0b14, 0x0868, 0x3e0c, 0x0054, +0x0070, 0x3db8, 0x0ac4, 0x08c0, 0x3dfc, 0x0058, +0x006c, 0x3dc0, 0x0a70, 0x091c, 0x3dec, 0x005c, +0x0068, 0x3dc8, 0x0a1c, 0x0974, 0x3de0, 0x0060, +0x0064, 0x3dd4, 0x09c8, 0x09c8, 0x3dd4, 0x0064, +}; + +static struct scale_ratio_to_reg_value_lookup easf_v_bf3_mode_lookup[] = { + {3, 10, 0x0000}, + {4, 10, 0x0000}, + {5, 10, 0x0000}, + {6, 10, 0x0000}, + {7, 10, 0x0000}, + {8, 10, 0x0000}, + {9, 10, 0x0000}, + {1, 1, 0x0000}, + {-1, -1, 0x0002}, +}; + +static struct scale_ratio_to_reg_value_lookup easf_h_bf3_mode_lookup[] = { + {3, 10, 0x0000}, + {4, 10, 0x0000}, + {5, 10, 0x0000}, + {6, 10, 0x0000}, + {7, 10, 0x0000}, + {8, 10, 0x0000}, + {9, 10, 0x0000}, + {1, 1, 0x0000}, + {-1, -1, 0x0002}, +}; + +static struct scale_ratio_to_reg_value_lookup easf_reducer_gain6_6tap_lookup[] = { + {3, 10, 0x4100}, + {4, 10, 0x4100}, + {5, 10, 0x4100}, + {6, 10, 0x4100}, + {7, 10, 0x4100}, + {8, 10, 0x4100}, + {9, 10, 0x4100}, + {1, 1, 0x4100}, + {-1, -1, 0x4100}, +}; + +static struct scale_ratio_to_reg_value_lookup easf_reducer_gain4_6tap_lookup[] = { + {3, 10, 0x4000}, + {4, 10, 0x4000}, + {5, 10, 0x4000}, + {6, 10, 0x4000}, + {7, 10, 0x4000}, + {8, 10, 0x4000}, + {9, 10, 0x4000}, + {1, 1, 0x4000}, + {-1, -1, 0x4000}, +}; + +static struct scale_ratio_to_reg_value_lookup easf_gain_ring6_6tap_lookup[] = { + {3, 10, 0x0000}, + {4, 10, 0x251F}, + {5, 10, 0x291F}, + {6, 10, 0xA51F}, + {7, 10, 0xA51F}, + {8, 10, 0xAA66}, + {9, 10, 0xA51F}, + {1, 1, 0xA640}, + {-1, -1, 0xA640}, +}; + +static struct scale_ratio_to_reg_value_lookup easf_gain_ring4_6tap_lookup[] = { + {3, 10, 0x0000}, + {4, 10, 0x9600}, + {5, 10, 0xA460}, + {6, 10, 0xA8E0}, + {7, 10, 0xAC00}, + {8, 10, 0xAD20}, + {9, 10, 0xAFC0}, + {1, 1, 0xB058}, + {-1, -1, 0xB058}, +}; + +static struct scale_ratio_to_reg_value_lookup easf_reducer_gain6_4tap_lookup[] = { + {3, 10, 0x4100}, + {4, 10, 0x4100}, + {5, 10, 0x4100}, + {6, 10, 0x4100}, + {7, 10, 0x4100}, + {8, 10, 0x4100}, + {9, 10, 0x4100}, + {1, 1, 0x4100}, + {-1, -1, 0x4100}, +}; + +static struct scale_ratio_to_reg_value_lookup easf_reducer_gain4_4tap_lookup[] = { + {3, 10, 0x4000}, + {4, 10, 0x4000}, + {5, 10, 0x4000}, + {6, 10, 0x4000}, + {7, 10, 0x4000}, + {8, 10, 0x4000}, + {9, 10, 0x4000}, + {1, 1, 0x4000}, + {-1, -1, 0x4000}, +}; + +static struct scale_ratio_to_reg_value_lookup easf_gain_ring6_4tap_lookup[] = { + {3, 10, 0x0000}, + {4, 10, 0x0000}, + {5, 10, 0x0000}, + {6, 10, 0x0000}, + {7, 10, 0x0000}, + {8, 10, 0x0000}, + {9, 10, 0x0000}, + {1, 1, 0x0000}, + {-1, -1, 0x0000}, +}; + +static struct scale_ratio_to_reg_value_lookup easf_gain_ring4_4tap_lookup[] = { + {3, 10, 0x0000}, + {4, 10, 0x0000}, + {5, 10, 0x0000}, + {6, 10, 0x9900}, + {7, 10, 0xA100}, + {8, 10, 0xA8C0}, + {9, 10, 0xAB20}, + {1, 1, 0xAC00}, + {-1, -1, 0xAC00}, +}; + +static struct scale_ratio_to_reg_value_lookup easf_3tap_dntilt_uptilt_offset_lookup[] = { + {3, 10, 0x0000}, + {4, 10, 0x0000}, + {5, 10, 0x0000}, + {6, 10, 0x0000}, + {7, 10, 0x0000}, + {8, 10, 0x4100}, + {9, 10, 0x9F00}, + {1, 1, 0xA4C0}, + {-1, -1, 0xA8D8}, +}; + +static struct scale_ratio_to_reg_value_lookup easf_3tap_uptilt_maxval_lookup[] = { + {3, 10, 0x0000}, + {4, 10, 0x0000}, + {5, 10, 0x0000}, + {6, 10, 0x0000}, + {7, 10, 0x0000}, + {8, 10, 0x4000}, + {9, 10, 0x24FE}, + {1, 1, 0x2D64}, + {-1, -1, 0x3ADB}, +}; + +static struct scale_ratio_to_reg_value_lookup easf_3tap_dntilt_slope_lookup[] = { + {3, 10, 0x3800}, + {4, 10, 0x3800}, + {5, 10, 0x3800}, + {6, 10, 0x3800}, + {7, 10, 0x3800}, + {8, 10, 0x3886}, + {9, 10, 0x3940}, + {1, 1, 0x3A4E}, + {-1, -1, 0x3B66}, +}; + +static struct scale_ratio_to_reg_value_lookup easf_3tap_uptilt1_slope_lookup[] = { + {3, 10, 0x3800}, + {4, 10, 0x3800}, + {5, 10, 0x3800}, + {6, 10, 0x3800}, + {7, 10, 0x3800}, + {8, 10, 0x36F4}, + {9, 10, 0x359C}, + {1, 1, 0x3360}, + {-1, -1, 0x2F20}, +}; + +static struct scale_ratio_to_reg_value_lookup easf_3tap_uptilt2_slope_lookup[] = { + {3, 10, 0x0000}, + {4, 10, 0x0000}, + {5, 10, 0x0000}, + {6, 10, 0x0000}, + {7, 10, 0x0000}, + {8, 10, 0x0000}, + {9, 10, 0x359C}, + {1, 1, 0x31F0}, + {-1, -1, 0x1F00}, +}; + +static struct scale_ratio_to_reg_value_lookup easf_3tap_uptilt2_offset_lookup[] = { + {3, 10, 0x0000}, + {4, 10, 0x0000}, + {5, 10, 0x0000}, + {6, 10, 0x0000}, + {7, 10, 0x0000}, + {8, 10, 0x0000}, + {9, 10, 0x9F00}, + {1, 1, 0xA400}, + {-1, -1, 0x9E00}, +}; + +static const uint16_t *spl_get_easf_filter_3tap_64p(struct spl_fixed31_32 ratio) +{ + if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(3, 10)).value) + return easf_filter_3tap_64p_ratio_0_30_s1_12; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 10)).value) + return easf_filter_3tap_64p_ratio_0_40_s1_12; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 10)).value) + return easf_filter_3tap_64p_ratio_0_50_s1_12; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(6, 10)).value) + return easf_filter_3tap_64p_ratio_0_60_s1_12; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(7, 10)).value) + return easf_filter_3tap_64p_ratio_0_70_s1_12; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(8, 10)).value) + return easf_filter_3tap_64p_ratio_0_80_s1_12; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(9, 10)).value) + return easf_filter_3tap_64p_ratio_0_90_s1_12; + else + return easf_filter_3tap_64p_ratio_1_00_s1_12; +} + +static const uint16_t *spl_get_easf_filter_4tap_64p(struct spl_fixed31_32 ratio) +{ + if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(3, 10)).value) + return easf_filter_4tap_64p_ratio_0_30_s1_12; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 10)).value) + return easf_filter_4tap_64p_ratio_0_40_s1_12; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 10)).value) + return easf_filter_4tap_64p_ratio_0_50_s1_12; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(6, 10)).value) + return easf_filter_4tap_64p_ratio_0_60_s1_12; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(7, 10)).value) + return easf_filter_4tap_64p_ratio_0_70_s1_12; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(8, 10)).value) + return easf_filter_4tap_64p_ratio_0_80_s1_12; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(9, 10)).value) + return easf_filter_4tap_64p_ratio_0_90_s1_12; + else + return easf_filter_4tap_64p_ratio_1_00_s1_12; +} + +static const uint16_t *spl_get_easf_filter_6tap_64p(struct spl_fixed31_32 ratio) +{ + if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(3, 10)).value) + return easf_filter_6tap_64p_ratio_0_30_s1_12; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 10)).value) + return easf_filter_6tap_64p_ratio_0_40_s1_12; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 10)).value) + return easf_filter_6tap_64p_ratio_0_50_s1_12; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(6, 10)).value) + return easf_filter_6tap_64p_ratio_0_60_s1_12; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(7, 10)).value) + return easf_filter_6tap_64p_ratio_0_70_s1_12; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(8, 10)).value) + return easf_filter_6tap_64p_ratio_0_80_s1_12; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(9, 10)).value) + return easf_filter_6tap_64p_ratio_0_90_s1_12; + else + return easf_filter_6tap_64p_ratio_1_00_s1_12; +} + +const uint16_t *SPL_NAMESPACE(spl_dscl_get_easf_filter_coeffs_64p( + int taps, struct spl_fixed31_32 ratio)) +{ + if (taps == 6) + return spl_get_easf_filter_6tap_64p(ratio); + else if (taps == 4) + return spl_get_easf_filter_4tap_64p(ratio); + else if (taps == 3) + return spl_get_easf_filter_3tap_64p(ratio); + else { + /* should never happen, bug */ + SPL_BREAK_TO_DEBUGGER(); + return NULL; + } +} + +static const uint16_t *spl_get_easf_filter_3tap_64p_s1_10(struct spl_fixed31_32 ratio) +{ + if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(3, 10)).value) + return easf_filter_3tap_64p_ratio_0_30; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 10)).value) + return easf_filter_3tap_64p_ratio_0_40; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 10)).value) + return easf_filter_3tap_64p_ratio_0_50; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(6, 10)).value) + return easf_filter_3tap_64p_ratio_0_60; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(7, 10)).value) + return easf_filter_3tap_64p_ratio_0_70; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(8, 10)).value) + return easf_filter_3tap_64p_ratio_0_80; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(9, 10)).value) + return easf_filter_3tap_64p_ratio_0_90; + else + return easf_filter_3tap_64p_ratio_1_00; +} + +static const uint16_t *spl_get_easf_filter_4tap_64p_s1_10(struct spl_fixed31_32 ratio) +{ + if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(3, 10)).value) + return easf_filter_4tap_64p_ratio_0_30; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 10)).value) + return easf_filter_4tap_64p_ratio_0_40; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 10)).value) + return easf_filter_4tap_64p_ratio_0_50; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(6, 10)).value) + return easf_filter_4tap_64p_ratio_0_60; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(7, 10)).value) + return easf_filter_4tap_64p_ratio_0_70; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(8, 10)).value) + return easf_filter_4tap_64p_ratio_0_80; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(9, 10)).value) + return easf_filter_4tap_64p_ratio_0_90; + else + return easf_filter_4tap_64p_ratio_1_00; +} + +static const uint16_t *spl_get_easf_filter_6tap_64p_s1_10(struct spl_fixed31_32 ratio) +{ + if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(3, 10)).value) + return easf_filter_6tap_64p_ratio_0_30; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 10)).value) + return easf_filter_6tap_64p_ratio_0_40; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 10)).value) + return easf_filter_6tap_64p_ratio_0_50; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(6, 10)).value) + return easf_filter_6tap_64p_ratio_0_60; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(7, 10)).value) + return easf_filter_6tap_64p_ratio_0_70; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(8, 10)).value) + return easf_filter_6tap_64p_ratio_0_80; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(9, 10)).value) + return easf_filter_6tap_64p_ratio_0_90; + else + return easf_filter_6tap_64p_ratio_1_00; +} + +const uint16_t *SPL_NAMESPACE(spl_dscl_get_easf_filter_coeffs_64p_s1_10( + int taps, struct spl_fixed31_32 ratio)) +{ + if (taps == 6) + return spl_get_easf_filter_6tap_64p_s1_10(ratio); + else if (taps == 4) + return spl_get_easf_filter_4tap_64p_s1_10(ratio); + else if (taps == 3) + return spl_get_easf_filter_3tap_64p_s1_10(ratio); + else { + /* should never happen, bug */ + SPL_BREAK_TO_DEBUGGER(); + return NULL; + } +} + +void SPL_NAMESPACE(spl_set_filters_data(struct dscl_prog_data *dscl_prog_data, + const struct spl_scaler_data *data, bool enable_easf_v, + bool enable_easf_h)) +{ + /* + * Old coefficients calculated scaling ratio = input / output + * New coefficients are calculated based on = output / input + */ + if (enable_easf_h) { + dscl_prog_data->filter_h = SPL_NAMESPACE(spl_dscl_get_easf_filter_coeffs_64p( + data->taps.h_taps, data->recip_ratios.horz)); + + dscl_prog_data->filter_h_c = SPL_NAMESPACE(spl_dscl_get_easf_filter_coeffs_64p( + data->taps.h_taps_c, data->recip_ratios.horz_c)); + } else { + dscl_prog_data->filter_h = SPL_NAMESPACE(spl_dscl_get_filter_coeffs_64p( + data->taps.h_taps, data->ratios.horz)); + + dscl_prog_data->filter_h_c = SPL_NAMESPACE(spl_dscl_get_filter_coeffs_64p( + data->taps.h_taps_c, data->ratios.horz_c)); + } + if (enable_easf_v) { + dscl_prog_data->filter_v = SPL_NAMESPACE(spl_dscl_get_easf_filter_coeffs_64p( + data->taps.v_taps, data->recip_ratios.vert)); + + dscl_prog_data->filter_v_c = SPL_NAMESPACE(spl_dscl_get_easf_filter_coeffs_64p( + data->taps.v_taps_c, data->recip_ratios.vert_c)); + } else { + dscl_prog_data->filter_v = SPL_NAMESPACE(spl_dscl_get_filter_coeffs_64p( + data->taps.v_taps, data->ratios.vert)); + + dscl_prog_data->filter_v_c = SPL_NAMESPACE(spl_dscl_get_filter_coeffs_64p( + data->taps.v_taps_c, data->ratios.vert_c)); + } +} + +static uint32_t spl_easf_get_scale_ratio_to_reg_value(struct spl_fixed31_32 ratio, + struct scale_ratio_to_reg_value_lookup *lookup_table_base_ptr, + unsigned int num_entries) +{ + unsigned int count = 0; + uint32_t value = 0; + struct scale_ratio_to_reg_value_lookup *lookup_table_index_ptr; + + lookup_table_index_ptr = (lookup_table_base_ptr + num_entries - 1); + value = lookup_table_index_ptr->reg_value; + + while (count < num_entries) { + + lookup_table_index_ptr = (lookup_table_base_ptr + count); + if (lookup_table_index_ptr->numer < 0) + break; + + if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction( + lookup_table_index_ptr->numer, + lookup_table_index_ptr->denom)).value) { + value = lookup_table_index_ptr->reg_value; + break; + } + + count++; + } + return value; +} +uint32_t SPL_NAMESPACE(spl_get_v_bf3_mode(struct spl_fixed31_32 ratio)) +{ + uint32_t value; + unsigned int num_entries = sizeof(easf_v_bf3_mode_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_v_bf3_mode_lookup, num_entries); + return value; +} +uint32_t SPL_NAMESPACE(spl_get_h_bf3_mode(struct spl_fixed31_32 ratio)) +{ + uint32_t value; + unsigned int num_entries = sizeof(easf_h_bf3_mode_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_h_bf3_mode_lookup, num_entries); + return value; +} +uint32_t SPL_NAMESPACE(spl_get_reducer_gain6(int taps, struct spl_fixed31_32 ratio)) +{ + uint32_t value; + unsigned int num_entries; + + if (taps == 4) { + num_entries = sizeof(easf_reducer_gain6_4tap_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_reducer_gain6_4tap_lookup, num_entries); + } else if (taps == 6) { + num_entries = sizeof(easf_reducer_gain6_6tap_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_reducer_gain6_6tap_lookup, num_entries); + } else + value = 0; + return value; +} +uint32_t SPL_NAMESPACE(spl_get_reducer_gain4(int taps, struct spl_fixed31_32 ratio)) +{ + uint32_t value; + unsigned int num_entries; + + if (taps == 4) { + num_entries = sizeof(easf_reducer_gain4_4tap_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_reducer_gain4_4tap_lookup, num_entries); + } else if (taps == 6) { + num_entries = sizeof(easf_reducer_gain4_6tap_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_reducer_gain4_6tap_lookup, num_entries); + } else + value = 0; + return value; +} +uint32_t SPL_NAMESPACE(spl_get_gainRing6(int taps, struct spl_fixed31_32 ratio)) +{ + uint32_t value; + unsigned int num_entries; + + if (taps == 4) { + num_entries = sizeof(easf_gain_ring6_4tap_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_gain_ring6_4tap_lookup, num_entries); + } else if (taps == 6) { + num_entries = sizeof(easf_gain_ring6_6tap_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_gain_ring6_6tap_lookup, num_entries); + } else + value = 0; + return value; +} +uint32_t SPL_NAMESPACE(spl_get_gainRing4(int taps, struct spl_fixed31_32 ratio)) +{ + uint32_t value; + unsigned int num_entries; + + if (taps == 4) { + num_entries = sizeof(easf_gain_ring4_4tap_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_gain_ring4_4tap_lookup, num_entries); + } else if (taps == 6) { + num_entries = sizeof(easf_gain_ring4_6tap_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_gain_ring4_6tap_lookup, num_entries); + } else + value = 0; + return value; +} +uint32_t SPL_NAMESPACE(spl_get_3tap_dntilt_uptilt_offset( + int taps, struct spl_fixed31_32 ratio)) +{ + uint32_t value; + unsigned int num_entries; + + if (taps == 3) { + num_entries = sizeof(easf_3tap_dntilt_uptilt_offset_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_3tap_dntilt_uptilt_offset_lookup, num_entries); + } else + value = 0; + return value; +} +uint32_t SPL_NAMESPACE(spl_get_3tap_uptilt_maxval(int taps, struct spl_fixed31_32 ratio)) +{ + uint32_t value; + unsigned int num_entries; + + if (taps == 3) { + num_entries = sizeof(easf_3tap_uptilt_maxval_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_3tap_uptilt_maxval_lookup, num_entries); + } else + value = 0; + return value; +} +uint32_t SPL_NAMESPACE(spl_get_3tap_dntilt_slope(int taps, struct spl_fixed31_32 ratio)) +{ + uint32_t value; + unsigned int num_entries; + + if (taps == 3) { + num_entries = sizeof(easf_3tap_dntilt_slope_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_3tap_dntilt_slope_lookup, num_entries); + } else + value = 0; + return value; +} +uint32_t SPL_NAMESPACE(spl_get_3tap_uptilt1_slope(int taps, struct spl_fixed31_32 ratio)) +{ + uint32_t value; + unsigned int num_entries; + + if (taps == 3) { + num_entries = sizeof(easf_3tap_uptilt1_slope_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_3tap_uptilt1_slope_lookup, num_entries); + } else + value = 0; + return value; +} +uint32_t SPL_NAMESPACE(spl_get_3tap_uptilt2_slope(int taps, struct spl_fixed31_32 ratio)) +{ + uint32_t value; + unsigned int num_entries; + + if (taps == 3) { + num_entries = sizeof(easf_3tap_uptilt2_slope_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_3tap_uptilt2_slope_lookup, num_entries); + } else + value = 0; + return value; +} +uint32_t SPL_NAMESPACE(spl_get_3tap_uptilt2_offset(int taps, struct spl_fixed31_32 ratio)) +{ + uint32_t value; + unsigned int num_entries; + + if (taps == 3) { + num_entries = sizeof(easf_3tap_uptilt2_offset_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_3tap_uptilt2_offset_lookup, num_entries); + } else + value = 0; + return value; +} diff --git a/src/amd/vpelib/src/imported/SPL/dc_spl_scl_easf_filters.h b/src/amd/vpelib/src/imported/SPL/dc_spl_scl_easf_filters.h new file mode 100644 index 00000000000..ba1cdb8be41 --- /dev/null +++ b/src/amd/vpelib/src/imported/SPL/dc_spl_scl_easf_filters.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: MIT */ + +/* Copyright 2024 Advanced Micro Devices, Inc. */ + +#ifndef __DC_SPL_SCL_EASF_FILTERS_H__ +#define __DC_SPL_SCL_EASF_FILTERS_H__ + +#include "dc_spl_types.h" + +struct scale_ratio_to_reg_value_lookup { + int numer; + int denom; + const uint32_t reg_value; +}; + +void SPL_NAMESPACE(spl_set_filters_data(struct dscl_prog_data *dscl_prog_data, + const struct spl_scaler_data *data, bool enable_easf_v, + bool enable_easf_h)); + +uint32_t SPL_NAMESPACE(spl_get_v_bf3_mode(struct spl_fixed31_32 ratio)); +uint32_t SPL_NAMESPACE(spl_get_h_bf3_mode(struct spl_fixed31_32 ratio)); +uint32_t SPL_NAMESPACE(spl_get_reducer_gain6(int taps, struct spl_fixed31_32 ratio)); +uint32_t SPL_NAMESPACE(spl_get_reducer_gain4(int taps, struct spl_fixed31_32 ratio)); +uint32_t SPL_NAMESPACE(spl_get_gainRing6(int taps, struct spl_fixed31_32 ratio)); +uint32_t SPL_NAMESPACE(spl_get_gainRing4(int taps, struct spl_fixed31_32 ratio)); +uint32_t SPL_NAMESPACE(spl_get_3tap_dntilt_uptilt_offset( + int taps, struct spl_fixed31_32 ratio)); +uint32_t SPL_NAMESPACE(spl_get_3tap_uptilt_maxval(int taps, struct spl_fixed31_32 ratio)); +uint32_t SPL_NAMESPACE(spl_get_3tap_dntilt_slope(int taps, struct spl_fixed31_32 ratio)); +uint32_t SPL_NAMESPACE(spl_get_3tap_uptilt1_slope(int taps, struct spl_fixed31_32 ratio)); +uint32_t SPL_NAMESPACE(spl_get_3tap_uptilt2_slope(int taps, struct spl_fixed31_32 ratio)); +uint32_t SPL_NAMESPACE(spl_get_3tap_uptilt2_offset(int taps, struct spl_fixed31_32 ratio)); + +/* public API */ +const uint16_t *SPL_NAMESPACE(spl_dscl_get_easf_filter_coeffs_64p( + int taps, struct spl_fixed31_32 ratio)); +const uint16_t *SPL_NAMESPACE(spl_dscl_get_easf_filter_coeffs_64p_s1_10( + int taps, struct spl_fixed31_32 ratio)); + +#endif /* __DC_SPL_SCL_EASF_FILTERS_H__ */ diff --git a/src/amd/vpelib/src/imported/SPL/dc_spl_scl_filters.c b/src/amd/vpelib/src/imported/SPL/dc_spl_scl_filters.c new file mode 100644 index 00000000000..2d73d0dce5f --- /dev/null +++ b/src/amd/vpelib/src/imported/SPL/dc_spl_scl_filters.c @@ -0,0 +1,1234 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2024 Advanced Micro Devices, Inc. + +#include "spl_debug.h" +#include "dc_spl_scl_filters.h" + +//========================================= +// = 2 +// = 64 +// = 0.833333 (input/output) +// = 0 +// = ModifiedLanczos +// = s1.10 +// = s1.12 +//========================================= +static const uint16_t filter_2tap_64p[66] = { + 0x1000, 0x0000, + 0x1000, 0x0000, + 0x0FFC, 0x0004, + 0x0FF8, 0x0008, + 0x0FF0, 0x0010, + 0x0FE4, 0x001C, + 0x0FD8, 0x0028, + 0x0FC4, 0x003C, + 0x0FB0, 0x0050, + 0x0F98, 0x0068, + 0x0F7C, 0x0084, + 0x0F58, 0x00A8, + 0x0F34, 0x00CC, + 0x0F08, 0x00F8, + 0x0ED8, 0x0128, + 0x0EA4, 0x015C, + 0x0E68, 0x0198, + 0x0E28, 0x01D8, + 0x0DE4, 0x021C, + 0x0D98, 0x0268, + 0x0D44, 0x02BC, + 0x0CEC, 0x0314, + 0x0C90, 0x0370, + 0x0C2C, 0x03D4, + 0x0BC4, 0x043C, + 0x0B58, 0x04A8, + 0x0AE8, 0x0518, + 0x0A74, 0x058C, + 0x09FC, 0x0604, + 0x0980, 0x0680, + 0x0900, 0x0700, + 0x0880, 0x0780, + 0x0800, 0x0800 +}; + +//========================================= +// = 3 +// = 64 +// = 0.83333 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_3tap_64p_upscale[99] = { + 0x0804, 0x07FC, 0x0000, + 0x07A8, 0x0860, 0x3FF8, + 0x0754, 0x08BC, 0x3FF0, + 0x0700, 0x0918, 0x3FE8, + 0x06AC, 0x0978, 0x3FDC, + 0x0654, 0x09D8, 0x3FD4, + 0x0604, 0x0A34, 0x3FC8, + 0x05B0, 0x0A90, 0x3FC0, + 0x055C, 0x0AF0, 0x3FB4, + 0x050C, 0x0B48, 0x3FAC, + 0x04BC, 0x0BA0, 0x3FA4, + 0x0470, 0x0BF4, 0x3F9C, + 0x0420, 0x0C50, 0x3F90, + 0x03D8, 0x0C9C, 0x3F8C, + 0x038C, 0x0CF0, 0x3F84, + 0x0344, 0x0D40, 0x3F7C, + 0x0300, 0x0D88, 0x3F78, + 0x02BC, 0x0DD0, 0x3F74, + 0x027C, 0x0E14, 0x3F70, + 0x023C, 0x0E54, 0x3F70, + 0x0200, 0x0E90, 0x3F70, + 0x01C8, 0x0EC8, 0x3F70, + 0x0190, 0x0EFC, 0x3F74, + 0x015C, 0x0F2C, 0x3F78, + 0x0128, 0x0F5C, 0x3F7C, + 0x00FC, 0x0F7C, 0x3F88, + 0x00CC, 0x0FA4, 0x3F90, + 0x00A4, 0x0FC0, 0x3F9C, + 0x007C, 0x0FD8, 0x3FAC, + 0x0058, 0x0FE8, 0x3FC0, + 0x0038, 0x0FF4, 0x3FD4, + 0x0018, 0x1000, 0x3FE8, + 0x0000, 0x1000, 0x0000 +}; + +//========================================= +// = 3 +// = 64 +// = 1.16666 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_3tap_64p_116[99] = { + 0x0804, 0x07FC, 0x0000, + 0x07C0, 0x0844, 0x3FFC, + 0x0780, 0x0888, 0x3FF8, + 0x0740, 0x08D0, 0x3FF0, + 0x0700, 0x0914, 0x3FEC, + 0x06C0, 0x0958, 0x3FE8, + 0x0684, 0x0998, 0x3FE4, + 0x0644, 0x09DC, 0x3FE0, + 0x0604, 0x0A1C, 0x3FE0, + 0x05C4, 0x0A5C, 0x3FE0, + 0x0588, 0x0A9C, 0x3FDC, + 0x0548, 0x0ADC, 0x3FDC, + 0x050C, 0x0B14, 0x3FE0, + 0x04CC, 0x0B54, 0x3FE0, + 0x0490, 0x0B8C, 0x3FE4, + 0x0458, 0x0BC0, 0x3FE8, + 0x041C, 0x0BF4, 0x3FF0, + 0x03E0, 0x0C28, 0x3FF8, + 0x03A8, 0x0C58, 0x0000, + 0x0374, 0x0C88, 0x0004, + 0x0340, 0x0CB0, 0x0010, + 0x0308, 0x0CD8, 0x0020, + 0x02D8, 0x0CFC, 0x002C, + 0x02A0, 0x0D20, 0x0040, + 0x0274, 0x0D3C, 0x0050, + 0x0244, 0x0D58, 0x0064, + 0x0214, 0x0D70, 0x007C, + 0x01E8, 0x0D84, 0x0094, + 0x01C0, 0x0D94, 0x00AC, + 0x0198, 0x0DA0, 0x00C8, + 0x0170, 0x0DAC, 0x00E4, + 0x014C, 0x0DB0, 0x0104, + 0x0128, 0x0DB4, 0x0124 +}; + +//========================================= +// = 3 +// = 64 +// = 1.49999 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_3tap_64p_149[99] = { + 0x0804, 0x07FC, 0x0000, + 0x07CC, 0x0834, 0x0000, + 0x0798, 0x0868, 0x0000, + 0x0764, 0x089C, 0x0000, + 0x0730, 0x08CC, 0x0004, + 0x0700, 0x08FC, 0x0004, + 0x06CC, 0x092C, 0x0008, + 0x0698, 0x095C, 0x000C, + 0x0660, 0x098C, 0x0014, + 0x062C, 0x09B8, 0x001C, + 0x05FC, 0x09E4, 0x0020, + 0x05C4, 0x0A10, 0x002C, + 0x0590, 0x0A3C, 0x0034, + 0x055C, 0x0A64, 0x0040, + 0x0528, 0x0A8C, 0x004C, + 0x04F8, 0x0AB0, 0x0058, + 0x04C4, 0x0AD4, 0x0068, + 0x0490, 0x0AF8, 0x0078, + 0x0460, 0x0B18, 0x0088, + 0x0430, 0x0B38, 0x0098, + 0x0400, 0x0B54, 0x00AC, + 0x03D0, 0x0B6C, 0x00C4, + 0x03A0, 0x0B88, 0x00D8, + 0x0374, 0x0B9C, 0x00F0, + 0x0348, 0x0BB0, 0x0108, + 0x0318, 0x0BC4, 0x0124, + 0x02EC, 0x0BD4, 0x0140, + 0x02C4, 0x0BE0, 0x015C, + 0x029C, 0x0BEC, 0x0178, + 0x0274, 0x0BF4, 0x0198, + 0x024C, 0x0BFC, 0x01B8, + 0x0228, 0x0BFC, 0x01DC, + 0x0200, 0x0C00, 0x0200 +}; + +//========================================= +// = 3 +// = 64 +// = 1.83332 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_3tap_64p_183[99] = { + 0x0804, 0x07FC, 0x0000, + 0x07D4, 0x0824, 0x0008, + 0x07AC, 0x0840, 0x0014, + 0x0780, 0x0860, 0x0020, + 0x0754, 0x0880, 0x002C, + 0x0728, 0x089C, 0x003C, + 0x0700, 0x08B8, 0x0048, + 0x06D4, 0x08D4, 0x0058, + 0x06A8, 0x08F0, 0x0068, + 0x067C, 0x090C, 0x0078, + 0x0650, 0x0924, 0x008C, + 0x0628, 0x093C, 0x009C, + 0x05FC, 0x0954, 0x00B0, + 0x05D0, 0x096C, 0x00C4, + 0x05A8, 0x0980, 0x00D8, + 0x0578, 0x0998, 0x00F0, + 0x0550, 0x09AC, 0x0104, + 0x0528, 0x09BC, 0x011C, + 0x04FC, 0x09D0, 0x0134, + 0x04D4, 0x09E0, 0x014C, + 0x04A8, 0x09F0, 0x0168, + 0x0480, 0x09FC, 0x0184, + 0x045C, 0x0A08, 0x019C, + 0x0434, 0x0A14, 0x01B8, + 0x0408, 0x0A20, 0x01D8, + 0x03E0, 0x0A2C, 0x01F4, + 0x03B8, 0x0A34, 0x0214, + 0x0394, 0x0A38, 0x0234, + 0x036C, 0x0A40, 0x0254, + 0x0348, 0x0A44, 0x0274, + 0x0324, 0x0A48, 0x0294, + 0x0300, 0x0A48, 0x02B8, + 0x02DC, 0x0A48, 0x02DC +}; + +//========================================= +// = 4 +// = 64 +// = 0.83333 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_4tap_64p_upscale[132] = { + 0x0000, 0x1000, 0x0000, 0x0000, + 0x3FDC, 0x0FFC, 0x0028, 0x0000, + 0x3FB4, 0x0FF8, 0x0054, 0x0000, + 0x3F94, 0x0FE8, 0x0084, 0x0000, + 0x3F74, 0x0FDC, 0x00B4, 0x3FFC, + 0x3F58, 0x0FC4, 0x00E8, 0x3FFC, + 0x3F3C, 0x0FAC, 0x0120, 0x3FF8, + 0x3F24, 0x0F90, 0x0158, 0x3FF4, + 0x3F0C, 0x0F70, 0x0194, 0x3FF0, + 0x3EF8, 0x0F4C, 0x01D0, 0x3FEC, + 0x3EE8, 0x0F20, 0x0210, 0x3FE8, + 0x3ED8, 0x0EF4, 0x0254, 0x3FE0, + 0x3ECC, 0x0EC4, 0x0298, 0x3FD8, + 0x3EC0, 0x0E90, 0x02DC, 0x3FD4, + 0x3EB8, 0x0E58, 0x0324, 0x3FCC, + 0x3EB0, 0x0E20, 0x036C, 0x3FC4, + 0x3EAC, 0x0DE4, 0x03B8, 0x3FB8, + 0x3EA8, 0x0DA4, 0x0404, 0x3FB0, + 0x3EA4, 0x0D60, 0x0454, 0x3FA8, + 0x3EA4, 0x0D1C, 0x04A4, 0x3F9C, + 0x3EA4, 0x0CD8, 0x04F4, 0x3F90, + 0x3EA8, 0x0C88, 0x0548, 0x3F88, + 0x3EAC, 0x0C3C, 0x059C, 0x3F7C, + 0x3EB0, 0x0BF0, 0x05F0, 0x3F70, + 0x3EB8, 0x0BA0, 0x0644, 0x3F64, + 0x3EBC, 0x0B54, 0x0698, 0x3F58, + 0x3EC4, 0x0B00, 0x06F0, 0x3F4C, + 0x3ECC, 0x0AAC, 0x0748, 0x3F40, + 0x3ED8, 0x0A54, 0x07A0, 0x3F34, + 0x3EE0, 0x0A04, 0x07F8, 0x3F24, + 0x3EEC, 0x09AC, 0x0850, 0x3F18, + 0x3EF8, 0x0954, 0x08A8, 0x3F0C, + 0x3F00, 0x08FC, 0x0900, 0x3F04 +}; + +//========================================= +// = 4 +// = 64 +// = 1.16666 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_4tap_64p_116[132] = { + 0x01A8, 0x0CB4, 0x01A4, 0x0000, + 0x017C, 0x0CB8, 0x01D0, 0x3FFC, + 0x0158, 0x0CB8, 0x01F8, 0x3FF8, + 0x0130, 0x0CB4, 0x0228, 0x3FF4, + 0x0110, 0x0CB0, 0x0254, 0x3FEC, + 0x00EC, 0x0CA8, 0x0284, 0x3FE8, + 0x00CC, 0x0C9C, 0x02B4, 0x3FE4, + 0x00AC, 0x0C90, 0x02E8, 0x3FDC, + 0x0090, 0x0C80, 0x031C, 0x3FD4, + 0x0070, 0x0C70, 0x0350, 0x3FD0, + 0x0058, 0x0C5C, 0x0384, 0x3FC8, + 0x003C, 0x0C48, 0x03BC, 0x3FC0, + 0x0024, 0x0C2C, 0x03F4, 0x3FBC, + 0x0010, 0x0C10, 0x042C, 0x3FB4, + 0x3FFC, 0x0BF4, 0x0464, 0x3FAC, + 0x3FE8, 0x0BD4, 0x04A0, 0x3FA4, + 0x3FD8, 0x0BAC, 0x04DC, 0x3FA0, + 0x3FC4, 0x0B8C, 0x0518, 0x3F98, + 0x3FB4, 0x0B68, 0x0554, 0x3F90, + 0x3FA8, 0x0B40, 0x0590, 0x3F88, + 0x3F9C, 0x0B14, 0x05CC, 0x3F84, + 0x3F90, 0x0AEC, 0x0608, 0x3F7C, + 0x3F84, 0x0ABC, 0x0648, 0x3F78, + 0x3F7C, 0x0A90, 0x0684, 0x3F70, + 0x3F70, 0x0A60, 0x06C4, 0x3F6C, + 0x3F6C, 0x0A2C, 0x0700, 0x3F68, + 0x3F64, 0x09F8, 0x0740, 0x3F64, + 0x3F60, 0x09C4, 0x077C, 0x3F60, + 0x3F5C, 0x098C, 0x07BC, 0x3F5C, + 0x3F58, 0x0958, 0x07F8, 0x3F58, + 0x3F58, 0x091C, 0x0834, 0x3F58, + 0x3F54, 0x08E4, 0x0870, 0x3F58, + 0x3F54, 0x08AC, 0x08AC, 0x3F54 +}; + +//========================================= +// = 4 +// = 64 +// = 1.49999 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_4tap_64p_149[132] = { + 0x02B8, 0x0A90, 0x02B8, 0x0000, + 0x0294, 0x0A94, 0x02DC, 0x3FFC, + 0x0274, 0x0A94, 0x0300, 0x3FF8, + 0x0250, 0x0A94, 0x0328, 0x3FF4, + 0x0230, 0x0A90, 0x0350, 0x3FF0, + 0x0214, 0x0A8C, 0x0374, 0x3FEC, + 0x01F0, 0x0A88, 0x03A0, 0x3FE8, + 0x01D4, 0x0A80, 0x03C8, 0x3FE4, + 0x01B8, 0x0A78, 0x03F0, 0x3FE0, + 0x0198, 0x0A70, 0x041C, 0x3FDC, + 0x0180, 0x0A64, 0x0444, 0x3FD8, + 0x0164, 0x0A54, 0x0470, 0x3FD8, + 0x0148, 0x0A48, 0x049C, 0x3FD4, + 0x0130, 0x0A38, 0x04C8, 0x3FD0, + 0x0118, 0x0A24, 0x04F4, 0x3FD0, + 0x0100, 0x0A14, 0x0520, 0x3FCC, + 0x00E8, 0x0A00, 0x054C, 0x3FCC, + 0x00D4, 0x09E8, 0x057C, 0x3FC8, + 0x00C0, 0x09D0, 0x05A8, 0x3FC8, + 0x00AC, 0x09B8, 0x05D4, 0x3FC8, + 0x0098, 0x09A0, 0x0600, 0x3FC8, + 0x0084, 0x0984, 0x0630, 0x3FC8, + 0x0074, 0x0964, 0x065C, 0x3FCC, + 0x0064, 0x0948, 0x0688, 0x3FCC, + 0x0054, 0x0928, 0x06B4, 0x3FD0, + 0x0044, 0x0908, 0x06E0, 0x3FD4, + 0x0038, 0x08E8, 0x070C, 0x3FD4, + 0x002C, 0x08C4, 0x0738, 0x3FD8, + 0x001C, 0x08A4, 0x0760, 0x3FE0, + 0x0014, 0x087C, 0x078C, 0x3FE4, + 0x0008, 0x0858, 0x07B4, 0x3FEC, + 0x0000, 0x0830, 0x07DC, 0x3FF4, + 0x3FFC, 0x0804, 0x0804, 0x3FFC +}; + +//========================================= +// = 4 +// = 64 +// = 1.83332 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_4tap_64p_183[132] = { + 0x03B0, 0x08A0, 0x03B0, 0x0000, + 0x0394, 0x08A0, 0x03CC, 0x0000, + 0x037C, 0x089C, 0x03E8, 0x0000, + 0x0360, 0x089C, 0x0400, 0x0004, + 0x0348, 0x0898, 0x041C, 0x0004, + 0x032C, 0x0894, 0x0438, 0x0008, + 0x0310, 0x0890, 0x0454, 0x000C, + 0x02F8, 0x0888, 0x0474, 0x000C, + 0x02DC, 0x0884, 0x0490, 0x0010, + 0x02C4, 0x087C, 0x04AC, 0x0014, + 0x02AC, 0x0874, 0x04C8, 0x0018, + 0x0290, 0x086C, 0x04E4, 0x0020, + 0x0278, 0x0864, 0x0500, 0x0024, + 0x0264, 0x0858, 0x051C, 0x0028, + 0x024C, 0x084C, 0x0538, 0x0030, + 0x0234, 0x0844, 0x0554, 0x0034, + 0x021C, 0x0838, 0x0570, 0x003C, + 0x0208, 0x0828, 0x058C, 0x0044, + 0x01F0, 0x081C, 0x05A8, 0x004C, + 0x01DC, 0x080C, 0x05C4, 0x0054, + 0x01C8, 0x07FC, 0x05E0, 0x005C, + 0x01B4, 0x07EC, 0x05FC, 0x0064, + 0x019C, 0x07DC, 0x0618, 0x0070, + 0x018C, 0x07CC, 0x0630, 0x0078, + 0x0178, 0x07B8, 0x064C, 0x0084, + 0x0164, 0x07A8, 0x0664, 0x0090, + 0x0150, 0x0794, 0x0680, 0x009C, + 0x0140, 0x0780, 0x0698, 0x00A8, + 0x0130, 0x076C, 0x06B0, 0x00B4, + 0x0120, 0x0758, 0x06C8, 0x00C0, + 0x0110, 0x0740, 0x06E0, 0x00D0, + 0x0100, 0x072C, 0x06F8, 0x00DC, + 0x00F0, 0x0714, 0x0710, 0x00EC +}; + +//========================================= +// = 5 +// = 64 +// = 0.83333 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_5tap_64p_upscale[165] = { + 0x3E40, 0x09C0, 0x09C0, 0x3E40, 0x0000, + 0x3E50, 0x0964, 0x0A18, 0x3E34, 0x0000, + 0x3E5C, 0x0908, 0x0A6C, 0x3E2C, 0x0004, + 0x3E6C, 0x08AC, 0x0AC0, 0x3E20, 0x0008, + 0x3E78, 0x0850, 0x0B14, 0x3E18, 0x000C, + 0x3E88, 0x07F4, 0x0B60, 0x3E14, 0x0010, + 0x3E98, 0x0798, 0x0BB0, 0x3E0C, 0x0014, + 0x3EA8, 0x073C, 0x0C00, 0x3E08, 0x0014, + 0x3EB8, 0x06E4, 0x0C48, 0x3E04, 0x0018, + 0x3ECC, 0x0684, 0x0C90, 0x3E04, 0x001C, + 0x3EDC, 0x062C, 0x0CD4, 0x3E04, 0x0020, + 0x3EEC, 0x05D4, 0x0D1C, 0x3E04, 0x0020, + 0x3EFC, 0x057C, 0x0D5C, 0x3E08, 0x0024, + 0x3F0C, 0x0524, 0x0D98, 0x3E10, 0x0028, + 0x3F20, 0x04CC, 0x0DD8, 0x3E14, 0x0028, + 0x3F30, 0x0478, 0x0E14, 0x3E1C, 0x0028, + 0x3F40, 0x0424, 0x0E48, 0x3E28, 0x002C, + 0x3F50, 0x03D4, 0x0E7C, 0x3E34, 0x002C, + 0x3F60, 0x0384, 0x0EAC, 0x3E44, 0x002C, + 0x3F6C, 0x0338, 0x0EDC, 0x3E54, 0x002C, + 0x3F7C, 0x02E8, 0x0F08, 0x3E68, 0x002C, + 0x3F8C, 0x02A0, 0x0F2C, 0x3E7C, 0x002C, + 0x3F98, 0x0258, 0x0F50, 0x3E94, 0x002C, + 0x3FA4, 0x0210, 0x0F74, 0x3EB0, 0x0028, + 0x3FB0, 0x01CC, 0x0F90, 0x3ECC, 0x0028, + 0x3FC0, 0x018C, 0x0FA8, 0x3EE8, 0x0024, + 0x3FC8, 0x014C, 0x0FC0, 0x3F0C, 0x0020, + 0x3FD4, 0x0110, 0x0FD4, 0x3F2C, 0x001C, + 0x3FE0, 0x00D4, 0x0FE0, 0x3F54, 0x0018, + 0x3FE8, 0x009C, 0x0FF0, 0x3F7C, 0x0010, + 0x3FF0, 0x0064, 0x0FFC, 0x3FA4, 0x000C, + 0x3FFC, 0x0030, 0x0FFC, 0x3FD4, 0x0004, + 0x0000, 0x0000, 0x1000, 0x0000, 0x0000 +}; + +//========================================= +// = 5 +// = 64 +// = 1.16666 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_5tap_64p_116[165] = { + 0x3EDC, 0x0924, 0x0924, 0x3EDC, 0x0000, + 0x3ED8, 0x08EC, 0x095C, 0x3EE0, 0x0000, + 0x3ED4, 0x08B0, 0x0994, 0x3EE8, 0x0000, + 0x3ED0, 0x0878, 0x09C8, 0x3EF0, 0x0000, + 0x3ED0, 0x083C, 0x09FC, 0x3EF8, 0x0000, + 0x3ED0, 0x0800, 0x0A2C, 0x3F04, 0x0000, + 0x3ED0, 0x07C4, 0x0A5C, 0x3F10, 0x0000, + 0x3ED0, 0x0788, 0x0A8C, 0x3F1C, 0x0000, + 0x3ED0, 0x074C, 0x0AC0, 0x3F28, 0x3FFC, + 0x3ED4, 0x0710, 0x0AE8, 0x3F38, 0x3FFC, + 0x3ED8, 0x06D0, 0x0B18, 0x3F48, 0x3FF8, + 0x3EDC, 0x0694, 0x0B3C, 0x3F5C, 0x3FF8, + 0x3EE0, 0x0658, 0x0B68, 0x3F6C, 0x3FF4, + 0x3EE4, 0x061C, 0x0B90, 0x3F80, 0x3FF0, + 0x3EEC, 0x05DC, 0x0BB4, 0x3F98, 0x3FEC, + 0x3EF0, 0x05A0, 0x0BD8, 0x3FB0, 0x3FE8, + 0x3EF8, 0x0564, 0x0BF8, 0x3FC8, 0x3FE4, + 0x3EFC, 0x0528, 0x0C1C, 0x3FE0, 0x3FE0, + 0x3F04, 0x04EC, 0x0C38, 0x3FFC, 0x3FDC, + 0x3F0C, 0x04B4, 0x0C54, 0x0014, 0x3FD8, + 0x3F14, 0x047C, 0x0C70, 0x0030, 0x3FD0, + 0x3F1C, 0x0440, 0x0C88, 0x0050, 0x3FCC, + 0x3F24, 0x0408, 0x0CA0, 0x0070, 0x3FC4, + 0x3F2C, 0x03D0, 0x0CB0, 0x0094, 0x3FC0, + 0x3F34, 0x0398, 0x0CC4, 0x00B8, 0x3FB8, + 0x3F3C, 0x0364, 0x0CD4, 0x00DC, 0x3FB0, + 0x3F48, 0x032C, 0x0CE0, 0x0100, 0x3FAC, + 0x3F50, 0x02F8, 0x0CEC, 0x0128, 0x3FA4, + 0x3F58, 0x02C4, 0x0CF8, 0x0150, 0x3F9C, + 0x3F60, 0x0290, 0x0D00, 0x017C, 0x3F94, + 0x3F68, 0x0260, 0x0D04, 0x01A8, 0x3F8C, + 0x3F74, 0x0230, 0x0D04, 0x01D4, 0x3F84, + 0x3F7C, 0x0200, 0x0D08, 0x0200, 0x3F7C +}; + +//========================================= +// = 5 +// = 64 +// = 1.49999 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_5tap_64p_149[165] = { + 0x3FF4, 0x080C, 0x080C, 0x3FF4, 0x0000, + 0x3FE8, 0x07E8, 0x0830, 0x0000, 0x0000, + 0x3FDC, 0x07C8, 0x0850, 0x0010, 0x3FFC, + 0x3FD0, 0x07A4, 0x0878, 0x001C, 0x3FF8, + 0x3FC4, 0x0780, 0x0898, 0x0030, 0x3FF4, + 0x3FB8, 0x075C, 0x08B8, 0x0040, 0x3FF4, + 0x3FB0, 0x0738, 0x08D8, 0x0050, 0x3FF0, + 0x3FA8, 0x0710, 0x08F8, 0x0064, 0x3FEC, + 0x3FA0, 0x06EC, 0x0914, 0x0078, 0x3FE8, + 0x3F98, 0x06C4, 0x0934, 0x008C, 0x3FE4, + 0x3F90, 0x06A0, 0x094C, 0x00A4, 0x3FE0, + 0x3F8C, 0x0678, 0x0968, 0x00B8, 0x3FDC, + 0x3F84, 0x0650, 0x0984, 0x00D0, 0x3FD8, + 0x3F80, 0x0628, 0x099C, 0x00E8, 0x3FD4, + 0x3F7C, 0x0600, 0x09B8, 0x0100, 0x3FCC, + 0x3F78, 0x05D8, 0x09D0, 0x0118, 0x3FC8, + 0x3F74, 0x05B0, 0x09E4, 0x0134, 0x3FC4, + 0x3F70, 0x0588, 0x09F8, 0x0150, 0x3FC0, + 0x3F70, 0x0560, 0x0A08, 0x016C, 0x3FBC, + 0x3F6C, 0x0538, 0x0A20, 0x0188, 0x3FB4, + 0x3F6C, 0x0510, 0x0A30, 0x01A4, 0x3FB0, + 0x3F6C, 0x04E8, 0x0A3C, 0x01C4, 0x3FAC, + 0x3F6C, 0x04C0, 0x0A48, 0x01E4, 0x3FA8, + 0x3F6C, 0x0498, 0x0A58, 0x0200, 0x3FA4, + 0x3F6C, 0x0470, 0x0A60, 0x0224, 0x3FA0, + 0x3F6C, 0x0448, 0x0A70, 0x0244, 0x3F98, + 0x3F70, 0x0420, 0x0A78, 0x0264, 0x3F94, + 0x3F70, 0x03F8, 0x0A80, 0x0288, 0x3F90, + 0x3F74, 0x03D4, 0x0A84, 0x02A8, 0x3F8C, + 0x3F74, 0x03AC, 0x0A8C, 0x02CC, 0x3F88, + 0x3F78, 0x0384, 0x0A90, 0x02F0, 0x3F84, + 0x3F7C, 0x0360, 0x0A90, 0x0314, 0x3F80, + 0x3F7C, 0x033C, 0x0A90, 0x033C, 0x3F7C +}; + +//========================================= +// = 5 +// = 64 +// = 1.83332 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_5tap_64p_183[165] = { + 0x0168, 0x069C, 0x0698, 0x0164, 0x0000, + 0x0154, 0x068C, 0x06AC, 0x0174, 0x0000, + 0x0144, 0x0674, 0x06C0, 0x0188, 0x0000, + 0x0138, 0x0664, 0x06D0, 0x0198, 0x3FFC, + 0x0128, 0x0654, 0x06E0, 0x01A8, 0x3FFC, + 0x0118, 0x0640, 0x06F0, 0x01BC, 0x3FFC, + 0x010C, 0x0630, 0x0700, 0x01CC, 0x3FF8, + 0x00FC, 0x061C, 0x0710, 0x01E0, 0x3FF8, + 0x00F0, 0x060C, 0x071C, 0x01F0, 0x3FF8, + 0x00E4, 0x05F4, 0x072C, 0x0204, 0x3FF8, + 0x00D8, 0x05E4, 0x0738, 0x0218, 0x3FF4, + 0x00CC, 0x05D0, 0x0744, 0x022C, 0x3FF4, + 0x00C0, 0x05B8, 0x0754, 0x0240, 0x3FF4, + 0x00B4, 0x05A4, 0x0760, 0x0254, 0x3FF4, + 0x00A8, 0x0590, 0x076C, 0x0268, 0x3FF4, + 0x009C, 0x057C, 0x0778, 0x027C, 0x3FF4, + 0x0094, 0x0564, 0x0780, 0x0294, 0x3FF4, + 0x0088, 0x0550, 0x0788, 0x02A8, 0x3FF8, + 0x0080, 0x0538, 0x0794, 0x02BC, 0x3FF8, + 0x0074, 0x0524, 0x079C, 0x02D4, 0x3FF8, + 0x006C, 0x0510, 0x07A4, 0x02E8, 0x3FF8, + 0x0064, 0x04F4, 0x07AC, 0x0300, 0x3FFC, + 0x005C, 0x04E4, 0x07B0, 0x0314, 0x3FFC, + 0x0054, 0x04C8, 0x07B8, 0x032C, 0x0000, + 0x004C, 0x04B4, 0x07C0, 0x0340, 0x0000, + 0x0044, 0x04A0, 0x07C4, 0x0358, 0x0000, + 0x003C, 0x0488, 0x07C8, 0x0370, 0x0004, + 0x0038, 0x0470, 0x07CC, 0x0384, 0x0008, + 0x0030, 0x045C, 0x07D0, 0x039C, 0x0008, + 0x002C, 0x0444, 0x07D0, 0x03B4, 0x000C, + 0x0024, 0x042C, 0x07D4, 0x03CC, 0x0010, + 0x0020, 0x0414, 0x07D4, 0x03E0, 0x0018, + 0x001C, 0x03FC, 0x07D4, 0x03F8, 0x001C +}; + +//========================================= +// = 6 +// = 64 +// = 0.83333 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_6tap_64p_upscale[198] = { + 0x0000, 0x0000, 0x1000, 0x0000, 0x0000, 0x0000, + 0x000C, 0x3FD0, 0x0FFC, 0x0034, 0x3FF4, 0x0000, + 0x0018, 0x3F9C, 0x0FF8, 0x006C, 0x3FE8, 0x0000, + 0x0024, 0x3F6C, 0x0FF0, 0x00A8, 0x3FD8, 0x0000, + 0x002C, 0x3F44, 0x0FE4, 0x00E4, 0x3FC8, 0x0000, + 0x0038, 0x3F18, 0x0FD4, 0x0124, 0x3FB8, 0x0000, + 0x0040, 0x3EF0, 0x0FC0, 0x0164, 0x3FA8, 0x0004, + 0x0048, 0x3EC8, 0x0FAC, 0x01A8, 0x3F98, 0x0004, + 0x0050, 0x3EA8, 0x0F94, 0x01EC, 0x3F84, 0x0004, + 0x0058, 0x3E84, 0x0F74, 0x0234, 0x3F74, 0x0008, + 0x0060, 0x3E68, 0x0F54, 0x027C, 0x3F60, 0x0008, + 0x0064, 0x3E4C, 0x0F30, 0x02C8, 0x3F4C, 0x000C, + 0x006C, 0x3E30, 0x0F04, 0x0314, 0x3F3C, 0x0010, + 0x0070, 0x3E18, 0x0EDC, 0x0360, 0x3F28, 0x0014, + 0x0074, 0x3E04, 0x0EB0, 0x03B0, 0x3F14, 0x0014, + 0x0078, 0x3DF0, 0x0E80, 0x0400, 0x3F00, 0x0018, + 0x0078, 0x3DE0, 0x0E4C, 0x0454, 0x3EEC, 0x001C, + 0x007C, 0x3DD0, 0x0E14, 0x04A8, 0x3ED8, 0x0020, + 0x007C, 0x3DC4, 0x0DDC, 0x04FC, 0x3EC4, 0x0024, + 0x007C, 0x3DBC, 0x0DA0, 0x0550, 0x3EB0, 0x0028, + 0x0080, 0x3DB4, 0x0D5C, 0x05A8, 0x3E9C, 0x002C, + 0x0080, 0x3DAC, 0x0D1C, 0x0600, 0x3E88, 0x0030, + 0x007C, 0x3DA8, 0x0CDC, 0x0658, 0x3E74, 0x0034, + 0x007C, 0x3DA4, 0x0C94, 0x06B0, 0x3E64, 0x0038, + 0x007C, 0x3DA4, 0x0C48, 0x0708, 0x3E50, 0x0040, + 0x0078, 0x3DA4, 0x0C00, 0x0760, 0x3E40, 0x0044, + 0x0078, 0x3DA8, 0x0BB4, 0x07B8, 0x3E2C, 0x0048, + 0x0074, 0x3DAC, 0x0B68, 0x0810, 0x3E1C, 0x004C, + 0x0070, 0x3DB4, 0x0B18, 0x0868, 0x3E0C, 0x0050, + 0x006C, 0x3DBC, 0x0AC4, 0x08C4, 0x3DFC, 0x0054, + 0x0068, 0x3DC4, 0x0A74, 0x0918, 0x3DF0, 0x0058, + 0x0068, 0x3DCC, 0x0A20, 0x0970, 0x3DE0, 0x005C, + 0x0064, 0x3DD4, 0x09C8, 0x09C8, 0x3DD4, 0x0064 +}; + +//========================================= +// = 6 +// = 64 +// = 1.16666 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_6tap_64p_116[198] = { + 0x3F0C, 0x0240, 0x0D68, 0x0240, 0x3F0C, 0x0000, + 0x3F18, 0x0210, 0x0D64, 0x0274, 0x3F00, 0x0000, + 0x3F24, 0x01E0, 0x0D58, 0x02A8, 0x3EF8, 0x0004, + 0x3F2C, 0x01B0, 0x0D58, 0x02DC, 0x3EEC, 0x0004, + 0x3F38, 0x0180, 0x0D50, 0x0310, 0x3EE0, 0x0008, + 0x3F44, 0x0154, 0x0D40, 0x0348, 0x3ED8, 0x0008, + 0x3F50, 0x0128, 0x0D34, 0x037C, 0x3ECC, 0x000C, + 0x3F5C, 0x00FC, 0x0D20, 0x03B4, 0x3EC4, 0x0010, + 0x3F64, 0x00D4, 0x0D14, 0x03EC, 0x3EB8, 0x0010, + 0x3F70, 0x00AC, 0x0CFC, 0x0424, 0x3EB0, 0x0014, + 0x3F78, 0x0084, 0x0CE8, 0x0460, 0x3EA8, 0x0014, + 0x3F84, 0x0060, 0x0CCC, 0x0498, 0x3EA0, 0x0018, + 0x3F90, 0x003C, 0x0CB4, 0x04D0, 0x3E98, 0x0018, + 0x3F98, 0x0018, 0x0C9C, 0x050C, 0x3E90, 0x0018, + 0x3FA0, 0x3FFC, 0x0C78, 0x0548, 0x3E88, 0x001C, + 0x3FAC, 0x3FDC, 0x0C54, 0x0584, 0x3E84, 0x001C, + 0x3FB4, 0x3FBC, 0x0C3C, 0x05BC, 0x3E7C, 0x001C, + 0x3FBC, 0x3FA0, 0x0C14, 0x05F8, 0x3E78, 0x0020, + 0x3FC4, 0x3F84, 0x0BF0, 0x0634, 0x3E74, 0x0020, + 0x3FCC, 0x3F68, 0x0BCC, 0x0670, 0x3E70, 0x0020, + 0x3FD4, 0x3F50, 0x0BA4, 0x06AC, 0x3E6C, 0x0020, + 0x3FDC, 0x3F38, 0x0B78, 0x06E8, 0x3E6C, 0x0020, + 0x3FE0, 0x3F24, 0x0B50, 0x0724, 0x3E68, 0x0020, + 0x3FE8, 0x3F0C, 0x0B24, 0x0760, 0x3E68, 0x0020, + 0x3FF0, 0x3EFC, 0x0AF4, 0x0798, 0x3E68, 0x0020, + 0x3FF4, 0x3EE8, 0x0AC8, 0x07D4, 0x3E68, 0x0020, + 0x3FFC, 0x3ED8, 0x0A94, 0x0810, 0x3E6C, 0x001C, + 0x0000, 0x3EC8, 0x0A64, 0x0848, 0x3E70, 0x001C, + 0x0000, 0x3EB8, 0x0A38, 0x0880, 0x3E74, 0x001C, + 0x0004, 0x3EAC, 0x0A04, 0x08BC, 0x3E78, 0x0018, + 0x0008, 0x3EA4, 0x09D0, 0x08F4, 0x3E7C, 0x0014, + 0x000C, 0x3E98, 0x0998, 0x092C, 0x3E84, 0x0014, + 0x0010, 0x3E90, 0x0964, 0x0960, 0x3E8C, 0x0010 +}; + +//========================================= +// = 6 +// = 64 +// = 1.49999 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_6tap_64p_149[198] = { + 0x3F14, 0x0394, 0x0AB0, 0x0394, 0x3F14, 0x0000, + 0x3F18, 0x036C, 0x0AB0, 0x03B8, 0x3F14, 0x0000, + 0x3F18, 0x0348, 0x0AAC, 0x03E0, 0x3F14, 0x0000, + 0x3F1C, 0x0320, 0x0AAC, 0x0408, 0x3F10, 0x0000, + 0x3F20, 0x02FC, 0x0AA8, 0x042C, 0x3F10, 0x0000, + 0x3F24, 0x02D8, 0x0AA0, 0x0454, 0x3F10, 0x0000, + 0x3F28, 0x02B4, 0x0A98, 0x047C, 0x3F10, 0x0000, + 0x3F28, 0x0290, 0x0A90, 0x04A4, 0x3F14, 0x0000, + 0x3F30, 0x026C, 0x0A84, 0x04CC, 0x3F14, 0x0000, + 0x3F34, 0x024C, 0x0A7C, 0x04F4, 0x3F14, 0x3FFC, + 0x3F38, 0x0228, 0x0A70, 0x051C, 0x3F18, 0x3FFC, + 0x3F3C, 0x0208, 0x0A64, 0x0544, 0x3F1C, 0x3FF8, + 0x3F40, 0x01E8, 0x0A54, 0x056C, 0x3F20, 0x3FF8, + 0x3F44, 0x01C8, 0x0A48, 0x0594, 0x3F24, 0x3FF4, + 0x3F4C, 0x01A8, 0x0A34, 0x05BC, 0x3F28, 0x3FF4, + 0x3F50, 0x0188, 0x0A28, 0x05E4, 0x3F2C, 0x3FF0, + 0x3F54, 0x016C, 0x0A10, 0x060C, 0x3F34, 0x3FF0, + 0x3F5C, 0x014C, 0x09FC, 0x0634, 0x3F3C, 0x3FEC, + 0x3F60, 0x0130, 0x09EC, 0x065C, 0x3F40, 0x3FE8, + 0x3F68, 0x0114, 0x09D0, 0x0684, 0x3F48, 0x3FE8, + 0x3F6C, 0x00F8, 0x09B8, 0x06AC, 0x3F54, 0x3FE4, + 0x3F74, 0x00E0, 0x09A0, 0x06D0, 0x3F5C, 0x3FE0, + 0x3F78, 0x00C4, 0x098C, 0x06F8, 0x3F64, 0x3FDC, + 0x3F7C, 0x00AC, 0x0970, 0x0720, 0x3F70, 0x3FD8, + 0x3F84, 0x0094, 0x0954, 0x0744, 0x3F7C, 0x3FD4, + 0x3F88, 0x007C, 0x093C, 0x0768, 0x3F88, 0x3FD0, + 0x3F90, 0x0064, 0x091C, 0x0790, 0x3F94, 0x3FCC, + 0x3F94, 0x0050, 0x08FC, 0x07B4, 0x3FA4, 0x3FC8, + 0x3F98, 0x003C, 0x08E0, 0x07D8, 0x3FB0, 0x3FC4, + 0x3FA0, 0x0024, 0x08C0, 0x07FC, 0x3FC0, 0x3FC0, + 0x3FA4, 0x0014, 0x08A4, 0x081C, 0x3FD0, 0x3FB8, + 0x3FAC, 0x0000, 0x0880, 0x0840, 0x3FE0, 0x3FB4, + 0x3FB0, 0x3FF0, 0x0860, 0x0860, 0x3FF0, 0x3FB0 +}; + +//========================================= +// = 6 +// = 64 +// = 1.83332 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_6tap_64p_183[198] = { + 0x002C, 0x0420, 0x076C, 0x041C, 0x002C, 0x0000, + 0x0028, 0x040C, 0x0768, 0x0430, 0x0034, 0x0000, + 0x0020, 0x03F8, 0x0768, 0x0448, 0x003C, 0x3FFC, + 0x0018, 0x03E4, 0x0768, 0x045C, 0x0044, 0x3FFC, + 0x0014, 0x03D0, 0x0768, 0x0470, 0x004C, 0x3FF8, + 0x000C, 0x03BC, 0x0764, 0x0484, 0x0058, 0x3FF8, + 0x0008, 0x03A4, 0x0764, 0x049C, 0x0060, 0x3FF4, + 0x0004, 0x0390, 0x0760, 0x04B0, 0x0068, 0x3FF4, + 0x0000, 0x037C, 0x0760, 0x04C4, 0x0070, 0x3FF0, + 0x3FFC, 0x0364, 0x075C, 0x04D8, 0x007C, 0x3FF0, + 0x3FF8, 0x0350, 0x0758, 0x04F0, 0x0084, 0x3FEC, + 0x3FF4, 0x033C, 0x0750, 0x0504, 0x0090, 0x3FEC, + 0x3FF0, 0x0328, 0x074C, 0x0518, 0x009C, 0x3FE8, + 0x3FEC, 0x0314, 0x0744, 0x052C, 0x00A8, 0x3FE8, + 0x3FE8, 0x0304, 0x0740, 0x0540, 0x00B0, 0x3FE4, + 0x3FE4, 0x02EC, 0x073C, 0x0554, 0x00BC, 0x3FE4, + 0x3FE0, 0x02DC, 0x0734, 0x0568, 0x00C8, 0x3FE0, + 0x3FE0, 0x02C4, 0x072C, 0x057C, 0x00D4, 0x3FE0, + 0x3FDC, 0x02B4, 0x0724, 0x058C, 0x00E4, 0x3FDC, + 0x3FDC, 0x02A0, 0x0718, 0x05A0, 0x00F0, 0x3FDC, + 0x3FD8, 0x028C, 0x0714, 0x05B4, 0x00FC, 0x3FD8, + 0x3FD8, 0x0278, 0x0704, 0x05C8, 0x010C, 0x3FD8, + 0x3FD4, 0x0264, 0x0700, 0x05D8, 0x0118, 0x3FD8, + 0x3FD4, 0x0254, 0x06F0, 0x05EC, 0x0128, 0x3FD4, + 0x3FD0, 0x0244, 0x06E8, 0x05FC, 0x0134, 0x3FD4, + 0x3FD0, 0x0230, 0x06DC, 0x060C, 0x0144, 0x3FD4, + 0x3FD0, 0x021C, 0x06D0, 0x0620, 0x0154, 0x3FD0, + 0x3FD0, 0x0208, 0x06C4, 0x0630, 0x0164, 0x3FD0, + 0x3FD0, 0x01F8, 0x06B8, 0x0640, 0x0170, 0x3FD0, + 0x3FCC, 0x01E8, 0x06AC, 0x0650, 0x0180, 0x3FD0, + 0x3FCC, 0x01D8, 0x069C, 0x0660, 0x0190, 0x3FD0, + 0x3FCC, 0x01C4, 0x068C, 0x0670, 0x01A4, 0x3FD0, + 0x3FCC, 0x01B8, 0x0680, 0x067C, 0x01B4, 0x3FCC +}; + +//========================================= +// = 7 +// = 64 +// = 0.83333 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_7tap_64p_upscale[231] = { + 0x00B0, 0x3D98, 0x09BC, 0x09B8, 0x3D94, 0x00B0, 0x0000, + 0x00AC, 0x3DA0, 0x0968, 0x0A10, 0x3D88, 0x00B4, 0x0000, + 0x00A8, 0x3DAC, 0x0914, 0x0A60, 0x3D80, 0x00B8, 0x0000, + 0x00A4, 0x3DB8, 0x08C0, 0x0AB4, 0x3D78, 0x00BC, 0x3FFC, + 0x00A0, 0x3DC8, 0x0868, 0x0B00, 0x3D74, 0x00C0, 0x3FFC, + 0x0098, 0x3DD8, 0x0818, 0x0B54, 0x3D6C, 0x00C0, 0x3FF8, + 0x0094, 0x3DE8, 0x07C0, 0x0B9C, 0x3D6C, 0x00C4, 0x3FF8, + 0x008C, 0x3DFC, 0x0768, 0x0BEC, 0x3D68, 0x00C4, 0x3FF8, + 0x0088, 0x3E0C, 0x0714, 0x0C38, 0x3D68, 0x00C4, 0x3FF4, + 0x0080, 0x3E20, 0x06BC, 0x0C80, 0x3D6C, 0x00C4, 0x3FF4, + 0x0078, 0x3E34, 0x0668, 0x0CC4, 0x3D70, 0x00C4, 0x3FF4, + 0x0074, 0x3E48, 0x0610, 0x0D08, 0x3D78, 0x00C4, 0x3FF0, + 0x006C, 0x3E5C, 0x05BC, 0x0D48, 0x3D80, 0x00C4, 0x3FF0, + 0x0068, 0x3E74, 0x0568, 0x0D84, 0x3D88, 0x00C0, 0x3FF0, + 0x0060, 0x3E88, 0x0514, 0x0DC8, 0x3D94, 0x00BC, 0x3FEC, + 0x0058, 0x3E9C, 0x04C0, 0x0E04, 0x3DA4, 0x00B8, 0x3FEC, + 0x0054, 0x3EB4, 0x046C, 0x0E38, 0x3DB4, 0x00B4, 0x3FEC, + 0x004C, 0x3ECC, 0x0418, 0x0E6C, 0x3DC8, 0x00B0, 0x3FEC, + 0x0044, 0x3EE0, 0x03C8, 0x0EA4, 0x3DDC, 0x00A8, 0x3FEC, + 0x0040, 0x3EF8, 0x0378, 0x0ED0, 0x3DF4, 0x00A0, 0x3FEC, + 0x0038, 0x3F0C, 0x032C, 0x0EFC, 0x3E10, 0x0098, 0x3FEC, + 0x0034, 0x3F24, 0x02DC, 0x0F24, 0x3E2C, 0x0090, 0x3FEC, + 0x002C, 0x3F38, 0x0294, 0x0F4C, 0x3E48, 0x0088, 0x3FEC, + 0x0028, 0x3F50, 0x0248, 0x0F68, 0x3E6C, 0x007C, 0x3FF0, + 0x0020, 0x3F64, 0x0200, 0x0F88, 0x3E90, 0x0074, 0x3FF0, + 0x001C, 0x3F7C, 0x01B8, 0x0FA4, 0x3EB4, 0x0068, 0x3FF0, + 0x0018, 0x3F90, 0x0174, 0x0FBC, 0x3EDC, 0x0058, 0x3FF4, + 0x0014, 0x3FA4, 0x0130, 0x0FD0, 0x3F08, 0x004C, 0x3FF4, + 0x000C, 0x3FB8, 0x00F0, 0x0FE4, 0x3F34, 0x003C, 0x3FF8, + 0x0008, 0x3FCC, 0x00B0, 0x0FF0, 0x3F64, 0x0030, 0x3FF8, + 0x0004, 0x3FDC, 0x0070, 0x0FFC, 0x3F98, 0x0020, 0x3FFC, + 0x0000, 0x3FF0, 0x0038, 0x0FFC, 0x3FCC, 0x0010, 0x0000, + 0x0000, 0x0000, 0x0000, 0x1000, 0x0000, 0x0000, 0x0000 +}; + +//========================================= +// = 7 +// = 64 +// = 1.16666 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_7tap_64p_116[231] = { + 0x0020, 0x3E58, 0x0988, 0x0988, 0x3E58, 0x0020, 0x0000, + 0x0024, 0x3E4C, 0x0954, 0x09C0, 0x3E64, 0x0018, 0x0000, + 0x002C, 0x3E44, 0x091C, 0x09F4, 0x3E70, 0x0010, 0x0000, + 0x0030, 0x3E3C, 0x08E8, 0x0A24, 0x3E80, 0x0008, 0x0000, + 0x0034, 0x3E34, 0x08AC, 0x0A5C, 0x3E90, 0x0000, 0x0000, + 0x003C, 0x3E30, 0x0870, 0x0A84, 0x3EA0, 0x3FFC, 0x0004, + 0x0040, 0x3E28, 0x0838, 0x0AB4, 0x3EB4, 0x3FF4, 0x0004, + 0x0044, 0x3E24, 0x07FC, 0x0AE4, 0x3EC8, 0x3FEC, 0x0004, + 0x0048, 0x3E24, 0x07C4, 0x0B08, 0x3EDC, 0x3FE4, 0x0008, + 0x0048, 0x3E20, 0x0788, 0x0B3C, 0x3EF4, 0x3FD8, 0x0008, + 0x004C, 0x3E20, 0x074C, 0x0B60, 0x3F0C, 0x3FD0, 0x000C, + 0x0050, 0x3E20, 0x0710, 0x0B8C, 0x3F24, 0x3FC4, 0x000C, + 0x0050, 0x3E20, 0x06D4, 0x0BB0, 0x3F40, 0x3FBC, 0x0010, + 0x0054, 0x3E24, 0x0698, 0x0BD4, 0x3F5C, 0x3FB0, 0x0010, + 0x0054, 0x3E24, 0x065C, 0x0BFC, 0x3F78, 0x3FA4, 0x0014, + 0x0054, 0x3E28, 0x0624, 0x0C1C, 0x3F98, 0x3F98, 0x0014, + 0x0058, 0x3E2C, 0x05E4, 0x0C3C, 0x3FB8, 0x3F8C, 0x0018, + 0x0058, 0x3E34, 0x05A8, 0x0C58, 0x3FD8, 0x3F80, 0x001C, + 0x0058, 0x3E38, 0x0570, 0x0C78, 0x3FF8, 0x3F74, 0x001C, + 0x0058, 0x3E40, 0x0534, 0x0C94, 0x0018, 0x3F68, 0x0020, + 0x0058, 0x3E48, 0x04F4, 0x0CAC, 0x0040, 0x3F5C, 0x0024, + 0x0058, 0x3E50, 0x04BC, 0x0CC4, 0x0064, 0x3F50, 0x0024, + 0x0054, 0x3E58, 0x0484, 0x0CD8, 0x008C, 0x3F44, 0x0028, + 0x0054, 0x3E60, 0x0448, 0x0CEC, 0x00B4, 0x3F38, 0x002C, + 0x0054, 0x3E68, 0x0410, 0x0CFC, 0x00E0, 0x3F28, 0x0030, + 0x0054, 0x3E74, 0x03D4, 0x0D0C, 0x010C, 0x3F1C, 0x0030, + 0x0050, 0x3E7C, 0x03A0, 0x0D18, 0x0138, 0x3F10, 0x0034, + 0x0050, 0x3E88, 0x0364, 0x0D24, 0x0164, 0x3F04, 0x0038, + 0x004C, 0x3E94, 0x0330, 0x0D30, 0x0194, 0x3EF4, 0x0038, + 0x004C, 0x3EA0, 0x02F8, 0x0D34, 0x01C4, 0x3EE8, 0x003C, + 0x0048, 0x3EAC, 0x02C0, 0x0D3C, 0x01F4, 0x3EDC, 0x0040, + 0x0048, 0x3EB8, 0x0290, 0x0D3C, 0x0224, 0x3ED0, 0x0040, + 0x0044, 0x3EC4, 0x0258, 0x0D40, 0x0258, 0x3EC4, 0x0044 +}; + +//========================================= +// = 7 +// = 64 +// = 1.49999 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_7tap_64p_149[231] = { + 0x3F68, 0x3FEC, 0x08A8, 0x08AC, 0x3FF0, 0x3F68, 0x0000, + 0x3F70, 0x3FDC, 0x0888, 0x08CC, 0x0000, 0x3F60, 0x0000, + 0x3F74, 0x3FC8, 0x0868, 0x08F0, 0x0014, 0x3F58, 0x0000, + 0x3F7C, 0x3FB4, 0x0844, 0x0908, 0x002C, 0x3F54, 0x0004, + 0x3F84, 0x3FA4, 0x0820, 0x0924, 0x0044, 0x3F4C, 0x0004, + 0x3F88, 0x3F90, 0x0800, 0x0944, 0x005C, 0x3F44, 0x0004, + 0x3F90, 0x3F80, 0x07D8, 0x095C, 0x0074, 0x3F40, 0x0008, + 0x3F98, 0x3F70, 0x07B0, 0x097C, 0x008C, 0x3F38, 0x0008, + 0x3F9C, 0x3F60, 0x0790, 0x0994, 0x00A8, 0x3F30, 0x0008, + 0x3FA4, 0x3F54, 0x0764, 0x09B0, 0x00C4, 0x3F28, 0x0008, + 0x3FA8, 0x3F48, 0x0740, 0x09C4, 0x00DC, 0x3F24, 0x000C, + 0x3FB0, 0x3F38, 0x0718, 0x09DC, 0x00FC, 0x3F1C, 0x000C, + 0x3FB4, 0x3F2C, 0x06F0, 0x09F4, 0x0118, 0x3F18, 0x000C, + 0x3FBC, 0x3F24, 0x06C8, 0x0A08, 0x0134, 0x3F10, 0x000C, + 0x3FC0, 0x3F18, 0x06A0, 0x0A1C, 0x0154, 0x3F08, 0x0010, + 0x3FC8, 0x3F10, 0x0678, 0x0A2C, 0x0170, 0x3F04, 0x0010, + 0x3FCC, 0x3F04, 0x0650, 0x0A40, 0x0190, 0x3F00, 0x0010, + 0x3FD0, 0x3EFC, 0x0628, 0x0A54, 0x01B0, 0x3EF8, 0x0010, + 0x3FD4, 0x3EF4, 0x0600, 0x0A64, 0x01D0, 0x3EF4, 0x0010, + 0x3FDC, 0x3EEC, 0x05D8, 0x0A6C, 0x01F4, 0x3EF0, 0x0010, + 0x3FE0, 0x3EE8, 0x05B0, 0x0A7C, 0x0214, 0x3EE8, 0x0010, + 0x3FE4, 0x3EE0, 0x0588, 0x0A88, 0x0238, 0x3EE4, 0x0010, + 0x3FE8, 0x3EDC, 0x055C, 0x0A98, 0x0258, 0x3EE0, 0x0010, + 0x3FEC, 0x3ED8, 0x0534, 0x0AA0, 0x027C, 0x3EDC, 0x0010, + 0x3FF0, 0x3ED4, 0x050C, 0x0AAC, 0x02A0, 0x3ED8, 0x000C, + 0x3FF4, 0x3ED0, 0x04E4, 0x0AB4, 0x02C4, 0x3ED4, 0x000C, + 0x3FF4, 0x3ECC, 0x04C0, 0x0ABC, 0x02E8, 0x3ED0, 0x000C, + 0x3FF8, 0x3ECC, 0x0494, 0x0AC0, 0x030C, 0x3ED0, 0x000C, + 0x3FFC, 0x3EC8, 0x046C, 0x0AC8, 0x0334, 0x3ECC, 0x0008, + 0x0000, 0x3EC8, 0x0444, 0x0AC8, 0x0358, 0x3ECC, 0x0008, + 0x0000, 0x3EC8, 0x041C, 0x0ACC, 0x0380, 0x3EC8, 0x0008, + 0x0000, 0x3EC8, 0x03F4, 0x0AD0, 0x03A8, 0x3EC8, 0x0004, + 0x0004, 0x3EC8, 0x03CC, 0x0AD0, 0x03CC, 0x3EC8, 0x0004 +}; + +//========================================= +// = 7 +// = 64 +// = 1.83332 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_7tap_64p_183[231] = { + 0x3FA4, 0x01E8, 0x0674, 0x0674, 0x01E8, 0x3FA4, 0x0000, + 0x3FA4, 0x01D4, 0x0668, 0x0684, 0x01F8, 0x3FA4, 0x0000, + 0x3FA4, 0x01C4, 0x0658, 0x0690, 0x0208, 0x3FA8, 0x0000, + 0x3FA0, 0x01B4, 0x064C, 0x06A0, 0x021C, 0x3FA8, 0x3FFC, + 0x3FA0, 0x01A4, 0x063C, 0x06AC, 0x022C, 0x3FAC, 0x3FFC, + 0x3FA0, 0x0194, 0x0630, 0x06B4, 0x0240, 0x3FAC, 0x3FFC, + 0x3FA0, 0x0184, 0x0620, 0x06C4, 0x0250, 0x3FB0, 0x3FF8, + 0x3FA0, 0x0174, 0x0614, 0x06CC, 0x0264, 0x3FB0, 0x3FF8, + 0x3FA0, 0x0164, 0x0604, 0x06D8, 0x0278, 0x3FB4, 0x3FF4, + 0x3FA0, 0x0154, 0x05F4, 0x06E4, 0x0288, 0x3FB8, 0x3FF4, + 0x3FA0, 0x0148, 0x05E4, 0x06EC, 0x029C, 0x3FBC, 0x3FF0, + 0x3FA0, 0x0138, 0x05D4, 0x06F4, 0x02B0, 0x3FC0, 0x3FF0, + 0x3FA0, 0x0128, 0x05C4, 0x0704, 0x02C4, 0x3FC0, 0x3FEC, + 0x3FA0, 0x011C, 0x05B4, 0x0708, 0x02D8, 0x3FC4, 0x3FEC, + 0x3FA4, 0x010C, 0x05A4, 0x0714, 0x02E8, 0x3FC8, 0x3FE8, + 0x3FA4, 0x0100, 0x0590, 0x0718, 0x02FC, 0x3FD0, 0x3FE8, + 0x3FA4, 0x00F0, 0x0580, 0x0724, 0x0310, 0x3FD4, 0x3FE4, + 0x3FA4, 0x00E4, 0x056C, 0x072C, 0x0324, 0x3FD8, 0x3FE4, + 0x3FA8, 0x00D8, 0x055C, 0x0730, 0x0338, 0x3FDC, 0x3FE0, + 0x3FA8, 0x00CC, 0x0548, 0x0738, 0x034C, 0x3FE4, 0x3FDC, + 0x3FA8, 0x00BC, 0x0538, 0x0740, 0x0360, 0x3FE8, 0x3FDC, + 0x3FAC, 0x00B0, 0x0528, 0x0744, 0x0374, 0x3FEC, 0x3FD8, + 0x3FAC, 0x00A4, 0x0514, 0x0748, 0x0388, 0x3FF4, 0x3FD8, + 0x3FB0, 0x0098, 0x0500, 0x074C, 0x039C, 0x3FFC, 0x3FD4, + 0x3FB0, 0x0090, 0x04EC, 0x0750, 0x03B0, 0x0000, 0x3FD4, + 0x3FB0, 0x0084, 0x04DC, 0x0758, 0x03C4, 0x0004, 0x3FD0, + 0x3FB4, 0x0078, 0x04CC, 0x0758, 0x03D8, 0x000C, 0x3FCC, + 0x3FB4, 0x006C, 0x04B8, 0x075C, 0x03EC, 0x0014, 0x3FCC, + 0x3FB8, 0x0064, 0x04A0, 0x0760, 0x0400, 0x001C, 0x3FC8, + 0x3FB8, 0x0058, 0x0490, 0x0760, 0x0414, 0x0024, 0x3FC8, + 0x3FBC, 0x0050, 0x047C, 0x0760, 0x0428, 0x002C, 0x3FC4, + 0x3FBC, 0x0048, 0x0464, 0x0764, 0x043C, 0x0034, 0x3FC4, + 0x3FC0, 0x003C, 0x0454, 0x0764, 0x0450, 0x003C, 0x3FC0 +}; + +//========================================= +// = 8 +// = 64 +// = 0.83333 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_8tap_64p_upscale[264] = { + 0x0000, 0x0000, 0x0000, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x3FFC, 0x0014, 0x3FC8, 0x1000, 0x0038, 0x3FEC, 0x0004, 0x0000, + 0x3FF4, 0x0024, 0x3F94, 0x0FFC, 0x0074, 0x3FD8, 0x000C, 0x0000, + 0x3FF0, 0x0038, 0x3F60, 0x0FEC, 0x00B4, 0x3FC4, 0x0014, 0x0000, + 0x3FEC, 0x004C, 0x3F2C, 0x0FE4, 0x00F4, 0x3FAC, 0x0018, 0x0000, + 0x3FE4, 0x005C, 0x3F00, 0x0FD4, 0x0138, 0x3F94, 0x0020, 0x0000, + 0x3FE0, 0x006C, 0x3ED0, 0x0FC4, 0x017C, 0x3F7C, 0x0028, 0x0000, + 0x3FDC, 0x007C, 0x3EA8, 0x0FA4, 0x01C4, 0x3F68, 0x0030, 0x0000, + 0x3FD8, 0x0088, 0x3E80, 0x0F90, 0x020C, 0x3F50, 0x0038, 0x3FFC, + 0x3FD4, 0x0098, 0x3E58, 0x0F70, 0x0258, 0x3F38, 0x0040, 0x3FFC, + 0x3FD0, 0x00A4, 0x3E34, 0x0F54, 0x02A0, 0x3F1C, 0x004C, 0x3FFC, + 0x3FD0, 0x00B0, 0x3E14, 0x0F28, 0x02F0, 0x3F04, 0x0054, 0x3FFC, + 0x3FCC, 0x00BC, 0x3DF4, 0x0F08, 0x033C, 0x3EEC, 0x005C, 0x3FF8, + 0x3FC8, 0x00C8, 0x3DD8, 0x0EDC, 0x038C, 0x3ED4, 0x0064, 0x3FF8, + 0x3FC8, 0x00D0, 0x3DC0, 0x0EAC, 0x03E0, 0x3EBC, 0x006C, 0x3FF4, + 0x3FC4, 0x00D8, 0x3DA8, 0x0E7C, 0x0430, 0x3EA4, 0x0078, 0x3FF4, + 0x3FC4, 0x00E0, 0x3D94, 0x0E48, 0x0484, 0x3E8C, 0x0080, 0x3FF0, + 0x3FC4, 0x00E8, 0x3D80, 0x0E10, 0x04D8, 0x3E74, 0x0088, 0x3FF0, + 0x3FC4, 0x00F0, 0x3D70, 0x0DD8, 0x052C, 0x3E5C, 0x0090, 0x3FEC, + 0x3FC0, 0x00F4, 0x3D60, 0x0DA0, 0x0584, 0x3E44, 0x0098, 0x3FEC, + 0x3FC0, 0x00F8, 0x3D54, 0x0D68, 0x05D8, 0x3E2C, 0x00A0, 0x3FE8, + 0x3FC0, 0x00FC, 0x3D48, 0x0D20, 0x0630, 0x3E18, 0x00AC, 0x3FE8, + 0x3FC0, 0x0100, 0x3D40, 0x0CE0, 0x0688, 0x3E00, 0x00B4, 0x3FE4, + 0x3FC4, 0x0100, 0x3D3C, 0x0C98, 0x06DC, 0x3DEC, 0x00BC, 0x3FE4, + 0x3FC4, 0x0100, 0x3D38, 0x0C58, 0x0734, 0x3DD8, 0x00C0, 0x3FE0, + 0x3FC4, 0x0104, 0x3D38, 0x0C0C, 0x078C, 0x3DC4, 0x00C8, 0x3FDC, + 0x3FC4, 0x0100, 0x3D38, 0x0BC4, 0x07E4, 0x3DB0, 0x00D0, 0x3FDC, + 0x3FC4, 0x0100, 0x3D38, 0x0B78, 0x083C, 0x3DA0, 0x00D8, 0x3FD8, + 0x3FC8, 0x0100, 0x3D3C, 0x0B28, 0x0890, 0x3D90, 0x00DC, 0x3FD8, + 0x3FC8, 0x00FC, 0x3D40, 0x0ADC, 0x08E8, 0x3D80, 0x00E4, 0x3FD4, + 0x3FCC, 0x00FC, 0x3D48, 0x0A84, 0x093C, 0x3D74, 0x00E8, 0x3FD4, + 0x3FCC, 0x00F8, 0x3D50, 0x0A38, 0x0990, 0x3D64, 0x00F0, 0x3FD0, + 0x3FD0, 0x00F4, 0x3D58, 0x09E0, 0x09E4, 0x3D5C, 0x00F4, 0x3FD0 +}; + +//========================================= +// = 8 +// = 64 +// = 1.16666 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_8tap_64p_116[264] = { + 0x0080, 0x3E90, 0x0268, 0x0D14, 0x0264, 0x3E90, 0x0080, 0x0000, + 0x007C, 0x3E9C, 0x0238, 0x0D14, 0x0298, 0x3E84, 0x0080, 0x0000, + 0x0078, 0x3EAC, 0x0200, 0x0D10, 0x02D0, 0x3E78, 0x0084, 0x0000, + 0x0078, 0x3EB8, 0x01D0, 0x0D0C, 0x0304, 0x3E6C, 0x0084, 0x0000, + 0x0074, 0x3EC8, 0x01A0, 0x0D00, 0x033C, 0x3E60, 0x0088, 0x0000, + 0x0070, 0x3ED4, 0x0170, 0x0D00, 0x0374, 0x3E54, 0x0088, 0x3FFC, + 0x006C, 0x3EE4, 0x0140, 0x0CF8, 0x03AC, 0x3E48, 0x0088, 0x3FFC, + 0x006C, 0x3EF0, 0x0114, 0x0CE8, 0x03E4, 0x3E3C, 0x008C, 0x3FFC, + 0x0068, 0x3F00, 0x00E8, 0x0CD8, 0x041C, 0x3E34, 0x008C, 0x3FFC, + 0x0064, 0x3F10, 0x00BC, 0x0CCC, 0x0454, 0x3E28, 0x008C, 0x3FFC, + 0x0060, 0x3F1C, 0x0090, 0x0CBC, 0x0490, 0x3E20, 0x008C, 0x3FFC, + 0x005C, 0x3F2C, 0x0068, 0x0CA4, 0x04CC, 0x3E18, 0x008C, 0x3FFC, + 0x0058, 0x3F38, 0x0040, 0x0C94, 0x0504, 0x3E10, 0x008C, 0x3FFC, + 0x0054, 0x3F48, 0x001C, 0x0C7C, 0x0540, 0x3E08, 0x0088, 0x3FFC, + 0x0050, 0x3F54, 0x3FF8, 0x0C60, 0x057C, 0x3E04, 0x0088, 0x3FFC, + 0x004C, 0x3F64, 0x3FD4, 0x0C44, 0x05B8, 0x3DFC, 0x0088, 0x3FFC, + 0x0048, 0x3F70, 0x3FB4, 0x0C28, 0x05F4, 0x3DF8, 0x0084, 0x3FFC, + 0x0044, 0x3F80, 0x3F90, 0x0C0C, 0x0630, 0x3DF4, 0x0080, 0x3FFC, + 0x0040, 0x3F8C, 0x3F70, 0x0BE8, 0x066C, 0x3DF4, 0x0080, 0x3FFC, + 0x003C, 0x3F9C, 0x3F50, 0x0BC8, 0x06A8, 0x3DF0, 0x007C, 0x3FFC, + 0x0038, 0x3FA8, 0x3F34, 0x0BA0, 0x06E4, 0x3DF0, 0x0078, 0x0000, + 0x0034, 0x3FB4, 0x3F18, 0x0B80, 0x071C, 0x3DF0, 0x0074, 0x0000, + 0x0030, 0x3FC0, 0x3EFC, 0x0B5C, 0x0758, 0x3DF0, 0x0070, 0x0000, + 0x002C, 0x3FCC, 0x3EE4, 0x0B34, 0x0794, 0x3DF4, 0x0068, 0x0000, + 0x002C, 0x3FDC, 0x3ECC, 0x0B08, 0x07CC, 0x3DF4, 0x0064, 0x0000, + 0x0028, 0x3FE4, 0x3EB4, 0x0AE0, 0x0808, 0x3DF8, 0x0060, 0x0000, + 0x0024, 0x3FF0, 0x3EA0, 0x0AB0, 0x0840, 0x3E00, 0x0058, 0x0004, + 0x0020, 0x3FFC, 0x3E90, 0x0A84, 0x0878, 0x3E04, 0x0050, 0x0004, + 0x001C, 0x0004, 0x3E7C, 0x0A54, 0x08B0, 0x3E0C, 0x004C, 0x0008, + 0x0018, 0x000C, 0x3E68, 0x0A28, 0x08E8, 0x3E18, 0x0044, 0x0008, + 0x0018, 0x0018, 0x3E54, 0x09F4, 0x0920, 0x3E20, 0x003C, 0x000C, + 0x0014, 0x0020, 0x3E48, 0x09C0, 0x0954, 0x3E2C, 0x0034, 0x0010, + 0x0010, 0x002C, 0x3E3C, 0x098C, 0x0988, 0x3E38, 0x002C, 0x0010 +}; + +//========================================= +// = 8 +// = 64 +// = 1.49999 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_8tap_64p_149[264] = { + 0x0008, 0x3E8C, 0x03F8, 0x0AE8, 0x03F8, 0x3E8C, 0x0008, 0x0000, + 0x000C, 0x3E8C, 0x03D0, 0x0AE8, 0x0420, 0x3E90, 0x0000, 0x0000, + 0x000C, 0x3E8C, 0x03AC, 0x0AE8, 0x0444, 0x3E90, 0x0000, 0x0000, + 0x0010, 0x3E90, 0x0384, 0x0AE0, 0x046C, 0x3E94, 0x3FFC, 0x0000, + 0x0014, 0x3E90, 0x035C, 0x0ADC, 0x0494, 0x3E94, 0x3FF8, 0x0004, + 0x0018, 0x3E90, 0x0334, 0x0AD8, 0x04BC, 0x3E98, 0x3FF4, 0x0004, + 0x001C, 0x3E94, 0x0310, 0x0AD0, 0x04E4, 0x3E9C, 0x3FEC, 0x0004, + 0x0020, 0x3E98, 0x02E8, 0x0AC4, 0x050C, 0x3EA0, 0x3FE8, 0x0008, + 0x0020, 0x3E98, 0x02C4, 0x0AC0, 0x0534, 0x3EA4, 0x3FE4, 0x0008, + 0x0024, 0x3E9C, 0x02A0, 0x0AB4, 0x055C, 0x3EAC, 0x3FDC, 0x0008, + 0x0024, 0x3EA0, 0x027C, 0x0AA8, 0x0584, 0x3EB0, 0x3FD8, 0x000C, + 0x0028, 0x3EA4, 0x0258, 0x0A9C, 0x05AC, 0x3EB8, 0x3FD0, 0x000C, + 0x0028, 0x3EA8, 0x0234, 0x0A90, 0x05D4, 0x3EC0, 0x3FC8, 0x0010, + 0x002C, 0x3EAC, 0x0210, 0x0A80, 0x05FC, 0x3EC8, 0x3FC4, 0x0010, + 0x002C, 0x3EB4, 0x01F0, 0x0A70, 0x0624, 0x3ED0, 0x3FBC, 0x0010, + 0x002C, 0x3EB8, 0x01CC, 0x0A60, 0x064C, 0x3EDC, 0x3FB4, 0x0014, + 0x0030, 0x3EBC, 0x01A8, 0x0A50, 0x0674, 0x3EE4, 0x3FB0, 0x0014, + 0x0030, 0x3EC4, 0x0188, 0x0A38, 0x069C, 0x3EF0, 0x3FA8, 0x0018, + 0x0030, 0x3ECC, 0x0168, 0x0A28, 0x06C0, 0x3EFC, 0x3FA0, 0x0018, + 0x0030, 0x3ED0, 0x0148, 0x0A14, 0x06E8, 0x3F08, 0x3F98, 0x001C, + 0x0030, 0x3ED8, 0x012C, 0x0A00, 0x070C, 0x3F14, 0x3F90, 0x001C, + 0x0034, 0x3EE0, 0x0108, 0x09E4, 0x0734, 0x3F24, 0x3F8C, 0x001C, + 0x0034, 0x3EE4, 0x00EC, 0x09CC, 0x0758, 0x3F34, 0x3F84, 0x0020, + 0x0034, 0x3EEC, 0x00D0, 0x09B8, 0x077C, 0x3F40, 0x3F7C, 0x0020, + 0x0034, 0x3EF4, 0x00B4, 0x0998, 0x07A4, 0x3F50, 0x3F74, 0x0024, + 0x0030, 0x3EFC, 0x0098, 0x0980, 0x07C8, 0x3F64, 0x3F6C, 0x0024, + 0x0030, 0x3F04, 0x0080, 0x0968, 0x07E8, 0x3F74, 0x3F64, 0x0024, + 0x0030, 0x3F0C, 0x0060, 0x094C, 0x080C, 0x3F88, 0x3F5C, 0x0028, + 0x0030, 0x3F14, 0x0048, 0x0930, 0x0830, 0x3F98, 0x3F54, 0x0028, + 0x0030, 0x3F1C, 0x0030, 0x0914, 0x0850, 0x3FAC, 0x3F4C, 0x0028, + 0x0030, 0x3F24, 0x0018, 0x08F0, 0x0874, 0x3FC0, 0x3F44, 0x002C, + 0x002C, 0x3F2C, 0x0000, 0x08D4, 0x0894, 0x3FD8, 0x3F3C, 0x002C, + 0x002C, 0x3F34, 0x3FEC, 0x08B4, 0x08B4, 0x3FEC, 0x3F34, 0x002C +}; + +//========================================= +// = 8 +// = 64 +// = 1.83332 (input/output) +// = 0 +// = ModifiedLanczos +// = 1.10 +// = 1.12 +//========================================= +static const uint16_t filter_8tap_64p_183[264] = { + 0x3F88, 0x0048, 0x047C, 0x0768, 0x047C, 0x0048, 0x3F88, 0x0000, + 0x3F88, 0x003C, 0x0468, 0x076C, 0x0490, 0x0054, 0x3F84, 0x0000, + 0x3F8C, 0x0034, 0x0454, 0x0768, 0x04A4, 0x005C, 0x3F84, 0x0000, + 0x3F8C, 0x0028, 0x0444, 0x076C, 0x04B4, 0x0068, 0x3F80, 0x0000, + 0x3F90, 0x0020, 0x042C, 0x0768, 0x04C8, 0x0074, 0x3F80, 0x0000, + 0x3F90, 0x0018, 0x041C, 0x0764, 0x04DC, 0x0080, 0x3F7C, 0x0000, + 0x3F94, 0x0010, 0x0408, 0x075C, 0x04F0, 0x008C, 0x3F7C, 0x0000, + 0x3F94, 0x0004, 0x03F8, 0x0760, 0x0500, 0x0098, 0x3F7C, 0x3FFC, + 0x3F98, 0x0000, 0x03E0, 0x075C, 0x0514, 0x00A4, 0x3F78, 0x3FFC, + 0x3F9C, 0x3FF8, 0x03CC, 0x0754, 0x0528, 0x00B0, 0x3F78, 0x3FFC, + 0x3F9C, 0x3FF0, 0x03B8, 0x0754, 0x0538, 0x00BC, 0x3F78, 0x3FFC, + 0x3FA0, 0x3FE8, 0x03A4, 0x0750, 0x054C, 0x00CC, 0x3F74, 0x3FF8, + 0x3FA4, 0x3FE0, 0x0390, 0x074C, 0x055C, 0x00D8, 0x3F74, 0x3FF8, + 0x3FA4, 0x3FDC, 0x037C, 0x0744, 0x0570, 0x00E4, 0x3F74, 0x3FF8, + 0x3FA8, 0x3FD4, 0x0368, 0x0740, 0x0580, 0x00F4, 0x3F74, 0x3FF4, + 0x3FA8, 0x3FCC, 0x0354, 0x073C, 0x0590, 0x0104, 0x3F74, 0x3FF4, + 0x3FAC, 0x3FC8, 0x0340, 0x0730, 0x05A4, 0x0110, 0x3F74, 0x3FF4, + 0x3FB0, 0x3FC0, 0x0330, 0x0728, 0x05B4, 0x0120, 0x3F74, 0x3FF0, + 0x3FB0, 0x3FBC, 0x031C, 0x0724, 0x05C4, 0x0130, 0x3F70, 0x3FF0, + 0x3FB4, 0x3FB4, 0x0308, 0x0720, 0x05D4, 0x013C, 0x3F70, 0x3FF0, + 0x3FB8, 0x3FB0, 0x02F4, 0x0714, 0x05E4, 0x014C, 0x3F74, 0x3FEC, + 0x3FB8, 0x3FAC, 0x02E0, 0x0708, 0x05F8, 0x015C, 0x3F74, 0x3FEC, + 0x3FBC, 0x3FA8, 0x02CC, 0x0704, 0x0604, 0x016C, 0x3F74, 0x3FE8, + 0x3FC0, 0x3FA0, 0x02BC, 0x06F8, 0x0614, 0x017C, 0x3F74, 0x3FE8, + 0x3FC0, 0x3F9C, 0x02A8, 0x06F4, 0x0624, 0x018C, 0x3F74, 0x3FE4, + 0x3FC4, 0x3F98, 0x0294, 0x06E8, 0x0634, 0x019C, 0x3F74, 0x3FE4, + 0x3FC8, 0x3F94, 0x0284, 0x06D8, 0x0644, 0x01AC, 0x3F78, 0x3FE0, + 0x3FC8, 0x3F90, 0x0270, 0x06D4, 0x0650, 0x01BC, 0x3F78, 0x3FE0, + 0x3FCC, 0x3F8C, 0x025C, 0x06C8, 0x0660, 0x01D0, 0x3F78, 0x3FDC, + 0x3FCC, 0x3F8C, 0x024C, 0x06B8, 0x066C, 0x01E0, 0x3F7C, 0x3FDC, + 0x3FD0, 0x3F88, 0x0238, 0x06B0, 0x067C, 0x01F0, 0x3F7C, 0x3FD8, + 0x3FD4, 0x3F84, 0x0228, 0x069C, 0x0688, 0x0204, 0x3F80, 0x3FD8, + 0x3FD4, 0x3F84, 0x0214, 0x0694, 0x0694, 0x0214, 0x3F84, 0x3FD4 +}; + +static const uint16_t *spl_get_filter_3tap_64p(struct spl_fixed31_32 ratio) +{ + if (ratio.value < spl_fixpt_one.value) + return filter_3tap_64p_upscale; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 3)).value) + return filter_3tap_64p_116; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 3)).value) + return filter_3tap_64p_149; + else + return filter_3tap_64p_183; +} + +static const uint16_t *spl_get_filter_4tap_64p(struct spl_fixed31_32 ratio) +{ + if (ratio.value < spl_fixpt_one.value) + return filter_4tap_64p_upscale; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 3)).value) + return filter_4tap_64p_116; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 3)).value) + return filter_4tap_64p_149; + else + return filter_4tap_64p_183; +} + +static const uint16_t *spl_get_filter_5tap_64p(struct spl_fixed31_32 ratio) +{ + if (ratio.value < spl_fixpt_one.value) + return filter_5tap_64p_upscale; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 3)).value) + return filter_5tap_64p_116; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 3)).value) + return filter_5tap_64p_149; + else + return filter_5tap_64p_183; +} + +static const uint16_t *spl_get_filter_6tap_64p(struct spl_fixed31_32 ratio) +{ + if (ratio.value < spl_fixpt_one.value) + return filter_6tap_64p_upscale; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 3)).value) + return filter_6tap_64p_116; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 3)).value) + return filter_6tap_64p_149; + else + return filter_6tap_64p_183; +} + +static const uint16_t *spl_get_filter_7tap_64p(struct spl_fixed31_32 ratio) +{ + if (ratio.value < spl_fixpt_one.value) + return filter_7tap_64p_upscale; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 3)).value) + return filter_7tap_64p_116; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 3)).value) + return filter_7tap_64p_149; + else + return filter_7tap_64p_183; +} + +static const uint16_t *spl_get_filter_8tap_64p(struct spl_fixed31_32 ratio) +{ + if (ratio.value < spl_fixpt_one.value) + return filter_8tap_64p_upscale; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 3)).value) + return filter_8tap_64p_116; + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 3)).value) + return filter_8tap_64p_149; + else + return filter_8tap_64p_183; +} + +static const uint16_t *spl_get_filter_2tap_64p(void) +{ + return filter_2tap_64p; +} + +const uint16_t *SPL_NAMESPACE(spl_dscl_get_filter_coeffs_64p( + int taps, struct spl_fixed31_32 ratio)) +{ + if (taps == 8) + return spl_get_filter_8tap_64p(ratio); + else if (taps == 7) + return spl_get_filter_7tap_64p(ratio); + else if (taps == 6) + return spl_get_filter_6tap_64p(ratio); + else if (taps == 5) + return spl_get_filter_5tap_64p(ratio); + else if (taps == 4) + return spl_get_filter_4tap_64p(ratio); + else if (taps == 3) + return spl_get_filter_3tap_64p(ratio); + else if (taps == 2) + return spl_get_filter_2tap_64p(); + else if (taps == 1) + return NULL; + else { + /* should never happen, bug */ + SPL_BREAK_TO_DEBUGGER(); + return NULL; + } +} diff --git a/src/amd/vpelib/src/imported/SPL/dc_spl_scl_filters.h b/src/amd/vpelib/src/imported/SPL/dc_spl_scl_filters.h new file mode 100644 index 00000000000..445d626863c --- /dev/null +++ b/src/amd/vpelib/src/imported/SPL/dc_spl_scl_filters.h @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2024 Advanced Micro Devices, Inc. + +#ifndef __DC_SPL_SCL_FILTERS_H__ +#define __DC_SPL_SCL_FILTERS_H__ + +#include "dc_spl_types.h" + +/* public API */ +const uint16_t *SPL_NAMESPACE(spl_dscl_get_filter_coeffs_64p( + int taps, struct spl_fixed31_32 ratio)); + +#endif /* __DC_SPL_SCL_FILTERS_H__ */ diff --git a/src/amd/vpelib/src/imported/SPL/dc_spl_types.h b/src/amd/vpelib/src/imported/SPL/dc_spl_types.h new file mode 100644 index 00000000000..9ad8f2e0ebc --- /dev/null +++ b/src/amd/vpelib/src/imported/SPL/dc_spl_types.h @@ -0,0 +1,624 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2024 Advanced Micro Devices, Inc. + +#ifndef __DC_SPL_TYPES_H__ +#define __DC_SPL_TYPES_H__ + +#include "spl_debug.h" +#include "spl_os_types.h" // swap +#include "spl_fixpt31_32.h" // fixed31_32 and related functions +#include "spl_custom_float.h" // custom float and related functions + +struct spl_size { + uint32_t width; + uint32_t height; +}; +struct spl_rect { + int x; + int y; + int width; + int height; +}; + +struct spl_ratios { + struct spl_fixed31_32 horz; + struct spl_fixed31_32 vert; + struct spl_fixed31_32 horz_c; + struct spl_fixed31_32 vert_c; +}; +struct spl_inits { + struct spl_fixed31_32 h; + struct spl_fixed31_32 h_c; + struct spl_fixed31_32 v; + struct spl_fixed31_32 v_c; +}; + +struct spl_taps { + uint32_t v_taps; + uint32_t h_taps; + uint32_t v_taps_c; + uint32_t h_taps_c; + bool integer_scaling; +}; +enum spl_view_3d { + SPL_VIEW_3D_NONE = 0, + SPL_VIEW_3D_FRAME_SEQUENTIAL, + SPL_VIEW_3D_SIDE_BY_SIDE, + SPL_VIEW_3D_TOP_AND_BOTTOM, + SPL_VIEW_3D_COUNT, + SPL_VIEW_3D_FIRST = SPL_VIEW_3D_FRAME_SEQUENTIAL +}; +/* Pixel format */ +enum spl_pixel_format { + /*graph*/ + SPL_PIXEL_FORMAT_UNINITIALIZED, + SPL_PIXEL_FORMAT_INDEX8, + SPL_PIXEL_FORMAT_RGB565, + SPL_PIXEL_FORMAT_ARGB8888, + SPL_PIXEL_FORMAT_ARGB2101010, + SPL_PIXEL_FORMAT_ARGB2101010_XRBIAS, + SPL_PIXEL_FORMAT_FP16, + /*video*/ + SPL_PIXEL_FORMAT_420BPP8, + SPL_PIXEL_FORMAT_420BPP10, +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) + SPL_PIXEL_FORMAT_422BPP8, + SPL_PIXEL_FORMAT_422BPP10, + SPL_PIXEL_FORMAT_422BPP12, + SPL_PIXEL_FORMAT_444BPP8, + SPL_PIXEL_FORMAT_444BPP10, +#endif + /*end of pixel format definition*/ + SPL_PIXEL_FORMAT_GRPH_BEGIN = SPL_PIXEL_FORMAT_INDEX8, + SPL_PIXEL_FORMAT_GRPH_END = SPL_PIXEL_FORMAT_FP16, + SPL_PIXEL_FORMAT_SUBSAMPLED_BEGIN = SPL_PIXEL_FORMAT_420BPP8, +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) + SPL_PIXEL_FORMAT_SUBSAMPLED_END = SPL_PIXEL_FORMAT_422BPP12, +#else + SPL_PIXEL_FORMAT_SUBSAMPLED_END = SPL_PIXEL_FORMAT_420BPP10, +#endif + SPL_PIXEL_FORMAT_VIDEO_BEGIN = SPL_PIXEL_FORMAT_420BPP8, +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) + SPL_PIXEL_FORMAT_VIDEO_END = SPL_PIXEL_FORMAT_444BPP10, +#else + SPL_PIXEL_FORMAT_VIDEO_END = SPL_PIXEL_FORMAT_420BPP10, +#endif + SPL_PIXEL_FORMAT_INVALID, + SPL_PIXEL_FORMAT_UNKNOWN +}; +enum lb_memory_config { + /* Enable all 3 pieces of memory */ + LB_MEMORY_CONFIG_0 = 0, + + /* Enable only the first piece of memory */ + LB_MEMORY_CONFIG_1 = 1, + + /* Enable only the second piece of memory */ + LB_MEMORY_CONFIG_2 = 2, + + /* Only applicable in 4:2:0 mode, enable all 3 pieces of memory and the + * last piece of chroma memory used for the luma storage + */ + LB_MEMORY_CONFIG_3 = 3 +}; +/* Rotation angle */ +enum spl_rotation_angle { + SPL_ROTATION_ANGLE_0 = 0, + SPL_ROTATION_ANGLE_90, + SPL_ROTATION_ANGLE_180, + SPL_ROTATION_ANGLE_270, + SPL_ROTATION_ANGLE_COUNT +}; +enum spl_color_space { + SPL_COLOR_SPACE_UNKNOWN, + SPL_COLOR_SPACE_SRGB, + SPL_COLOR_SPACE_XR_RGB, + SPL_COLOR_SPACE_SRGB_LIMITED, + SPL_COLOR_SPACE_MSREF_SCRGB, + SPL_COLOR_SPACE_YCBCR601, + SPL_COLOR_SPACE_YCBCR709, + SPL_COLOR_SPACE_XV_YCC_709, + SPL_COLOR_SPACE_XV_YCC_601, + SPL_COLOR_SPACE_YCBCR601_LIMITED, + SPL_COLOR_SPACE_YCBCR709_LIMITED, + SPL_COLOR_SPACE_2020_RGB_FULLRANGE, + SPL_COLOR_SPACE_2020_RGB_LIMITEDRANGE, + SPL_COLOR_SPACE_2020_YCBCR, + SPL_COLOR_SPACE_ADOBERGB, + SPL_COLOR_SPACE_DCIP3, + SPL_COLOR_SPACE_DISPLAYNATIVE, + SPL_COLOR_SPACE_DOLBYVISION, + SPL_COLOR_SPACE_APPCTRL, + SPL_COLOR_SPACE_CUSTOMPOINTS, + SPL_COLOR_SPACE_YCBCR709_BLACK, +}; + +enum chroma_cositing { + CHROMA_COSITING_NONE, + CHROMA_COSITING_LEFT, + CHROMA_COSITING_TOPLEFT, + CHROMA_COSITING_COUNT +}; +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) + +enum upsp_mode { + UPSP_BYPASS = 0, + UPSP_HORIZONTAL_UPSAMPLING_ONLY, + UPSP_VERTICAL_UPSAMPLING_ONLY, + UPSP_HORIZONTAL_VERTICAL_UPSAMPLING +}; + +enum upsp_num_taps { + UPSP_2_TAPS, + UPSP_4_TAPS +}; + +enum upsp_boundary_mode { + UPSP_BOUNDARY_EDGE, //Replace out of bound samples with the edge samples + UPSP_BOUNDARY_BLACK //Replace out of bound samples with black as 12bpc(0x800) +}; +#endif + +// Scratch space for calculating scaler params +struct spl_scaler_data { + int h_active; + int v_active; + struct spl_taps taps; + struct spl_rect viewport; + struct spl_rect viewport_c; + struct spl_rect recout; + struct spl_ratios ratios; + struct spl_ratios recip_ratios; + struct spl_inits inits; +}; + +enum spl_transfer_func_type { + SPL_TF_TYPE_PREDEFINED, + SPL_TF_TYPE_DISTRIBUTED_POINTS, + SPL_TF_TYPE_BYPASS, + SPL_TF_TYPE_HWPWL +}; + +enum spl_transfer_func_predefined { + SPL_TRANSFER_FUNCTION_SRGB, + SPL_TRANSFER_FUNCTION_BT709, + SPL_TRANSFER_FUNCTION_PQ, + SPL_TRANSFER_FUNCTION_LINEAR, + SPL_TRANSFER_FUNCTION_UNITY, + SPL_TRANSFER_FUNCTION_HLG, + SPL_TRANSFER_FUNCTION_HLG12, + SPL_TRANSFER_FUNCTION_GAMMA22, + SPL_TRANSFER_FUNCTION_GAMMA24, + SPL_TRANSFER_FUNCTION_GAMMA26 +}; + +/*==============================================================*/ +/* Below structs are defined to hold hw register data */ + +// SPL output is used to set below registers + +// MPC_SIZE - set based on scl_data h_active and v_active +struct mpc_size { + uint32_t width; + uint32_t height; +}; +// SCL_MODE - set based on scl_data.ratios and always_scale +enum scl_mode { + SCL_MODE_SCALING_444_BYPASS = 0, + SCL_MODE_SCALING_444_RGB_ENABLE = 1, + SCL_MODE_SCALING_444_YCBCR_ENABLE = 2, + SCL_MODE_SCALING_420_YCBCR_ENABLE = 3, + SCL_MODE_SCALING_420_LUMA_BYPASS = 4, + SCL_MODE_SCALING_420_CHROMA_BYPASS = 5, + SCL_MODE_DSCL_BYPASS = 6 +}; +// SCL_BLACK_COLOR - set based on scl_data.format +struct scl_black_color { + uint32_t offset_rgb_y; + uint32_t offset_rgb_cbcr; +}; +// RATIO - set based on scl_data.ratios +struct ratio { + uint32_t h_scale_ratio; + uint32_t v_scale_ratio; + uint32_t h_scale_ratio_c; + uint32_t v_scale_ratio_c; +}; + +// INIT - set based on scl_data.init +struct init { + // SCL_HORZ_FILTER_INIT + uint32_t h_filter_init_frac; // SCL_H_INIT_FRAC + uint32_t h_filter_init_int; // SCL_H_INIT_INT + // SCL_HORZ_FILTER_INIT_C + uint32_t h_filter_init_frac_c; // SCL_H_INIT_FRAC_C + uint32_t h_filter_init_int_c; // SCL_H_INIT_INT_C + // SCL_VERT_FILTER_INIT + uint32_t v_filter_init_frac; // SCL_V_INIT_FRAC + uint32_t v_filter_init_int; // SCL_V_INIT_INT + // SCL_VERT_FILTER_INIT_C + uint32_t v_filter_init_frac_c; // SCL_V_INIT_FRAC_C + uint32_t v_filter_init_int_c; // SCL_V_INIT_INT_C + // SCL_VERT_FILTER_INIT_BOT + uint32_t v_filter_init_bot_frac; // SCL_V_INIT_FRAC_BOT + uint32_t v_filter_init_bot_int; // SCL_V_INIT_INT_BOT + // SCL_VERT_FILTER_INIT_BOT_C + uint32_t v_filter_init_bot_frac_c; // SCL_V_INIT_FRAC_BOT_C + uint32_t v_filter_init_bot_int_c; // SCL_V_INIT_INT_BOT_C +}; + +// FILTER - calculated based on scl_data ratios and taps + +// iSHARP +struct isharp_noise_det { + uint32_t enable; // ISHARP_NOISEDET_EN + uint32_t mode; // ISHARP_NOISEDET_MODE + uint32_t uthreshold; // ISHARP_NOISEDET_UTHRE + uint32_t dthreshold; // ISHARP_NOISEDET_DTHRE + uint32_t pwl_start_in; // ISHARP_NOISEDET_PWL_START_IN + uint32_t pwl_end_in; // ISHARP_NOISEDET_PWL_END_IN + uint32_t pwl_slope; // ISHARP_NOISEDET_PWL_SLOPE +}; +struct isharp_lba { + uint32_t mode; // ISHARP_LBA_MODE + uint32_t in_seg[6]; + uint32_t base_seg[6]; + uint32_t slope_seg[6]; +}; +struct isharp_fmt { + uint32_t mode; // ISHARP_FMT_MODE + uint32_t norm; // ISHARP_FMT_NORM +}; +struct isharp_nldelta_sclip { + uint32_t enable_p; // ISHARP_NLDELTA_SCLIP_EN_P + uint32_t pivot_p; // ISHARP_NLDELTA_SCLIP_PIVOT_P + uint32_t slope_p; // ISHARP_NLDELTA_SCLIP_SLOPE_P + uint32_t enable_n; // ISHARP_NLDELTA_SCLIP_EN_N + uint32_t pivot_n; // ISHARP_NLDELTA_SCLIP_PIVOT_N + uint32_t slope_n; // ISHARP_NLDELTA_SCLIP_SLOPE_N +}; +enum isharp_en { + ISHARP_DISABLE, + ISHARP_ENABLE +}; +#define ISHARP_LUT_TABLE_SIZE 32 +// Below struct holds values that can be directly used to program +// hardware registers. No conversion/clamping is required +struct dscl_prog_data { + struct spl_rect recout; // RECOUT - set based on scl_data.recout + struct mpc_size mpc_size; + uint32_t dscl_mode; + struct scl_black_color scl_black_color; + struct ratio ratios; + struct init init; + struct spl_taps taps; // TAPS - set based on scl_data.taps + struct spl_rect viewport; + struct spl_rect viewport_c; + // raw filter + const uint16_t *filter_h; + const uint16_t *filter_v; + const uint16_t *filter_h_c; + const uint16_t *filter_v_c; + // EASF registers + uint32_t easf_matrix_mode; + uint32_t easf_ltonl_en; + uint32_t easf_v_en; + uint32_t easf_v_sharp_factor; + uint32_t easf_v_ring; + uint32_t easf_v_bf1_en; + uint32_t easf_v_bf2_mode; + uint32_t easf_v_bf3_mode; + uint32_t easf_v_bf2_flat1_gain; + uint32_t easf_v_bf2_flat2_gain; + uint32_t easf_v_bf2_roc_gain; + uint32_t easf_v_ringest_3tap_dntilt_uptilt; + uint32_t easf_v_ringest_3tap_uptilt_max; + uint32_t easf_v_ringest_3tap_dntilt_slope; + uint32_t easf_v_ringest_3tap_uptilt1_slope; + uint32_t easf_v_ringest_3tap_uptilt2_slope; + uint32_t easf_v_ringest_3tap_uptilt2_offset; + uint32_t easf_v_ringest_eventap_reduceg1; + uint32_t easf_v_ringest_eventap_reduceg2; + uint32_t easf_v_ringest_eventap_gain1; + uint32_t easf_v_ringest_eventap_gain2; + uint32_t easf_v_bf_maxa; + uint32_t easf_v_bf_maxb; + uint32_t easf_v_bf_mina; + uint32_t easf_v_bf_minb; + uint32_t easf_v_bf1_pwl_in_seg0; + uint32_t easf_v_bf1_pwl_base_seg0; + uint32_t easf_v_bf1_pwl_slope_seg0; + uint32_t easf_v_bf1_pwl_in_seg1; + uint32_t easf_v_bf1_pwl_base_seg1; + uint32_t easf_v_bf1_pwl_slope_seg1; + uint32_t easf_v_bf1_pwl_in_seg2; + uint32_t easf_v_bf1_pwl_base_seg2; + uint32_t easf_v_bf1_pwl_slope_seg2; + uint32_t easf_v_bf1_pwl_in_seg3; + uint32_t easf_v_bf1_pwl_base_seg3; + uint32_t easf_v_bf1_pwl_slope_seg3; + uint32_t easf_v_bf1_pwl_in_seg4; + uint32_t easf_v_bf1_pwl_base_seg4; + uint32_t easf_v_bf1_pwl_slope_seg4; + uint32_t easf_v_bf1_pwl_in_seg5; + uint32_t easf_v_bf1_pwl_base_seg5; + uint32_t easf_v_bf1_pwl_slope_seg5; + uint32_t easf_v_bf1_pwl_in_seg6; + uint32_t easf_v_bf1_pwl_base_seg6; + uint32_t easf_v_bf1_pwl_slope_seg6; + uint32_t easf_v_bf1_pwl_in_seg7; + uint32_t easf_v_bf1_pwl_base_seg7; + uint32_t easf_v_bf3_pwl_in_set0; + uint32_t easf_v_bf3_pwl_base_set0; + uint32_t easf_v_bf3_pwl_slope_set0; + uint32_t easf_v_bf3_pwl_in_set1; + uint32_t easf_v_bf3_pwl_base_set1; + uint32_t easf_v_bf3_pwl_slope_set1; + uint32_t easf_v_bf3_pwl_in_set2; + uint32_t easf_v_bf3_pwl_base_set2; + uint32_t easf_v_bf3_pwl_slope_set2; + uint32_t easf_v_bf3_pwl_in_set3; + uint32_t easf_v_bf3_pwl_base_set3; + uint32_t easf_v_bf3_pwl_slope_set3; + uint32_t easf_v_bf3_pwl_in_set4; + uint32_t easf_v_bf3_pwl_base_set4; + uint32_t easf_v_bf3_pwl_slope_set4; + uint32_t easf_v_bf3_pwl_in_set5; + uint32_t easf_v_bf3_pwl_base_set5; + uint32_t easf_h_en; + uint32_t easf_h_sharp_factor; + uint32_t easf_h_ring; + uint32_t easf_h_bf1_en; + uint32_t easf_h_bf2_mode; + uint32_t easf_h_bf3_mode; + uint32_t easf_h_bf2_flat1_gain; + uint32_t easf_h_bf2_flat2_gain; + uint32_t easf_h_bf2_roc_gain; + uint32_t easf_h_ringest_eventap_reduceg1; + uint32_t easf_h_ringest_eventap_reduceg2; + uint32_t easf_h_ringest_eventap_gain1; + uint32_t easf_h_ringest_eventap_gain2; + uint32_t easf_h_bf_maxa; + uint32_t easf_h_bf_maxb; + uint32_t easf_h_bf_mina; + uint32_t easf_h_bf_minb; + uint32_t easf_h_bf1_pwl_in_seg0; + uint32_t easf_h_bf1_pwl_base_seg0; + uint32_t easf_h_bf1_pwl_slope_seg0; + uint32_t easf_h_bf1_pwl_in_seg1; + uint32_t easf_h_bf1_pwl_base_seg1; + uint32_t easf_h_bf1_pwl_slope_seg1; + uint32_t easf_h_bf1_pwl_in_seg2; + uint32_t easf_h_bf1_pwl_base_seg2; + uint32_t easf_h_bf1_pwl_slope_seg2; + uint32_t easf_h_bf1_pwl_in_seg3; + uint32_t easf_h_bf1_pwl_base_seg3; + uint32_t easf_h_bf1_pwl_slope_seg3; + uint32_t easf_h_bf1_pwl_in_seg4; + uint32_t easf_h_bf1_pwl_base_seg4; + uint32_t easf_h_bf1_pwl_slope_seg4; + uint32_t easf_h_bf1_pwl_in_seg5; + uint32_t easf_h_bf1_pwl_base_seg5; + uint32_t easf_h_bf1_pwl_slope_seg5; + uint32_t easf_h_bf1_pwl_in_seg6; + uint32_t easf_h_bf1_pwl_base_seg6; + uint32_t easf_h_bf1_pwl_slope_seg6; + uint32_t easf_h_bf1_pwl_in_seg7; + uint32_t easf_h_bf1_pwl_base_seg7; + uint32_t easf_h_bf3_pwl_in_set0; + uint32_t easf_h_bf3_pwl_base_set0; + uint32_t easf_h_bf3_pwl_slope_set0; + uint32_t easf_h_bf3_pwl_in_set1; + uint32_t easf_h_bf3_pwl_base_set1; + uint32_t easf_h_bf3_pwl_slope_set1; + uint32_t easf_h_bf3_pwl_in_set2; + uint32_t easf_h_bf3_pwl_base_set2; + uint32_t easf_h_bf3_pwl_slope_set2; + uint32_t easf_h_bf3_pwl_in_set3; + uint32_t easf_h_bf3_pwl_base_set3; + uint32_t easf_h_bf3_pwl_slope_set3; + uint32_t easf_h_bf3_pwl_in_set4; + uint32_t easf_h_bf3_pwl_base_set4; + uint32_t easf_h_bf3_pwl_slope_set4; + uint32_t easf_h_bf3_pwl_in_set5; + uint32_t easf_h_bf3_pwl_base_set5; + uint32_t easf_matrix_c0; + uint32_t easf_matrix_c1; + uint32_t easf_matrix_c2; + uint32_t easf_matrix_c3; +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) + // UPSP registers + uint32_t upsp_mode;//UPSP_MODE + uint32_t upsp_v_num_taps; + uint32_t upsp_v_init_int; + uint32_t upsp_v_init_frac; + uint32_t upsp_h_num_taps; + uint32_t upsp_h_init_int; + uint32_t upsp_h_init_frac; + uint32_t upsp_boundary_mode; + uint32_t upsp_v_coef_tap0_p0;//UPSP_V_COEF_P0 + uint32_t upsp_v_coef_tap1_p0; + uint32_t upsp_v_coef_tap2_p0; + uint32_t upsp_v_coef_tap3_p0; + uint32_t upsp_v_coef_tap0_p1;//UPSP_V_COEF_P1 + uint32_t upsp_v_coef_tap1_p1; + uint32_t upsp_v_coef_tap2_p1; + uint32_t upsp_v_coef_tap3_p1; + uint32_t upsp_h_coef_tap0_p0;//UPSP_H_COEF_P0 + uint32_t upsp_h_coef_tap1_p0; + uint32_t upsp_h_coef_tap2_p0; + uint32_t upsp_h_coef_tap3_p0; + uint32_t upsp_h_coef_tap0_p1;//UPSP_H_COEF_P1 + uint32_t upsp_h_coef_tap1_p1; + uint32_t upsp_h_coef_tap2_p1; + uint32_t upsp_h_coef_tap3_p1; + uint32_t upsp_clamp_max;//UPSP_CLAMP + uint32_t upsp_clamp_min; +#endif + // iSharp + uint32_t isharp_en; // ISHARP_EN + struct isharp_noise_det isharp_noise_det; // ISHARP_NOISEDET + uint32_t isharp_nl_en; // ISHARP_NL_EN ? TODO:check this + struct isharp_lba isharp_lba; // ISHARP_LBA + struct isharp_fmt isharp_fmt; // ISHARP_FMT + uint32_t isharp_delta[ISHARP_LUT_TABLE_SIZE]; + struct isharp_nldelta_sclip isharp_nldelta_sclip; // ISHARP_NLDELTA_SCLIP + /* blur and scale filter */ + const uint16_t *filter_blur_scale_v; + const uint16_t *filter_blur_scale_h; + int sharpness_level; /* Track sharpness level */ +}; + +/* SPL input and output definitions */ +// SPL scratch struct +struct spl_scratch { + // Pack all SPL outputs in scl_data + struct spl_scaler_data scl_data; +}; + +/* SPL input and output definitions */ +// SPL outputs struct +struct spl_out { + // Pack all output need to program hw registers + struct dscl_prog_data *dscl_prog_data; +}; + +// end of SPL outputs + +// SPL inputs + +// opp extra adjustment for rect +struct spl_opp_adjust { + int x; + int y; + int width; + int height; +}; + +// Basic input information +struct basic_in { + enum spl_pixel_format format; // Pixel Format + enum chroma_cositing cositing; /* Chroma Subsampling Offset */ + struct spl_rect src_rect; // Source rect + struct spl_rect dst_rect; // Destination Rect + struct spl_rect clip_rect; // Clip rect + enum spl_rotation_angle rotation; // Rotation + bool horizontal_mirror; // Horizontal mirror + struct { // previous mpc_combine_h - split count + bool use_recout_width_aligned; + union { + int mpc_num_h_slices; + int mpc_recout_width_align; + } num_slices_recout_width; + } num_h_slices_recout_width_align; + int mpc_h_slice_index; // previous mpc_combine_v - split_idx + struct spl_opp_adjust opp_recout_adjust; + // Inputs for adaptive scaler - TODO + enum spl_transfer_func_type tf_type; /* Transfer function type */ + enum spl_transfer_func_predefined tf_predefined_type; /* Transfer function predefined type */ + // enum dc_transfer_func_predefined tf; + enum spl_color_space color_space; // Color Space + unsigned int max_luminance; // Max Luminance TODO: Is determined in dc_hw_sequencer.c is_sdr + bool film_grain_applied; // Film Grain Applied // TODO: To check from where to get this? + int custom_width; // Width for non-standard segmentation - used when != 0 + int custom_x; // Start x for non-standard segmentation - used when custom_width != 0 +}; + +// Basic output information +struct basic_out { + struct spl_size output_size; // Output Size + struct spl_rect dst_rect; // Destination Rect + struct spl_rect src_rect; // Source rect + int odm_combine_factor; // deprecated + struct spl_rect odm_slice_rect; // OPP input rect in timing active + enum spl_view_3d view_format; // TODO: View format Check if it is chroma subsampling + bool always_scale; // Is always scale enabled? Required for getting SCL_MODE + int max_downscale_src_width; // Required to get optimal no of taps + bool alpha_en; + bool use_two_pixels_per_container; +}; +enum sharpness_setting { + SHARPNESS_HW_OFF = 0, + SHARPNESS_ZERO, + SHARPNESS_CUSTOM +}; +enum sharpness_range_source { + SHARPNESS_RANGE_DCN = 0, + SHARPNESS_RANGE_DCN_OVERRIDE +}; +struct spl_sharpness_range { + int sdr_rgb_min; + int sdr_rgb_max; + int sdr_rgb_mid; + int sdr_yuv_min; + int sdr_yuv_max; + int sdr_yuv_mid; + int hdr_rgb_min; + int hdr_rgb_max; + int hdr_rgb_mid; +}; +struct adaptive_sharpness { + bool enable; + unsigned int sharpness_level; + struct spl_sharpness_range sharpness_range; +}; +enum linear_light_scaling { // convert it in translation logic + LLS_PREF_DONT_CARE = 0, + LLS_PREF_YES, + LLS_PREF_NO +}; +enum sharpen_policy { + SHARPEN_ALWAYS = 0, + SHARPEN_YUV = 1, + SHARPEN_RGB_FULLSCREEN_YUV = 2, + SHARPEN_FULLSCREEN_ALL = 3 +}; +enum scale_to_sharpness_policy { + NO_SCALE_TO_SHARPNESS_ADJ = 0, + SCALE_TO_SHARPNESS_ADJ_YUV = 1, + SCALE_TO_SHARPNESS_ADJ_ALL = 2 +}; +struct spl_callbacks { + void (*spl_calc_lb_num_partitions) + (bool alpha_en, + const struct spl_scaler_data *scl_data, + enum lb_memory_config lb_config, + int *num_part_y, + int *num_part_c); +}; + +struct spl_debug { + unsigned int visual_confirm_base_offset; + unsigned int visual_confirm_dpp_offset; + enum scale_to_sharpness_policy scale_to_sharpness_policy; +}; + +struct spl_in { + struct basic_out basic_out; + struct basic_in basic_in; + // Basic slice information + int odm_slice_index; // ODM Slice Index using get_odm_split_index + struct spl_taps scaling_quality; // Explicit Scaling Quality + struct spl_callbacks callbacks; + // Inputs for isharp and EASF + struct adaptive_sharpness adaptive_sharpness; // Adaptive Sharpness + enum linear_light_scaling lls_pref; // Linear Light Scaling + bool prefer_easf; + bool disable_easf; + bool override_easf; /* If true, keep EASF enabled but use provided in_taps */ + struct spl_debug debug; + bool is_fullscreen; + bool is_hdr_on; + int h_active; + int v_active; + int min_viewport_size; + int sdr_white_level_nits; + enum sharpen_policy sharpen_policy; +#if defined(CONFIG_DRM_AMD_DC_DCN6_0) || !defined(TRIM_SPL_VPE) + enum upsp_mode upsp_mode; +#endif +}; +// end of SPL inputs + +#endif /* __DC_SPL_TYPES_H__ */ diff --git a/src/amd/vpelib/src/imported/SPL/spl_custom_float.c b/src/amd/vpelib/src/imported/SPL/spl_custom_float.c new file mode 100644 index 00000000000..0700b3dbbda --- /dev/null +++ b/src/amd/vpelib/src/imported/SPL/spl_custom_float.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2024 Advanced Micro Devices, Inc. + +#include "spl_debug.h" +#include "spl_custom_float.h" + +static bool spl_build_custom_float(struct spl_fixed31_32 value, + const struct spl_custom_float_format *format, + bool *negative, + uint32_t *mantissa, + uint32_t *exponenta) +{ + uint32_t exp_offset = (1 << (format->exponenta_bits - 1)) - 1; + + const struct spl_fixed31_32 mantissa_constant_plus_max_fraction = + SPL_NAMESPACE(spl_fixpt_from_fraction((1LL << (format->mantissa_bits + 1)) - 1, + 1LL << format->mantissa_bits)); + + struct spl_fixed31_32 mantiss; + + if (spl_fixpt_eq(value, spl_fixpt_zero)) { + *negative = false; + *mantissa = 0; + *exponenta = 0; + return true; + } + + if (spl_fixpt_lt(value, spl_fixpt_zero)) { + *negative = format->sign; + value = spl_fixpt_neg(value); + } else { + *negative = false; + } + + if (spl_fixpt_lt(value, spl_fixpt_one)) { + uint32_t i = 1; + + do { + value = spl_fixpt_shl(value, 1); + ++i; + } while (spl_fixpt_lt(value, spl_fixpt_one)); + + --i; + + if (exp_offset <= i) { + *mantissa = 0; + *exponenta = 0; + return true; + } + + *exponenta = exp_offset - i; + } else if (spl_fixpt_le(mantissa_constant_plus_max_fraction, value)) { + uint32_t i = 1; + + do { + value = spl_fixpt_shr(value, 1); + ++i; + } while (spl_fixpt_lt(mantissa_constant_plus_max_fraction, value)); + + *exponenta = exp_offset + i - 1; + } else { + *exponenta = exp_offset; + } + + mantiss = spl_fixpt_sub(value, spl_fixpt_one); + + if (spl_fixpt_lt(mantiss, spl_fixpt_zero) || + spl_fixpt_lt(spl_fixpt_one, mantiss)) + mantiss = spl_fixpt_zero; + else + mantiss = spl_fixpt_shl(mantiss, format->mantissa_bits); + + *mantissa = spl_fixpt_floor(mantiss); + + return true; +} + +static bool spl_setup_custom_float(const struct spl_custom_float_format *format, + bool negative, + uint32_t mantissa, + uint32_t exponenta, + uint32_t *result) +{ + uint32_t i = 0; + uint32_t j = 0; + uint32_t value = 0; + + /* verification code: + * once calculation is ok we can remove it + */ + + const uint32_t mantissa_mask = + (1 << (format->mantissa_bits + 1)) - 1; + + const uint32_t exponenta_mask = + (1 << (format->exponenta_bits + 1)) - 1; + + if (mantissa & ~mantissa_mask) { + SPL_BREAK_TO_DEBUGGER(); + mantissa = mantissa_mask; + } + + if (exponenta & ~exponenta_mask) { + SPL_BREAK_TO_DEBUGGER(); + exponenta = exponenta_mask; + } + + /* end of verification code */ + + while (i < format->mantissa_bits) { + uint32_t mask = 1 << i; + + if (mantissa & mask) + value |= mask; + + ++i; + } + + while (j < format->exponenta_bits) { + uint32_t mask = 1 << j; + + if (exponenta & mask) + value |= mask << i; + + ++j; + } + + if (negative && format->sign) + value |= 1 << (i + j); + + *result = value; + + return true; +} + +bool SPL_NAMESPACE(spl_convert_to_custom_float_format( + struct spl_fixed31_32 value, + const struct spl_custom_float_format *format, + uint32_t *result)) +{ + uint32_t mantissa; + uint32_t exponenta; + bool negative; + + return spl_build_custom_float(value, format, &negative, &mantissa, &exponenta) && + spl_setup_custom_float(format, + negative, + mantissa, + exponenta, + result); +} diff --git a/src/amd/vpelib/src/imported/SPL/spl_custom_float.h b/src/amd/vpelib/src/imported/SPL/spl_custom_float.h new file mode 100644 index 00000000000..f3fd8d30e63 --- /dev/null +++ b/src/amd/vpelib/src/imported/SPL/spl_custom_float.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: MIT */ + +/* Copyright 2024 Advanced Micro Devices, Inc. */ + +#ifndef SPL_CUSTOM_FLOAT_H_ +#define SPL_CUSTOM_FLOAT_H_ + +#include "spl_os_types.h" +#include "spl_fixpt31_32.h" + +struct spl_custom_float_format { + uint32_t mantissa_bits; + uint32_t exponenta_bits; + bool sign; +}; + +struct spl_custom_float_value { + uint32_t mantissa; + uint32_t exponenta; + uint32_t value; + bool negative; +}; + +bool SPL_NAMESPACE(spl_convert_to_custom_float_format( + struct spl_fixed31_32 value, + const struct spl_custom_float_format *format, + uint32_t *result)); + +#endif //SPL_CUSTOM_FLOAT_H_ diff --git a/src/amd/vpelib/src/imported/SPL/spl_debug.h b/src/amd/vpelib/src/imported/SPL/spl_debug.h new file mode 100644 index 00000000000..5688d03f7ce --- /dev/null +++ b/src/amd/vpelib/src/imported/SPL/spl_debug.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: MIT */ + +/* Copyright 2024 Advanced Micro Devices, Inc. */ + +#ifndef SPL_DEBUG_H +#define SPL_DEBUG_H + +#if defined(LINUX_DM) +#if defined(CONFIG_HAVE_KGDB) || defined(CONFIG_KGDB) +#define SPL_ASSERT_CRITICAL(expr) do { \ + if (WARN_ON(!(expr))) { \ + kgdb_breakpoint(); \ + } \ +} while (0) +#else +#define SPL_ASSERT_CRITICAL(expr) do { \ + if (WARN_ON(!(expr))) { \ + ; \ + } \ +} while (0) +#endif /* CONFIG_HAVE_KGDB || CONFIG_KGDB */ + +#if defined(CONFIG_DEBUG_KERNEL_DC) +#define SPL_ASSERT(expr) SPL_ASSERT_CRITICAL(expr) +#else +#define SPL_ASSERT(expr) WARN_ON(!(expr)) +#endif /* CONFIG_DEBUG_KERNEL_DC */ + +#define SPL_BREAK_TO_DEBUGGER() SPL_ASSERT(0) + +#else /* other DMs */ + +#ifdef DBG + +/* + * Definition of a break to the debugger that should cover all platforms that + * we expect to run under. This break goes directly to the platform provided + * method for breaking. It does not use the MCIL interface. + */ +#if defined(__GNUC__) +#if defined(__i386__) || defined(__x86_64__) +#define SPL_BREAK_TO_DEBUGGER() __asm("int3;") +#elif defined(__powerpc__) +#define SPL_BREAK_TO_DEBUGGER() __asm(".long 0x7d821008 ") +#else +/* + * Unsupported GCC architecture. Define macro to + * generate error during compilation. + */ +#define SPL_BREAK_TO_DEBUGGER() 0 +#endif +#elif defined(_WIN32) +/* + * Assume that we are using Microsoft compiler. + * Let's use compiler intrinsic + */ +#define SPL_BREAK_TO_DEBUGGER() __debugbreak() +#else +/* + * Unsupported Architecture. Define macro to + * generate error during compilation. + */ +#define SPL_BREAK_TO_DEBUGGER() 0 +#endif + +/* + * Hard assert with no message. Goes stright to debugger. + * Not supported through MCIL. + */ +#ifdef SPL_ASSERT +#undef SPL_ASSERT +#endif +#define SPL_ASSERT(b) {if (!(b)) {SPL_BREAK_TO_DEBUGGER(); }} + +#define SPL_ASSERT_CRITICAL(expr) do {if (!(expr)) SPL_BREAK_TO_DEBUGGER(); } while (0) + + /* + * DebugPrint() is a method of the DalBaseClass. + * This macro makes the assumption that it will be called from within a C++ object derived + * from the DalBaseClass. + * + * DALMSG uses the MCIL interface to display a runtime debug message. + */ +#define SPL_DALMSG(b) {DebugPrint b; } +#define SPL_DAL_ASSERT_MSG(b, m) {bool __bCondition_ = (b); if (!__bCondition_) {SPL_DALMSG(m) {SPL_BREAK_TO_DEBUGGER(); }; }; } + +#else // DBG + +#ifdef SPL_ASSERT +#undef SPL_ASSERT +#endif +//#define SPL_ASSERT(_bool) (do {} while (0)) +#define SPL_ASSERT(_bool) + +#define SPL_ASSERT_CRITICAL(expr) do {if (expr)/* Do nothing */; } while (0) + +#ifdef SPL_BREAK_TO_DEBUGGER +#undef SPL_BREAK_TO_DEBUGGER +#endif +#define SPL_BREAK_TO_DEBUGGER() + +#ifdef SPL_DALMSG +#undef SPL_DALMSG +#endif +#define SPL_DALMSG(b) + +#ifdef SPL_DAL_ASSERT_MSG +#undef SPL_DAL_ASSERT_MSG +#endif +#define SPL_DAL_ASSERT_MSG(b, m) + +#endif // DBG + +#endif /* LINUX_DM */ + +#endif // SPL_DEBUG_H diff --git a/src/amd/vpelib/src/imported/SPL/spl_fixpt31_32.c b/src/amd/vpelib/src/imported/SPL/spl_fixpt31_32.c new file mode 100644 index 00000000000..5462f28bc1f --- /dev/null +++ b/src/amd/vpelib/src/imported/SPL/spl_fixpt31_32.c @@ -0,0 +1,496 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2024 Advanced Micro Devices, Inc. + +#include "spl_fixpt31_32.h" + +static const struct spl_fixed31_32 spl_fixpt_two_pi = { 26986075409LL }; +static const struct spl_fixed31_32 spl_fixpt_ln2 = { 2977044471LL }; +static const struct spl_fixed31_32 spl_fixpt_ln2_div_2 = { 1488522236LL }; + +static inline unsigned long long abs_i64( + long long arg) +{ + if (arg > 0) + return (unsigned long long)arg; + else + return (unsigned long long)(-arg); +} + +/* + * @brief + * result = dividend / divisor + * *remainder = dividend % divisor + */ +static inline unsigned long long spl_complete_integer_division_u64( + unsigned long long dividend, + unsigned long long divisor, + unsigned long long *remainder) +{ + unsigned long long result; + + result = spl_div64_u64_rem(dividend, divisor, (uint64_t *)remainder); + + return result; +} + + +#define FRACTIONAL_PART_MASK \ + ((1ULL << FIXED31_32_BITS_PER_FRACTIONAL_PART) - 1) + +#define GET_INTEGER_PART(x) \ + ((x) >> FIXED31_32_BITS_PER_FRACTIONAL_PART) + +#define GET_FRACTIONAL_PART(x) \ + (FRACTIONAL_PART_MASK & (x)) + +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_from_fraction( + long long numerator, long long denominator)) +{ + struct spl_fixed31_32 res; + + bool arg1_negative = numerator < 0; + bool arg2_negative = denominator < 0; + + unsigned long long arg1_value = arg1_negative ? -numerator : numerator; + unsigned long long arg2_value = arg2_negative ? -denominator : denominator; + + unsigned long long remainder; + + /* determine integer part */ + + unsigned long long res_value = spl_complete_integer_division_u64( + arg1_value, arg2_value, &remainder); + + SPL_ASSERT(res_value <= (unsigned long long)LONG_MAX); + + /* determine fractional part */ + { + unsigned int i = FIXED31_32_BITS_PER_FRACTIONAL_PART; + + do { + remainder <<= 1; + + res_value <<= 1; + + if (remainder >= arg2_value) { + res_value |= 1; + remainder -= arg2_value; + } + } while (--i != 0); + } + + /* round up LSB */ + { + unsigned long long summand = (remainder << 1) >= arg2_value; + + SPL_ASSERT(res_value <= (unsigned long long)LLONG_MAX - summand); + + res_value += summand; + } + + res.value = (long long)res_value; + + if (arg1_negative ^ arg2_negative) + res.value = -res.value; + + return res; +} + +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_mul( + struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2)) +{ + struct spl_fixed31_32 res; + + bool arg1_negative = arg1.value < 0; + bool arg2_negative = arg2.value < 0; + + unsigned long long arg1_value = arg1_negative ? -arg1.value : arg1.value; + unsigned long long arg2_value = arg2_negative ? -arg2.value : arg2.value; + + unsigned long long arg1_int = GET_INTEGER_PART(arg1_value); + unsigned long long arg2_int = GET_INTEGER_PART(arg2_value); + + unsigned long long arg1_fra = GET_FRACTIONAL_PART(arg1_value); + unsigned long long arg2_fra = GET_FRACTIONAL_PART(arg2_value); + + unsigned long long tmp; + + res.value = arg1_int * arg2_int; + + SPL_ASSERT(res.value <= (long long)LONG_MAX); + + res.value <<= FIXED31_32_BITS_PER_FRACTIONAL_PART; + + tmp = arg1_int * arg2_fra; + + SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + + res.value += tmp; + + tmp = arg2_int * arg1_fra; + + SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + + res.value += tmp; + + tmp = arg1_fra * arg2_fra; + + tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) + + (tmp >= (unsigned long long)spl_fixpt_half.value); + + SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + + res.value += tmp; + + if (arg1_negative ^ arg2_negative) + res.value = -res.value; + + return res; +} + +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_sqr(struct spl_fixed31_32 arg)) +{ + struct spl_fixed31_32 res; + + unsigned long long arg_value = abs_i64(arg.value); + + unsigned long long arg_int = GET_INTEGER_PART(arg_value); + + unsigned long long arg_fra = GET_FRACTIONAL_PART(arg_value); + + unsigned long long tmp; + + res.value = arg_int * arg_int; + + SPL_ASSERT(res.value <= (long long)LONG_MAX); + + res.value <<= FIXED31_32_BITS_PER_FRACTIONAL_PART; + + tmp = arg_int * arg_fra; + + SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + + res.value += tmp; + + SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + + res.value += tmp; + + tmp = arg_fra * arg_fra; + + tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) + + (tmp >= (unsigned long long)spl_fixpt_half.value); + + SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + + res.value += tmp; + + return res; +} + +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_recip(struct spl_fixed31_32 arg)) +{ + /* + * @note + * Good idea to use Newton's method + */ + + return SPL_NAMESPACE(spl_fixpt_from_fraction( + spl_fixpt_one.value, + arg.value)); +} + +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_sinc(struct spl_fixed31_32 arg)) +{ + struct spl_fixed31_32 square; + + struct spl_fixed31_32 res = spl_fixpt_one; + + int n = 27; + + struct spl_fixed31_32 arg_norm = arg; + + if (spl_fixpt_le( + spl_fixpt_two_pi, + spl_fixpt_abs(arg))) { + arg_norm = spl_fixpt_sub( + arg_norm, + spl_fixpt_mul_int( + spl_fixpt_two_pi, + (int)spl_div64_s64( + arg_norm.value, + spl_fixpt_two_pi.value))); + } + + square = SPL_NAMESPACE(spl_fixpt_sqr(arg_norm)); + + do { + res = spl_fixpt_sub( + spl_fixpt_one, + spl_fixpt_div_int( + SPL_NAMESPACE(spl_fixpt_mul( + square, + res)), + n * (n - 1))); + + n -= 2; + } while (n > 2); + + if (arg.value != arg_norm.value) + res = spl_fixpt_div( + SPL_NAMESPACE(spl_fixpt_mul(res, arg_norm)), + arg); + + return res; +} + +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_sin(struct spl_fixed31_32 arg)) +{ + return SPL_NAMESPACE(spl_fixpt_mul( + arg, + SPL_NAMESPACE(spl_fixpt_sinc(arg)))); +} + +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_cos(struct spl_fixed31_32 arg)) +{ + /* TODO implement argument normalization */ + + const struct spl_fixed31_32 square = SPL_NAMESPACE(spl_fixpt_sqr(arg)); + + struct spl_fixed31_32 res = spl_fixpt_one; + + int n = 26; + + do { + res = spl_fixpt_sub( + spl_fixpt_one, + spl_fixpt_div_int( + SPL_NAMESPACE(spl_fixpt_mul( + square, + res)), + n * (n - 1))); + + n -= 2; + } while (n != 0); + + return res; +} + +/* + * @brief + * result = exp(arg), + * where abs(arg) < 1 + * + * Calculated as Taylor series. + */ +static struct spl_fixed31_32 spl_fixed31_32_exp_from_taylor_series(struct spl_fixed31_32 arg) +{ + unsigned int n = 9; + + struct spl_fixed31_32 res = SPL_NAMESPACE(spl_fixpt_from_fraction( + n + 2, + n + 1)); + /* TODO find correct res */ + + SPL_ASSERT(spl_fixpt_lt(arg, spl_fixpt_one)); + + do + res = spl_fixpt_add( + spl_fixpt_one, + spl_fixpt_div_int( + SPL_NAMESPACE(spl_fixpt_mul( + arg, + res)), + n)); + while (--n != 1); + + return spl_fixpt_add( + spl_fixpt_one, + SPL_NAMESPACE(spl_fixpt_mul( + arg, + res))); +} + +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_exp(struct spl_fixed31_32 arg)) +{ + /* + * @brief + * Main equation is: + * exp(x) = exp(r + m * ln(2)) = (1 << m) * exp(r), + * where m = round(x / ln(2)), r = x - m * ln(2) + */ + + if (spl_fixpt_le( + spl_fixpt_ln2_div_2, + spl_fixpt_abs(arg))) { + int m = spl_fixpt_round( + spl_fixpt_div( + arg, + spl_fixpt_ln2)); + + struct spl_fixed31_32 r = spl_fixpt_sub( + arg, + spl_fixpt_mul_int( + spl_fixpt_ln2, + m)); + + SPL_ASSERT(m != 0); + + SPL_ASSERT(spl_fixpt_lt( + spl_fixpt_abs(r), + spl_fixpt_one)); + + if (m > 0) + return spl_fixpt_shl( + spl_fixed31_32_exp_from_taylor_series(r), + (unsigned int)m); + else + return spl_fixpt_div_int( + spl_fixed31_32_exp_from_taylor_series(r), + 1LL << -m); + } else if (arg.value != 0) + return spl_fixed31_32_exp_from_taylor_series(arg); + else + return spl_fixpt_one; +} + +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_log(struct spl_fixed31_32 arg)) +{ + struct spl_fixed31_32 res = spl_fixpt_neg(spl_fixpt_one); + /* TODO improve 1st estimation */ + + struct spl_fixed31_32 error; + + SPL_ASSERT(arg.value > 0); + /* TODO if arg is negative, return NaN */ + /* TODO if arg is zero, return -INF */ + + do { + struct spl_fixed31_32 res1 = spl_fixpt_add( + spl_fixpt_sub( + res, + spl_fixpt_one), + spl_fixpt_div( + arg, + SPL_NAMESPACE(spl_fixpt_exp(res)))); + + error = spl_fixpt_sub( + res, + res1); + + res = res1; + /* TODO determine max_allowed_error based on quality of exp() */ + } while (abs_i64(error.value) > 100ULL); + + return res; +} + + +/* this function is a generic helper to translate fixed point value to + * specified integer format that will consist of integer_bits integer part and + * fractional_bits fractional part. For example it is used in + * spl_fixpt_u2d19 to receive 2 bits integer part and 19 bits fractional + * part in 32 bits. It is used in hw programming (scaler) + */ + +static inline unsigned int spl_ux_dy( + long long value, + unsigned int integer_bits, + unsigned int fractional_bits) +{ + /* 1. create mask of integer part */ + unsigned int result = (1 << integer_bits) - 1; + /* 2. mask out fractional part */ + unsigned int fractional_part = FRACTIONAL_PART_MASK & value; + /* 3. shrink fixed point integer part to be of integer_bits width*/ + result &= GET_INTEGER_PART(value); + /* 4. make space for fractional part to be filled in after integer */ + result <<= fractional_bits; + /* 5. shrink fixed point fractional part to of fractional_bits width*/ + fractional_part >>= FIXED31_32_BITS_PER_FRACTIONAL_PART - fractional_bits; + /* 6. merge the result */ + return result | fractional_part; +} + +static inline unsigned int spl_clamp_ux_dy( + long long value, + unsigned int integer_bits, + unsigned int fractional_bits, + unsigned int min_clamp) +{ + unsigned int truncated_val = spl_ux_dy(value, integer_bits, fractional_bits); + + if (value >= (1LL << (integer_bits + FIXED31_32_BITS_PER_FRACTIONAL_PART))) + return (1 << (integer_bits + fractional_bits)) - 1; + else if (truncated_val > min_clamp) + return truncated_val; + else + return min_clamp; +} + +unsigned int SPL_NAMESPACE(spl_fixpt_u4d19(struct spl_fixed31_32 arg)) +{ + return spl_ux_dy(arg.value, 4, 19); +} + +unsigned int SPL_NAMESPACE(spl_fixpt_u3d19(struct spl_fixed31_32 arg)) +{ + return spl_ux_dy(arg.value, 3, 19); +} + +unsigned int SPL_NAMESPACE(spl_fixpt_u2d19(struct spl_fixed31_32 arg)) +{ + return spl_ux_dy(arg.value, 2, 19); +} + +unsigned int SPL_NAMESPACE(spl_fixpt_u0d19(struct spl_fixed31_32 arg)) +{ + return spl_ux_dy(arg.value, 0, 19); +} + +unsigned int SPL_NAMESPACE(spl_fixpt_clamp_u0d14(struct spl_fixed31_32 arg)) +{ + return spl_clamp_ux_dy(arg.value, 0, 14, 1); +} + +unsigned int SPL_NAMESPACE(spl_fixpt_clamp_u0d10(struct spl_fixed31_32 arg)) +{ + return spl_clamp_ux_dy(arg.value, 0, 10, 1); +} + +int SPL_NAMESPACE(spl_fixpt_s4d19(struct spl_fixed31_32 arg)) +{ + if (arg.value < 0) + return -(int)spl_ux_dy(spl_fixpt_abs(arg).value, 4, 19); + else + return spl_ux_dy(arg.value, 4, 19); +} + +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_from_ux_dy(unsigned int value, + unsigned int integer_bits, + unsigned int fractional_bits)) +{ + struct spl_fixed31_32 fixpt_value = spl_fixpt_zero; + struct spl_fixed31_32 fixpt_int_value = spl_fixpt_zero; + long long frac_mask = ((long long)1 << (long long)integer_bits) - 1; + + fixpt_value.value = (long long)value << (FIXED31_32_BITS_PER_FRACTIONAL_PART - fractional_bits); + frac_mask = frac_mask << fractional_bits; + fixpt_int_value.value = value & frac_mask; + fixpt_int_value.value <<= (FIXED31_32_BITS_PER_FRACTIONAL_PART - fractional_bits); + fixpt_value.value |= fixpt_int_value.value; + return fixpt_value; +} + +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_from_int_dy(unsigned int int_value, + unsigned int frac_value, + unsigned int integer_bits, + unsigned int fractional_bits)) +{ + (void)integer_bits; + struct spl_fixed31_32 fixpt_value = spl_fixpt_from_int(int_value); + + fixpt_value.value |= (long long)frac_value << (FIXED31_32_BITS_PER_FRACTIONAL_PART - fractional_bits); + return fixpt_value; +} diff --git a/src/amd/vpelib/src/imported/SPL/spl_fixpt31_32.h b/src/amd/vpelib/src/imported/SPL/spl_fixpt31_32.h new file mode 100644 index 00000000000..ebf4b9088fd --- /dev/null +++ b/src/amd/vpelib/src/imported/SPL/spl_fixpt31_32.h @@ -0,0 +1,526 @@ +/* SPDX-License-Identifier: MIT */ + +/* Copyright 2024 Advanced Micro Devices, Inc. */ + +#ifndef __SPL_FIXED31_32_H__ +#define __SPL_FIXED31_32_H__ + +#include "spl_debug.h" +#include "spl_os_types.h" // swap + +#ifndef LLONG_MAX +#define LLONG_MAX 9223372036854775807ll +#endif +#ifndef LLONG_MIN +#define LLONG_MIN (-LLONG_MAX - 1ll) +#endif + +#define FIXED31_32_BITS_PER_FRACTIONAL_PART 32 +#ifndef LLONG_MIN +#define LLONG_MIN (1LL<<63) +#endif +#ifndef LLONG_MAX +#define LLONG_MAX (-1LL>>1) +#endif + +/* + * @brief + * Arithmetic operations on real numbers + * represented as fixed-point numbers. + * There are: 1 bit for sign, + * 31 bit for integer part, + * 32 bits for fractional part. + * + * @note + * Currently, overflows and underflows are asserted; + * no special result returned. + */ + +struct spl_fixed31_32 { + long long value; +}; + + +/* + * @brief + * Useful constants + */ + +static const struct spl_fixed31_32 spl_fixpt_zero = { 0 }; +static const struct spl_fixed31_32 spl_fixpt_epsilon = { 1LL }; +static const struct spl_fixed31_32 spl_fixpt_half = { 0x80000000LL }; +static const struct spl_fixed31_32 spl_fixpt_one = { 0x100000000LL }; + +/* + * @brief + * Initialization routines + */ + +/* + * @brief + * result = numerator / denominator + */ +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_from_fraction( + long long numerator, long long denominator)); + +/* + * @brief + * result = arg + */ +static inline struct spl_fixed31_32 spl_fixpt_from_int(int arg) +{ + struct spl_fixed31_32 res; + + res.value = (long long) arg << FIXED31_32_BITS_PER_FRACTIONAL_PART; + + return res; +} + +/* + * @brief + * Unary operators + */ + +/* + * @brief + * result = -arg + */ +static inline struct spl_fixed31_32 spl_fixpt_neg(struct spl_fixed31_32 arg) +{ + struct spl_fixed31_32 res; + + res.value = -arg.value; + + return res; +} + +/* + * @brief + * result = abs(arg) := (arg >= 0) ? arg : -arg + */ +static inline struct spl_fixed31_32 spl_fixpt_abs(struct spl_fixed31_32 arg) +{ + if (arg.value < 0) + return spl_fixpt_neg(arg); + else + return arg; +} + +/* + * @brief + * Binary relational operators + */ + +/* + * @brief + * result = arg1 < arg2 + */ +static inline bool spl_fixpt_lt(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2) +{ + return arg1.value < arg2.value; +} + +/* + * @brief + * result = arg1 <= arg2 + */ +static inline bool spl_fixpt_le(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2) +{ + return arg1.value <= arg2.value; +} + +/* + * @brief + * result = arg1 == arg2 + */ +static inline bool spl_fixpt_eq(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2) +{ + return arg1.value == arg2.value; +} + +/* + * @brief + * result = min(arg1, arg2) := (arg1 <= arg2) ? arg1 : arg2 + */ +static inline struct spl_fixed31_32 spl_fixpt_min(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2) +{ + if (arg1.value <= arg2.value) + return arg1; + else + return arg2; +} + +/* + * @brief + * result = max(arg1, arg2) := (arg1 <= arg2) ? arg2 : arg1 + */ +static inline struct spl_fixed31_32 spl_fixpt_max(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2) +{ + if (arg1.value <= arg2.value) + return arg2; + else + return arg1; +} + +/* + * @brief + * | min_value, when arg <= min_value + * result = | arg, when min_value < arg < max_value + * | max_value, when arg >= max_value + */ +static inline struct spl_fixed31_32 spl_fixpt_clamp( + struct spl_fixed31_32 arg, + struct spl_fixed31_32 min_value, + struct spl_fixed31_32 max_value) +{ + if (spl_fixpt_le(arg, min_value)) + return min_value; + else if (spl_fixpt_le(max_value, arg)) + return max_value; + else + return arg; +} + +/* + * @brief + * Binary shift operators + */ + +/* + * @brief + * result = arg << shift + */ +static inline struct spl_fixed31_32 spl_fixpt_shl(struct spl_fixed31_32 arg, unsigned int shift) +{ + SPL_ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) || + ((arg.value < 0) && (arg.value >= ~(LLONG_MAX >> shift)))); + + arg.value = arg.value << shift; + + return arg; +} + +/* + * @brief + * result = arg >> shift + */ +static inline struct spl_fixed31_32 spl_fixpt_shr(struct spl_fixed31_32 arg, unsigned int shift) +{ + bool negative = arg.value < 0; + + if (negative) + arg.value = -arg.value; + arg.value = arg.value >> shift; + if (negative) + arg.value = -arg.value; + return arg; +} + +/* + * @brief + * Binary additive operators + */ + +/* + * @brief + * result = arg1 + arg2 + */ +static inline struct spl_fixed31_32 spl_fixpt_add(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2) +{ + struct spl_fixed31_32 res; + + SPL_ASSERT(((arg1.value >= 0) && (LLONG_MAX - arg1.value >= arg2.value)) || + ((arg1.value < 0) && (LLONG_MIN - arg1.value <= arg2.value))); + + res.value = arg1.value + arg2.value; + + return res; +} + +/* + * @brief + * result = arg1 + arg2 + */ +static inline struct spl_fixed31_32 spl_fixpt_add_int(struct spl_fixed31_32 arg1, int arg2) +{ + return spl_fixpt_add(arg1, spl_fixpt_from_int(arg2)); +} + +/* + * @brief + * result = arg1 - arg2 + */ +static inline struct spl_fixed31_32 spl_fixpt_sub(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2) +{ + struct spl_fixed31_32 res; + + SPL_ASSERT(((arg2.value >= 0) && (LLONG_MIN + arg2.value <= arg1.value)) || + ((arg2.value < 0) && (LLONG_MAX + arg2.value >= arg1.value))); + + res.value = arg1.value - arg2.value; + + return res; +} + +/* + * @brief + * result = arg1 - arg2 + */ +static inline struct spl_fixed31_32 spl_fixpt_sub_int(struct spl_fixed31_32 arg1, int arg2) +{ + return spl_fixpt_sub(arg1, spl_fixpt_from_int(arg2)); +} + + +/* + * @brief + * Binary multiplicative operators + */ + +/* + * @brief + * result = arg1 * arg2 + */ +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_mul( + struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2)); + + +/* + * @brief + * result = arg1 * arg2 + */ +static inline struct spl_fixed31_32 spl_fixpt_mul_int(struct spl_fixed31_32 arg1, int arg2) +{ + return SPL_NAMESPACE(spl_fixpt_mul(arg1, spl_fixpt_from_int(arg2))); +} + +/* + * @brief + * result = square(arg) := arg * arg + */ +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_sqr(struct spl_fixed31_32 arg)); + +/* + * @brief + * result = arg1 / arg2 + */ +static inline struct spl_fixed31_32 spl_fixpt_div_int(struct spl_fixed31_32 arg1, long long arg2) +{ + return SPL_NAMESPACE(spl_fixpt_from_fraction(arg1.value, + spl_fixpt_from_int((int)arg2).value)); +} + +/* + * @brief + * result = arg1 / arg2 + */ +static inline struct spl_fixed31_32 spl_fixpt_div(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2) +{ + return SPL_NAMESPACE(spl_fixpt_from_fraction(arg1.value, arg2.value)); +} + +/* + * @brief + * Reciprocal function + */ + +/* + * @brief + * result = reciprocal(arg) := 1 / arg + * + * @note + * No special actions taken in case argument is zero. + */ +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_recip(struct spl_fixed31_32 arg)); + +/* + * @brief + * Trigonometric functions + */ + +/* + * @brief + * result = sinc(arg) := sin(arg) / arg + * + * @note + * Argument specified in radians, + * internally it's normalized to [-2pi...2pi] range. + */ +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_sinc(struct spl_fixed31_32 arg)); + +/* + * @brief + * result = sin(arg) + * + * @note + * Argument specified in radians, + * internally it's normalized to [-2pi...2pi] range. + */ +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_sin(struct spl_fixed31_32 arg)); + +/* + * @brief + * result = cos(arg) + * + * @note + * Argument specified in radians + * and should be in [-2pi...2pi] range - + * passing arguments outside that range + * will cause incorrect result! + */ +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_cos(struct spl_fixed31_32 arg)); + +/* + * @brief + * Transcendent functions + */ + +/* + * @brief + * result = exp(arg) + * + * @note + * Currently, function is verified for abs(arg) <= 1. + */ +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_exp(struct spl_fixed31_32 arg)); + +/* + * @brief + * result = log(arg) + * + * @note + * Currently, abs(arg) should be less than 1. + * No normalization is done. + * Currently, no special actions taken + * in case of invalid argument(s). Take care! + */ +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_log(struct spl_fixed31_32 arg)); + +/* + * @brief + * Power function + */ + +/* + * @brief + * result = pow(arg1, arg2) + * + * @note + * Currently, abs(arg1) should be less than 1. Take care! + */ +static inline struct spl_fixed31_32 spl_fixpt_pow(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2) +{ + if (arg1.value == 0) + return arg2.value == 0 ? spl_fixpt_one : spl_fixpt_zero; + + return SPL_NAMESPACE(spl_fixpt_exp( + SPL_NAMESPACE(spl_fixpt_mul( + SPL_NAMESPACE(spl_fixpt_log(arg1)), + arg2)))); +} + +/* + * @brief + * Rounding functions + */ + +/* + * @brief + * result = floor(arg) := greatest integer lower than or equal to arg + */ +static inline int spl_fixpt_floor(struct spl_fixed31_32 arg) +{ + unsigned long long arg_value = (unsigned long long)(arg.value > 0 ? arg.value : -arg.value); + + if (arg.value >= 0) + return (int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART); + else + return -(int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART); +} + +/* + * @brief + * result = round(arg) := integer nearest to arg + */ +static inline int spl_fixpt_round(struct spl_fixed31_32 arg) +{ + unsigned long long arg_value = (unsigned long long)(arg.value > 0 ? arg.value : -arg.value); + + const long long summand = spl_fixpt_half.value; + + SPL_ASSERT(LLONG_MAX - (long long)arg_value >= summand); + + arg_value += summand; + + if (arg.value >= 0) + return (int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART); + else + return -(int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART); +} + +/* + * @brief + * result = ceil(arg) := lowest integer greater than or equal to arg + */ +static inline int spl_fixpt_ceil(struct spl_fixed31_32 arg) +{ + unsigned long long arg_value = (unsigned long long)(arg.value > 0 ? arg.value : -arg.value); + + const long long summand = spl_fixpt_one.value - + spl_fixpt_epsilon.value; + + SPL_ASSERT(LLONG_MAX - (long long)arg_value >= summand); + + arg_value += summand; + + if (arg.value >= 0) + return (int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART); + else + return -(int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART); +} + +/* the following two function are used in scaler hw programming to convert fixed + * point value to format 2 bits from integer part and 19 bits from fractional + * part. The same applies for u0d19, 0 bits from integer part and 19 bits from + * fractional + */ + +unsigned int SPL_NAMESPACE(spl_fixpt_u4d19(struct spl_fixed31_32 arg)); + +unsigned int SPL_NAMESPACE(spl_fixpt_u3d19(struct spl_fixed31_32 arg)); + +unsigned int SPL_NAMESPACE(spl_fixpt_u2d19(struct spl_fixed31_32 arg)); + +unsigned int SPL_NAMESPACE(spl_fixpt_u0d19(struct spl_fixed31_32 arg)); + +unsigned int SPL_NAMESPACE(spl_fixpt_clamp_u0d14(struct spl_fixed31_32 arg)); + +unsigned int SPL_NAMESPACE(spl_fixpt_clamp_u0d10(struct spl_fixed31_32 arg)); + +int SPL_NAMESPACE(spl_fixpt_s4d19(struct spl_fixed31_32 arg)); + +static inline struct spl_fixed31_32 spl_fixpt_truncate(struct spl_fixed31_32 arg, unsigned int frac_bits) +{ + bool negative = arg.value < 0; + + if (frac_bits >= FIXED31_32_BITS_PER_FRACTIONAL_PART) { + SPL_ASSERT(frac_bits == FIXED31_32_BITS_PER_FRACTIONAL_PART); + return arg; + } + + if (negative) + arg.value = -arg.value; + arg.value &= (~0ULL) << (FIXED31_32_BITS_PER_FRACTIONAL_PART - frac_bits); + if (negative) + arg.value = -arg.value; + return arg; +} + +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_from_ux_dy(unsigned int value, + unsigned int integer_bits, unsigned int fractional_bits)); +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_from_int_dy(unsigned int int_value, + unsigned int frac_value, + unsigned int integer_bits, + unsigned int fractional_bits)); + +#endif diff --git a/src/amd/vpelib/src/imported/SPL/spl_os_types.h b/src/amd/vpelib/src/imported/SPL/spl_os_types.h new file mode 100644 index 00000000000..e7f46becb02 --- /dev/null +++ b/src/amd/vpelib/src/imported/SPL/spl_os_types.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: MIT */ + +/* Copyright 2024 Advanced Micro Devices, Inc. */ +/* Copyright 2019 Raptor Engineering, LLC */ + +#ifndef _SPL_OS_TYPES_H_ +#define _SPL_OS_TYPES_H_ + +#include "spl_debug.h" + +#ifdef LINUX_DM +#include +#include +#include +#include +#include +#include +#else /* _WIN32 || DIAGS_BUILD */ +#include +#include +#include +#include +#include +#include +#include +#endif /* LINUX_DM */ + +/* + * + * general debug capabilities + * + */ +#if defined(LINUX_DM) + +static inline uint64_t spl_div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder) +{ + return div_u64_rem(dividend, divisor, remainder); +} + +static inline uint64_t spl_div_u64(uint64_t dividend, uint32_t divisor) +{ + return div_u64(dividend, divisor); +} + +static inline uint64_t spl_div64_u64(uint64_t dividend, uint64_t divisor) +{ + return div64_u64(dividend, divisor); +} + +static inline uint64_t spl_div64_u64_rem(uint64_t dividend, uint64_t divisor, uint64_t *remainder) +{ + return div64_u64_rem(dividend, divisor, remainder); +} + +static inline int64_t spl_div64_s64(int64_t dividend, int64_t divisor) +{ + return div64_s64(dividend, divisor); +} + +#else + +static inline uint64_t spl_div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder) +{ + if (remainder) + *remainder = dividend % divisor; + return dividend / divisor; +} + +static inline uint64_t spl_div_u64(uint64_t dividend, uint32_t divisor) +{ + return dividend / divisor; +} + +static inline uint64_t spl_div64_u64(uint64_t dividend, uint64_t divisor) +{ + return dividend / divisor; +} + +static inline uint64_t spl_div64_u64_rem(uint64_t dividend, uint64_t divisor, uint64_t *remainder) +{ + if (remainder) + *remainder = dividend % divisor; + return dividend / divisor; +} + +static inline int64_t spl_div64_s64(int64_t dividend, int64_t divisor) +{ + return dividend / divisor; +} + +#endif /*LINUX_DM */ + +#if defined(_WIN32) + +#define spl_swap(x, y) do { \ + unsigned char swap_temp[sizeof(x) == sizeof(y) ? (signed int) sizeof(x) : -1]; \ + memcpy(swap_temp, &y, sizeof(x)); \ + y = x; \ + memcpy(&x, swap_temp, sizeof(x)); \ +} while (0) + +#else + +#define spl_swap(a, b) \ + do { __typeof__(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0) + +#endif /* _WIN32 */ + +#ifndef spl_min +#define spl_min(a, b) (((a) < (b)) ? (a):(b)) +#endif + +/* SPL namespace macros */ +#ifndef SPL_PFX_ +#define SPL_PFX_ +#endif + +#define SPL_EXPAND2(a, b) a##b +#define SPL_EXPAND(a, b) SPL_EXPAND2(a, b) +#define SPL_NAMESPACE(symbol) SPL_EXPAND(SPL_PFX_, symbol) + +#endif /* _SPL_OS_TYPES_H_ */