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intel/brw: Combine a1/a16 3src type decoding functions

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Align16 is only used on Gfx9, while Align1 is used on Gfx11+.  We can
decode both kinds of encodings in the same function with a simple
devinfo check.  One snag is that the align16 encodings didn't have a
separate exec_type field, but we can just pass 0.

This lets us have a single function named brw_type_decode_for_3src,
which is much less of a mouthful.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28847>
This commit is contained in:
Kenneth Graunke 2024-04-21 01:15:22 -07:00 • committed by Marge Bot
parent 28034aac34
commit 9205f6ff51
3 changed files with 19 additions and 32 deletions
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6
src/intel/compiler/brw_inst.h
View file

@ -394,7 +394,7 @@ brw_inst_3src_a16_##reg##_type(const struct intel_device_info *devinfo, \
const brw_inst *inst) \
{ \
unsigned hw_type = brw_inst_3src_a16_##reg##_hw_type(devinfo, inst); \
return brw_a16_hw_3src_type_to_reg_type(devinfo, hw_type); \
return brw_type_decode_for_3src(devinfo, hw_type, 0); \
}
REG_TYPE(dst)
@ -467,7 +467,7 @@ brw_inst_3src_a1_##reg##_type(const struct intel_device_info *devinfo, \
(enum gfx10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
inst); \
unsigned hw_type = brw_inst_3src_a1_##reg##_hw_type(devinfo, inst); \
return brw_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type); \
return brw_type_decode_for_3src(devinfo, hw_type, exec_type); \
}
REG_TYPE(dst)
@ -577,7 +577,7 @@ brw_inst_dpas_3src_##reg##_type(const struct intel_device_info *devinfo, \
(enum gfx10_align1_3src_exec_type) brw_inst_dpas_3src_exec_type(devinfo,\
inst); \
unsigned hw_type = brw_inst_dpas_3src_##reg##_hw_type(devinfo, inst); \
return brw_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type); \
return brw_type_decode_for_3src(devinfo, hw_type, exec_type); \
}
REG_TYPE(dst)

37
src/intel/compiler/brw_reg_type.c
View file

@ -224,30 +224,11 @@ brw_type_encode_for_3src(const struct intel_device_info *devinfo,
}
/**
* Convert the hardware representation for a 3-src align16 instruction into a
* brw_reg_type enumeration value.
* Convert the hardware encoding for a 3-src instruction into a brw_reg_type.
*/
enum brw_reg_type
brw_a16_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
unsigned hw_type)
{
static const enum brw_reg_type tbl[] = {
[0] = BRW_TYPE_F,
[1] = BRW_TYPE_D,
[2] = BRW_TYPE_UD,
[3] = BRW_TYPE_DF,
[4] = BRW_TYPE_HF,
};
return hw_type < ARRAY_SIZE(tbl) ? tbl[hw_type] : BRW_TYPE_INVALID;
}
/**
* Convert the hardware representation for a 3-src align1 instruction into a
* brw_reg_type enumeration value.
*/
enum brw_reg_type
brw_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
unsigned hw_type, unsigned exec_type)
brw_type_decode_for_3src(const struct intel_device_info *devinfo,
unsigned hw_type, unsigned exec_type)
{
STATIC_ASSERT(BRW_ALIGN1_3SRC_EXEC_TYPE_INT == 0);
STATIC_ASSERT(BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT == 1);
@ -262,7 +243,7 @@ brw_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
return BRW_TYPE_INVALID;
}
return (enum brw_reg_type) (base_field | size_field);
} else {
} else if (devinfo->ver >= 11) {
if (exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT) {
return hw_type > 1 ? BRW_TYPE_INVALID :
hw_type ? BRW_TYPE_F : BRW_TYPE_HF;
@ -271,6 +252,16 @@ brw_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
unsigned size_field = 2 >> (hw_type >> 1);
unsigned base_field = (hw_type & 1) << 2;
return (enum brw_reg_type) (base_field | size_field);
} else {
/* align16 encodings */
static const enum brw_reg_type tbl[] = {
[0] = BRW_TYPE_F,
[1] = BRW_TYPE_D,
[2] = BRW_TYPE_UD,
[3] = BRW_TYPE_DF,
[4] = BRW_TYPE_HF,
};
return hw_type < ARRAY_SIZE(tbl) ? tbl[hw_type] : BRW_TYPE_INVALID;
}
}

8
src/intel/compiler/brw_reg_type.h
View file

@ -166,12 +166,8 @@ brw_type_encode_for_3src(const struct intel_device_info *devinfo,
enum brw_reg_type type);
enum brw_reg_type
brw_a16_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
unsigned hw_type);
enum brw_reg_type
brw_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
unsigned hw_type, unsigned exec_type);
brw_type_decode_for_3src(const struct intel_device_info *devinfo,
unsigned hw_type, unsigned exec_type);
const char *
brw_reg_type_to_letters(enum brw_reg_type type);