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freedreno/regs: update UBWC related bits

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Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Jonathan Marek 2019-11-18 16:17:55 -05:00
parent 6613a4a029
commit 91fd83d142
3 changed files with 11 additions and 7 deletions
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14
src/freedreno/registers/a6xx.xml
View file

@ -3294,7 +3294,12 @@ to upconvert to 32b float internally?
-->
<bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
<bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
<bitfield name="UNK27" pos="27" type="boolean"/>
<!--
by default levels with w < 16 are linear
TILE_ALL makes all levels have tiling
seems required when using UBWC, since all levels have UBWC (can possibly be disabled?)
-->
<bitfield name="TILE_ALL" pos="27" type="boolean"/>
<bitfield name="FLAG" pos="28" type="boolean"/>
</reg32>
<reg32 offset="4" name="4">
@ -3315,11 +3320,10 @@ to upconvert to 32b float internally?
<bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
</reg32>
<reg32 offset="10" name="10">
<!--
I see some other bits set by blob above FLAG_BUFFER_PITCH, but they
don't seem to be particularly sensible... or needed for UBWC to work
-->
<bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
<!-- log2 size of the first level, required for mipmapping -->
<bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/>
<bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/>
</reg32>
<reg32 offset="11" name="11"/>
<reg32 offset="12" name="12"/>

2
src/gallium/drivers/freedreno/a6xx/fd6_image.c
View file

@ -183,7 +183,7 @@ static void emit_image_tex(struct fd_ringbuffer *ring, struct fd6_image *img)
A6XX_TEX_CONST_2_TYPE(img->type) |
A6XX_TEX_CONST_2_PITCH(img->pitch));
OUT_RING(ring, A6XX_TEX_CONST_3_ARRAY_PITCH(img->array_pitch) |
COND(ubwc_enabled, A6XX_TEX_CONST_3_FLAG | A6XX_TEX_CONST_3_UNK27));
COND(ubwc_enabled, A6XX_TEX_CONST_3_FLAG | A6XX_TEX_CONST_3_TILE_ALL));
if (img->bo) {
OUT_RELOC(ring, img->bo, img->offset,
(uint64_t)A6XX_TEX_CONST_5_DEPTH(img->depth) << 32, 0);

2
src/gallium/drivers/freedreno/a6xx/fd6_texture.c
View file

@ -318,7 +318,7 @@ fd6_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
}
if (so->ubwc_enabled) {
so->texconst3 |= A6XX_TEX_CONST_3_FLAG | A6XX_TEX_CONST_3_UNK27;
so->texconst3 |= A6XX_TEX_CONST_3_FLAG | A6XX_TEX_CONST_3_TILE_ALL;
}
return &so->base;