fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-08 09:08:10 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

freedreno/ir3: drop shader->num_ubos

Browse source 
The only difference between this and `const_state->num_ubos` was that
the latter is counting # of ubos loaded via `ldg` (based on UBO addrs
in push-consts).  But turns out there isn't really any reason to care.
Instead just add an early return in the one code-path that cares about
the number of `ldg` UBOs.

This gets rid of one more thing we need to move from `ir3_shader` to
`ir3_shader_variant`.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
This commit is contained in:
Rob Clark 2020-06-14 12:54:05 -07:00 • committed by Marge Bot
parent 70fbd48b3a
commit 91ed8b7fe3
4 changed files with 15 additions and 17 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
src/freedreno/ir3/ir3_nir.c
View file

@ -468,13 +468,7 @@ ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir,
MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1); MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1);
} }
/* On a6xx, we use UBO descriptors and LDC instead of UBO pointers in the const_state->num_ubos = nir->info.num_ubos;
* constbuf.
*/
if (compiler->gpu_id >= 600)
shader->num_ubos = nir->info.num_ubos;
else
const_state->num_ubos = nir->info.num_ubos;
/* num_driver_params is scalar, align to vec4: */ /* num_driver_params is scalar, align to vec4: */
const_state->num_driver_params = align(const_state->num_driver_params, 4); const_state->num_driver_params = align(const_state->num_driver_params, 4);

5
src/freedreno/ir3/ir3_shader.h
View file

@ -622,11 +622,6 @@ struct ir3_shader {
struct ir3_compiler *compiler; struct ir3_compiler *compiler;
/* Number of UBOs loaded by LDC, as opposed to LDG through pointers in
* ubo_state.
*/
unsigned num_ubos;
struct ir3_const_state const_state; struct ir3_const_state const_state;
struct nir_shader *nir; struct nir_shader *nir;

12
src/gallium/drivers/freedreno/a6xx/fd6_const.c
View file

@ -233,10 +233,11 @@ static void
fd6_emit_ubos(struct fd_context *ctx, const struct ir3_shader_variant *v, fd6_emit_ubos(struct fd_context *ctx, const struct ir3_shader_variant *v,
struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf) struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf)
{ {
if (!v->shader->num_ubos) const struct ir3_const_state *const_state = ir3_const_state(v);
return; int num_ubos = const_state->num_ubos;
int num_ubos = v->shader->num_ubos; if (!num_ubos)
return;
OUT_PKT7(ring, fd6_stage2opcode(v->type), 3 + (2 * num_ubos)); OUT_PKT7(ring, fd6_stage2opcode(v->type), 3 + (2 * num_ubos));
OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) | OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
@ -280,7 +281,8 @@ fd6_emit_ubos(struct fd_context *ctx, const struct ir3_shader_variant *v,
static unsigned static unsigned
user_consts_cmdstream_size(struct ir3_shader_variant *v) user_consts_cmdstream_size(struct ir3_shader_variant *v)
{ {
struct ir3_ubo_analysis_state *ubo_state = &ir3_const_state(v)->ubo_state; struct ir3_const_state *const_state = ir3_const_state(v);
struct ir3_ubo_analysis_state *ubo_state = &const_state->ubo_state;
if (unlikely(!ubo_state->cmdstream_size)) { if (unlikely(!ubo_state->cmdstream_size)) {
unsigned packets, size; unsigned packets, size;
@ -290,7 +292,7 @@ user_consts_cmdstream_size(struct ir3_shader_variant *v)
/* also account for UBO addresses: */ /* also account for UBO addresses: */
packets += 1; packets += 1;
size += 2 * v->shader->num_ubos; size += 2 * const_state->num_ubos;
unsigned sizedwords = (4 * packets) + size; unsigned sizedwords = (4 * packets) + size;
ubo_state->cmdstream_size = sizedwords * 4; ubo_state->cmdstream_size = sizedwords * 4;

7
src/gallium/drivers/freedreno/ir3/ir3_const.h
View file

@ -136,6 +136,13 @@ ir3_emit_ubos(struct fd_context *ctx, const struct ir3_shader_variant *v,
{ {
const struct ir3_const_state *const_state = ir3_const_state(v); const struct ir3_const_state *const_state = ir3_const_state(v);
uint32_t offset = const_state->offsets.ubo; uint32_t offset = const_state->offsets.ubo;
/* a6xx+ uses UBO state and ldc instead of pointers emitted in
* const state and ldg:
*/
if (ctx->screen->gpu_id >= 600)
return;
if (v->constlen > offset) { if (v->constlen > offset) {
uint32_t params = const_state->num_ubos; uint32_t params = const_state->num_ubos;
uint32_t offsets[params]; uint32_t offsets[params];