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pan/midgard: Don't special case inline_constant

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Another constant source of bugs. Ain't that special.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
This commit is contained in:
Alyssa Rosenzweig 2019-07-30 12:25:21 -07:00
parent 29416a8599
commit 91c4acedaf
7 changed files with 13 additions and 30 deletions
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2
src/panfrost/midgard/midgard_compile.c
View file

@ -1921,7 +1921,7 @@ embedded_to_inline_constant(compiler_context *ctx)
/* Get rid of the embedded constant */
ins->has_constants = false;
ins->ssa_args.src1 = SSA_UNUSED_0;
ins->ssa_args.src1 = -1;
ins->ssa_args.inline_constant = true;
ins->inline_constant = scaled_constant;
}

2
src/panfrost/midgard/midgard_liveness.c
View file

@ -34,7 +34,7 @@ midgard_is_live_in_instr(midgard_instruction *ins, int src)
if (ins->ssa_args.src0 == src)
return true;
if (!ins->ssa_args.inline_constant && ins->ssa_args.src1 == src)
if (ins->ssa_args.src1 == src)
return true;
return false;

1
src/panfrost/midgard/midgard_opt_dce.c
View file

@ -113,7 +113,6 @@ midgard_opt_post_move_eliminate(compiler_context *ctx, midgard_block *block, str
ra_get_node_reg(g, iB);
if (A != B) continue;
if (ins->ssa_args.inline_constant) continue;
/* Check we're in the work zone. TODO: promoted
* uniforms? */

2
src/panfrost/midgard/midgard_opt_invert.c
View file

@ -42,7 +42,7 @@ midgard_lower_invert(compiler_context *ctx, midgard_block *block)
.mask = ins->mask,
.ssa_args = {
.src0 = temp,
.src1 = 0,
.src1 = -1,
.dest = ins->ssa_args.dest,
.inline_constant = true
},

14
src/panfrost/midgard/midgard_ra.c
View file

@ -422,9 +422,7 @@ mir_lower_special_reads(compiler_context *ctx)
case TAG_ALU_4:
mark_node_class(aluw, ins->ssa_args.dest);
mark_node_class(alur, ins->ssa_args.src0);
if (!ins->ssa_args.inline_constant)
mark_node_class(alur, ins->ssa_args.src1);
mark_node_class(alur, ins->ssa_args.src1);
break;
case TAG_LOAD_STORE_4:
@ -604,9 +602,7 @@ allocate_registers(compiler_context *ctx, bool *spilled)
mir_foreach_instr_global(ctx, ins) {
assert(check_write_class(found_class, ins->type, ins->ssa_args.dest));
assert(check_read_class(found_class, ins->type, ins->ssa_args.src0));
if (!ins->ssa_args.inline_constant)
assert(check_read_class(found_class, ins->type, ins->ssa_args.src1));
assert(check_read_class(found_class, ins->type, ins->ssa_args.src1));
}
for (unsigned i = 0; i < ctx->temp_count; ++i) {
@ -651,9 +647,6 @@ allocate_registers(compiler_context *ctx, bool *spilled)
for (int src = 0; src < 2; ++src) {
int s = sources[src];
if (ins->ssa_args.inline_constant && src == 1)
continue;
if (s < 0) continue;
if (s >= SSA_FIXED_MINIMUM) continue;
@ -718,9 +711,8 @@ install_registers_instr(
switch (ins->type) {
case TAG_ALU_4: {
int adjusted_src = args.inline_constant ? -1 : args.src1;
struct phys_reg src1 = index_to_reg(ctx, g, args.src0);
struct phys_reg src2 = index_to_reg(ctx, g, adjusted_src);
struct phys_reg src2 = index_to_reg(ctx, g, args.src1);
struct phys_reg dest = index_to_reg(ctx, g, args.dest);
unsigned uncomposed_mask = ins->mask;

14
src/panfrost/midgard/midgard_schedule.c
View file

@ -285,13 +285,10 @@ schedule_bundle(compiler_context *ctx, midgard_block *block, midgard_instruction
could_scalar &= !s1.half;
if (!ains->ssa_args.inline_constant) {
midgard_vector_alu_src s2 =
vector_alu_from_unsigned(ains->alu.src2);
could_scalar &= !s2.half;
}
midgard_vector_alu_src s2 =
vector_alu_from_unsigned(ains->alu.src2);
could_scalar &= !s2.half;
}
bool scalar = could_scalar && scalarable;
@ -688,10 +685,7 @@ mir_squeeze_index(compiler_context *ctx)
mir_foreach_instr_global(ctx, ins) {
ins->ssa_args.dest = find_or_allocate_temp(ctx, ins->ssa_args.dest);
ins->ssa_args.src0 = find_or_allocate_temp(ctx, ins->ssa_args.src0);
if (!ins->ssa_args.inline_constant)
ins->ssa_args.src1 = find_or_allocate_temp(ctx, ins->ssa_args.src1);
ins->ssa_args.src1 = find_or_allocate_temp(ctx, ins->ssa_args.src1);
}
}

8
src/panfrost/midgard/mir.c
View file

@ -29,8 +29,7 @@ void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsign
if (ins->ssa_args.src0 == old)
ins->ssa_args.src0 = new;
if (ins->ssa_args.src1 == old &&
!ins->ssa_args.inline_constant)
if (ins->ssa_args.src1 == old)
ins->ssa_args.src1 = new;
}
@ -104,8 +103,7 @@ mir_rewrite_index_src_single_swizzle(midgard_instruction *ins, unsigned old, uns
pan_compose_swizzle(mir_get_swizzle(ins, 0), swizzle));
}
if (ins->ssa_args.src1 == old &&
!ins->ssa_args.inline_constant) {
if (ins->ssa_args.src1 == old) {
ins->ssa_args.src1 = new;
mir_set_swizzle(ins, 1,
@ -335,7 +333,7 @@ mir_mask_of_read_components(midgard_instruction *ins, unsigned node)
if (ins->ssa_args.src0 == node)
mask |= mir_mask_of_read_components_single(ins->alu.src1, ins->mask);
if (ins->ssa_args.src1 == node && !ins->ssa_args.inline_constant)
if (ins->ssa_args.src1 == node)
mask |= mir_mask_of_read_components_single(ins->alu.src2, ins->mask);
return mask;