diff --git a/src/amd/common/ac_vcn_enc.c b/src/amd/common/ac_vcn_enc.c
index e9766ff4b7e..358ce59b11f 100644
--- a/src/amd/common/ac_vcn_enc.c
+++ b/src/amd/common/ac_vcn_enc.c
@@ -136,12 +136,20 @@ void ac_vcn_enc_init_cmds(rvcn_enc_cmd_t *cmd, enum vcn_version version)
 }
 
 bool
-ac_vcn_enc_variable_slice_mode_supported(const struct radeon_info *info)
+ac_vcn_enc_variable_slice_mode_supported(const struct radeon_info *info, bool preencode)
 {
-   if (info->vcn_ip_version >= VCN_5_0_0)
-      return info->vcn_enc_minor_version >= 11;
-   else if (info->vcn_ip_version >= VCN_4_0_0)
-      return info->vcn_enc_minor_version >= 24;
-   else
+   if (info->vcn_ip_version >= VCN_5_0_0) {
+      if (preencode)
+         return info->vcn_enc_minor_version > 12 ||
+                (info->vcn_enc_minor_version == 12 && info->vcn_fw_revision >= 0xA);
+      else
+         return info->vcn_enc_minor_version >= 11;
+   } else if (info->vcn_ip_version >= VCN_4_0_0) {
+      if (preencode)
+         return info->vcn_enc_minor_version > 24 ||
+                (info->vcn_enc_minor_version == 24 && info->vcn_fw_revision >= 0x23);
+      else
+         return info->vcn_enc_minor_version >= 24;
+   } else
       return false;
 }
diff --git a/src/amd/common/ac_vcn_enc.h b/src/amd/common/ac_vcn_enc.h
index 7c0518abf0f..a90d3854327 100644
--- a/src/amd/common/ac_vcn_enc.h
+++ b/src/amd/common/ac_vcn_enc.h
@@ -779,6 +779,6 @@ typedef struct rvcn_enc_hevc_slice_info_var_s
 } rvcn_enc_hevc_slice_info_var_t;
 
 void ac_vcn_enc_init_cmds(rvcn_enc_cmd_t *cmd, enum vcn_version version);
-bool ac_vcn_enc_variable_slice_mode_supported(const struct radeon_info *info);
+bool ac_vcn_enc_variable_slice_mode_supported(const struct radeon_info *info, bool preencode);
 
 #endif
diff --git a/src/amd/vulkan/radv_video_enc.c b/src/amd/vulkan/radv_video_enc.c
index b7485a68c1b..9e434e1983a 100644
--- a/src/amd/vulkan/radv_video_enc.c
+++ b/src/amd/vulkan/radv_video_enc.c
@@ -611,7 +611,7 @@ radv_enc_slice_control(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoE
 
    uint32_t slice_control_mode = RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS;
 
-   if (ac_vcn_enc_variable_slice_mode_supported(&pdev->info) &&
+   if (ac_vcn_enc_variable_slice_mode_supported(&pdev->info, false) &&
        h264_picture_info->naluSliceEntryCount <= RENCODE_MAX_NUM_SLICES) {
       uint32_t last_mb = 0;
       slice_control_mode = RENCODE_H264_SLICE_CONTROL_MODE_VARIABLE_MBS;
@@ -718,7 +718,7 @@ radv_enc_slice_control_hevc(struct radv_cmd_buffer *cmd_buffer, const struct VkV
    num_ctbs_in_slice = DIV_ROUND_UP(width_in_ctb * height_in_ctb, h265_picture_info->naluSliceSegmentEntryCount);
 
    uint32_t slice_control_mode = RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS;
-   if (ac_vcn_enc_variable_slice_mode_supported(&pdev->info) &&
+   if (ac_vcn_enc_variable_slice_mode_supported(&pdev->info, false) &&
        h265_picture_info->naluSliceSegmentEntryCount <= RENCODE_MAX_NUM_SLICES) {
       uint32_t last_ctb = 0;
       slice_control_mode = RENCODE_HEVC_SLICE_CONTROL_MODE_VARIABLE_CTBS;
diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc.c b/src/gallium/drivers/radeonsi/radeon_vcn_enc.c
index a7632a2fb94..9c193b948b7 100644
--- a/src/gallium/drivers/radeonsi/radeon_vcn_enc.c
+++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc.c
@@ -435,7 +435,8 @@ static void radeon_vcn_enc_h264_get_slice_ctrl_param(struct radeon_encoder *enc,
    enc->enc_pic.slice_ctrl.slice_control_mode = RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS;
    enc->enc_pic.slice_ctrl.num_mbs_per_slice = num_mbs_in_slice;
 
-   if (ac_vcn_enc_variable_slice_mode_supported(&((struct si_screen *)enc->screen)->info) &&
+   if (ac_vcn_enc_variable_slice_mode_supported(&((struct si_screen *)enc->screen)->info,
+                                                enc->enc_pic.quality_modes.pre_encode_mode) &&
        pic->num_slice_descriptors <= RENCODE_MAX_NUM_SLICES)
    {
       enc->enc_pic.slice_ctrl.slice_control_mode = RENCODE_H264_SLICE_CONTROL_MODE_VARIABLE_MBS;
@@ -833,7 +834,8 @@ static void radeon_vcn_enc_hevc_get_slice_ctrl_param(struct radeon_encoder *enc,
    enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment =
       num_ctbs_in_slice;
 
-   if (ac_vcn_enc_variable_slice_mode_supported(&((struct si_screen *)enc->screen)->info) &&
+   if (ac_vcn_enc_variable_slice_mode_supported(&((struct si_screen *)enc->screen)->info,
+                                                enc->enc_pic.quality_modes.pre_encode_mode) &&
        pic->num_slice_descriptors <= RENCODE_MAX_NUM_SLICES)
    {
       enc->enc_pic.hevc_slice_ctrl.slice_control_mode = RENCODE_HEVC_SLICE_CONTROL_MODE_VARIABLE_CTBS;