mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-08 11:18:08 +02:00
radeon: Delete DRI1 screen init code and thus support for !kernel_mm.
It's past time, and it was going to get in the way of the renderbuffer mapping refactor. We dropped all the other DRI1 drivers for this release, and I can't imagine anybody supporting DRI1 radeon classic in a new release of Mesa. Cleanup of the resulting dead code to follow. Acked-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Eric Anholt
parent
a34c28f1aa
commit
9171bfe5f6
1 changed files with 5 additions and 495 deletions
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@ -254,84 +254,6 @@ radeonGetParam(__DRIscreen *sPriv, int param, void *value)
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return ret;
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}
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static const __DRIconfig **
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radeonFillInModes( __DRIscreen *psp,
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unsigned pixel_bits, unsigned depth_bits,
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unsigned stencil_bits, GLboolean have_back_buffer )
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{
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__DRIconfig **configs;
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struct gl_config *m;
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unsigned depth_buffer_factor;
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unsigned back_buffer_factor;
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int i;
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/* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
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* enough to add support. Basically, if a context is created with an
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* fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
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* will never be used.
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*/
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static const GLenum back_buffer_modes[] = {
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GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
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};
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uint8_t depth_bits_array[2];
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uint8_t stencil_bits_array[2];
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uint8_t msaa_samples_array[1];
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depth_bits_array[0] = depth_bits;
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depth_bits_array[1] = depth_bits;
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/* Just like with the accumulation buffer, always provide some modes
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* with a stencil buffer. It will be a sw fallback, but some apps won't
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* care about that.
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*/
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stencil_bits_array[0] = stencil_bits;
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stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
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msaa_samples_array[0] = 0;
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depth_buffer_factor = (stencil_bits == 0) ? 2 : 1;
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back_buffer_factor = (have_back_buffer) ? 2 : 1;
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if (pixel_bits == 16) {
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__DRIconfig **configs_a8r8g8b8;
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__DRIconfig **configs_r5g6b5;
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configs_r5g6b5 = driCreateConfigs(GL_RGB, GL_UNSIGNED_SHORT_5_6_5,
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depth_bits_array, stencil_bits_array,
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depth_buffer_factor, back_buffer_modes,
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back_buffer_factor, msaa_samples_array,
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1, GL_TRUE);
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configs_a8r8g8b8 = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
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depth_bits_array, stencil_bits_array,
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1, back_buffer_modes, 1,
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msaa_samples_array, 1, GL_TRUE);
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configs = driConcatConfigs(configs_r5g6b5, configs_a8r8g8b8);
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} else
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configs = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
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depth_bits_array, stencil_bits_array,
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depth_buffer_factor,
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back_buffer_modes, back_buffer_factor,
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msaa_samples_array, 1, GL_TRUE);
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if (configs == NULL) {
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fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
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__func__, __LINE__ );
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return NULL;
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}
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/* Mark the visual as slow if there are "fake" stencil bits.
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*/
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for (i = 0; configs[i]; i++) {
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m = &configs[i]->modes;
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if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
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m->visualRating = GLX_SLOW_CONFIG;
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}
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}
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return (const __DRIconfig **) configs;
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}
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#if defined(RADEON_R100)
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static const __DRItexOffsetExtension radeonTexOffsetExtension = {
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{ __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
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@ -1247,353 +1169,6 @@ static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
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return 0;
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}
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/* Create the device specific screen private data struct.
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*/
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static radeonScreenPtr
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radeonCreateScreen( __DRIscreen *sPriv )
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{
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radeonScreenPtr screen;
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RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
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unsigned char *RADEONMMIO = NULL;
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int i;
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int ret;
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uint32_t temp = 0;
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if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
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fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
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return GL_FALSE;
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}
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/* Allocate the private area */
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screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
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if ( !screen ) {
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__driUtilMessage("%s: Could not allocate memory for screen structure",
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__FUNCTION__);
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return NULL;
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}
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radeon_init_debug();
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/* parse information in __driConfigOptions */
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driParseOptionInfo (&screen->optionCache,
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__driConfigOptions, __driNConfigOptions);
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/* This is first since which regions we map depends on whether or
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* not we are using a PCI card.
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*/
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screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
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{
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int ret;
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ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BUFFER_OFFSET,
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&screen->gart_buffer_offset);
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if (ret) {
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FREE( screen );
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fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
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return NULL;
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}
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ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BASE,
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&screen->gart_base);
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if (ret) {
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FREE( screen );
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fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
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return NULL;
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}
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ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR,
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&screen->irq);
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if (ret) {
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FREE( screen );
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fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
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return NULL;
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}
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screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
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screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
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screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
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screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
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screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
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screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
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screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
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screen->drmSupportsOcclusionQueries = (sPriv->drm_version.minor >= 30);
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}
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ret = radeon_set_screen_flags(screen, dri_priv->deviceID);
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if (ret == -1)
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return NULL;
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screen->mmio.handle = dri_priv->registerHandle;
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screen->mmio.size = dri_priv->registerSize;
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if ( drmMap( sPriv->fd,
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screen->mmio.handle,
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screen->mmio.size,
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&screen->mmio.map ) ) {
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FREE( screen );
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__driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
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return NULL;
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}
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RADEONMMIO = screen->mmio.map;
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screen->status.handle = dri_priv->statusHandle;
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screen->status.size = dri_priv->statusSize;
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if ( drmMap( sPriv->fd,
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screen->status.handle,
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screen->status.size,
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&screen->status.map ) ) {
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drmUnmap( screen->mmio.map, screen->mmio.size );
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FREE( screen );
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__driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
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return NULL;
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}
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if (screen->chip_family < CHIP_FAMILY_R600)
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screen->scratch = (__volatile__ uint32_t *)
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((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
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else
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screen->scratch = (__volatile__ uint32_t *)
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((GLubyte *)screen->status.map + R600_SCRATCH_REG_OFFSET);
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screen->buffers = drmMapBufs( sPriv->fd );
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if ( !screen->buffers ) {
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drmUnmap( screen->status.map, screen->status.size );
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drmUnmap( screen->mmio.map, screen->mmio.size );
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FREE( screen );
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__driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
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return NULL;
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}
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if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
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screen->gartTextures.handle = dri_priv->gartTexHandle;
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screen->gartTextures.size = dri_priv->gartTexMapSize;
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if ( drmMap( sPriv->fd,
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screen->gartTextures.handle,
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screen->gartTextures.size,
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(drmAddressPtr)&screen->gartTextures.map ) ) {
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drmUnmapBufs( screen->buffers );
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drmUnmap( screen->status.map, screen->status.size );
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drmUnmap( screen->mmio.map, screen->mmio.size );
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FREE( screen );
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__driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
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return NULL;
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}
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screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
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}
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if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
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sPriv->ddx_version.minor < 2) {
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fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
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return NULL;
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}
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if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) {
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fprintf(stderr, "R500 support requires a newer drm.\n");
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return NULL;
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}
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if (getenv("R300_NO_TCL"))
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screen->chip_flags &= ~RADEON_CHIPSET_TCL;
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if (screen->chip_family <= CHIP_FAMILY_RS200)
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screen->chip_flags |= RADEON_CLASS_R100;
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else if (screen->chip_family <= CHIP_FAMILY_RV280)
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screen->chip_flags |= RADEON_CLASS_R200;
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else if (screen->chip_family <= CHIP_FAMILY_RV570)
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screen->chip_flags |= RADEON_CLASS_R300;
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else
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screen->chip_flags |= RADEON_CLASS_R600;
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/* set group bytes for r6xx+ */
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if (screen->chip_family >= CHIP_FAMILY_CEDAR)
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screen->group_bytes = 512;
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else
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screen->group_bytes = 256;
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screen->cpp = dri_priv->bpp / 8;
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screen->AGPMode = dri_priv->AGPMode;
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ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp);
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/* +r6/r7 */
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if(screen->chip_family >= CHIP_FAMILY_R600)
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{
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if (ret)
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{
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FREE( screen );
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fprintf(stderr, "Unable to get fb location need newer drm\n");
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return NULL;
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}
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else
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{
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screen->fbLocation = (temp & 0xffff) << 24;
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}
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}
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else
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{
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if (ret)
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{
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if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm)
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screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
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else
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{
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FREE( screen );
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fprintf(stderr, "Unable to get fb location need newer drm\n");
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return NULL;
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}
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}
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else
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{
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screen->fbLocation = (temp & 0xffff) << 16;
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}
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}
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if (IS_R300_CLASS(screen)) {
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ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
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if (ret) {
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fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
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switch (screen->chip_family) {
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case CHIP_FAMILY_R300:
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case CHIP_FAMILY_R350:
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screen->num_gb_pipes = 2;
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break;
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case CHIP_FAMILY_R420:
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case CHIP_FAMILY_R520:
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case CHIP_FAMILY_R580:
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case CHIP_FAMILY_RV560:
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case CHIP_FAMILY_RV570:
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screen->num_gb_pipes = 4;
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break;
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case CHIP_FAMILY_RV350:
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case CHIP_FAMILY_RV515:
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case CHIP_FAMILY_RV530:
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case CHIP_FAMILY_RV410:
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default:
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screen->num_gb_pipes = 1;
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break;
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}
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} else {
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screen->num_gb_pipes = temp;
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}
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/* pipe overrides */
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switch (dri_priv->deviceID) {
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case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
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case PCI_CHIP_R350_AH: /* 9800 SE only have 1 quadpipe */
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case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
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case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
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screen->num_gb_pipes = 1;
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break;
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default:
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break;
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}
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if ( sPriv->drm_version.minor >= 31 ) {
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ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp);
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if (ret)
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screen->num_z_pipes = 2;
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else
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screen->num_z_pipes = temp;
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} else
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screen->num_z_pipes = 2;
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}
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if ( sPriv->drm_version.minor >= 10 ) {
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drm_radeon_setparam_t sp;
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sp.param = RADEON_SETPARAM_FB_LOCATION;
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sp.value = screen->fbLocation;
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drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
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&sp, sizeof( sp ) );
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}
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screen->frontOffset = dri_priv->frontOffset;
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screen->frontPitch = dri_priv->frontPitch;
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screen->backOffset = dri_priv->backOffset;
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screen->backPitch = dri_priv->backPitch;
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screen->depthOffset = dri_priv->depthOffset;
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screen->depthPitch = dri_priv->depthPitch;
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/* Check if ddx has set up a surface reg to cover depth buffer */
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screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
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/* these chips don't use tiled z without hyperz. So always pretend
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we have set up a surface which will cause linear reads/writes */
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(IS_R100_CLASS(screen) &&
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!(screen->chip_flags & RADEON_CHIPSET_TCL));
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if ( dri_priv->textureSize == 0 ) {
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screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
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screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
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screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
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dri_priv->log2GARTTexGran;
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} else {
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screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
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+ screen->fbLocation;
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screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
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screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
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dri_priv->log2TexGran;
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}
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if ( !screen->gartTextures.map || dri_priv->textureSize == 0
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|| getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
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screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
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screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
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screen->texSize[RADEON_GART_TEX_HEAP] = 0;
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screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
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} else {
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screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
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screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
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screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
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screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
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dri_priv->log2GARTTexGran;
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}
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i = 0;
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screen->extensions[i++] = &driCopySubBufferExtension.base;
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screen->extensions[i++] = &driReadDrawableExtension;
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if ( screen->irq != 0 ) {
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screen->extensions[i++] = &driSwapControlExtension.base;
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screen->extensions[i++] = &driMediaStreamCounterExtension.base;
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}
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#if defined(RADEON_R100)
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screen->extensions[i++] = &radeonTexOffsetExtension.base;
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#endif
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#if defined(RADEON_R200)
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screen->extensions[i++] = &r200texOffsetExtension.base;
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#endif
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#if defined(RADEON_R300)
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screen->extensions[i++] = &r300texOffsetExtension.base;
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#endif
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#if defined(RADEON_R600)
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screen->extensions[i++] = &r600texOffsetExtension.base;
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#endif
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screen->extensions[i++] = &dri2ConfigQueryExtension.base;
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screen->extensions[i++] = NULL;
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sPriv->extensions = screen->extensions;
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screen->driScreen = sPriv;
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screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
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screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
|
||||
screen->sarea_priv_offset);
|
||||
|
||||
screen->bom = radeon_bo_manager_legacy_ctor(screen);
|
||||
if (screen->bom == NULL) {
|
||||
free(screen);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return screen;
|
||||
}
|
||||
|
||||
static radeonScreenPtr
|
||||
radeonCreateScreen2(__DRIscreen *sPriv)
|
||||
{
|
||||
|
|
@ -1618,7 +1193,6 @@ radeonCreateScreen2(__DRIscreen *sPriv)
|
|||
driParseOptionInfo (&screen->optionCache,
|
||||
__driConfigOptions, __driNConfigOptions);
|
||||
|
||||
screen->kernel_mm = 1;
|
||||
screen->chip_flags = 0;
|
||||
|
||||
/* if we have kms we can support all of these */
|
||||
|
|
@ -1862,21 +1436,10 @@ radeonDestroyScreen( __DRIscreen *sPriv )
|
|||
if (!screen)
|
||||
return;
|
||||
|
||||
if (screen->kernel_mm) {
|
||||
#ifdef RADEON_BO_TRACK
|
||||
radeon_tracker_print(&screen->bom->tracker, stderr);
|
||||
radeon_tracker_print(&screen->bom->tracker, stderr);
|
||||
#endif
|
||||
radeon_bo_manager_gem_dtor(screen->bom);
|
||||
} else {
|
||||
radeon_bo_manager_legacy_dtor(screen->bom);
|
||||
|
||||
if ( screen->gartTextures.map ) {
|
||||
drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
|
||||
}
|
||||
drmUnmapBufs( screen->buffers );
|
||||
drmUnmap( screen->status.map, screen->status.size );
|
||||
drmUnmap( screen->mmio.map, screen->mmio.size );
|
||||
}
|
||||
radeon_bo_manager_gem_dtor(screen->bom);
|
||||
|
||||
/* free all option information */
|
||||
driDestroyOptionInfo (&screen->optionCache);
|
||||
|
|
@ -1891,11 +1454,9 @@ radeonDestroyScreen( __DRIscreen *sPriv )
|
|||
static GLboolean
|
||||
radeonInitDriver( __DRIscreen *sPriv )
|
||||
{
|
||||
if (sPriv->dri2.enabled) {
|
||||
sPriv->private = (void *) radeonCreateScreen2( sPriv );
|
||||
} else {
|
||||
sPriv->private = (void *) radeonCreateScreen( sPriv );
|
||||
}
|
||||
assert(sPriv->dri2.enabled);
|
||||
|
||||
sPriv->private = (void *) radeonCreateScreen2( sPriv );
|
||||
if ( !sPriv->private ) {
|
||||
radeonDestroyScreen( sPriv );
|
||||
return GL_FALSE;
|
||||
|
|
@ -2026,56 +1587,6 @@ radeonDestroyBuffer(__DRIdrawable *driDrawPriv)
|
|||
_mesa_reference_framebuffer((struct gl_framebuffer **)(&(driDrawPriv->driverPrivate)), NULL);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* This is the driver specific part of the createNewScreen entry point.
|
||||
*
|
||||
* \todo maybe fold this into intelInitDriver
|
||||
*
|
||||
* \return the struct gl_config supported by this driver
|
||||
*/
|
||||
static const __DRIconfig **
|
||||
radeonInitScreen(__DRIscreen *psp)
|
||||
{
|
||||
#if defined(RADEON_R100)
|
||||
static const char *driver_name = "Radeon";
|
||||
static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
|
||||
static const __DRIversion dri_expected = { 4, 0, 0 };
|
||||
static const __DRIversion drm_expected = { 1, 6, 0 };
|
||||
#elif defined(RADEON_R200)
|
||||
static const char *driver_name = "R200";
|
||||
static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
|
||||
static const __DRIversion dri_expected = { 4, 0, 0 };
|
||||
static const __DRIversion drm_expected = { 1, 6, 0 };
|
||||
#elif defined(RADEON_R300)
|
||||
static const char *driver_name = "R300";
|
||||
static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
|
||||
static const __DRIversion dri_expected = { 4, 0, 0 };
|
||||
static const __DRIversion drm_expected = { 1, 24, 0 };
|
||||
#elif defined(RADEON_R600)
|
||||
static const char *driver_name = "R600";
|
||||
static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
|
||||
static const __DRIversion dri_expected = { 4, 0, 0 };
|
||||
static const __DRIversion drm_expected = { 1, 24, 0 };
|
||||
#endif
|
||||
RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
|
||||
|
||||
if ( ! driCheckDriDdxDrmVersions3( driver_name,
|
||||
&psp->dri_version, & dri_expected,
|
||||
&psp->ddx_version, & ddx_expected,
|
||||
&psp->drm_version, & drm_expected ) ) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (!radeonInitDriver(psp))
|
||||
return NULL;
|
||||
|
||||
/* for now fill in all modes */
|
||||
return radeonFillInModes( psp,
|
||||
dri_priv->bpp,
|
||||
(dri_priv->bpp == 16) ? 16 : 24,
|
||||
(dri_priv->bpp == 16) ? 0 : 8, 1);
|
||||
}
|
||||
#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
|
||||
|
||||
/**
|
||||
|
|
@ -2176,7 +1687,6 @@ getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo )
|
|||
}
|
||||
|
||||
const struct __DriverAPIRec driDriverAPI = {
|
||||
.InitScreen = radeonInitScreen,
|
||||
.DestroyScreen = radeonDestroyScreen,
|
||||
#if defined(RADEON_R200)
|
||||
.CreateContext = r200CreateContext,
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue