From 910f5a18cf891828ff2675bfc5290a459783f99b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tapani=20P=C3=A4lli?= <tapani.palli@intel.com>
Date: Wed, 23 Nov 2022 08:40:59 +0200
Subject: [PATCH] intel/genxml: add disable preemption field for gen125
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Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20438>
---
 src/intel/genxml/gen125.xml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml
index 72c076f93aa..1cb5d11503e 100644
--- a/src/intel/genxml/gen125.xml
+++ b/src/intel/genxml/gen125.xml
@@ -7414,7 +7414,9 @@
       <value name="Mid-cmdbuffer Preemption" value="0" />
       <value name="Object Level Preemption" value="1" />
     </field>
+    <field name="Disable Preemption and High Priority Pausing due to 3DPRIMITIVE Command" start="10" end="10" type="bool" />
     <field name="Replay Mode Mask" start="16" end="16" type="bool" />
+    <field name="Disable Preemption and High Priority Pausing due to 3DPRIMITIVE Command Mask" start="26" end="26" type="bool" />
   </register>
   <register name="CS_DEBUG_MODE2" length="1" num="0x20d8">
     <field name="3D Rendering Instruction Disable" start="0" end="0" type="bool" />
@@ -7704,4 +7706,4 @@
   <register name="VS_INVOCATION_COUNT" length="2" num="0x2320">
     <field name="VS Invocation Count Report" start="0" end="63" type="uint" />
   </register>
-</genxml>
\ No newline at end of file
+</genxml>