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radv: add a new dirty state for the VRS surface state on GFX11+

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Unlike GFX10.3, on GFX11+ VRS override is part of PA_SC_VRS_OVERRIDE_CNTL
which also controls whether the VRS surface is enabled or not. This
new dirty state will allow us to re-emit that state without re-emitting
the complete framebuffer for VRS flat shading.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38527>
This commit is contained in:
Samuel Pitoiset 2025-11-18 19:41:07 +01:00 • committed by Marge Bot
parent af461de026
commit 90f761a7d5
2 changed files with 15 additions and 5 deletions
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17
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -5478,7 +5478,7 @@ radv_emit_mip_change_flush_default(struct radv_cmd_buffer *cmd_buffer)
}
static void
radv_gfx11_emit_vrs_surface(struct radv_cmd_buffer *cmd_buffer)
radv_emit_fsr_surface_state(struct radv_cmd_buffer *cmd_buffer)
{
const struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
@ -5489,6 +5489,8 @@ radv_gfx11_emit_vrs_surface(struct radv_cmd_buffer *cmd_buffer)
uint8_t swizzle_mode = 0;
uint64_t va = 0;
assert(pdev->info.gfx_level >= GFX11);
if (vrs_surface_enable) {
const struct radv_image_view *vrs_iview = render->vrs_att.iview;
struct radv_image *vrs_image = vrs_iview->image;
@ -5687,9 +5689,6 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
radv_gfx6_emit_null_ds_state(cmd_buffer);
}
if (pdev->info.gfx_level >= GFX11)
radv_gfx11_emit_vrs_surface(cmd_buffer);
assert(cs->b->cdw <= cdw_max);
}
@ -9757,6 +9756,9 @@ radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCou
}
}
}
if (primary->state.render.active && (primary->state.dirty & RADV_CMD_DIRTY_FSR_SURFACE_STATE))
radv_emit_fsr_surface_state(primary);
}
if (secondary->gang.cs) {
@ -10162,6 +10164,8 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RBPLUS;
if (pdev->info.gfx_level >= GFX10_3)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FSR_STATE;
if (pdev->info.gfx_level >= GFX11)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FSR_SURFACE_STATE;
if (render->vrs_att.iview && pdev->info.gfx_level == GFX10_3) {
if (render->ds_att.iview &&
@ -12564,6 +12568,11 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r
cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
}
if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FSR_SURFACE_STATE) {
radv_emit_fsr_surface_state(cmd_buffer);
cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FSR_SURFACE_STATE;
}
if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_GUARDBAND) {
radv_emit_guardband_state(cmd_buffer);
cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_GUARDBAND;

3
src/amd/vulkan/radv_cmd_buffer.h
View file

@ -123,7 +123,8 @@ enum radv_cmd_dirty_bits {
RADV_CMD_DIRTY_NGGC_SETTINGS = 1ull << 36,
RADV_CMD_DIRTY_PS_EPILOG_SHADER = 1ull << 37,
RADV_CMD_DIRTY_PS_EPILOG_STATE = 1ull << 38,
RADV_CMD_DIRTY_ALL = (1ull << 39) - 1,
RADV_CMD_DIRTY_FSR_SURFACE_STATE = 1ull << 39,
RADV_CMD_DIRTY_ALL = (1ull << 40) - 1,
RADV_CMD_DIRTY_SHADER_QUERY = RADV_CMD_DIRTY_NGG_STATE | RADV_CMD_DIRTY_TASK_STATE,
};