From 9033916d84e11cc8272b89411a9ec74b8f642685 Mon Sep 17 00:00:00 2001 From: Connor Abbott Date: Thu, 9 Sep 2021 14:16:08 +0200 Subject: [PATCH] ir3: Add bar to beginning of HS with tess_use_shared This matches the blob. In theory, this is necessary only because the VS/HS workgroup can now span more than one wave and a patch may be assigned to different waves in the VS and HS. However I've seen it fix tests where the entire draw should fit in one wave, so there may some other sort of waiting this does or the HW dispatch may be inefficient sometimes. Fixes EQP-VK.tessellation.user_defined_io.per_patch.vertex_io_array_size_implicit.* when run immediately after dEQP-VK.tessellation.invariance.outer_triangle_set.quads_fractional_even_spacing or when all of dEQP-VK.tessellation.* is run in sequence on a650. Part-of: --- src/freedreno/ir3/ir3_compiler_nir.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index cf2b087eaf5..18509be2148 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -3805,6 +3805,15 @@ emit_instructions(struct ir3_context *ctx) nir_foreach_register (reg, &fxn->registers) { ir3_declare_array(ctx, reg); } + + if (ctx->so->type == MESA_SHADER_TESS_CTRL && + ctx->compiler->tess_use_shared) { + struct ir3_instruction *barrier = ir3_BAR(ctx->block); + barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY; + barrier->barrier_class = IR3_BARRIER_EVERYTHING; + array_insert(ctx->block, ctx->block->keeps, barrier); + } + /* And emit the body: */ ctx->impl = fxn; emit_function(ctx, fxn);