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tu: C++-proofing: cast result when extracting field from reg value

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Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
This commit is contained in:
Danylo Piliaiev 2023-03-15 11:33:32 +01:00 • committed by Marge Bot
parent 28a703ea43
commit 903072ea03
3 changed files with 36 additions and 29 deletions
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13
src/freedreno/vulkan/tu_clear_blit.c
View file

@ -248,7 +248,8 @@ r2d_src(struct tu_cmd_buffer *cmd,
if (filter != VK_FILTER_NEAREST)
src_info |= A6XX_SP_PS_2D_SRC_INFO_FILTER;
enum a6xx_format fmt = (src_info & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK);
enum a6xx_format fmt = (enum a6xx_format)(
src_info & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK);
enum pipe_format src_format = iview->format;
fixup_src_format(&src_format, dst_format, &fmt);
@ -327,7 +328,8 @@ r2d_dst(struct tu_cs *cs, const struct fdl6_view *iview, uint32_t layer,
enum pipe_format src_format)
{
uint32_t dst_info = iview->RB_2D_DST_INFO;
enum a6xx_format fmt = dst_info & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
enum a6xx_format fmt =
(enum a6xx_format)(dst_info & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK);
enum pipe_format dst_format = iview->format;
fixup_dst_format(src_format, &dst_format, &fmt);
@ -1049,8 +1051,8 @@ r3d_src(struct tu_cmd_buffer *cmd,
uint32_t desc[A6XX_TEX_CONST_DWORDS];
memcpy(desc, iview->descriptor, sizeof(desc));
enum a6xx_format fmt = (desc[0] & A6XX_TEX_CONST_0_FMT__MASK) >>
A6XX_TEX_CONST_0_FMT__SHIFT;
enum a6xx_format fmt = (enum a6xx_format)(
(desc[0] & A6XX_TEX_CONST_0_FMT__MASK) >> A6XX_TEX_CONST_0_FMT__SHIFT);
enum pipe_format src_format = iview->format;
fixup_src_format(&src_format, dst_format, &fmt);
desc[0] = (desc[0] & ~A6XX_TEX_CONST_0_FMT__MASK) |
@ -1143,7 +1145,8 @@ r3d_dst(struct tu_cs *cs, const struct fdl6_view *iview, uint32_t layer,
{
uint32_t mrt_buf_info = iview->RB_MRT_BUF_INFO;
enum a6xx_format fmt = mrt_buf_info & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
enum a6xx_format fmt = (enum a6xx_format)(
mrt_buf_info & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK);
enum pipe_format dst_format = iview->format;
fixup_dst_format(src_format, &dst_format, &fmt);
mrt_buf_info =

33
src/freedreno/vulkan/tu_cmd_buffer.c
View file

@ -1237,8 +1237,9 @@ tu_emit_input_attachments(struct tu_cmd_buffer *cmd,
* of a renderpass. We have to patch the descriptor to make it compatible
* with how it is sampled in shader.
*/
enum a6xx_tex_type tex_type = (dst[2] & A6XX_TEX_CONST_2_TYPE__MASK) >>
A6XX_TEX_CONST_2_TYPE__SHIFT;
enum a6xx_tex_type tex_type =
(enum a6xx_tex_type)((dst[2] & A6XX_TEX_CONST_2_TYPE__MASK) >>
A6XX_TEX_CONST_2_TYPE__SHIFT);
if (tex_type == A6XX_TEX_CUBE) {
dst[2] &= ~A6XX_TEX_CONST_2_TYPE__MASK;
dst[2] |= A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D);
@ -4786,18 +4787,18 @@ tu6_update_simplified_stencil_state(struct tu_cmd_buffer *cmd)
((cmd->state.dynamic_stencil_wrmask & 0xff00) >> 8) :
(cmd->state.pipeline->ds.stencil_wrmask & 0xff00) >> 8;
VkStencilOp front_fail_op =
(cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FAIL__MASK) >> A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT;
VkStencilOp front_pass_op =
(cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK) >> A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT;
VkStencilOp front_depth_fail_op =
(cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK) >> A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT;
VkStencilOp back_fail_op =
(cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK) >> A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT;
VkStencilOp back_pass_op =
(cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK) >> A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT;
VkStencilOp back_depth_fail_op =
(cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK) >> A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT;
VkStencilOp front_fail_op = (VkStencilOp)
((cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FAIL__MASK) >> A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT);
VkStencilOp front_pass_op = (VkStencilOp)
((cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK) >> A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT);
VkStencilOp front_depth_fail_op = (VkStencilOp)
((cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK) >> A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT);
VkStencilOp back_fail_op = (VkStencilOp)
((cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK) >> A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT);
VkStencilOp back_pass_op = (VkStencilOp)
((cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK) >> A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT);
VkStencilOp back_depth_fail_op = (VkStencilOp)
((cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK) >> A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT);
bool stencil_front_op_writes =
front_pass_op != VK_STENCIL_OP_KEEP ||
@ -4821,8 +4822,8 @@ tu6_writes_depth(struct tu_cmd_buffer *cmd, bool depth_test_enable)
bool depth_write_enable =
cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
VkCompareOp depth_compare_op =
(cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK) >> A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT;
VkCompareOp depth_compare_op = (VkCompareOp)
((cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK) >> A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT);
bool depth_compare_op_writes = depth_compare_op != VK_COMPARE_OP_NEVER;

19
src/freedreno/vulkan/tu_lrz.c
View file

@ -560,10 +560,13 @@ tu6_calculate_lrz_state(struct tu_cmd_buffer *cmd,
const uint32_t a)
{
struct tu_pipeline *pipeline = cmd->state.pipeline;
bool z_test_enable = cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
bool z_write_enable = cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
bool z_bounds_enable = cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE;
VkCompareOp depth_compare_op = (cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK) >> A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT;
bool z_test_enable = (bool) (cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE);
bool z_write_enable = (bool) (cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE);
bool z_bounds_enable = (bool) (cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE);
VkCompareOp depth_compare_op =
(VkCompareOp) ((cmd->state.rb_depth_cntl &
A6XX_RB_DEPTH_CNTL_ZFUNC__MASK) >>
A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT);
struct A6XX_GRAS_LRZ_CNTL gras_lrz_cntl = { 0 };
@ -760,11 +763,11 @@ tu6_calculate_lrz_state(struct tu_cmd_buffer *cmd,
/* Invalidate LRZ and disable write if stencil test is enabled */
bool stencil_test_enable = cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE;
if (!disable_lrz && stencil_test_enable) {
VkCompareOp stencil_front_compare_op =
(cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FUNC__MASK) >> A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT;
VkCompareOp stencil_front_compare_op = (VkCompareOp)
((cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FUNC__MASK) >> A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT);
VkCompareOp stencil_back_compare_op =
(cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK) >> A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT;
VkCompareOp stencil_back_compare_op = (VkCompareOp)
((cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK) >> A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT);
bool lrz_allowed = true;
lrz_allowed = lrz_allowed && tu6_stencil_op_lrz_allowed(