diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index fa2174bac5d..ea53697c503 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -75,134 +75,134 @@ * This is the only reason why the buffer descriptor must be in words [4:7]. */ static uint32_t null_texture_descriptor[8] = { - 0, - 0, - 0, - S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1) | - S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D) - /* the rest must contain zeros, which is also used by the buffer - * descriptor */ + 0, + 0, + 0, + S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_1) | + S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D) + /* the rest must contain zeros, which is also used by the buffer + * descriptor */ }; static uint32_t null_image_descriptor[8] = { - 0, - 0, - 0, - S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D) - /* the rest must contain zeros, which is also used by the buffer - * descriptor */ + 0, + 0, + 0, + S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D) + /* the rest must contain zeros, which is also used by the buffer + * descriptor */ }; static uint64_t si_desc_extract_buffer_address(const uint32_t *desc) { - uint64_t va = desc[0] | - ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc[1]) << 32); + uint64_t va = desc[0] | + ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc[1]) << 32); - /* Sign-extend the 48-bit address. */ - va <<= 16; - va = (int64_t)va >> 16; - return va; + /* Sign-extend the 48-bit address. */ + va <<= 16; + va = (int64_t)va >> 16; + return va; } static void si_init_descriptor_list(uint32_t *desc_list, - unsigned element_dw_size, - unsigned num_elements, - const uint32_t *null_descriptor) + unsigned element_dw_size, + unsigned num_elements, + const uint32_t *null_descriptor) { - int i; + int i; - /* Initialize the array to NULL descriptors if the element size is 8. */ - if (null_descriptor) { - assert(element_dw_size % 8 == 0); - for (i = 0; i < num_elements * element_dw_size / 8; i++) - memcpy(desc_list + i * 8, null_descriptor, 8 * 4); - } + /* Initialize the array to NULL descriptors if the element size is 8. */ + if (null_descriptor) { + assert(element_dw_size % 8 == 0); + for (i = 0; i < num_elements * element_dw_size / 8; i++) + memcpy(desc_list + i * 8, null_descriptor, 8 * 4); + } } static void si_init_descriptors(struct si_descriptors *desc, - short shader_userdata_rel_index, - unsigned element_dw_size, - unsigned num_elements) + short shader_userdata_rel_index, + unsigned element_dw_size, + unsigned num_elements) { - desc->list = CALLOC(num_elements, element_dw_size * 4); - desc->element_dw_size = element_dw_size; - desc->num_elements = num_elements; - desc->shader_userdata_offset = shader_userdata_rel_index * 4; - desc->slot_index_to_bind_directly = -1; + desc->list = CALLOC(num_elements, element_dw_size * 4); + desc->element_dw_size = element_dw_size; + desc->num_elements = num_elements; + desc->shader_userdata_offset = shader_userdata_rel_index * 4; + desc->slot_index_to_bind_directly = -1; } static void si_release_descriptors(struct si_descriptors *desc) { - si_resource_reference(&desc->buffer, NULL); - FREE(desc->list); + si_resource_reference(&desc->buffer, NULL); + FREE(desc->list); } static bool si_upload_descriptors(struct si_context *sctx, - struct si_descriptors *desc) + struct si_descriptors *desc) { - unsigned slot_size = desc->element_dw_size * 4; - unsigned first_slot_offset = desc->first_active_slot * slot_size; - unsigned upload_size = desc->num_active_slots * slot_size; + unsigned slot_size = desc->element_dw_size * 4; + unsigned first_slot_offset = desc->first_active_slot * slot_size; + unsigned upload_size = desc->num_active_slots * slot_size; - /* Skip the upload if no shader is using the descriptors. dirty_mask - * will stay dirty and the descriptors will be uploaded when there is - * a shader using them. - */ - if (!upload_size) - return true; + /* Skip the upload if no shader is using the descriptors. dirty_mask + * will stay dirty and the descriptors will be uploaded when there is + * a shader using them. + */ + if (!upload_size) + return true; - /* If there is just one active descriptor, bind it directly. */ - if ((int)desc->first_active_slot == desc->slot_index_to_bind_directly && - desc->num_active_slots == 1) { - uint32_t *descriptor = &desc->list[desc->slot_index_to_bind_directly * - desc->element_dw_size]; + /* If there is just one active descriptor, bind it directly. */ + if ((int)desc->first_active_slot == desc->slot_index_to_bind_directly && + desc->num_active_slots == 1) { + uint32_t *descriptor = &desc->list[desc->slot_index_to_bind_directly * + desc->element_dw_size]; - /* The buffer is already in the buffer list. */ - si_resource_reference(&desc->buffer, NULL); - desc->gpu_list = NULL; - desc->gpu_address = si_desc_extract_buffer_address(descriptor); - si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers); - return true; - } + /* The buffer is already in the buffer list. */ + si_resource_reference(&desc->buffer, NULL); + desc->gpu_list = NULL; + desc->gpu_address = si_desc_extract_buffer_address(descriptor); + si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers); + return true; + } - uint32_t *ptr; - unsigned buffer_offset; - u_upload_alloc(sctx->b.const_uploader, first_slot_offset, upload_size, - si_optimal_tcc_alignment(sctx, upload_size), - &buffer_offset, (struct pipe_resource**)&desc->buffer, - (void**)&ptr); - if (!desc->buffer) { - desc->gpu_address = 0; - return false; /* skip the draw call */ - } + uint32_t *ptr; + unsigned buffer_offset; + u_upload_alloc(sctx->b.const_uploader, first_slot_offset, upload_size, + si_optimal_tcc_alignment(sctx, upload_size), + &buffer_offset, (struct pipe_resource**)&desc->buffer, + (void**)&ptr); + if (!desc->buffer) { + desc->gpu_address = 0; + return false; /* skip the draw call */ + } - util_memcpy_cpu_to_le32(ptr, (char*)desc->list + first_slot_offset, - upload_size); - desc->gpu_list = ptr - first_slot_offset / 4; + util_memcpy_cpu_to_le32(ptr, (char*)desc->list + first_slot_offset, + upload_size); + desc->gpu_list = ptr - first_slot_offset / 4; - radeon_add_to_buffer_list(sctx, sctx->gfx_cs, desc->buffer, + radeon_add_to_buffer_list(sctx, sctx->gfx_cs, desc->buffer, RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS); - /* The shader pointer should point to slot 0. */ - buffer_offset -= first_slot_offset; - desc->gpu_address = desc->buffer->gpu_address + buffer_offset; + /* The shader pointer should point to slot 0. */ + buffer_offset -= first_slot_offset; + desc->gpu_address = desc->buffer->gpu_address + buffer_offset; - assert(desc->buffer->flags & RADEON_FLAG_32BIT); - assert((desc->buffer->gpu_address >> 32) == sctx->screen->info.address32_hi); - assert((desc->gpu_address >> 32) == sctx->screen->info.address32_hi); + assert(desc->buffer->flags & RADEON_FLAG_32BIT); + assert((desc->buffer->gpu_address >> 32) == sctx->screen->info.address32_hi); + assert((desc->gpu_address >> 32) == sctx->screen->info.address32_hi); - si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers); - return true; + si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers); + return true; } static void si_descriptors_begin_new_cs(struct si_context *sctx, struct si_descriptors *desc) { - if (!desc->buffer) - return; + if (!desc->buffer) + return; - radeon_add_to_buffer_list(sctx, sctx->gfx_cs, desc->buffer, - RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS); + radeon_add_to_buffer_list(sctx, sctx->gfx_cs, desc->buffer, + RADEON_USAGE_READ, RADEON_PRIO_DESCRIPTORS); } /* SAMPLER VIEWS */ @@ -210,429 +210,429 @@ si_descriptors_begin_new_cs(struct si_context *sctx, struct si_descriptors *desc static inline enum radeon_bo_priority si_get_sampler_view_priority(struct si_resource *res) { - if (res->b.b.target == PIPE_BUFFER) - return RADEON_PRIO_SAMPLER_BUFFER; + if (res->b.b.target == PIPE_BUFFER) + return RADEON_PRIO_SAMPLER_BUFFER; - if (res->b.b.nr_samples > 1) - return RADEON_PRIO_SAMPLER_TEXTURE_MSAA; + if (res->b.b.nr_samples > 1) + return RADEON_PRIO_SAMPLER_TEXTURE_MSAA; - return RADEON_PRIO_SAMPLER_TEXTURE; + return RADEON_PRIO_SAMPLER_TEXTURE; } static struct si_descriptors * si_sampler_and_image_descriptors(struct si_context *sctx, unsigned shader) { - return &sctx->descriptors[si_sampler_and_image_descriptors_idx(shader)]; + return &sctx->descriptors[si_sampler_and_image_descriptors_idx(shader)]; } static void si_release_sampler_views(struct si_samplers *samplers) { - int i; + int i; - for (i = 0; i < ARRAY_SIZE(samplers->views); i++) { - pipe_sampler_view_reference(&samplers->views[i], NULL); - } + for (i = 0; i < ARRAY_SIZE(samplers->views); i++) { + pipe_sampler_view_reference(&samplers->views[i], NULL); + } } static void si_sampler_view_add_buffer(struct si_context *sctx, - struct pipe_resource *resource, - enum radeon_bo_usage usage, - bool is_stencil_sampler, - bool check_mem) + struct pipe_resource *resource, + enum radeon_bo_usage usage, + bool is_stencil_sampler, + bool check_mem) { - struct si_texture *tex = (struct si_texture*)resource; - enum radeon_bo_priority priority; + struct si_texture *tex = (struct si_texture*)resource; + enum radeon_bo_priority priority; - if (!resource) - return; + if (!resource) + return; - /* Use the flushed depth texture if direct sampling is unsupported. */ - if (resource->target != PIPE_BUFFER && - tex->is_depth && !si_can_sample_zs(tex, is_stencil_sampler)) - tex = tex->flushed_depth_texture; + /* Use the flushed depth texture if direct sampling is unsupported. */ + if (resource->target != PIPE_BUFFER && + tex->is_depth && !si_can_sample_zs(tex, is_stencil_sampler)) + tex = tex->flushed_depth_texture; - priority = si_get_sampler_view_priority(&tex->buffer); - radeon_add_to_gfx_buffer_list_check_mem(sctx, &tex->buffer, usage, priority, - check_mem); + priority = si_get_sampler_view_priority(&tex->buffer); + radeon_add_to_gfx_buffer_list_check_mem(sctx, &tex->buffer, usage, priority, + check_mem); - if (resource->target == PIPE_BUFFER) - return; + if (resource->target == PIPE_BUFFER) + return; - /* Add separate DCC. */ - if (tex->dcc_separate_buffer) { - radeon_add_to_gfx_buffer_list_check_mem(sctx, tex->dcc_separate_buffer, - usage, RADEON_PRIO_SEPARATE_META, check_mem); - } + /* Add separate DCC. */ + if (tex->dcc_separate_buffer) { + radeon_add_to_gfx_buffer_list_check_mem(sctx, tex->dcc_separate_buffer, + usage, RADEON_PRIO_SEPARATE_META, check_mem); + } } static void si_sampler_views_begin_new_cs(struct si_context *sctx, - struct si_samplers *samplers) + struct si_samplers *samplers) { - unsigned mask = samplers->enabled_mask; + unsigned mask = samplers->enabled_mask; - /* Add buffers to the CS. */ - while (mask) { - int i = u_bit_scan(&mask); - struct si_sampler_view *sview = (struct si_sampler_view *)samplers->views[i]; + /* Add buffers to the CS. */ + while (mask) { + int i = u_bit_scan(&mask); + struct si_sampler_view *sview = (struct si_sampler_view *)samplers->views[i]; - si_sampler_view_add_buffer(sctx, sview->base.texture, - RADEON_USAGE_READ, - sview->is_stencil_sampler, false); - } + si_sampler_view_add_buffer(sctx, sview->base.texture, + RADEON_USAGE_READ, + sview->is_stencil_sampler, false); + } } /* Set buffer descriptor fields that can be changed by reallocations. */ static void si_set_buf_desc_address(struct si_resource *buf, - uint64_t offset, uint32_t *state) + uint64_t offset, uint32_t *state) { - uint64_t va = buf->gpu_address + offset; + uint64_t va = buf->gpu_address + offset; - state[0] = va; - state[1] &= C_008F04_BASE_ADDRESS_HI; - state[1] |= S_008F04_BASE_ADDRESS_HI(va >> 32); + state[0] = va; + state[1] &= C_008F04_BASE_ADDRESS_HI; + state[1] |= S_008F04_BASE_ADDRESS_HI(va >> 32); } /* Set texture descriptor fields that can be changed by reallocations. * - * \param tex texture - * \param base_level_info information of the level of BASE_ADDRESS - * \param base_level the level of BASE_ADDRESS - * \param first_level pipe_sampler_view.u.tex.first_level - * \param block_width util_format_get_blockwidth() - * \param is_stencil select between separate Z & Stencil - * \param state descriptor to update + * \param tex texture + * \param base_level_info information of the level of BASE_ADDRESS + * \param base_level the level of BASE_ADDRESS + * \param first_level pipe_sampler_view.u.tex.first_level + * \param block_width util_format_get_blockwidth() + * \param is_stencil select between separate Z & Stencil + * \param state descriptor to update */ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, - struct si_texture *tex, - const struct legacy_surf_level *base_level_info, - unsigned base_level, unsigned first_level, - unsigned block_width, bool is_stencil, - uint32_t *state) + struct si_texture *tex, + const struct legacy_surf_level *base_level_info, + unsigned base_level, unsigned first_level, + unsigned block_width, bool is_stencil, + uint32_t *state) { - uint64_t va, meta_va = 0; + uint64_t va, meta_va = 0; - if (tex->is_depth && !si_can_sample_zs(tex, is_stencil)) { - tex = tex->flushed_depth_texture; - is_stencil = false; - } + if (tex->is_depth && !si_can_sample_zs(tex, is_stencil)) { + tex = tex->flushed_depth_texture; + is_stencil = false; + } - va = tex->buffer.gpu_address; + va = tex->buffer.gpu_address; - if (sscreen->info.chip_class >= GFX9) { - /* Only stencil_offset needs to be added here. */ - if (is_stencil) - va += tex->surface.u.gfx9.stencil_offset; - else - va += tex->surface.u.gfx9.surf_offset; - } else { - va += base_level_info->offset; - } + if (sscreen->info.chip_class >= GFX9) { + /* Only stencil_offset needs to be added here. */ + if (is_stencil) + va += tex->surface.u.gfx9.stencil_offset; + else + va += tex->surface.u.gfx9.surf_offset; + } else { + va += base_level_info->offset; + } - state[0] = va >> 8; - state[1] &= C_008F14_BASE_ADDRESS_HI; - state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40); + state[0] = va >> 8; + state[1] &= C_008F14_BASE_ADDRESS_HI; + state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40); - /* Only macrotiled modes can set tile swizzle. - * GFX9 doesn't use (legacy) base_level_info. - */ - if (sscreen->info.chip_class >= GFX9 || - base_level_info->mode == RADEON_SURF_MODE_2D) - state[0] |= tex->surface.tile_swizzle; + /* Only macrotiled modes can set tile swizzle. + * GFX9 doesn't use (legacy) base_level_info. + */ + if (sscreen->info.chip_class >= GFX9 || + base_level_info->mode == RADEON_SURF_MODE_2D) + state[0] |= tex->surface.tile_swizzle; - if (sscreen->info.chip_class >= GFX8) { - state[6] &= C_008F28_COMPRESSION_EN; + if (sscreen->info.chip_class >= GFX8) { + state[6] &= C_008F28_COMPRESSION_EN; - if (vi_dcc_enabled(tex, first_level)) { - meta_va = (!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) + - tex->surface.dcc_offset; + if (vi_dcc_enabled(tex, first_level)) { + meta_va = (!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) + + tex->surface.dcc_offset; - if (sscreen->info.chip_class == GFX8) { - meta_va += base_level_info->dcc_offset; - assert(base_level_info->mode == RADEON_SURF_MODE_2D); - } + if (sscreen->info.chip_class == GFX8) { + meta_va += base_level_info->dcc_offset; + assert(base_level_info->mode == RADEON_SURF_MODE_2D); + } - unsigned dcc_tile_swizzle = tex->surface.tile_swizzle << 8; - dcc_tile_swizzle &= tex->surface.dcc_alignment - 1; - meta_va |= dcc_tile_swizzle; - } else if (vi_tc_compat_htile_enabled(tex, first_level, - is_stencil ? PIPE_MASK_S : PIPE_MASK_Z)) { - meta_va = tex->buffer.gpu_address + tex->surface.htile_offset; - } + unsigned dcc_tile_swizzle = tex->surface.tile_swizzle << 8; + dcc_tile_swizzle &= tex->surface.dcc_alignment - 1; + meta_va |= dcc_tile_swizzle; + } else if (vi_tc_compat_htile_enabled(tex, first_level, + is_stencil ? PIPE_MASK_S : PIPE_MASK_Z)) { + meta_va = tex->buffer.gpu_address + tex->surface.htile_offset; + } - if (meta_va) - state[6] |= S_008F28_COMPRESSION_EN(1); - } + if (meta_va) + state[6] |= S_008F28_COMPRESSION_EN(1); + } - if (sscreen->info.chip_class >= GFX8 && sscreen->info.chip_class <= GFX9) - state[7] = meta_va >> 8; + if (sscreen->info.chip_class >= GFX8 && sscreen->info.chip_class <= GFX9) + state[7] = meta_va >> 8; - if (sscreen->info.chip_class >= GFX10) { - state[3] &= C_00A00C_SW_MODE; + if (sscreen->info.chip_class >= GFX10) { + state[3] &= C_00A00C_SW_MODE; - if (is_stencil) { - state[3] |= S_00A00C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode); - } else { - state[3] |= S_00A00C_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode); - } + if (is_stencil) { + state[3] |= S_00A00C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode); + } else { + state[3] |= S_00A00C_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode); + } - state[6] &= C_00A018_META_DATA_ADDRESS_LO & - C_00A018_META_PIPE_ALIGNED; + state[6] &= C_00A018_META_DATA_ADDRESS_LO & + C_00A018_META_PIPE_ALIGNED; - if (meta_va) { - struct gfx9_surf_meta_flags meta; + if (meta_va) { + struct gfx9_surf_meta_flags meta; - if (tex->surface.dcc_offset) - meta = tex->surface.u.gfx9.dcc; - else - meta = tex->surface.u.gfx9.htile; + if (tex->surface.dcc_offset) + meta = tex->surface.u.gfx9.dcc; + else + meta = tex->surface.u.gfx9.htile; - state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) | - S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8); - } + state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) | + S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8); + } - state[7] = meta_va >> 16; - } else if (sscreen->info.chip_class == GFX9) { - state[3] &= C_008F1C_SW_MODE; - state[4] &= C_008F20_PITCH; + state[7] = meta_va >> 16; + } else if (sscreen->info.chip_class == GFX9) { + state[3] &= C_008F1C_SW_MODE; + state[4] &= C_008F20_PITCH; - if (is_stencil) { - state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode); - state[4] |= S_008F20_PITCH(tex->surface.u.gfx9.stencil.epitch); - } else { - state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode); - state[4] |= S_008F20_PITCH(tex->surface.u.gfx9.surf.epitch); - } + if (is_stencil) { + state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode); + state[4] |= S_008F20_PITCH(tex->surface.u.gfx9.stencil.epitch); + } else { + state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode); + state[4] |= S_008F20_PITCH(tex->surface.u.gfx9.surf.epitch); + } - state[5] &= C_008F24_META_DATA_ADDRESS & - C_008F24_META_PIPE_ALIGNED & - C_008F24_META_RB_ALIGNED; - if (meta_va) { - struct gfx9_surf_meta_flags meta; + state[5] &= C_008F24_META_DATA_ADDRESS & + C_008F24_META_PIPE_ALIGNED & + C_008F24_META_RB_ALIGNED; + if (meta_va) { + struct gfx9_surf_meta_flags meta; - if (tex->surface.dcc_offset) - meta = tex->surface.u.gfx9.dcc; - else - meta = tex->surface.u.gfx9.htile; + if (tex->surface.dcc_offset) + meta = tex->surface.u.gfx9.dcc; + else + meta = tex->surface.u.gfx9.htile; - state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) | - S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) | - S_008F24_META_RB_ALIGNED(meta.rb_aligned); - } - } else { - /* GFX6-GFX8 */ - unsigned pitch = base_level_info->nblk_x * block_width; - unsigned index = si_tile_mode_index(tex, base_level, is_stencil); + state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) | + S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) | + S_008F24_META_RB_ALIGNED(meta.rb_aligned); + } + } else { + /* GFX6-GFX8 */ + unsigned pitch = base_level_info->nblk_x * block_width; + unsigned index = si_tile_mode_index(tex, base_level, is_stencil); - state[3] &= C_008F1C_TILING_INDEX; - state[3] |= S_008F1C_TILING_INDEX(index); - state[4] &= C_008F20_PITCH; - state[4] |= S_008F20_PITCH(pitch - 1); - } + state[3] &= C_008F1C_TILING_INDEX; + state[3] |= S_008F1C_TILING_INDEX(index); + state[4] &= C_008F20_PITCH; + state[4] |= S_008F20_PITCH(pitch - 1); + } } static void si_set_sampler_state_desc(struct si_sampler_state *sstate, - struct si_sampler_view *sview, - struct si_texture *tex, - uint32_t *desc) + struct si_sampler_view *sview, + struct si_texture *tex, + uint32_t *desc) { - if (sview && sview->is_integer) - memcpy(desc, sstate->integer_val, 4*4); - else if (tex && tex->upgraded_depth && - (!sview || !sview->is_stencil_sampler)) - memcpy(desc, sstate->upgraded_depth_val, 4*4); - else - memcpy(desc, sstate->val, 4*4); + if (sview && sview->is_integer) + memcpy(desc, sstate->integer_val, 4*4); + else if (tex && tex->upgraded_depth && + (!sview || !sview->is_stencil_sampler)) + memcpy(desc, sstate->upgraded_depth_val, 4*4); + else + memcpy(desc, sstate->val, 4*4); } static void si_set_sampler_view_desc(struct si_context *sctx, - struct si_sampler_view *sview, - struct si_sampler_state *sstate, - uint32_t *desc) + struct si_sampler_view *sview, + struct si_sampler_state *sstate, + uint32_t *desc) { - struct pipe_sampler_view *view = &sview->base; - struct si_texture *tex = (struct si_texture *)view->texture; - bool is_buffer = tex->buffer.b.b.target == PIPE_BUFFER; + struct pipe_sampler_view *view = &sview->base; + struct si_texture *tex = (struct si_texture *)view->texture; + bool is_buffer = tex->buffer.b.b.target == PIPE_BUFFER; - if (unlikely(!is_buffer && sview->dcc_incompatible)) { - if (vi_dcc_enabled(tex, view->u.tex.first_level)) - if (!si_texture_disable_dcc(sctx, tex)) - si_decompress_dcc(sctx, tex); + if (unlikely(!is_buffer && sview->dcc_incompatible)) { + if (vi_dcc_enabled(tex, view->u.tex.first_level)) + if (!si_texture_disable_dcc(sctx, tex)) + si_decompress_dcc(sctx, tex); - sview->dcc_incompatible = false; - } + sview->dcc_incompatible = false; + } - assert(tex); /* views with texture == NULL aren't supported */ - memcpy(desc, sview->state, 8*4); + assert(tex); /* views with texture == NULL aren't supported */ + memcpy(desc, sview->state, 8*4); - if (is_buffer) { - si_set_buf_desc_address(&tex->buffer, - sview->base.u.buf.offset, - desc + 4); - } else { - bool is_separate_stencil = tex->db_compatible && - sview->is_stencil_sampler; + if (is_buffer) { + si_set_buf_desc_address(&tex->buffer, + sview->base.u.buf.offset, + desc + 4); + } else { + bool is_separate_stencil = tex->db_compatible && + sview->is_stencil_sampler; - si_set_mutable_tex_desc_fields(sctx->screen, tex, - sview->base_level_info, - sview->base_level, - sview->base.u.tex.first_level, - sview->block_width, - is_separate_stencil, - desc); - } + si_set_mutable_tex_desc_fields(sctx->screen, tex, + sview->base_level_info, + sview->base_level, + sview->base.u.tex.first_level, + sview->block_width, + is_separate_stencil, + desc); + } - if (!is_buffer && tex->surface.fmask_size) { - memcpy(desc + 8, sview->fmask_state, 8*4); - } else { - /* Disable FMASK and bind sampler state in [12:15]. */ - memcpy(desc + 8, null_texture_descriptor, 4*4); + if (!is_buffer && tex->surface.fmask_size) { + memcpy(desc + 8, sview->fmask_state, 8*4); + } else { + /* Disable FMASK and bind sampler state in [12:15]. */ + memcpy(desc + 8, null_texture_descriptor, 4*4); - if (sstate) - si_set_sampler_state_desc(sstate, sview, - is_buffer ? NULL : tex, - desc + 12); - } + if (sstate) + si_set_sampler_state_desc(sstate, sview, + is_buffer ? NULL : tex, + desc + 12); + } } static bool color_needs_decompression(struct si_texture *tex) { - return tex->surface.fmask_size || - (tex->dirty_level_mask && - (tex->cmask_buffer || tex->surface.dcc_offset)); + return tex->surface.fmask_size || + (tex->dirty_level_mask && + (tex->cmask_buffer || tex->surface.dcc_offset)); } static bool depth_needs_decompression(struct si_texture *tex) { - /* If the depth/stencil texture is TC-compatible, no decompression - * will be done. The decompression function will only flush DB caches - * to make it coherent with shaders. That's necessary because the driver - * doesn't flush DB caches in any other case. - */ - return tex->db_compatible; + /* If the depth/stencil texture is TC-compatible, no decompression + * will be done. The decompression function will only flush DB caches + * to make it coherent with shaders. That's necessary because the driver + * doesn't flush DB caches in any other case. + */ + return tex->db_compatible; } static void si_set_sampler_view(struct si_context *sctx, - unsigned shader, - unsigned slot, struct pipe_sampler_view *view, - bool disallow_early_out) + unsigned shader, + unsigned slot, struct pipe_sampler_view *view, + bool disallow_early_out) { - struct si_samplers *samplers = &sctx->samplers[shader]; - struct si_sampler_view *sview = (struct si_sampler_view*)view; - struct si_descriptors *descs = si_sampler_and_image_descriptors(sctx, shader); - unsigned desc_slot = si_get_sampler_slot(slot); - uint32_t *desc = descs->list + desc_slot * 16; + struct si_samplers *samplers = &sctx->samplers[shader]; + struct si_sampler_view *sview = (struct si_sampler_view*)view; + struct si_descriptors *descs = si_sampler_and_image_descriptors(sctx, shader); + unsigned desc_slot = si_get_sampler_slot(slot); + uint32_t *desc = descs->list + desc_slot * 16; - if (samplers->views[slot] == view && !disallow_early_out) - return; + if (samplers->views[slot] == view && !disallow_early_out) + return; - if (view) { - struct si_texture *tex = (struct si_texture *)view->texture; + if (view) { + struct si_texture *tex = (struct si_texture *)view->texture; - si_set_sampler_view_desc(sctx, sview, - samplers->sampler_states[slot], desc); + si_set_sampler_view_desc(sctx, sview, + samplers->sampler_states[slot], desc); - if (tex->buffer.b.b.target == PIPE_BUFFER) { - tex->buffer.bind_history |= PIPE_BIND_SAMPLER_VIEW; - samplers->needs_depth_decompress_mask &= ~(1u << slot); - samplers->needs_color_decompress_mask &= ~(1u << slot); - } else { - if (depth_needs_decompression(tex)) { - samplers->needs_depth_decompress_mask |= 1u << slot; - } else { - samplers->needs_depth_decompress_mask &= ~(1u << slot); - } - if (color_needs_decompression(tex)) { - samplers->needs_color_decompress_mask |= 1u << slot; - } else { - samplers->needs_color_decompress_mask &= ~(1u << slot); - } + if (tex->buffer.b.b.target == PIPE_BUFFER) { + tex->buffer.bind_history |= PIPE_BIND_SAMPLER_VIEW; + samplers->needs_depth_decompress_mask &= ~(1u << slot); + samplers->needs_color_decompress_mask &= ~(1u << slot); + } else { + if (depth_needs_decompression(tex)) { + samplers->needs_depth_decompress_mask |= 1u << slot; + } else { + samplers->needs_depth_decompress_mask &= ~(1u << slot); + } + if (color_needs_decompression(tex)) { + samplers->needs_color_decompress_mask |= 1u << slot; + } else { + samplers->needs_color_decompress_mask &= ~(1u << slot); + } - if (tex->surface.dcc_offset && - p_atomic_read(&tex->framebuffers_bound)) - sctx->need_check_render_feedback = true; - } + if (tex->surface.dcc_offset && + p_atomic_read(&tex->framebuffers_bound)) + sctx->need_check_render_feedback = true; + } - pipe_sampler_view_reference(&samplers->views[slot], view); - samplers->enabled_mask |= 1u << slot; + pipe_sampler_view_reference(&samplers->views[slot], view); + samplers->enabled_mask |= 1u << slot; - /* Since this can flush, it must be done after enabled_mask is - * updated. */ - si_sampler_view_add_buffer(sctx, view->texture, - RADEON_USAGE_READ, - sview->is_stencil_sampler, true); - } else { - pipe_sampler_view_reference(&samplers->views[slot], NULL); - memcpy(desc, null_texture_descriptor, 8*4); - /* Only clear the lower dwords of FMASK. */ - memcpy(desc + 8, null_texture_descriptor, 4*4); - /* Re-set the sampler state if we are transitioning from FMASK. */ - if (samplers->sampler_states[slot]) - si_set_sampler_state_desc(samplers->sampler_states[slot], NULL, NULL, - desc + 12); + /* Since this can flush, it must be done after enabled_mask is + * updated. */ + si_sampler_view_add_buffer(sctx, view->texture, + RADEON_USAGE_READ, + sview->is_stencil_sampler, true); + } else { + pipe_sampler_view_reference(&samplers->views[slot], NULL); + memcpy(desc, null_texture_descriptor, 8*4); + /* Only clear the lower dwords of FMASK. */ + memcpy(desc + 8, null_texture_descriptor, 4*4); + /* Re-set the sampler state if we are transitioning from FMASK. */ + if (samplers->sampler_states[slot]) + si_set_sampler_state_desc(samplers->sampler_states[slot], NULL, NULL, + desc + 12); - samplers->enabled_mask &= ~(1u << slot); - samplers->needs_depth_decompress_mask &= ~(1u << slot); - samplers->needs_color_decompress_mask &= ~(1u << slot); - } + samplers->enabled_mask &= ~(1u << slot); + samplers->needs_depth_decompress_mask &= ~(1u << slot); + samplers->needs_color_decompress_mask &= ~(1u << slot); + } - sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader); + sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader); } static void si_update_shader_needs_decompress_mask(struct si_context *sctx, - unsigned shader) + unsigned shader) { - struct si_samplers *samplers = &sctx->samplers[shader]; - unsigned shader_bit = 1 << shader; + struct si_samplers *samplers = &sctx->samplers[shader]; + unsigned shader_bit = 1 << shader; - if (samplers->needs_depth_decompress_mask || - samplers->needs_color_decompress_mask || - sctx->images[shader].needs_color_decompress_mask) - sctx->shader_needs_decompress_mask |= shader_bit; - else - sctx->shader_needs_decompress_mask &= ~shader_bit; + if (samplers->needs_depth_decompress_mask || + samplers->needs_color_decompress_mask || + sctx->images[shader].needs_color_decompress_mask) + sctx->shader_needs_decompress_mask |= shader_bit; + else + sctx->shader_needs_decompress_mask &= ~shader_bit; } static void si_set_sampler_views(struct pipe_context *ctx, - enum pipe_shader_type shader, unsigned start, + enum pipe_shader_type shader, unsigned start, unsigned count, - struct pipe_sampler_view **views) + struct pipe_sampler_view **views) { - struct si_context *sctx = (struct si_context *)ctx; - int i; + struct si_context *sctx = (struct si_context *)ctx; + int i; - if (!count || shader >= SI_NUM_SHADERS) - return; + if (!count || shader >= SI_NUM_SHADERS) + return; - if (views) { - for (i = 0; i < count; i++) - si_set_sampler_view(sctx, shader, start + i, views[i], false); - } else { - for (i = 0; i < count; i++) - si_set_sampler_view(sctx, shader, start + i, NULL, false); - } + if (views) { + for (i = 0; i < count; i++) + si_set_sampler_view(sctx, shader, start + i, views[i], false); + } else { + for (i = 0; i < count; i++) + si_set_sampler_view(sctx, shader, start + i, NULL, false); + } - si_update_shader_needs_decompress_mask(sctx, shader); + si_update_shader_needs_decompress_mask(sctx, shader); } static void si_samplers_update_needs_color_decompress_mask(struct si_samplers *samplers) { - unsigned mask = samplers->enabled_mask; + unsigned mask = samplers->enabled_mask; - while (mask) { - int i = u_bit_scan(&mask); - struct pipe_resource *res = samplers->views[i]->texture; + while (mask) { + int i = u_bit_scan(&mask); + struct pipe_resource *res = samplers->views[i]->texture; - if (res && res->target != PIPE_BUFFER) { - struct si_texture *tex = (struct si_texture *)res; + if (res && res->target != PIPE_BUFFER) { + struct si_texture *tex = (struct si_texture *)res; - if (color_needs_decompression(tex)) { - samplers->needs_color_decompress_mask |= 1u << i; - } else { - samplers->needs_color_decompress_mask &= ~(1u << i); - } - } - } + if (color_needs_decompression(tex)) { + samplers->needs_color_decompress_mask |= 1u << i; + } else { + samplers->needs_color_decompress_mask &= ~(1u << i); + } + } + } } /* IMAGE VIEWS */ @@ -640,311 +640,311 @@ si_samplers_update_needs_color_decompress_mask(struct si_samplers *samplers) static void si_release_image_views(struct si_images *images) { - unsigned i; + unsigned i; - for (i = 0; i < SI_NUM_IMAGES; ++i) { - struct pipe_image_view *view = &images->views[i]; + for (i = 0; i < SI_NUM_IMAGES; ++i) { + struct pipe_image_view *view = &images->views[i]; - pipe_resource_reference(&view->resource, NULL); - } + pipe_resource_reference(&view->resource, NULL); + } } static void si_image_views_begin_new_cs(struct si_context *sctx, struct si_images *images) { - uint mask = images->enabled_mask; + uint mask = images->enabled_mask; - /* Add buffers to the CS. */ - while (mask) { - int i = u_bit_scan(&mask); - struct pipe_image_view *view = &images->views[i]; + /* Add buffers to the CS. */ + while (mask) { + int i = u_bit_scan(&mask); + struct pipe_image_view *view = &images->views[i]; - assert(view->resource); + assert(view->resource); - si_sampler_view_add_buffer(sctx, view->resource, - RADEON_USAGE_READWRITE, false, false); - } + si_sampler_view_add_buffer(sctx, view->resource, + RADEON_USAGE_READWRITE, false, false); + } } static void si_disable_shader_image(struct si_context *ctx, unsigned shader, unsigned slot) { - struct si_images *images = &ctx->images[shader]; + struct si_images *images = &ctx->images[shader]; - if (images->enabled_mask & (1u << slot)) { - struct si_descriptors *descs = si_sampler_and_image_descriptors(ctx, shader); - unsigned desc_slot = si_get_image_slot(slot); + if (images->enabled_mask & (1u << slot)) { + struct si_descriptors *descs = si_sampler_and_image_descriptors(ctx, shader); + unsigned desc_slot = si_get_image_slot(slot); - pipe_resource_reference(&images->views[slot].resource, NULL); - images->needs_color_decompress_mask &= ~(1 << slot); + pipe_resource_reference(&images->views[slot].resource, NULL); + images->needs_color_decompress_mask &= ~(1 << slot); - memcpy(descs->list + desc_slot*8, null_image_descriptor, 8*4); - images->enabled_mask &= ~(1u << slot); - ctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader); - } + memcpy(descs->list + desc_slot*8, null_image_descriptor, 8*4); + images->enabled_mask &= ~(1u << slot); + ctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader); + } } static void si_mark_image_range_valid(const struct pipe_image_view *view) { - struct si_resource *res = si_resource(view->resource); + struct si_resource *res = si_resource(view->resource); - if (res->b.b.target != PIPE_BUFFER) - return; + if (res->b.b.target != PIPE_BUFFER) + return; - util_range_add(&res->b.b, &res->valid_buffer_range, - view->u.buf.offset, - view->u.buf.offset + view->u.buf.size); + util_range_add(&res->b.b, &res->valid_buffer_range, + view->u.buf.offset, + view->u.buf.offset + view->u.buf.size); } static void si_set_shader_image_desc(struct si_context *ctx, - const struct pipe_image_view *view, - bool skip_decompress, - uint32_t *desc, uint32_t *fmask_desc) + const struct pipe_image_view *view, + bool skip_decompress, + uint32_t *desc, uint32_t *fmask_desc) { - struct si_screen *screen = ctx->screen; - struct si_resource *res; + struct si_screen *screen = ctx->screen; + struct si_resource *res; - res = si_resource(view->resource); + res = si_resource(view->resource); - if (res->b.b.target == PIPE_BUFFER || - view->shader_access & SI_IMAGE_ACCESS_AS_BUFFER) { - if (view->access & PIPE_IMAGE_ACCESS_WRITE) - si_mark_image_range_valid(view); + if (res->b.b.target == PIPE_BUFFER || + view->shader_access & SI_IMAGE_ACCESS_AS_BUFFER) { + if (view->access & PIPE_IMAGE_ACCESS_WRITE) + si_mark_image_range_valid(view); - si_make_buffer_descriptor(screen, res, - view->format, - view->u.buf.offset, - view->u.buf.size, desc); - si_set_buf_desc_address(res, view->u.buf.offset, desc + 4); - } else { - static const unsigned char swizzle[4] = { 0, 1, 2, 3 }; - struct si_texture *tex = (struct si_texture *)res; - unsigned level = view->u.tex.level; - unsigned width, height, depth, hw_level; - bool uses_dcc = vi_dcc_enabled(tex, level); - unsigned access = view->access; + si_make_buffer_descriptor(screen, res, + view->format, + view->u.buf.offset, + view->u.buf.size, desc); + si_set_buf_desc_address(res, view->u.buf.offset, desc + 4); + } else { + static const unsigned char swizzle[4] = { 0, 1, 2, 3 }; + struct si_texture *tex = (struct si_texture *)res; + unsigned level = view->u.tex.level; + unsigned width, height, depth, hw_level; + bool uses_dcc = vi_dcc_enabled(tex, level); + unsigned access = view->access; - assert(!tex->is_depth); - assert(fmask_desc || tex->surface.fmask_offset == 0); + assert(!tex->is_depth); + assert(fmask_desc || tex->surface.fmask_offset == 0); - if (uses_dcc && !skip_decompress && - (access & PIPE_IMAGE_ACCESS_WRITE || - !vi_dcc_formats_compatible(screen, res->b.b.format, view->format))) { - /* If DCC can't be disabled, at least decompress it. - * The decompression is relatively cheap if the surface - * has been decompressed already. - */ - if (!si_texture_disable_dcc(ctx, tex)) - si_decompress_dcc(ctx, tex); - } + if (uses_dcc && !skip_decompress && + (access & PIPE_IMAGE_ACCESS_WRITE || + !vi_dcc_formats_compatible(screen, res->b.b.format, view->format))) { + /* If DCC can't be disabled, at least decompress it. + * The decompression is relatively cheap if the surface + * has been decompressed already. + */ + if (!si_texture_disable_dcc(ctx, tex)) + si_decompress_dcc(ctx, tex); + } - if (ctx->chip_class >= GFX9) { - /* Always set the base address. The swizzle modes don't - * allow setting mipmap level offsets as the base. - */ - width = res->b.b.width0; - height = res->b.b.height0; - depth = res->b.b.depth0; - hw_level = level; - } else { - /* Always force the base level to the selected level. - * - * This is required for 3D textures, where otherwise - * selecting a single slice for non-layered bindings - * fails. It doesn't hurt the other targets. - */ - width = u_minify(res->b.b.width0, level); - height = u_minify(res->b.b.height0, level); - depth = u_minify(res->b.b.depth0, level); - hw_level = 0; - } + if (ctx->chip_class >= GFX9) { + /* Always set the base address. The swizzle modes don't + * allow setting mipmap level offsets as the base. + */ + width = res->b.b.width0; + height = res->b.b.height0; + depth = res->b.b.depth0; + hw_level = level; + } else { + /* Always force the base level to the selected level. + * + * This is required for 3D textures, where otherwise + * selecting a single slice for non-layered bindings + * fails. It doesn't hurt the other targets. + */ + width = u_minify(res->b.b.width0, level); + height = u_minify(res->b.b.height0, level); + depth = u_minify(res->b.b.depth0, level); + hw_level = 0; + } - screen->make_texture_descriptor(screen, tex, - false, res->b.b.target, - view->format, swizzle, - hw_level, hw_level, - view->u.tex.first_layer, - view->u.tex.last_layer, - width, height, depth, - desc, fmask_desc); - si_set_mutable_tex_desc_fields(screen, tex, - &tex->surface.u.legacy.level[level], - level, level, - util_format_get_blockwidth(view->format), - false, desc); - } + screen->make_texture_descriptor(screen, tex, + false, res->b.b.target, + view->format, swizzle, + hw_level, hw_level, + view->u.tex.first_layer, + view->u.tex.last_layer, + width, height, depth, + desc, fmask_desc); + si_set_mutable_tex_desc_fields(screen, tex, + &tex->surface.u.legacy.level[level], + level, level, + util_format_get_blockwidth(view->format), + false, desc); + } } static void si_set_shader_image(struct si_context *ctx, - unsigned shader, - unsigned slot, const struct pipe_image_view *view, - bool skip_decompress) + unsigned shader, + unsigned slot, const struct pipe_image_view *view, + bool skip_decompress) { - struct si_images *images = &ctx->images[shader]; - struct si_descriptors *descs = si_sampler_and_image_descriptors(ctx, shader); - struct si_resource *res; + struct si_images *images = &ctx->images[shader]; + struct si_descriptors *descs = si_sampler_and_image_descriptors(ctx, shader); + struct si_resource *res; - if (!view || !view->resource) { - si_disable_shader_image(ctx, shader, slot); - return; - } + if (!view || !view->resource) { + si_disable_shader_image(ctx, shader, slot); + return; + } - res = si_resource(view->resource); + res = si_resource(view->resource); - if (&images->views[slot] != view) - util_copy_image_view(&images->views[slot], view); + if (&images->views[slot] != view) + util_copy_image_view(&images->views[slot], view); - si_set_shader_image_desc(ctx, view, skip_decompress, - descs->list + si_get_image_slot(slot) * 8, - descs->list + si_get_image_slot(slot + SI_NUM_IMAGES) * 8); + si_set_shader_image_desc(ctx, view, skip_decompress, + descs->list + si_get_image_slot(slot) * 8, + descs->list + si_get_image_slot(slot + SI_NUM_IMAGES) * 8); - if (res->b.b.target == PIPE_BUFFER || - view->shader_access & SI_IMAGE_ACCESS_AS_BUFFER) { - images->needs_color_decompress_mask &= ~(1 << slot); - res->bind_history |= PIPE_BIND_SHADER_IMAGE; - } else { - struct si_texture *tex = (struct si_texture *)res; - unsigned level = view->u.tex.level; + if (res->b.b.target == PIPE_BUFFER || + view->shader_access & SI_IMAGE_ACCESS_AS_BUFFER) { + images->needs_color_decompress_mask &= ~(1 << slot); + res->bind_history |= PIPE_BIND_SHADER_IMAGE; + } else { + struct si_texture *tex = (struct si_texture *)res; + unsigned level = view->u.tex.level; - if (color_needs_decompression(tex)) { - images->needs_color_decompress_mask |= 1 << slot; - } else { - images->needs_color_decompress_mask &= ~(1 << slot); - } + if (color_needs_decompression(tex)) { + images->needs_color_decompress_mask |= 1 << slot; + } else { + images->needs_color_decompress_mask &= ~(1 << slot); + } - if (vi_dcc_enabled(tex, level) && - p_atomic_read(&tex->framebuffers_bound)) - ctx->need_check_render_feedback = true; - } + if (vi_dcc_enabled(tex, level) && + p_atomic_read(&tex->framebuffers_bound)) + ctx->need_check_render_feedback = true; + } - images->enabled_mask |= 1u << slot; - ctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader); + images->enabled_mask |= 1u << slot; + ctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader); - /* Since this can flush, it must be done after enabled_mask is updated. */ - si_sampler_view_add_buffer(ctx, &res->b.b, - (view->access & PIPE_IMAGE_ACCESS_WRITE) ? - RADEON_USAGE_READWRITE : RADEON_USAGE_READ, - false, true); + /* Since this can flush, it must be done after enabled_mask is updated. */ + si_sampler_view_add_buffer(ctx, &res->b.b, + (view->access & PIPE_IMAGE_ACCESS_WRITE) ? + RADEON_USAGE_READWRITE : RADEON_USAGE_READ, + false, true); } static void si_set_shader_images(struct pipe_context *pipe, - enum pipe_shader_type shader, - unsigned start_slot, unsigned count, - const struct pipe_image_view *views) + enum pipe_shader_type shader, + unsigned start_slot, unsigned count, + const struct pipe_image_view *views) { - struct si_context *ctx = (struct si_context *)pipe; - unsigned i, slot; + struct si_context *ctx = (struct si_context *)pipe; + unsigned i, slot; - assert(shader < SI_NUM_SHADERS); + assert(shader < SI_NUM_SHADERS); - if (!count) - return; + if (!count) + return; - assert(start_slot + count <= SI_NUM_IMAGES); + assert(start_slot + count <= SI_NUM_IMAGES); - if (views) { - for (i = 0, slot = start_slot; i < count; ++i, ++slot) - si_set_shader_image(ctx, shader, slot, &views[i], false); - } else { - for (i = 0, slot = start_slot; i < count; ++i, ++slot) - si_set_shader_image(ctx, shader, slot, NULL, false); - } + if (views) { + for (i = 0, slot = start_slot; i < count; ++i, ++slot) + si_set_shader_image(ctx, shader, slot, &views[i], false); + } else { + for (i = 0, slot = start_slot; i < count; ++i, ++slot) + si_set_shader_image(ctx, shader, slot, NULL, false); + } - si_update_shader_needs_decompress_mask(ctx, shader); + si_update_shader_needs_decompress_mask(ctx, shader); } static void si_images_update_needs_color_decompress_mask(struct si_images *images) { - unsigned mask = images->enabled_mask; + unsigned mask = images->enabled_mask; - while (mask) { - int i = u_bit_scan(&mask); - struct pipe_resource *res = images->views[i].resource; + while (mask) { + int i = u_bit_scan(&mask); + struct pipe_resource *res = images->views[i].resource; - if (res && res->target != PIPE_BUFFER) { - struct si_texture *tex = (struct si_texture *)res; + if (res && res->target != PIPE_BUFFER) { + struct si_texture *tex = (struct si_texture *)res; - if (color_needs_decompression(tex)) { - images->needs_color_decompress_mask |= 1 << i; - } else { - images->needs_color_decompress_mask &= ~(1 << i); - } - } - } + if (color_needs_decompression(tex)) { + images->needs_color_decompress_mask |= 1 << i; + } else { + images->needs_color_decompress_mask &= ~(1 << i); + } + } + } } void si_update_ps_colorbuf0_slot(struct si_context *sctx) { - struct si_buffer_resources *buffers = &sctx->rw_buffers; - struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS]; - unsigned slot = SI_PS_IMAGE_COLORBUF0; - struct pipe_surface *surf = NULL; + struct si_buffer_resources *buffers = &sctx->rw_buffers; + struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS]; + unsigned slot = SI_PS_IMAGE_COLORBUF0; + struct pipe_surface *surf = NULL; - /* si_texture_disable_dcc can get us here again. */ - if (sctx->blitter->running) - return; + /* si_texture_disable_dcc can get us here again. */ + if (sctx->blitter->running) + return; - /* See whether FBFETCH is used and color buffer 0 is set. */ - if (sctx->ps_shader.cso && - sctx->ps_shader.cso->info.uses_fbfetch && - sctx->framebuffer.state.nr_cbufs && - sctx->framebuffer.state.cbufs[0]) - surf = sctx->framebuffer.state.cbufs[0]; + /* See whether FBFETCH is used and color buffer 0 is set. */ + if (sctx->ps_shader.cso && + sctx->ps_shader.cso->info.uses_fbfetch && + sctx->framebuffer.state.nr_cbufs && + sctx->framebuffer.state.cbufs[0]) + surf = sctx->framebuffer.state.cbufs[0]; - /* Return if FBFETCH transitions from disabled to disabled. */ - if (!buffers->buffers[slot] && !surf) - return; + /* Return if FBFETCH transitions from disabled to disabled. */ + if (!buffers->buffers[slot] && !surf) + return; - sctx->ps_uses_fbfetch = surf != NULL; - si_update_ps_iter_samples(sctx); + sctx->ps_uses_fbfetch = surf != NULL; + si_update_ps_iter_samples(sctx); - if (surf) { - struct si_texture *tex = (struct si_texture*)surf->texture; - struct pipe_image_view view = {0}; + if (surf) { + struct si_texture *tex = (struct si_texture*)surf->texture; + struct pipe_image_view view = {0}; - assert(tex); - assert(!tex->is_depth); + assert(tex); + assert(!tex->is_depth); - /* Disable DCC, because the texture is used as both a sampler - * and color buffer. - */ - si_texture_disable_dcc(sctx, tex); + /* Disable DCC, because the texture is used as both a sampler + * and color buffer. + */ + si_texture_disable_dcc(sctx, tex); - if (tex->buffer.b.b.nr_samples <= 1 && tex->cmask_buffer) { - /* Disable CMASK. */ - assert(tex->cmask_buffer != &tex->buffer); - si_eliminate_fast_color_clear(sctx, tex); - si_texture_discard_cmask(sctx->screen, tex); - } + if (tex->buffer.b.b.nr_samples <= 1 && tex->cmask_buffer) { + /* Disable CMASK. */ + assert(tex->cmask_buffer != &tex->buffer); + si_eliminate_fast_color_clear(sctx, tex); + si_texture_discard_cmask(sctx->screen, tex); + } - view.resource = surf->texture; - view.format = surf->format; - view.access = PIPE_IMAGE_ACCESS_READ; - view.u.tex.first_layer = surf->u.tex.first_layer; - view.u.tex.last_layer = surf->u.tex.last_layer; - view.u.tex.level = surf->u.tex.level; + view.resource = surf->texture; + view.format = surf->format; + view.access = PIPE_IMAGE_ACCESS_READ; + view.u.tex.first_layer = surf->u.tex.first_layer; + view.u.tex.last_layer = surf->u.tex.last_layer; + view.u.tex.level = surf->u.tex.level; - /* Set the descriptor. */ - uint32_t *desc = descs->list + slot*4; - memset(desc, 0, 16 * 4); - si_set_shader_image_desc(sctx, &view, true, desc, desc + 8); + /* Set the descriptor. */ + uint32_t *desc = descs->list + slot*4; + memset(desc, 0, 16 * 4); + si_set_shader_image_desc(sctx, &view, true, desc, desc + 8); - pipe_resource_reference(&buffers->buffers[slot], &tex->buffer.b.b); - radeon_add_to_buffer_list(sctx, sctx->gfx_cs, - &tex->buffer, RADEON_USAGE_READ, - RADEON_PRIO_SHADER_RW_IMAGE); - buffers->enabled_mask |= 1u << slot; - } else { - /* Clear the descriptor. */ - memset(descs->list + slot*4, 0, 8*4); - pipe_resource_reference(&buffers->buffers[slot], NULL); - buffers->enabled_mask &= ~(1u << slot); - } + pipe_resource_reference(&buffers->buffers[slot], &tex->buffer.b.b); + radeon_add_to_buffer_list(sctx, sctx->gfx_cs, + &tex->buffer, RADEON_USAGE_READ, + RADEON_PRIO_SHADER_RW_IMAGE); + buffers->enabled_mask |= 1u << slot; + } else { + /* Clear the descriptor. */ + memset(descs->list + slot*4, 0, 8*4); + pipe_resource_reference(&buffers->buffers[slot], NULL); + buffers->enabled_mask &= ~(1u << slot); + } - sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS; + sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS; } /* SAMPLER STATES */ @@ -953,255 +953,255 @@ static void si_bind_sampler_states(struct pipe_context *ctx, enum pipe_shader_type shader, unsigned start, unsigned count, void **states) { - struct si_context *sctx = (struct si_context *)ctx; - struct si_samplers *samplers = &sctx->samplers[shader]; - struct si_descriptors *desc = si_sampler_and_image_descriptors(sctx, shader); - struct si_sampler_state **sstates = (struct si_sampler_state**)states; - int i; + struct si_context *sctx = (struct si_context *)ctx; + struct si_samplers *samplers = &sctx->samplers[shader]; + struct si_descriptors *desc = si_sampler_and_image_descriptors(sctx, shader); + struct si_sampler_state **sstates = (struct si_sampler_state**)states; + int i; - if (!count || shader >= SI_NUM_SHADERS || !sstates) - return; + if (!count || shader >= SI_NUM_SHADERS || !sstates) + return; - for (i = 0; i < count; i++) { - unsigned slot = start + i; - unsigned desc_slot = si_get_sampler_slot(slot); + for (i = 0; i < count; i++) { + unsigned slot = start + i; + unsigned desc_slot = si_get_sampler_slot(slot); - if (!sstates[i] || - sstates[i] == samplers->sampler_states[slot]) - continue; + if (!sstates[i] || + sstates[i] == samplers->sampler_states[slot]) + continue; #ifndef NDEBUG - assert(sstates[i]->magic == SI_SAMPLER_STATE_MAGIC); + assert(sstates[i]->magic == SI_SAMPLER_STATE_MAGIC); #endif - samplers->sampler_states[slot] = sstates[i]; + samplers->sampler_states[slot] = sstates[i]; - /* If FMASK is bound, don't overwrite it. - * The sampler state will be set after FMASK is unbound. - */ - struct si_sampler_view *sview = - (struct si_sampler_view *)samplers->views[slot]; + /* If FMASK is bound, don't overwrite it. + * The sampler state will be set after FMASK is unbound. + */ + struct si_sampler_view *sview = + (struct si_sampler_view *)samplers->views[slot]; - struct si_texture *tex = NULL; + struct si_texture *tex = NULL; - if (sview && sview->base.texture && - sview->base.texture->target != PIPE_BUFFER) - tex = (struct si_texture *)sview->base.texture; + if (sview && sview->base.texture && + sview->base.texture->target != PIPE_BUFFER) + tex = (struct si_texture *)sview->base.texture; - if (tex && tex->surface.fmask_size) - continue; + if (tex && tex->surface.fmask_size) + continue; - si_set_sampler_state_desc(sstates[i], sview, tex, - desc->list + desc_slot * 16 + 12); + si_set_sampler_state_desc(sstates[i], sview, tex, + desc->list + desc_slot * 16 + 12); - sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader); - } + sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader); + } } /* BUFFER RESOURCES */ static void si_init_buffer_resources(struct si_buffer_resources *buffers, - struct si_descriptors *descs, - unsigned num_buffers, - short shader_userdata_rel_index, - enum radeon_bo_priority priority, - enum radeon_bo_priority priority_constbuf) + struct si_descriptors *descs, + unsigned num_buffers, + short shader_userdata_rel_index, + enum radeon_bo_priority priority, + enum radeon_bo_priority priority_constbuf) { - buffers->priority = priority; - buffers->priority_constbuf = priority_constbuf; - buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*)); - buffers->offsets = CALLOC(num_buffers, sizeof(buffers->offsets[0])); + buffers->priority = priority; + buffers->priority_constbuf = priority_constbuf; + buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*)); + buffers->offsets = CALLOC(num_buffers, sizeof(buffers->offsets[0])); - si_init_descriptors(descs, shader_userdata_rel_index, 4, num_buffers); + si_init_descriptors(descs, shader_userdata_rel_index, 4, num_buffers); } static void si_release_buffer_resources(struct si_buffer_resources *buffers, - struct si_descriptors *descs) + struct si_descriptors *descs) { - int i; + int i; - for (i = 0; i < descs->num_elements; i++) { - pipe_resource_reference(&buffers->buffers[i], NULL); - } + for (i = 0; i < descs->num_elements; i++) { + pipe_resource_reference(&buffers->buffers[i], NULL); + } - FREE(buffers->buffers); - FREE(buffers->offsets); + FREE(buffers->buffers); + FREE(buffers->offsets); } static void si_buffer_resources_begin_new_cs(struct si_context *sctx, - struct si_buffer_resources *buffers) + struct si_buffer_resources *buffers) { - unsigned mask = buffers->enabled_mask; + unsigned mask = buffers->enabled_mask; - /* Add buffers to the CS. */ - while (mask) { - int i = u_bit_scan(&mask); + /* Add buffers to the CS. */ + while (mask) { + int i = u_bit_scan(&mask); - radeon_add_to_buffer_list(sctx, sctx->gfx_cs, - si_resource(buffers->buffers[i]), - buffers->writable_mask & (1u << i) ? RADEON_USAGE_READWRITE : - RADEON_USAGE_READ, - i < SI_NUM_SHADER_BUFFERS ? buffers->priority : - buffers->priority_constbuf); - } + radeon_add_to_buffer_list(sctx, sctx->gfx_cs, + si_resource(buffers->buffers[i]), + buffers->writable_mask & (1u << i) ? RADEON_USAGE_READWRITE : + RADEON_USAGE_READ, + i < SI_NUM_SHADER_BUFFERS ? buffers->priority : + buffers->priority_constbuf); + } } static void si_get_buffer_from_descriptors(struct si_buffer_resources *buffers, - struct si_descriptors *descs, - unsigned idx, struct pipe_resource **buf, - unsigned *offset, unsigned *size) + struct si_descriptors *descs, + unsigned idx, struct pipe_resource **buf, + unsigned *offset, unsigned *size) { - pipe_resource_reference(buf, buffers->buffers[idx]); - if (*buf) { - struct si_resource *res = si_resource(*buf); - const uint32_t *desc = descs->list + idx * 4; - uint64_t va; + pipe_resource_reference(buf, buffers->buffers[idx]); + if (*buf) { + struct si_resource *res = si_resource(*buf); + const uint32_t *desc = descs->list + idx * 4; + uint64_t va; - *size = desc[2]; + *size = desc[2]; - assert(G_008F04_STRIDE(desc[1]) == 0); - va = si_desc_extract_buffer_address(desc); + assert(G_008F04_STRIDE(desc[1]) == 0); + va = si_desc_extract_buffer_address(desc); - assert(va >= res->gpu_address && va + *size <= res->gpu_address + res->bo_size); - *offset = va - res->gpu_address; - } + assert(va >= res->gpu_address && va + *size <= res->gpu_address + res->bo_size); + *offset = va - res->gpu_address; + } } /* VERTEX BUFFERS */ static void si_vertex_buffers_begin_new_cs(struct si_context *sctx) { - int count = sctx->num_vertex_elements; - int i; + int count = sctx->num_vertex_elements; + int i; - for (i = 0; i < count; i++) { - int vb = sctx->vertex_elements->vertex_buffer_index[i]; + for (i = 0; i < count; i++) { + int vb = sctx->vertex_elements->vertex_buffer_index[i]; - if (vb >= ARRAY_SIZE(sctx->vertex_buffer)) - continue; - if (!sctx->vertex_buffer[vb].buffer.resource) - continue; + if (vb >= ARRAY_SIZE(sctx->vertex_buffer)) + continue; + if (!sctx->vertex_buffer[vb].buffer.resource) + continue; - radeon_add_to_buffer_list(sctx, sctx->gfx_cs, - si_resource(sctx->vertex_buffer[vb].buffer.resource), - RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER); - } + radeon_add_to_buffer_list(sctx, sctx->gfx_cs, + si_resource(sctx->vertex_buffer[vb].buffer.resource), + RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER); + } - if (!sctx->vb_descriptors_buffer) - return; - radeon_add_to_buffer_list(sctx, sctx->gfx_cs, - sctx->vb_descriptors_buffer, RADEON_USAGE_READ, - RADEON_PRIO_DESCRIPTORS); + if (!sctx->vb_descriptors_buffer) + return; + radeon_add_to_buffer_list(sctx, sctx->gfx_cs, + sctx->vb_descriptors_buffer, RADEON_USAGE_READ, + RADEON_PRIO_DESCRIPTORS); } bool si_upload_vertex_buffer_descriptors(struct si_context *sctx) { - unsigned i, count = sctx->num_vertex_elements; - uint32_t *ptr; + unsigned i, count = sctx->num_vertex_elements; + uint32_t *ptr; - if (!sctx->vertex_buffers_dirty || !count) - return true; + if (!sctx->vertex_buffers_dirty || !count) + return true; - struct si_vertex_elements *velems = sctx->vertex_elements; - unsigned alloc_size = velems->vb_desc_list_alloc_size; + struct si_vertex_elements *velems = sctx->vertex_elements; + unsigned alloc_size = velems->vb_desc_list_alloc_size; - if (alloc_size) { - /* Vertex buffer descriptors are the only ones which are uploaded - * directly through a staging buffer and don't go through - * the fine-grained upload path. - */ - u_upload_alloc(sctx->b.const_uploader, 0, - alloc_size, - si_optimal_tcc_alignment(sctx, alloc_size), - &sctx->vb_descriptors_offset, - (struct pipe_resource**)&sctx->vb_descriptors_buffer, - (void**)&ptr); - if (!sctx->vb_descriptors_buffer) { - sctx->vb_descriptors_offset = 0; - sctx->vb_descriptors_gpu_list = NULL; - return false; - } + if (alloc_size) { + /* Vertex buffer descriptors are the only ones which are uploaded + * directly through a staging buffer and don't go through + * the fine-grained upload path. + */ + u_upload_alloc(sctx->b.const_uploader, 0, + alloc_size, + si_optimal_tcc_alignment(sctx, alloc_size), + &sctx->vb_descriptors_offset, + (struct pipe_resource**)&sctx->vb_descriptors_buffer, + (void**)&ptr); + if (!sctx->vb_descriptors_buffer) { + sctx->vb_descriptors_offset = 0; + sctx->vb_descriptors_gpu_list = NULL; + return false; + } - sctx->vb_descriptors_gpu_list = ptr; - radeon_add_to_buffer_list(sctx, sctx->gfx_cs, - sctx->vb_descriptors_buffer, RADEON_USAGE_READ, - RADEON_PRIO_DESCRIPTORS); - sctx->vertex_buffer_pointer_dirty = true; - sctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS; - } else { - si_resource_reference(&sctx->vb_descriptors_buffer, NULL); - sctx->vertex_buffer_pointer_dirty = false; - sctx->prefetch_L2_mask &= ~SI_PREFETCH_VBO_DESCRIPTORS; - } + sctx->vb_descriptors_gpu_list = ptr; + radeon_add_to_buffer_list(sctx, sctx->gfx_cs, + sctx->vb_descriptors_buffer, RADEON_USAGE_READ, + RADEON_PRIO_DESCRIPTORS); + sctx->vertex_buffer_pointer_dirty = true; + sctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS; + } else { + si_resource_reference(&sctx->vb_descriptors_buffer, NULL); + sctx->vertex_buffer_pointer_dirty = false; + sctx->prefetch_L2_mask &= ~SI_PREFETCH_VBO_DESCRIPTORS; + } - assert(count <= SI_MAX_ATTRIBS); + assert(count <= SI_MAX_ATTRIBS); - unsigned first_vb_use_mask = velems->first_vb_use_mask; - unsigned num_vbos_in_user_sgprs = sctx->screen->num_vbos_in_user_sgprs; + unsigned first_vb_use_mask = velems->first_vb_use_mask; + unsigned num_vbos_in_user_sgprs = sctx->screen->num_vbos_in_user_sgprs; - for (i = 0; i < count; i++) { - struct pipe_vertex_buffer *vb; - struct si_resource *buf; - unsigned vbo_index = velems->vertex_buffer_index[i]; - uint32_t *desc = i < num_vbos_in_user_sgprs ? - &sctx->vb_descriptor_user_sgprs[i * 4] : - &ptr[(i - num_vbos_in_user_sgprs) * 4]; + for (i = 0; i < count; i++) { + struct pipe_vertex_buffer *vb; + struct si_resource *buf; + unsigned vbo_index = velems->vertex_buffer_index[i]; + uint32_t *desc = i < num_vbos_in_user_sgprs ? + &sctx->vb_descriptor_user_sgprs[i * 4] : + &ptr[(i - num_vbos_in_user_sgprs) * 4]; - vb = &sctx->vertex_buffer[vbo_index]; - buf = si_resource(vb->buffer.resource); - if (!buf) { - memset(desc, 0, 16); - continue; - } + vb = &sctx->vertex_buffer[vbo_index]; + buf = si_resource(vb->buffer.resource); + if (!buf) { + memset(desc, 0, 16); + continue; + } - int64_t offset = (int64_t)((int)vb->buffer_offset) + - velems->src_offset[i]; + int64_t offset = (int64_t)((int)vb->buffer_offset) + + velems->src_offset[i]; - if (offset >= buf->b.b.width0) { - assert(offset < buf->b.b.width0); - memset(desc, 0, 16); - continue; - } + if (offset >= buf->b.b.width0) { + assert(offset < buf->b.b.width0); + memset(desc, 0, 16); + continue; + } - uint64_t va = buf->gpu_address + offset; + uint64_t va = buf->gpu_address + offset; - int64_t num_records = (int64_t)buf->b.b.width0 - offset; - if (sctx->chip_class != GFX8 && vb->stride) { - /* Round up by rounding down and adding 1 */ - num_records = (num_records - velems->format_size[i]) / - vb->stride + 1; - } - assert(num_records >= 0 && num_records <= UINT_MAX); + int64_t num_records = (int64_t)buf->b.b.width0 - offset; + if (sctx->chip_class != GFX8 && vb->stride) { + /* Round up by rounding down and adding 1 */ + num_records = (num_records - velems->format_size[i]) / + vb->stride + 1; + } + assert(num_records >= 0 && num_records <= UINT_MAX); - uint32_t rsrc_word3 = velems->rsrc_word3[i]; + uint32_t rsrc_word3 = velems->rsrc_word3[i]; - /* OOB_SELECT chooses the out-of-bounds check: - * - 1: index >= NUM_RECORDS (Structured) - * - 3: offset >= NUM_RECORDS (Raw) - */ - if (sctx->chip_class >= GFX10) - rsrc_word3 |= S_008F0C_OOB_SELECT(vb->stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW); + /* OOB_SELECT chooses the out-of-bounds check: + * - 1: index >= NUM_RECORDS (Structured) + * - 3: offset >= NUM_RECORDS (Raw) + */ + if (sctx->chip_class >= GFX10) + rsrc_word3 |= S_008F0C_OOB_SELECT(vb->stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW); - desc[0] = va; - desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | - S_008F04_STRIDE(vb->stride); - desc[2] = num_records; - desc[3] = rsrc_word3; + desc[0] = va; + desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | + S_008F04_STRIDE(vb->stride); + desc[2] = num_records; + desc[3] = rsrc_word3; - if (first_vb_use_mask & (1 << i)) { - radeon_add_to_buffer_list(sctx, sctx->gfx_cs, - si_resource(vb->buffer.resource), - RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER); - } - } + if (first_vb_use_mask & (1 << i)) { + radeon_add_to_buffer_list(sctx, sctx->gfx_cs, + si_resource(vb->buffer.resource), + RADEON_USAGE_READ, RADEON_PRIO_VERTEX_BUFFER); + } + } - /* Don't flush the const cache. It would have a very negative effect - * on performance (confirmed by testing). New descriptors are always - * uploaded to a fresh new buffer, so I don't think flushing the const - * cache is needed. */ - si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers); - sctx->vertex_buffer_user_sgprs_dirty = num_vbos_in_user_sgprs > 0; - sctx->vertex_buffers_dirty = false; - return true; + /* Don't flush the const cache. It would have a very negative effect + * on performance (confirmed by testing). New descriptors are always + * uploaded to a fresh new buffer, so I don't think flushing the const + * cache is needed. */ + si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers); + sctx->vertex_buffer_user_sgprs_dirty = num_vbos_in_user_sgprs > 0; + sctx->vertex_buffers_dirty = false; + return true; } @@ -1210,366 +1210,366 @@ bool si_upload_vertex_buffer_descriptors(struct si_context *sctx) static struct si_descriptors * si_const_and_shader_buffer_descriptors(struct si_context *sctx, unsigned shader) { - return &sctx->descriptors[si_const_and_shader_buffer_descriptors_idx(shader)]; + return &sctx->descriptors[si_const_and_shader_buffer_descriptors_idx(shader)]; } void si_upload_const_buffer(struct si_context *sctx, struct si_resource **buf, - const uint8_t *ptr, unsigned size, uint32_t *const_offset) + const uint8_t *ptr, unsigned size, uint32_t *const_offset) { - void *tmp; + void *tmp; - u_upload_alloc(sctx->b.const_uploader, 0, size, - si_optimal_tcc_alignment(sctx, size), - const_offset, - (struct pipe_resource**)buf, &tmp); - if (*buf) - util_memcpy_cpu_to_le32(tmp, ptr, size); + u_upload_alloc(sctx->b.const_uploader, 0, size, + si_optimal_tcc_alignment(sctx, size), + const_offset, + (struct pipe_resource**)buf, &tmp); + if (*buf) + util_memcpy_cpu_to_le32(tmp, ptr, size); } static void si_set_constant_buffer(struct si_context *sctx, - struct si_buffer_resources *buffers, - unsigned descriptors_idx, - uint slot, const struct pipe_constant_buffer *input) + struct si_buffer_resources *buffers, + unsigned descriptors_idx, + uint slot, const struct pipe_constant_buffer *input) { - struct si_descriptors *descs = &sctx->descriptors[descriptors_idx]; - assert(slot < descs->num_elements); - pipe_resource_reference(&buffers->buffers[slot], NULL); + struct si_descriptors *descs = &sctx->descriptors[descriptors_idx]; + assert(slot < descs->num_elements); + pipe_resource_reference(&buffers->buffers[slot], NULL); - /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD is buggy - * with a NULL buffer). We need to use a dummy buffer instead. */ - if (sctx->chip_class == GFX7 && - (!input || (!input->buffer && !input->user_buffer))) - input = &sctx->null_const_buf; + /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD is buggy + * with a NULL buffer). We need to use a dummy buffer instead. */ + if (sctx->chip_class == GFX7 && + (!input || (!input->buffer && !input->user_buffer))) + input = &sctx->null_const_buf; - if (input && (input->buffer || input->user_buffer)) { - struct pipe_resource *buffer = NULL; - uint64_t va; - unsigned buffer_offset; + if (input && (input->buffer || input->user_buffer)) { + struct pipe_resource *buffer = NULL; + uint64_t va; + unsigned buffer_offset; - /* Upload the user buffer if needed. */ - if (input->user_buffer) { - si_upload_const_buffer(sctx, - (struct si_resource**)&buffer, input->user_buffer, - input->buffer_size, &buffer_offset); - if (!buffer) { - /* Just unbind on failure. */ - si_set_constant_buffer(sctx, buffers, descriptors_idx, slot, NULL); - return; - } - } else { - pipe_resource_reference(&buffer, input->buffer); - buffer_offset = input->buffer_offset; - } + /* Upload the user buffer if needed. */ + if (input->user_buffer) { + si_upload_const_buffer(sctx, + (struct si_resource**)&buffer, input->user_buffer, + input->buffer_size, &buffer_offset); + if (!buffer) { + /* Just unbind on failure. */ + si_set_constant_buffer(sctx, buffers, descriptors_idx, slot, NULL); + return; + } + } else { + pipe_resource_reference(&buffer, input->buffer); + buffer_offset = input->buffer_offset; + } - va = si_resource(buffer)->gpu_address + buffer_offset; + va = si_resource(buffer)->gpu_address + buffer_offset; - /* Set the descriptor. */ - uint32_t *desc = descs->list + slot*4; - desc[0] = va; - desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | - S_008F04_STRIDE(0); - desc[2] = input->buffer_size; - desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | - S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | - S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | - S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); + /* Set the descriptor. */ + uint32_t *desc = descs->list + slot*4; + desc[0] = va; + desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | + S_008F04_STRIDE(0); + desc[2] = input->buffer_size; + desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | + S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | + S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | + S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); - if (sctx->chip_class >= GFX10) { - desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) | - S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | - S_008F0C_RESOURCE_LEVEL(1); - } else { - desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) | - S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32); - } + if (sctx->chip_class >= GFX10) { + desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) | + S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | + S_008F0C_RESOURCE_LEVEL(1); + } else { + desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) | + S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32); + } - buffers->buffers[slot] = buffer; - buffers->offsets[slot] = buffer_offset; - radeon_add_to_gfx_buffer_list_check_mem(sctx, - si_resource(buffer), - RADEON_USAGE_READ, - buffers->priority_constbuf, true); - buffers->enabled_mask |= 1u << slot; - } else { - /* Clear the descriptor. */ - memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4); - buffers->enabled_mask &= ~(1u << slot); - } + buffers->buffers[slot] = buffer; + buffers->offsets[slot] = buffer_offset; + radeon_add_to_gfx_buffer_list_check_mem(sctx, + si_resource(buffer), + RADEON_USAGE_READ, + buffers->priority_constbuf, true); + buffers->enabled_mask |= 1u << slot; + } else { + /* Clear the descriptor. */ + memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4); + buffers->enabled_mask &= ~(1u << slot); + } - sctx->descriptors_dirty |= 1u << descriptors_idx; + sctx->descriptors_dirty |= 1u << descriptors_idx; } static void si_pipe_set_constant_buffer(struct pipe_context *ctx, - enum pipe_shader_type shader, uint slot, - const struct pipe_constant_buffer *input) + enum pipe_shader_type shader, uint slot, + const struct pipe_constant_buffer *input) { - struct si_context *sctx = (struct si_context *)ctx; + struct si_context *sctx = (struct si_context *)ctx; - if (shader >= SI_NUM_SHADERS) - return; + if (shader >= SI_NUM_SHADERS) + return; - if (slot == 0 && input && input->buffer && - !(si_resource(input->buffer)->flags & RADEON_FLAG_32BIT)) { - assert(!"constant buffer 0 must have a 32-bit VM address, use const_uploader"); - return; - } + if (slot == 0 && input && input->buffer && + !(si_resource(input->buffer)->flags & RADEON_FLAG_32BIT)) { + assert(!"constant buffer 0 must have a 32-bit VM address, use const_uploader"); + return; + } - if (input && input->buffer) - si_resource(input->buffer)->bind_history |= PIPE_BIND_CONSTANT_BUFFER; + if (input && input->buffer) + si_resource(input->buffer)->bind_history |= PIPE_BIND_CONSTANT_BUFFER; - slot = si_get_constbuf_slot(slot); - si_set_constant_buffer(sctx, &sctx->const_and_shader_buffers[shader], - si_const_and_shader_buffer_descriptors_idx(shader), - slot, input); + slot = si_get_constbuf_slot(slot); + si_set_constant_buffer(sctx, &sctx->const_and_shader_buffers[shader], + si_const_and_shader_buffer_descriptors_idx(shader), + slot, input); } void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader, - uint slot, struct pipe_constant_buffer *cbuf) + uint slot, struct pipe_constant_buffer *cbuf) { - cbuf->user_buffer = NULL; - si_get_buffer_from_descriptors( - &sctx->const_and_shader_buffers[shader], - si_const_and_shader_buffer_descriptors(sctx, shader), - si_get_constbuf_slot(slot), - &cbuf->buffer, &cbuf->buffer_offset, &cbuf->buffer_size); + cbuf->user_buffer = NULL; + si_get_buffer_from_descriptors( + &sctx->const_and_shader_buffers[shader], + si_const_and_shader_buffer_descriptors(sctx, shader), + si_get_constbuf_slot(slot), + &cbuf->buffer, &cbuf->buffer_offset, &cbuf->buffer_size); } /* SHADER BUFFERS */ static void si_set_shader_buffer(struct si_context *sctx, - struct si_buffer_resources *buffers, - unsigned descriptors_idx, - uint slot, const struct pipe_shader_buffer *sbuffer, - bool writable, enum radeon_bo_priority priority) + struct si_buffer_resources *buffers, + unsigned descriptors_idx, + uint slot, const struct pipe_shader_buffer *sbuffer, + bool writable, enum radeon_bo_priority priority) { - struct si_descriptors *descs = &sctx->descriptors[descriptors_idx]; - uint32_t *desc = descs->list + slot * 4; + struct si_descriptors *descs = &sctx->descriptors[descriptors_idx]; + uint32_t *desc = descs->list + slot * 4; - if (!sbuffer || !sbuffer->buffer) { - pipe_resource_reference(&buffers->buffers[slot], NULL); - memset(desc, 0, sizeof(uint32_t) * 4); - buffers->enabled_mask &= ~(1u << slot); - buffers->writable_mask &= ~(1u << slot); - sctx->descriptors_dirty |= 1u << descriptors_idx; - return; - } + if (!sbuffer || !sbuffer->buffer) { + pipe_resource_reference(&buffers->buffers[slot], NULL); + memset(desc, 0, sizeof(uint32_t) * 4); + buffers->enabled_mask &= ~(1u << slot); + buffers->writable_mask &= ~(1u << slot); + sctx->descriptors_dirty |= 1u << descriptors_idx; + return; + } - struct si_resource *buf = si_resource(sbuffer->buffer); - uint64_t va = buf->gpu_address + sbuffer->buffer_offset; + struct si_resource *buf = si_resource(sbuffer->buffer); + uint64_t va = buf->gpu_address + sbuffer->buffer_offset; - desc[0] = va; - desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | - S_008F04_STRIDE(0); - desc[2] = sbuffer->buffer_size; - desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | - S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | - S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | - S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); + desc[0] = va; + desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | + S_008F04_STRIDE(0); + desc[2] = sbuffer->buffer_size; + desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | + S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | + S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | + S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W); - if (sctx->chip_class >= GFX10) { - desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) | - S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | - S_008F0C_RESOURCE_LEVEL(1); - } else { - desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) | - S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32); - } + if (sctx->chip_class >= GFX10) { + desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) | + S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | + S_008F0C_RESOURCE_LEVEL(1); + } else { + desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) | + S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32); + } - pipe_resource_reference(&buffers->buffers[slot], &buf->b.b); - buffers->offsets[slot] = sbuffer->buffer_offset; - radeon_add_to_gfx_buffer_list_check_mem(sctx, buf, - writable ? RADEON_USAGE_READWRITE : - RADEON_USAGE_READ, - priority, true); - if (writable) - buffers->writable_mask |= 1u << slot; - else - buffers->writable_mask &= ~(1u << slot); + pipe_resource_reference(&buffers->buffers[slot], &buf->b.b); + buffers->offsets[slot] = sbuffer->buffer_offset; + radeon_add_to_gfx_buffer_list_check_mem(sctx, buf, + writable ? RADEON_USAGE_READWRITE : + RADEON_USAGE_READ, + priority, true); + if (writable) + buffers->writable_mask |= 1u << slot; + else + buffers->writable_mask &= ~(1u << slot); - buffers->enabled_mask |= 1u << slot; - sctx->descriptors_dirty |= 1u << descriptors_idx; + buffers->enabled_mask |= 1u << slot; + sctx->descriptors_dirty |= 1u << descriptors_idx; - util_range_add(&buf->b.b, &buf->valid_buffer_range, sbuffer->buffer_offset, - sbuffer->buffer_offset + sbuffer->buffer_size); + util_range_add(&buf->b.b, &buf->valid_buffer_range, sbuffer->buffer_offset, + sbuffer->buffer_offset + sbuffer->buffer_size); } static void si_set_shader_buffers(struct pipe_context *ctx, - enum pipe_shader_type shader, - unsigned start_slot, unsigned count, - const struct pipe_shader_buffer *sbuffers, - unsigned writable_bitmask) + enum pipe_shader_type shader, + unsigned start_slot, unsigned count, + const struct pipe_shader_buffer *sbuffers, + unsigned writable_bitmask) { - struct si_context *sctx = (struct si_context *)ctx; - struct si_buffer_resources *buffers = &sctx->const_and_shader_buffers[shader]; - unsigned descriptors_idx = si_const_and_shader_buffer_descriptors_idx(shader); - unsigned i; + struct si_context *sctx = (struct si_context *)ctx; + struct si_buffer_resources *buffers = &sctx->const_and_shader_buffers[shader]; + unsigned descriptors_idx = si_const_and_shader_buffer_descriptors_idx(shader); + unsigned i; - assert(start_slot + count <= SI_NUM_SHADER_BUFFERS); + assert(start_slot + count <= SI_NUM_SHADER_BUFFERS); - for (i = 0; i < count; ++i) { - const struct pipe_shader_buffer *sbuffer = sbuffers ? &sbuffers[i] : NULL; - unsigned slot = si_get_shaderbuf_slot(start_slot + i); + for (i = 0; i < count; ++i) { + const struct pipe_shader_buffer *sbuffer = sbuffers ? &sbuffers[i] : NULL; + unsigned slot = si_get_shaderbuf_slot(start_slot + i); - if (sbuffer && sbuffer->buffer) - si_resource(sbuffer->buffer)->bind_history |= PIPE_BIND_SHADER_BUFFER; + if (sbuffer && sbuffer->buffer) + si_resource(sbuffer->buffer)->bind_history |= PIPE_BIND_SHADER_BUFFER; - si_set_shader_buffer(sctx, buffers, descriptors_idx, slot, sbuffer, - !!(writable_bitmask & (1u << i)), - buffers->priority); - } + si_set_shader_buffer(sctx, buffers, descriptors_idx, slot, sbuffer, + !!(writable_bitmask & (1u << i)), + buffers->priority); + } } void si_get_shader_buffers(struct si_context *sctx, - enum pipe_shader_type shader, - uint start_slot, uint count, - struct pipe_shader_buffer *sbuf) + enum pipe_shader_type shader, + uint start_slot, uint count, + struct pipe_shader_buffer *sbuf) { - struct si_buffer_resources *buffers = &sctx->const_and_shader_buffers[shader]; - struct si_descriptors *descs = si_const_and_shader_buffer_descriptors(sctx, shader); + struct si_buffer_resources *buffers = &sctx->const_and_shader_buffers[shader]; + struct si_descriptors *descs = si_const_and_shader_buffer_descriptors(sctx, shader); - for (unsigned i = 0; i < count; ++i) { - si_get_buffer_from_descriptors( - buffers, descs, - si_get_shaderbuf_slot(start_slot + i), - &sbuf[i].buffer, &sbuf[i].buffer_offset, - &sbuf[i].buffer_size); - } + for (unsigned i = 0; i < count; ++i) { + si_get_buffer_from_descriptors( + buffers, descs, + si_get_shaderbuf_slot(start_slot + i), + &sbuf[i].buffer, &sbuf[i].buffer_offset, + &sbuf[i].buffer_size); + } } /* RING BUFFERS */ void si_set_rw_buffer(struct si_context *sctx, - uint slot, const struct pipe_constant_buffer *input) + uint slot, const struct pipe_constant_buffer *input) { - si_set_constant_buffer(sctx, &sctx->rw_buffers, SI_DESCS_RW_BUFFERS, - slot, input); + si_set_constant_buffer(sctx, &sctx->rw_buffers, SI_DESCS_RW_BUFFERS, + slot, input); } void si_set_rw_shader_buffer(struct si_context *sctx, uint slot, - const struct pipe_shader_buffer *sbuffer) + const struct pipe_shader_buffer *sbuffer) { - si_set_shader_buffer(sctx, &sctx->rw_buffers, SI_DESCS_RW_BUFFERS, - slot, sbuffer, true, RADEON_PRIO_SHADER_RW_BUFFER); + si_set_shader_buffer(sctx, &sctx->rw_buffers, SI_DESCS_RW_BUFFERS, + slot, sbuffer, true, RADEON_PRIO_SHADER_RW_BUFFER); } void si_set_ring_buffer(struct si_context *sctx, uint slot, - struct pipe_resource *buffer, - unsigned stride, unsigned num_records, - bool add_tid, bool swizzle, - unsigned element_size, unsigned index_stride, uint64_t offset) + struct pipe_resource *buffer, + unsigned stride, unsigned num_records, + bool add_tid, bool swizzle, + unsigned element_size, unsigned index_stride, uint64_t offset) { - struct si_buffer_resources *buffers = &sctx->rw_buffers; - struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS]; + struct si_buffer_resources *buffers = &sctx->rw_buffers; + struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS]; - /* The stride field in the resource descriptor has 14 bits */ - assert(stride < (1 << 14)); + /* The stride field in the resource descriptor has 14 bits */ + assert(stride < (1 << 14)); - assert(slot < descs->num_elements); - pipe_resource_reference(&buffers->buffers[slot], NULL); + assert(slot < descs->num_elements); + pipe_resource_reference(&buffers->buffers[slot], NULL); - if (buffer) { - uint64_t va; + if (buffer) { + uint64_t va; - va = si_resource(buffer)->gpu_address + offset; + va = si_resource(buffer)->gpu_address + offset; - switch (element_size) { - default: - assert(!"Unsupported ring buffer element size"); - case 0: - case 2: - element_size = 0; - break; - case 4: - element_size = 1; - break; - case 8: - element_size = 2; - break; - case 16: - element_size = 3; - break; - } + switch (element_size) { + default: + assert(!"Unsupported ring buffer element size"); + case 0: + case 2: + element_size = 0; + break; + case 4: + element_size = 1; + break; + case 8: + element_size = 2; + break; + case 16: + element_size = 3; + break; + } - switch (index_stride) { - default: - assert(!"Unsupported ring buffer index stride"); - case 0: - case 8: - index_stride = 0; - break; - case 16: - index_stride = 1; - break; - case 32: - index_stride = 2; - break; - case 64: - index_stride = 3; - break; - } + switch (index_stride) { + default: + assert(!"Unsupported ring buffer index stride"); + case 0: + case 8: + index_stride = 0; + break; + case 16: + index_stride = 1; + break; + case 32: + index_stride = 2; + break; + case 64: + index_stride = 3; + break; + } - if (sctx->chip_class >= GFX8 && stride) - num_records *= stride; + if (sctx->chip_class >= GFX8 && stride) + num_records *= stride; - /* Set the descriptor. */ - uint32_t *desc = descs->list + slot*4; - desc[0] = va; - desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | - S_008F04_STRIDE(stride) | - S_008F04_SWIZZLE_ENABLE(swizzle); - desc[2] = num_records; - desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | - S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | - S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | - S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) | - S_008F0C_INDEX_STRIDE(index_stride) | - S_008F0C_ADD_TID_ENABLE(add_tid); + /* Set the descriptor. */ + uint32_t *desc = descs->list + slot*4; + desc[0] = va; + desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | + S_008F04_STRIDE(stride) | + S_008F04_SWIZZLE_ENABLE(swizzle); + desc[2] = num_records; + desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | + S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | + S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | + S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) | + S_008F0C_INDEX_STRIDE(index_stride) | + S_008F0C_ADD_TID_ENABLE(add_tid); - if (sctx->chip_class >= GFX9) - assert(!swizzle || element_size == 1); /* always 4 bytes on GFX9 */ - else - desc[3] |= S_008F0C_ELEMENT_SIZE(element_size); + if (sctx->chip_class >= GFX9) + assert(!swizzle || element_size == 1); /* always 4 bytes on GFX9 */ + else + desc[3] |= S_008F0C_ELEMENT_SIZE(element_size); - if (sctx->chip_class >= GFX10) { - desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) | - S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | - S_008F0C_RESOURCE_LEVEL(1); - } else { - desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) | - S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32); - } + if (sctx->chip_class >= GFX10) { + desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) | + S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) | + S_008F0C_RESOURCE_LEVEL(1); + } else { + desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) | + S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32); + } - pipe_resource_reference(&buffers->buffers[slot], buffer); - radeon_add_to_buffer_list(sctx, sctx->gfx_cs, - si_resource(buffer), - RADEON_USAGE_READWRITE, buffers->priority); - buffers->enabled_mask |= 1u << slot; - } else { - /* Clear the descriptor. */ - memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4); - buffers->enabled_mask &= ~(1u << slot); - } + pipe_resource_reference(&buffers->buffers[slot], buffer); + radeon_add_to_buffer_list(sctx, sctx->gfx_cs, + si_resource(buffer), + RADEON_USAGE_READWRITE, buffers->priority); + buffers->enabled_mask |= 1u << slot; + } else { + /* Clear the descriptor. */ + memset(descs->list + slot*4, 0, sizeof(uint32_t) * 4); + buffers->enabled_mask &= ~(1u << slot); + } - sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS; + sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS; } /* INTERNAL CONST BUFFERS */ static void si_set_polygon_stipple(struct pipe_context *ctx, - const struct pipe_poly_stipple *state) + const struct pipe_poly_stipple *state) { - struct si_context *sctx = (struct si_context *)ctx; - struct pipe_constant_buffer cb = {}; - unsigned stipple[32]; - int i; + struct si_context *sctx = (struct si_context *)ctx; + struct pipe_constant_buffer cb = {}; + unsigned stipple[32]; + int i; - for (i = 0; i < 32; i++) - stipple[i] = util_bitreverse(state->stipple[i]); + for (i = 0; i < 32; i++) + stipple[i] = util_bitreverse(state->stipple[i]); - cb.user_buffer = stipple; - cb.buffer_size = sizeof(stipple); + cb.user_buffer = stipple; + cb.buffer_size = sizeof(stipple); - si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &cb); + si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &cb); } /* TEXTURE METADATA ENABLE/DISABLE */ @@ -1577,41 +1577,41 @@ static void si_set_polygon_stipple(struct pipe_context *ctx, static void si_resident_handles_update_needs_color_decompress(struct si_context *sctx) { - util_dynarray_clear(&sctx->resident_tex_needs_color_decompress); - util_dynarray_clear(&sctx->resident_img_needs_color_decompress); + util_dynarray_clear(&sctx->resident_tex_needs_color_decompress); + util_dynarray_clear(&sctx->resident_img_needs_color_decompress); - util_dynarray_foreach(&sctx->resident_tex_handles, - struct si_texture_handle *, tex_handle) { - struct pipe_resource *res = (*tex_handle)->view->texture; - struct si_texture *tex; + util_dynarray_foreach(&sctx->resident_tex_handles, + struct si_texture_handle *, tex_handle) { + struct pipe_resource *res = (*tex_handle)->view->texture; + struct si_texture *tex; - if (!res || res->target == PIPE_BUFFER) - continue; + if (!res || res->target == PIPE_BUFFER) + continue; - tex = (struct si_texture *)res; - if (!color_needs_decompression(tex)) - continue; + tex = (struct si_texture *)res; + if (!color_needs_decompression(tex)) + continue; - util_dynarray_append(&sctx->resident_tex_needs_color_decompress, - struct si_texture_handle *, *tex_handle); - } + util_dynarray_append(&sctx->resident_tex_needs_color_decompress, + struct si_texture_handle *, *tex_handle); + } - util_dynarray_foreach(&sctx->resident_img_handles, - struct si_image_handle *, img_handle) { - struct pipe_image_view *view = &(*img_handle)->view; - struct pipe_resource *res = view->resource; - struct si_texture *tex; + util_dynarray_foreach(&sctx->resident_img_handles, + struct si_image_handle *, img_handle) { + struct pipe_image_view *view = &(*img_handle)->view; + struct pipe_resource *res = view->resource; + struct si_texture *tex; - if (!res || res->target == PIPE_BUFFER) - continue; + if (!res || res->target == PIPE_BUFFER) + continue; - tex = (struct si_texture *)res; - if (!color_needs_decompression(tex)) - continue; + tex = (struct si_texture *)res; + if (!color_needs_decompression(tex)) + continue; - util_dynarray_append(&sctx->resident_img_needs_color_decompress, - struct si_image_handle *, *img_handle); - } + util_dynarray_append(&sctx->resident_img_needs_color_decompress, + struct si_image_handle *, *img_handle); + } } /* CMASK can be enabled (for fast clear) and disabled (for texture export) @@ -1620,13 +1620,13 @@ si_resident_handles_update_needs_color_decompress(struct si_context *sctx) */ void si_update_needs_color_decompress_masks(struct si_context *sctx) { - for (int i = 0; i < SI_NUM_SHADERS; ++i) { - si_samplers_update_needs_color_decompress_mask(&sctx->samplers[i]); - si_images_update_needs_color_decompress_mask(&sctx->images[i]); - si_update_shader_needs_decompress_mask(sctx, i); - } + for (int i = 0; i < SI_NUM_SHADERS; ++i) { + si_samplers_update_needs_color_decompress_mask(&sctx->samplers[i]); + si_images_update_needs_color_decompress_mask(&sctx->images[i]); + si_update_shader_needs_decompress_mask(sctx, i); + } - si_resident_handles_update_needs_color_decompress(sctx); + si_resident_handles_update_needs_color_decompress(sctx); } /* BUFFER DISCARD/INVALIDATION */ @@ -1635,32 +1635,32 @@ void si_update_needs_color_decompress_masks(struct si_context *sctx) * If buf == NULL, reset all descriptors. */ static void si_reset_buffer_resources(struct si_context *sctx, - struct si_buffer_resources *buffers, - unsigned descriptors_idx, - unsigned slot_mask, - struct pipe_resource *buf, - enum radeon_bo_priority priority) + struct si_buffer_resources *buffers, + unsigned descriptors_idx, + unsigned slot_mask, + struct pipe_resource *buf, + enum radeon_bo_priority priority) { - struct si_descriptors *descs = &sctx->descriptors[descriptors_idx]; - unsigned mask = buffers->enabled_mask & slot_mask; + struct si_descriptors *descs = &sctx->descriptors[descriptors_idx]; + unsigned mask = buffers->enabled_mask & slot_mask; - while (mask) { - unsigned i = u_bit_scan(&mask); - struct pipe_resource *buffer = buffers->buffers[i]; + while (mask) { + unsigned i = u_bit_scan(&mask); + struct pipe_resource *buffer = buffers->buffers[i]; - if (buffer && (!buf || buffer == buf)) { - si_set_buf_desc_address(si_resource(buffer), buffers->offsets[i], - descs->list + i*4); - sctx->descriptors_dirty |= 1u << descriptors_idx; + if (buffer && (!buf || buffer == buf)) { + si_set_buf_desc_address(si_resource(buffer), buffers->offsets[i], + descs->list + i*4); + sctx->descriptors_dirty |= 1u << descriptors_idx; - radeon_add_to_gfx_buffer_list_check_mem(sctx, - si_resource(buffer), - buffers->writable_mask & (1u << i) ? - RADEON_USAGE_READWRITE : - RADEON_USAGE_READ, - priority, true); - } - } + radeon_add_to_gfx_buffer_list_check_mem(sctx, + si_resource(buffer), + buffers->writable_mask & (1u << i) ? + RADEON_USAGE_READWRITE : + RADEON_USAGE_READ, + priority, true); + } + } } /* Update all buffer bindings where the buffer is bound, including @@ -1671,436 +1671,436 @@ static void si_reset_buffer_resources(struct si_context *sctx, */ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf) { - struct si_resource *buffer = si_resource(buf); - unsigned i, shader; - unsigned num_elems = sctx->num_vertex_elements; + struct si_resource *buffer = si_resource(buf); + unsigned i, shader; + unsigned num_elems = sctx->num_vertex_elements; - /* We changed the buffer, now we need to bind it where the old one - * was bound. This consists of 2 things: - * 1) Updating the resource descriptor and dirtying it. - * 2) Adding a relocation to the CS, so that it's usable. - */ + /* We changed the buffer, now we need to bind it where the old one + * was bound. This consists of 2 things: + * 1) Updating the resource descriptor and dirtying it. + * 2) Adding a relocation to the CS, so that it's usable. + */ - /* Vertex buffers. */ - if (!buffer) { - if (num_elems) - sctx->vertex_buffers_dirty = true; - } else if (buffer->bind_history & PIPE_BIND_VERTEX_BUFFER) { - for (i = 0; i < num_elems; i++) { - int vb = sctx->vertex_elements->vertex_buffer_index[i]; + /* Vertex buffers. */ + if (!buffer) { + if (num_elems) + sctx->vertex_buffers_dirty = true; + } else if (buffer->bind_history & PIPE_BIND_VERTEX_BUFFER) { + for (i = 0; i < num_elems; i++) { + int vb = sctx->vertex_elements->vertex_buffer_index[i]; - if (vb >= ARRAY_SIZE(sctx->vertex_buffer)) - continue; - if (!sctx->vertex_buffer[vb].buffer.resource) - continue; + if (vb >= ARRAY_SIZE(sctx->vertex_buffer)) + continue; + if (!sctx->vertex_buffer[vb].buffer.resource) + continue; - if (sctx->vertex_buffer[vb].buffer.resource == buf) { - sctx->vertex_buffers_dirty = true; - break; - } - } - } + if (sctx->vertex_buffer[vb].buffer.resource == buf) { + sctx->vertex_buffers_dirty = true; + break; + } + } + } - /* Streamout buffers. (other internal buffers can't be invalidated) */ - if (!buffer || buffer->bind_history & PIPE_BIND_STREAM_OUTPUT) { - for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) { - struct si_buffer_resources *buffers = &sctx->rw_buffers; - struct si_descriptors *descs = - &sctx->descriptors[SI_DESCS_RW_BUFFERS]; - struct pipe_resource *buffer = buffers->buffers[i]; + /* Streamout buffers. (other internal buffers can't be invalidated) */ + if (!buffer || buffer->bind_history & PIPE_BIND_STREAM_OUTPUT) { + for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) { + struct si_buffer_resources *buffers = &sctx->rw_buffers; + struct si_descriptors *descs = + &sctx->descriptors[SI_DESCS_RW_BUFFERS]; + struct pipe_resource *buffer = buffers->buffers[i]; - if (!buffer || (buf && buffer != buf)) - continue; + if (!buffer || (buf && buffer != buf)) + continue; - si_set_buf_desc_address(si_resource(buffer), buffers->offsets[i], - descs->list + i*4); - sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS; + si_set_buf_desc_address(si_resource(buffer), buffers->offsets[i], + descs->list + i*4); + sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS; - radeon_add_to_gfx_buffer_list_check_mem(sctx, - si_resource(buffer), - RADEON_USAGE_WRITE, - RADEON_PRIO_SHADER_RW_BUFFER, - true); + radeon_add_to_gfx_buffer_list_check_mem(sctx, + si_resource(buffer), + RADEON_USAGE_WRITE, + RADEON_PRIO_SHADER_RW_BUFFER, + true); - /* Update the streamout state. */ - if (sctx->streamout.begin_emitted) - si_emit_streamout_end(sctx); - sctx->streamout.append_bitmask = - sctx->streamout.enabled_mask; - si_streamout_buffers_dirty(sctx); - } - } + /* Update the streamout state. */ + if (sctx->streamout.begin_emitted) + si_emit_streamout_end(sctx); + sctx->streamout.append_bitmask = + sctx->streamout.enabled_mask; + si_streamout_buffers_dirty(sctx); + } + } - /* Constant and shader buffers. */ - if (!buffer || buffer->bind_history & PIPE_BIND_CONSTANT_BUFFER) { - for (shader = 0; shader < SI_NUM_SHADERS; shader++) - si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader], - si_const_and_shader_buffer_descriptors_idx(shader), - u_bit_consecutive(SI_NUM_SHADER_BUFFERS, SI_NUM_CONST_BUFFERS), - buf, - sctx->const_and_shader_buffers[shader].priority_constbuf); - } + /* Constant and shader buffers. */ + if (!buffer || buffer->bind_history & PIPE_BIND_CONSTANT_BUFFER) { + for (shader = 0; shader < SI_NUM_SHADERS; shader++) + si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader], + si_const_and_shader_buffer_descriptors_idx(shader), + u_bit_consecutive(SI_NUM_SHADER_BUFFERS, SI_NUM_CONST_BUFFERS), + buf, + sctx->const_and_shader_buffers[shader].priority_constbuf); + } - if (!buffer || buffer->bind_history & PIPE_BIND_SHADER_BUFFER) { - for (shader = 0; shader < SI_NUM_SHADERS; shader++) - si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader], - si_const_and_shader_buffer_descriptors_idx(shader), - u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS), - buf, - sctx->const_and_shader_buffers[shader].priority); - } + if (!buffer || buffer->bind_history & PIPE_BIND_SHADER_BUFFER) { + for (shader = 0; shader < SI_NUM_SHADERS; shader++) + si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader], + si_const_and_shader_buffer_descriptors_idx(shader), + u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS), + buf, + sctx->const_and_shader_buffers[shader].priority); + } - if (!buffer || buffer->bind_history & PIPE_BIND_SAMPLER_VIEW) { - /* Texture buffers - update bindings. */ - for (shader = 0; shader < SI_NUM_SHADERS; shader++) { - struct si_samplers *samplers = &sctx->samplers[shader]; - struct si_descriptors *descs = - si_sampler_and_image_descriptors(sctx, shader); - unsigned mask = samplers->enabled_mask; + if (!buffer || buffer->bind_history & PIPE_BIND_SAMPLER_VIEW) { + /* Texture buffers - update bindings. */ + for (shader = 0; shader < SI_NUM_SHADERS; shader++) { + struct si_samplers *samplers = &sctx->samplers[shader]; + struct si_descriptors *descs = + si_sampler_and_image_descriptors(sctx, shader); + unsigned mask = samplers->enabled_mask; - while (mask) { - unsigned i = u_bit_scan(&mask); - struct pipe_resource *buffer = samplers->views[i]->texture; + while (mask) { + unsigned i = u_bit_scan(&mask); + struct pipe_resource *buffer = samplers->views[i]->texture; - if (buffer && buffer->target == PIPE_BUFFER && - (!buf || buffer == buf)) { - unsigned desc_slot = si_get_sampler_slot(i); + if (buffer && buffer->target == PIPE_BUFFER && + (!buf || buffer == buf)) { + unsigned desc_slot = si_get_sampler_slot(i); - si_set_buf_desc_address(si_resource(buffer), - samplers->views[i]->u.buf.offset, - descs->list + desc_slot * 16 + 4); - sctx->descriptors_dirty |= - 1u << si_sampler_and_image_descriptors_idx(shader); + si_set_buf_desc_address(si_resource(buffer), + samplers->views[i]->u.buf.offset, + descs->list + desc_slot * 16 + 4); + sctx->descriptors_dirty |= + 1u << si_sampler_and_image_descriptors_idx(shader); - radeon_add_to_gfx_buffer_list_check_mem( - sctx, si_resource(buffer), - RADEON_USAGE_READ, - RADEON_PRIO_SAMPLER_BUFFER, true); - } - } - } - } + radeon_add_to_gfx_buffer_list_check_mem( + sctx, si_resource(buffer), + RADEON_USAGE_READ, + RADEON_PRIO_SAMPLER_BUFFER, true); + } + } + } + } - /* Shader images */ - if (!buffer || buffer->bind_history & PIPE_BIND_SHADER_IMAGE) { - for (shader = 0; shader < SI_NUM_SHADERS; ++shader) { - struct si_images *images = &sctx->images[shader]; - struct si_descriptors *descs = - si_sampler_and_image_descriptors(sctx, shader); - unsigned mask = images->enabled_mask; + /* Shader images */ + if (!buffer || buffer->bind_history & PIPE_BIND_SHADER_IMAGE) { + for (shader = 0; shader < SI_NUM_SHADERS; ++shader) { + struct si_images *images = &sctx->images[shader]; + struct si_descriptors *descs = + si_sampler_and_image_descriptors(sctx, shader); + unsigned mask = images->enabled_mask; - while (mask) { - unsigned i = u_bit_scan(&mask); - struct pipe_resource *buffer = images->views[i].resource; + while (mask) { + unsigned i = u_bit_scan(&mask); + struct pipe_resource *buffer = images->views[i].resource; - if (buffer && buffer->target == PIPE_BUFFER && - (!buf || buffer == buf)) { - unsigned desc_slot = si_get_image_slot(i); + if (buffer && buffer->target == PIPE_BUFFER && + (!buf || buffer == buf)) { + unsigned desc_slot = si_get_image_slot(i); - if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE) - si_mark_image_range_valid(&images->views[i]); + if (images->views[i].access & PIPE_IMAGE_ACCESS_WRITE) + si_mark_image_range_valid(&images->views[i]); - si_set_buf_desc_address(si_resource(buffer), - images->views[i].u.buf.offset, - descs->list + desc_slot * 8 + 4); - sctx->descriptors_dirty |= - 1u << si_sampler_and_image_descriptors_idx(shader); + si_set_buf_desc_address(si_resource(buffer), + images->views[i].u.buf.offset, + descs->list + desc_slot * 8 + 4); + sctx->descriptors_dirty |= + 1u << si_sampler_and_image_descriptors_idx(shader); - radeon_add_to_gfx_buffer_list_check_mem( - sctx, si_resource(buffer), - RADEON_USAGE_READWRITE, - RADEON_PRIO_SAMPLER_BUFFER, true); - } - } - } - } + radeon_add_to_gfx_buffer_list_check_mem( + sctx, si_resource(buffer), + RADEON_USAGE_READWRITE, + RADEON_PRIO_SAMPLER_BUFFER, true); + } + } + } + } - /* Bindless texture handles */ - if (!buffer || buffer->texture_handle_allocated) { - struct si_descriptors *descs = &sctx->bindless_descriptors; + /* Bindless texture handles */ + if (!buffer || buffer->texture_handle_allocated) { + struct si_descriptors *descs = &sctx->bindless_descriptors; - util_dynarray_foreach(&sctx->resident_tex_handles, - struct si_texture_handle *, tex_handle) { - struct pipe_sampler_view *view = (*tex_handle)->view; - unsigned desc_slot = (*tex_handle)->desc_slot; - struct pipe_resource *buffer = view->texture; + util_dynarray_foreach(&sctx->resident_tex_handles, + struct si_texture_handle *, tex_handle) { + struct pipe_sampler_view *view = (*tex_handle)->view; + unsigned desc_slot = (*tex_handle)->desc_slot; + struct pipe_resource *buffer = view->texture; - if (buffer && buffer->target == PIPE_BUFFER && - (!buf || buffer == buf)) { - si_set_buf_desc_address(si_resource(buffer), - view->u.buf.offset, - descs->list + - desc_slot * 16 + 4); + if (buffer && buffer->target == PIPE_BUFFER && + (!buf || buffer == buf)) { + si_set_buf_desc_address(si_resource(buffer), + view->u.buf.offset, + descs->list + + desc_slot * 16 + 4); - (*tex_handle)->desc_dirty = true; - sctx->bindless_descriptors_dirty = true; + (*tex_handle)->desc_dirty = true; + sctx->bindless_descriptors_dirty = true; - radeon_add_to_gfx_buffer_list_check_mem( - sctx, si_resource(buffer), - RADEON_USAGE_READ, - RADEON_PRIO_SAMPLER_BUFFER, true); - } - } - } + radeon_add_to_gfx_buffer_list_check_mem( + sctx, si_resource(buffer), + RADEON_USAGE_READ, + RADEON_PRIO_SAMPLER_BUFFER, true); + } + } + } - /* Bindless image handles */ - if (!buffer || buffer->image_handle_allocated) { - struct si_descriptors *descs = &sctx->bindless_descriptors; + /* Bindless image handles */ + if (!buffer || buffer->image_handle_allocated) { + struct si_descriptors *descs = &sctx->bindless_descriptors; - util_dynarray_foreach(&sctx->resident_img_handles, - struct si_image_handle *, img_handle) { - struct pipe_image_view *view = &(*img_handle)->view; - unsigned desc_slot = (*img_handle)->desc_slot; - struct pipe_resource *buffer = view->resource; + util_dynarray_foreach(&sctx->resident_img_handles, + struct si_image_handle *, img_handle) { + struct pipe_image_view *view = &(*img_handle)->view; + unsigned desc_slot = (*img_handle)->desc_slot; + struct pipe_resource *buffer = view->resource; - if (buffer && buffer->target == PIPE_BUFFER && - (!buf || buffer == buf)) { - if (view->access & PIPE_IMAGE_ACCESS_WRITE) - si_mark_image_range_valid(view); + if (buffer && buffer->target == PIPE_BUFFER && + (!buf || buffer == buf)) { + if (view->access & PIPE_IMAGE_ACCESS_WRITE) + si_mark_image_range_valid(view); - si_set_buf_desc_address(si_resource(buffer), - view->u.buf.offset, - descs->list + - desc_slot * 16 + 4); + si_set_buf_desc_address(si_resource(buffer), + view->u.buf.offset, + descs->list + + desc_slot * 16 + 4); - (*img_handle)->desc_dirty = true; - sctx->bindless_descriptors_dirty = true; + (*img_handle)->desc_dirty = true; + sctx->bindless_descriptors_dirty = true; - radeon_add_to_gfx_buffer_list_check_mem( - sctx, si_resource(buffer), - RADEON_USAGE_READWRITE, - RADEON_PRIO_SAMPLER_BUFFER, true); - } - } - } + radeon_add_to_gfx_buffer_list_check_mem( + sctx, si_resource(buffer), + RADEON_USAGE_READWRITE, + RADEON_PRIO_SAMPLER_BUFFER, true); + } + } + } - if (buffer) { - /* Do the same for other contexts. They will invoke this function - * with buffer == NULL. - */ - unsigned new_counter = p_atomic_inc_return(&sctx->screen->dirty_buf_counter); + if (buffer) { + /* Do the same for other contexts. They will invoke this function + * with buffer == NULL. + */ + unsigned new_counter = p_atomic_inc_return(&sctx->screen->dirty_buf_counter); - /* Skip the update for the current context, because we have already updated - * the buffer bindings. - */ - if (new_counter == sctx->last_dirty_buf_counter + 1) - sctx->last_dirty_buf_counter = new_counter; - } + /* Skip the update for the current context, because we have already updated + * the buffer bindings. + */ + if (new_counter == sctx->last_dirty_buf_counter + 1) + sctx->last_dirty_buf_counter = new_counter; + } } static void si_upload_bindless_descriptor(struct si_context *sctx, - unsigned desc_slot, - unsigned num_dwords) + unsigned desc_slot, + unsigned num_dwords) { - struct si_descriptors *desc = &sctx->bindless_descriptors; - unsigned desc_slot_offset = desc_slot * 16; - uint32_t *data; - uint64_t va; + struct si_descriptors *desc = &sctx->bindless_descriptors; + unsigned desc_slot_offset = desc_slot * 16; + uint32_t *data; + uint64_t va; - data = desc->list + desc_slot_offset; - va = desc->gpu_address + desc_slot_offset * 4; + data = desc->list + desc_slot_offset; + va = desc->gpu_address + desc_slot_offset * 4; - si_cp_write_data(sctx, desc->buffer, va - desc->buffer->gpu_address, - num_dwords * 4, V_370_TC_L2, V_370_ME, data); + si_cp_write_data(sctx, desc->buffer, va - desc->buffer->gpu_address, + num_dwords * 4, V_370_TC_L2, V_370_ME, data); } static void si_upload_bindless_descriptors(struct si_context *sctx) { - if (!sctx->bindless_descriptors_dirty) - return; + if (!sctx->bindless_descriptors_dirty) + return; - /* Wait for graphics/compute to be idle before updating the resident - * descriptors directly in memory, in case the GPU is using them. - */ - sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | - SI_CONTEXT_CS_PARTIAL_FLUSH; - sctx->emit_cache_flush(sctx); + /* Wait for graphics/compute to be idle before updating the resident + * descriptors directly in memory, in case the GPU is using them. + */ + sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | + SI_CONTEXT_CS_PARTIAL_FLUSH; + sctx->emit_cache_flush(sctx); - util_dynarray_foreach(&sctx->resident_tex_handles, - struct si_texture_handle *, tex_handle) { - unsigned desc_slot = (*tex_handle)->desc_slot; + util_dynarray_foreach(&sctx->resident_tex_handles, + struct si_texture_handle *, tex_handle) { + unsigned desc_slot = (*tex_handle)->desc_slot; - if (!(*tex_handle)->desc_dirty) - continue; + if (!(*tex_handle)->desc_dirty) + continue; - si_upload_bindless_descriptor(sctx, desc_slot, 16); - (*tex_handle)->desc_dirty = false; - } + si_upload_bindless_descriptor(sctx, desc_slot, 16); + (*tex_handle)->desc_dirty = false; + } - util_dynarray_foreach(&sctx->resident_img_handles, - struct si_image_handle *, img_handle) { - unsigned desc_slot = (*img_handle)->desc_slot; + util_dynarray_foreach(&sctx->resident_img_handles, + struct si_image_handle *, img_handle) { + unsigned desc_slot = (*img_handle)->desc_slot; - if (!(*img_handle)->desc_dirty) - continue; + if (!(*img_handle)->desc_dirty) + continue; - si_upload_bindless_descriptor(sctx, desc_slot, 8); - (*img_handle)->desc_dirty = false; - } + si_upload_bindless_descriptor(sctx, desc_slot, 8); + (*img_handle)->desc_dirty = false; + } - /* Invalidate L1 because it doesn't know that L2 changed. */ - sctx->flags |= SI_CONTEXT_INV_SCACHE; - sctx->emit_cache_flush(sctx); + /* Invalidate L1 because it doesn't know that L2 changed. */ + sctx->flags |= SI_CONTEXT_INV_SCACHE; + sctx->emit_cache_flush(sctx); - sctx->bindless_descriptors_dirty = false; + sctx->bindless_descriptors_dirty = false; } /* Update mutable image descriptor fields of all resident textures. */ static void si_update_bindless_texture_descriptor(struct si_context *sctx, - struct si_texture_handle *tex_handle) + struct si_texture_handle *tex_handle) { - struct si_sampler_view *sview = (struct si_sampler_view *)tex_handle->view; - struct si_descriptors *desc = &sctx->bindless_descriptors; - unsigned desc_slot_offset = tex_handle->desc_slot * 16; - uint32_t desc_list[16]; + struct si_sampler_view *sview = (struct si_sampler_view *)tex_handle->view; + struct si_descriptors *desc = &sctx->bindless_descriptors; + unsigned desc_slot_offset = tex_handle->desc_slot * 16; + uint32_t desc_list[16]; - if (sview->base.texture->target == PIPE_BUFFER) - return; + if (sview->base.texture->target == PIPE_BUFFER) + return; - memcpy(desc_list, desc->list + desc_slot_offset, sizeof(desc_list)); - si_set_sampler_view_desc(sctx, sview, &tex_handle->sstate, - desc->list + desc_slot_offset); + memcpy(desc_list, desc->list + desc_slot_offset, sizeof(desc_list)); + si_set_sampler_view_desc(sctx, sview, &tex_handle->sstate, + desc->list + desc_slot_offset); - if (memcmp(desc_list, desc->list + desc_slot_offset, - sizeof(desc_list))) { - tex_handle->desc_dirty = true; - sctx->bindless_descriptors_dirty = true; - } + if (memcmp(desc_list, desc->list + desc_slot_offset, + sizeof(desc_list))) { + tex_handle->desc_dirty = true; + sctx->bindless_descriptors_dirty = true; + } } static void si_update_bindless_image_descriptor(struct si_context *sctx, - struct si_image_handle *img_handle) + struct si_image_handle *img_handle) { - struct si_descriptors *desc = &sctx->bindless_descriptors; - unsigned desc_slot_offset = img_handle->desc_slot * 16; - struct pipe_image_view *view = &img_handle->view; - struct pipe_resource *res = view->resource; - uint32_t image_desc[16]; - unsigned desc_size = (res->nr_samples >= 2 ? 16 : 8) * 4; + struct si_descriptors *desc = &sctx->bindless_descriptors; + unsigned desc_slot_offset = img_handle->desc_slot * 16; + struct pipe_image_view *view = &img_handle->view; + struct pipe_resource *res = view->resource; + uint32_t image_desc[16]; + unsigned desc_size = (res->nr_samples >= 2 ? 16 : 8) * 4; - if (res->target == PIPE_BUFFER) - return; + if (res->target == PIPE_BUFFER) + return; - memcpy(image_desc, desc->list + desc_slot_offset, desc_size); - si_set_shader_image_desc(sctx, view, true, - desc->list + desc_slot_offset, - desc->list + desc_slot_offset + 8); + memcpy(image_desc, desc->list + desc_slot_offset, desc_size); + si_set_shader_image_desc(sctx, view, true, + desc->list + desc_slot_offset, + desc->list + desc_slot_offset + 8); - if (memcmp(image_desc, desc->list + desc_slot_offset, desc_size)) { - img_handle->desc_dirty = true; - sctx->bindless_descriptors_dirty = true; - } + if (memcmp(image_desc, desc->list + desc_slot_offset, desc_size)) { + img_handle->desc_dirty = true; + sctx->bindless_descriptors_dirty = true; + } } static void si_update_all_resident_texture_descriptors(struct si_context *sctx) { - util_dynarray_foreach(&sctx->resident_tex_handles, - struct si_texture_handle *, tex_handle) { - si_update_bindless_texture_descriptor(sctx, *tex_handle); - } + util_dynarray_foreach(&sctx->resident_tex_handles, + struct si_texture_handle *, tex_handle) { + si_update_bindless_texture_descriptor(sctx, *tex_handle); + } - util_dynarray_foreach(&sctx->resident_img_handles, - struct si_image_handle *, img_handle) { - si_update_bindless_image_descriptor(sctx, *img_handle); - } + util_dynarray_foreach(&sctx->resident_img_handles, + struct si_image_handle *, img_handle) { + si_update_bindless_image_descriptor(sctx, *img_handle); + } - si_upload_bindless_descriptors(sctx); + si_upload_bindless_descriptors(sctx); } /* Update mutable image descriptor fields of all bound textures. */ void si_update_all_texture_descriptors(struct si_context *sctx) { - unsigned shader; + unsigned shader; - for (shader = 0; shader < SI_NUM_SHADERS; shader++) { - struct si_samplers *samplers = &sctx->samplers[shader]; - struct si_images *images = &sctx->images[shader]; - unsigned mask; + for (shader = 0; shader < SI_NUM_SHADERS; shader++) { + struct si_samplers *samplers = &sctx->samplers[shader]; + struct si_images *images = &sctx->images[shader]; + unsigned mask; - /* Images. */ - mask = images->enabled_mask; - while (mask) { - unsigned i = u_bit_scan(&mask); - struct pipe_image_view *view = &images->views[i]; + /* Images. */ + mask = images->enabled_mask; + while (mask) { + unsigned i = u_bit_scan(&mask); + struct pipe_image_view *view = &images->views[i]; - if (!view->resource || - view->resource->target == PIPE_BUFFER) - continue; + if (!view->resource || + view->resource->target == PIPE_BUFFER) + continue; - si_set_shader_image(sctx, shader, i, view, true); - } + si_set_shader_image(sctx, shader, i, view, true); + } - /* Sampler views. */ - mask = samplers->enabled_mask; - while (mask) { - unsigned i = u_bit_scan(&mask); - struct pipe_sampler_view *view = samplers->views[i]; + /* Sampler views. */ + mask = samplers->enabled_mask; + while (mask) { + unsigned i = u_bit_scan(&mask); + struct pipe_sampler_view *view = samplers->views[i]; - if (!view || - !view->texture || - view->texture->target == PIPE_BUFFER) - continue; + if (!view || + !view->texture || + view->texture->target == PIPE_BUFFER) + continue; - si_set_sampler_view(sctx, shader, i, - samplers->views[i], true); - } + si_set_sampler_view(sctx, shader, i, + samplers->views[i], true); + } - si_update_shader_needs_decompress_mask(sctx, shader); - } + si_update_shader_needs_decompress_mask(sctx, shader); + } - si_update_all_resident_texture_descriptors(sctx); - si_update_ps_colorbuf0_slot(sctx); + si_update_all_resident_texture_descriptors(sctx); + si_update_ps_colorbuf0_slot(sctx); } /* SHADER USER DATA */ static void si_mark_shader_pointers_dirty(struct si_context *sctx, - unsigned shader) + unsigned shader) { - sctx->shader_pointers_dirty |= - u_bit_consecutive(SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS, - SI_NUM_SHADER_DESCS); + sctx->shader_pointers_dirty |= + u_bit_consecutive(SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS, + SI_NUM_SHADER_DESCS); - if (shader == PIPE_SHADER_VERTEX) { - sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL; - sctx->vertex_buffer_user_sgprs_dirty = sctx->num_vertex_elements > 0 && - sctx->screen->num_vbos_in_user_sgprs; - } + if (shader == PIPE_SHADER_VERTEX) { + sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL; + sctx->vertex_buffer_user_sgprs_dirty = sctx->num_vertex_elements > 0 && + sctx->screen->num_vbos_in_user_sgprs; + } - si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers); + si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers); } static void si_shader_pointers_begin_new_cs(struct si_context *sctx) { - sctx->shader_pointers_dirty = u_bit_consecutive(0, SI_NUM_DESCS); - sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL; - sctx->vertex_buffer_user_sgprs_dirty = sctx->num_vertex_elements > 0 && - sctx->screen->num_vbos_in_user_sgprs; - si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers); - sctx->graphics_bindless_pointer_dirty = sctx->bindless_descriptors.buffer != NULL; - sctx->compute_bindless_pointer_dirty = sctx->bindless_descriptors.buffer != NULL; + sctx->shader_pointers_dirty = u_bit_consecutive(0, SI_NUM_DESCS); + sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL; + sctx->vertex_buffer_user_sgprs_dirty = sctx->num_vertex_elements > 0 && + sctx->screen->num_vbos_in_user_sgprs; + si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers); + sctx->graphics_bindless_pointer_dirty = sctx->bindless_descriptors.buffer != NULL; + sctx->compute_bindless_pointer_dirty = sctx->bindless_descriptors.buffer != NULL; } /* Set a base register address for user data constants in the given shader. * This assigns a mapping from PIPE_SHADER_* to SPI_SHADER_USER_DATA_*. */ static void si_set_user_data_base(struct si_context *sctx, - unsigned shader, uint32_t new_base) + unsigned shader, uint32_t new_base) { - uint32_t *base = &sctx->shader_pointers.sh_base[shader]; + uint32_t *base = &sctx->shader_pointers.sh_base[shader]; - if (*base != new_base) { - *base = new_base; + if (*base != new_base) { + *base = new_base; - if (new_base) - si_mark_shader_pointers_dirty(sctx, shader); + if (new_base) + si_mark_shader_pointers_dirty(sctx, shader); - /* Any change in enabled shader stages requires re-emitting - * the VS state SGPR, because it contains the clamp_vertex_color - * state, which can be done in VS, TES, and GS. - */ - sctx->last_vs_state = ~0; - } + /* Any change in enabled shader stages requires re-emitting + * the VS state SGPR, because it contains the clamp_vertex_color + * state, which can be done in VS, TES, and GS. + */ + sctx->last_vs_state = ~0; + } } /* This must be called when these are changed between enabled and disabled @@ -2110,922 +2110,922 @@ static void si_set_user_data_base(struct si_context *sctx, */ void si_shader_change_notify(struct si_context *sctx) { - /* VS can be bound as VS, ES, or LS. */ - if (sctx->tes_shader.cso) { - if (sctx->chip_class >= GFX10) { - si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, - R_00B430_SPI_SHADER_USER_DATA_HS_0); - } else if (sctx->chip_class == GFX9) { - si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, - R_00B430_SPI_SHADER_USER_DATA_LS_0); - } else { - si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, - R_00B530_SPI_SHADER_USER_DATA_LS_0); - } - } else if (sctx->chip_class >= GFX10) { - if (sctx->ngg || sctx->gs_shader.cso) { - si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, - R_00B230_SPI_SHADER_USER_DATA_GS_0); - } else { - si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, - R_00B130_SPI_SHADER_USER_DATA_VS_0); - } - } else if (sctx->gs_shader.cso) { - si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, - R_00B330_SPI_SHADER_USER_DATA_ES_0); - } else { - si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, - R_00B130_SPI_SHADER_USER_DATA_VS_0); - } + /* VS can be bound as VS, ES, or LS. */ + if (sctx->tes_shader.cso) { + if (sctx->chip_class >= GFX10) { + si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, + R_00B430_SPI_SHADER_USER_DATA_HS_0); + } else if (sctx->chip_class == GFX9) { + si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, + R_00B430_SPI_SHADER_USER_DATA_LS_0); + } else { + si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, + R_00B530_SPI_SHADER_USER_DATA_LS_0); + } + } else if (sctx->chip_class >= GFX10) { + if (sctx->ngg || sctx->gs_shader.cso) { + si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, + R_00B230_SPI_SHADER_USER_DATA_GS_0); + } else { + si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, + R_00B130_SPI_SHADER_USER_DATA_VS_0); + } + } else if (sctx->gs_shader.cso) { + si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, + R_00B330_SPI_SHADER_USER_DATA_ES_0); + } else { + si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, + R_00B130_SPI_SHADER_USER_DATA_VS_0); + } - /* TES can be bound as ES, VS, or not bound. */ - if (sctx->tes_shader.cso) { - if (sctx->chip_class >= GFX10) { - if (sctx->ngg || sctx->gs_shader.cso) { - si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, - R_00B230_SPI_SHADER_USER_DATA_GS_0); - } else { - si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, - R_00B130_SPI_SHADER_USER_DATA_VS_0); - } - } else if (sctx->gs_shader.cso) { - si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, - R_00B330_SPI_SHADER_USER_DATA_ES_0); - } else { - si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, - R_00B130_SPI_SHADER_USER_DATA_VS_0); - } - } else { - si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, 0); - } + /* TES can be bound as ES, VS, or not bound. */ + if (sctx->tes_shader.cso) { + if (sctx->chip_class >= GFX10) { + if (sctx->ngg || sctx->gs_shader.cso) { + si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, + R_00B230_SPI_SHADER_USER_DATA_GS_0); + } else { + si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, + R_00B130_SPI_SHADER_USER_DATA_VS_0); + } + } else if (sctx->gs_shader.cso) { + si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, + R_00B330_SPI_SHADER_USER_DATA_ES_0); + } else { + si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, + R_00B130_SPI_SHADER_USER_DATA_VS_0); + } + } else { + si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, 0); + } } static void si_emit_shader_pointer_head(struct radeon_cmdbuf *cs, - unsigned sh_offset, - unsigned pointer_count) + unsigned sh_offset, + unsigned pointer_count) { - radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count, 0)); - radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2); + radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count, 0)); + radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2); } static void si_emit_shader_pointer_body(struct si_screen *sscreen, - struct radeon_cmdbuf *cs, - uint64_t va) + struct radeon_cmdbuf *cs, + uint64_t va) { - radeon_emit(cs, va); + radeon_emit(cs, va); - assert(va == 0 || (va >> 32) == sscreen->info.address32_hi); + assert(va == 0 || (va >> 32) == sscreen->info.address32_hi); } static void si_emit_shader_pointer(struct si_context *sctx, - struct si_descriptors *desc, - unsigned sh_base) + struct si_descriptors *desc, + unsigned sh_base) { - struct radeon_cmdbuf *cs = sctx->gfx_cs; - unsigned sh_offset = sh_base + desc->shader_userdata_offset; + struct radeon_cmdbuf *cs = sctx->gfx_cs; + unsigned sh_offset = sh_base + desc->shader_userdata_offset; - si_emit_shader_pointer_head(cs, sh_offset, 1); - si_emit_shader_pointer_body(sctx->screen, cs, desc->gpu_address); + si_emit_shader_pointer_head(cs, sh_offset, 1); + si_emit_shader_pointer_body(sctx->screen, cs, desc->gpu_address); } static void si_emit_consecutive_shader_pointers(struct si_context *sctx, - unsigned pointer_mask, - unsigned sh_base) + unsigned pointer_mask, + unsigned sh_base) { - if (!sh_base) - return; + if (!sh_base) + return; - struct radeon_cmdbuf *cs = sctx->gfx_cs; - unsigned mask = sctx->shader_pointers_dirty & pointer_mask; + struct radeon_cmdbuf *cs = sctx->gfx_cs; + unsigned mask = sctx->shader_pointers_dirty & pointer_mask; - while (mask) { - int start, count; - u_bit_scan_consecutive_range(&mask, &start, &count); + while (mask) { + int start, count; + u_bit_scan_consecutive_range(&mask, &start, &count); - struct si_descriptors *descs = &sctx->descriptors[start]; - unsigned sh_offset = sh_base + descs->shader_userdata_offset; + struct si_descriptors *descs = &sctx->descriptors[start]; + unsigned sh_offset = sh_base + descs->shader_userdata_offset; - si_emit_shader_pointer_head(cs, sh_offset, count); - for (int i = 0; i < count; i++) - si_emit_shader_pointer_body(sctx->screen, cs, - descs[i].gpu_address); - } + si_emit_shader_pointer_head(cs, sh_offset, count); + for (int i = 0; i < count; i++) + si_emit_shader_pointer_body(sctx->screen, cs, + descs[i].gpu_address); + } } static void si_emit_global_shader_pointers(struct si_context *sctx, - struct si_descriptors *descs) + struct si_descriptors *descs) { - if (sctx->chip_class >= GFX10) { - si_emit_shader_pointer(sctx, descs, - R_00B030_SPI_SHADER_USER_DATA_PS_0); - /* HW VS stage only used in non-NGG mode. */ - si_emit_shader_pointer(sctx, descs, - R_00B130_SPI_SHADER_USER_DATA_VS_0); - si_emit_shader_pointer(sctx, descs, - R_00B230_SPI_SHADER_USER_DATA_GS_0); - si_emit_shader_pointer(sctx, descs, - R_00B430_SPI_SHADER_USER_DATA_HS_0); - return; - } else if (sctx->chip_class == GFX9) { - /* Broadcast it to all shader stages. */ - si_emit_shader_pointer(sctx, descs, - R_00B530_SPI_SHADER_USER_DATA_COMMON_0); - return; - } + if (sctx->chip_class >= GFX10) { + si_emit_shader_pointer(sctx, descs, + R_00B030_SPI_SHADER_USER_DATA_PS_0); + /* HW VS stage only used in non-NGG mode. */ + si_emit_shader_pointer(sctx, descs, + R_00B130_SPI_SHADER_USER_DATA_VS_0); + si_emit_shader_pointer(sctx, descs, + R_00B230_SPI_SHADER_USER_DATA_GS_0); + si_emit_shader_pointer(sctx, descs, + R_00B430_SPI_SHADER_USER_DATA_HS_0); + return; + } else if (sctx->chip_class == GFX9) { + /* Broadcast it to all shader stages. */ + si_emit_shader_pointer(sctx, descs, + R_00B530_SPI_SHADER_USER_DATA_COMMON_0); + return; + } - si_emit_shader_pointer(sctx, descs, - R_00B030_SPI_SHADER_USER_DATA_PS_0); - si_emit_shader_pointer(sctx, descs, - R_00B130_SPI_SHADER_USER_DATA_VS_0); - si_emit_shader_pointer(sctx, descs, - R_00B330_SPI_SHADER_USER_DATA_ES_0); - si_emit_shader_pointer(sctx, descs, - R_00B230_SPI_SHADER_USER_DATA_GS_0); - si_emit_shader_pointer(sctx, descs, - R_00B430_SPI_SHADER_USER_DATA_HS_0); - si_emit_shader_pointer(sctx, descs, - R_00B530_SPI_SHADER_USER_DATA_LS_0); + si_emit_shader_pointer(sctx, descs, + R_00B030_SPI_SHADER_USER_DATA_PS_0); + si_emit_shader_pointer(sctx, descs, + R_00B130_SPI_SHADER_USER_DATA_VS_0); + si_emit_shader_pointer(sctx, descs, + R_00B330_SPI_SHADER_USER_DATA_ES_0); + si_emit_shader_pointer(sctx, descs, + R_00B230_SPI_SHADER_USER_DATA_GS_0); + si_emit_shader_pointer(sctx, descs, + R_00B430_SPI_SHADER_USER_DATA_HS_0); + si_emit_shader_pointer(sctx, descs, + R_00B530_SPI_SHADER_USER_DATA_LS_0); } void si_emit_graphics_shader_pointers(struct si_context *sctx) { - uint32_t *sh_base = sctx->shader_pointers.sh_base; + uint32_t *sh_base = sctx->shader_pointers.sh_base; - if (sctx->shader_pointers_dirty & (1 << SI_DESCS_RW_BUFFERS)) { - si_emit_global_shader_pointers(sctx, - &sctx->descriptors[SI_DESCS_RW_BUFFERS]); - } + if (sctx->shader_pointers_dirty & (1 << SI_DESCS_RW_BUFFERS)) { + si_emit_global_shader_pointers(sctx, + &sctx->descriptors[SI_DESCS_RW_BUFFERS]); + } - si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(VERTEX), - sh_base[PIPE_SHADER_VERTEX]); - si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(TESS_EVAL), - sh_base[PIPE_SHADER_TESS_EVAL]); - si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(FRAGMENT), - sh_base[PIPE_SHADER_FRAGMENT]); - si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(TESS_CTRL), - sh_base[PIPE_SHADER_TESS_CTRL]); - si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(GEOMETRY), - sh_base[PIPE_SHADER_GEOMETRY]); + si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(VERTEX), + sh_base[PIPE_SHADER_VERTEX]); + si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(TESS_EVAL), + sh_base[PIPE_SHADER_TESS_EVAL]); + si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(FRAGMENT), + sh_base[PIPE_SHADER_FRAGMENT]); + si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(TESS_CTRL), + sh_base[PIPE_SHADER_TESS_CTRL]); + si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(GEOMETRY), + sh_base[PIPE_SHADER_GEOMETRY]); - sctx->shader_pointers_dirty &= - ~u_bit_consecutive(SI_DESCS_RW_BUFFERS, SI_DESCS_FIRST_COMPUTE); + sctx->shader_pointers_dirty &= + ~u_bit_consecutive(SI_DESCS_RW_BUFFERS, SI_DESCS_FIRST_COMPUTE); - if (sctx->vertex_buffer_pointer_dirty && sctx->num_vertex_elements) { - struct radeon_cmdbuf *cs = sctx->gfx_cs; + if (sctx->vertex_buffer_pointer_dirty && sctx->num_vertex_elements) { + struct radeon_cmdbuf *cs = sctx->gfx_cs; - /* Find the location of the VB descriptor pointer. */ - unsigned sh_dw_offset = SI_VS_NUM_USER_SGPR; - if (sctx->chip_class >= GFX9) { - if (sctx->tes_shader.cso) - sh_dw_offset = GFX9_TCS_NUM_USER_SGPR; - else if (sctx->gs_shader.cso) - sh_dw_offset = GFX9_VSGS_NUM_USER_SGPR; - } + /* Find the location of the VB descriptor pointer. */ + unsigned sh_dw_offset = SI_VS_NUM_USER_SGPR; + if (sctx->chip_class >= GFX9) { + if (sctx->tes_shader.cso) + sh_dw_offset = GFX9_TCS_NUM_USER_SGPR; + else if (sctx->gs_shader.cso) + sh_dw_offset = GFX9_VSGS_NUM_USER_SGPR; + } - unsigned sh_offset = sh_base[PIPE_SHADER_VERTEX] + sh_dw_offset * 4; - si_emit_shader_pointer_head(cs, sh_offset, 1); - si_emit_shader_pointer_body(sctx->screen, cs, - sctx->vb_descriptors_buffer->gpu_address + - sctx->vb_descriptors_offset); - sctx->vertex_buffer_pointer_dirty = false; - } + unsigned sh_offset = sh_base[PIPE_SHADER_VERTEX] + sh_dw_offset * 4; + si_emit_shader_pointer_head(cs, sh_offset, 1); + si_emit_shader_pointer_body(sctx->screen, cs, + sctx->vb_descriptors_buffer->gpu_address + + sctx->vb_descriptors_offset); + sctx->vertex_buffer_pointer_dirty = false; + } - if (sctx->vertex_buffer_user_sgprs_dirty && - sctx->num_vertex_elements && - sctx->screen->num_vbos_in_user_sgprs) { - struct radeon_cmdbuf *cs = sctx->gfx_cs; - unsigned num_desc = MIN2(sctx->num_vertex_elements, - sctx->screen->num_vbos_in_user_sgprs); - unsigned sh_offset = sh_base[PIPE_SHADER_VERTEX] + SI_SGPR_VS_VB_DESCRIPTOR_FIRST * 4; + if (sctx->vertex_buffer_user_sgprs_dirty && + sctx->num_vertex_elements && + sctx->screen->num_vbos_in_user_sgprs) { + struct radeon_cmdbuf *cs = sctx->gfx_cs; + unsigned num_desc = MIN2(sctx->num_vertex_elements, + sctx->screen->num_vbos_in_user_sgprs); + unsigned sh_offset = sh_base[PIPE_SHADER_VERTEX] + SI_SGPR_VS_VB_DESCRIPTOR_FIRST * 4; - si_emit_shader_pointer_head(cs, sh_offset, num_desc * 4); - radeon_emit_array(cs, sctx->vb_descriptor_user_sgprs, num_desc * 4); - sctx->vertex_buffer_user_sgprs_dirty = false; - } + si_emit_shader_pointer_head(cs, sh_offset, num_desc * 4); + radeon_emit_array(cs, sctx->vb_descriptor_user_sgprs, num_desc * 4); + sctx->vertex_buffer_user_sgprs_dirty = false; + } - if (sctx->graphics_bindless_pointer_dirty) { - si_emit_global_shader_pointers(sctx, - &sctx->bindless_descriptors); - sctx->graphics_bindless_pointer_dirty = false; - } + if (sctx->graphics_bindless_pointer_dirty) { + si_emit_global_shader_pointers(sctx, + &sctx->bindless_descriptors); + sctx->graphics_bindless_pointer_dirty = false; + } } void si_emit_compute_shader_pointers(struct si_context *sctx) { - unsigned base = R_00B900_COMPUTE_USER_DATA_0; + unsigned base = R_00B900_COMPUTE_USER_DATA_0; - si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(COMPUTE), - R_00B900_COMPUTE_USER_DATA_0); - sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(COMPUTE); + si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(COMPUTE), + R_00B900_COMPUTE_USER_DATA_0); + sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(COMPUTE); - if (sctx->compute_bindless_pointer_dirty) { - si_emit_shader_pointer(sctx, &sctx->bindless_descriptors, base); - sctx->compute_bindless_pointer_dirty = false; - } + if (sctx->compute_bindless_pointer_dirty) { + si_emit_shader_pointer(sctx, &sctx->bindless_descriptors, base); + sctx->compute_bindless_pointer_dirty = false; + } } /* BINDLESS */ static void si_init_bindless_descriptors(struct si_context *sctx, - struct si_descriptors *desc, - short shader_userdata_rel_index, - unsigned num_elements) + struct si_descriptors *desc, + short shader_userdata_rel_index, + unsigned num_elements) { - ASSERTED unsigned desc_slot; + ASSERTED unsigned desc_slot; - si_init_descriptors(desc, shader_userdata_rel_index, 16, num_elements); - sctx->bindless_descriptors.num_active_slots = num_elements; + si_init_descriptors(desc, shader_userdata_rel_index, 16, num_elements); + sctx->bindless_descriptors.num_active_slots = num_elements; - /* The first bindless descriptor is stored at slot 1, because 0 is not - * considered to be a valid handle. - */ - sctx->num_bindless_descriptors = 1; + /* The first bindless descriptor is stored at slot 1, because 0 is not + * considered to be a valid handle. + */ + sctx->num_bindless_descriptors = 1; - /* Track which bindless slots are used (or not). */ - util_idalloc_init(&sctx->bindless_used_slots); - util_idalloc_resize(&sctx->bindless_used_slots, num_elements); + /* Track which bindless slots are used (or not). */ + util_idalloc_init(&sctx->bindless_used_slots); + util_idalloc_resize(&sctx->bindless_used_slots, num_elements); - /* Reserve slot 0 because it's an invalid handle for bindless. */ - desc_slot = util_idalloc_alloc(&sctx->bindless_used_slots); - assert(desc_slot == 0); + /* Reserve slot 0 because it's an invalid handle for bindless. */ + desc_slot = util_idalloc_alloc(&sctx->bindless_used_slots); + assert(desc_slot == 0); } static void si_release_bindless_descriptors(struct si_context *sctx) { - si_release_descriptors(&sctx->bindless_descriptors); - util_idalloc_fini(&sctx->bindless_used_slots); + si_release_descriptors(&sctx->bindless_descriptors); + util_idalloc_fini(&sctx->bindless_used_slots); } static unsigned si_get_first_free_bindless_slot(struct si_context *sctx) { - struct si_descriptors *desc = &sctx->bindless_descriptors; - unsigned desc_slot; + struct si_descriptors *desc = &sctx->bindless_descriptors; + unsigned desc_slot; - desc_slot = util_idalloc_alloc(&sctx->bindless_used_slots); - if (desc_slot >= desc->num_elements) { - /* The array of bindless descriptors is full, resize it. */ - unsigned slot_size = desc->element_dw_size * 4; - unsigned new_num_elements = desc->num_elements * 2; + desc_slot = util_idalloc_alloc(&sctx->bindless_used_slots); + if (desc_slot >= desc->num_elements) { + /* The array of bindless descriptors is full, resize it. */ + unsigned slot_size = desc->element_dw_size * 4; + unsigned new_num_elements = desc->num_elements * 2; - desc->list = REALLOC(desc->list, desc->num_elements * slot_size, - new_num_elements * slot_size); - desc->num_elements = new_num_elements; - desc->num_active_slots = new_num_elements; - } + desc->list = REALLOC(desc->list, desc->num_elements * slot_size, + new_num_elements * slot_size); + desc->num_elements = new_num_elements; + desc->num_active_slots = new_num_elements; + } - assert(desc_slot); - return desc_slot; + assert(desc_slot); + return desc_slot; } static unsigned si_create_bindless_descriptor(struct si_context *sctx, uint32_t *desc_list, - unsigned size) + unsigned size) { - struct si_descriptors *desc = &sctx->bindless_descriptors; - unsigned desc_slot, desc_slot_offset; + struct si_descriptors *desc = &sctx->bindless_descriptors; + unsigned desc_slot, desc_slot_offset; - /* Find a free slot. */ - desc_slot = si_get_first_free_bindless_slot(sctx); + /* Find a free slot. */ + desc_slot = si_get_first_free_bindless_slot(sctx); - /* For simplicity, sampler and image bindless descriptors use fixed - * 16-dword slots for now. Image descriptors only need 8-dword but this - * doesn't really matter because no real apps use image handles. - */ - desc_slot_offset = desc_slot * 16; + /* For simplicity, sampler and image bindless descriptors use fixed + * 16-dword slots for now. Image descriptors only need 8-dword but this + * doesn't really matter because no real apps use image handles. + */ + desc_slot_offset = desc_slot * 16; - /* Copy the descriptor into the array. */ - memcpy(desc->list + desc_slot_offset, desc_list, size); + /* Copy the descriptor into the array. */ + memcpy(desc->list + desc_slot_offset, desc_list, size); - /* Re-upload the whole array of bindless descriptors into a new buffer. - */ - if (!si_upload_descriptors(sctx, desc)) - return 0; + /* Re-upload the whole array of bindless descriptors into a new buffer. + */ + if (!si_upload_descriptors(sctx, desc)) + return 0; - /* Make sure to re-emit the shader pointers for all stages. */ - sctx->graphics_bindless_pointer_dirty = true; - sctx->compute_bindless_pointer_dirty = true; + /* Make sure to re-emit the shader pointers for all stages. */ + sctx->graphics_bindless_pointer_dirty = true; + sctx->compute_bindless_pointer_dirty = true; - return desc_slot; + return desc_slot; } static void si_update_bindless_buffer_descriptor(struct si_context *sctx, - unsigned desc_slot, - struct pipe_resource *resource, - uint64_t offset, - bool *desc_dirty) + unsigned desc_slot, + struct pipe_resource *resource, + uint64_t offset, + bool *desc_dirty) { - struct si_descriptors *desc = &sctx->bindless_descriptors; - struct si_resource *buf = si_resource(resource); - unsigned desc_slot_offset = desc_slot * 16; - uint32_t *desc_list = desc->list + desc_slot_offset + 4; - uint64_t old_desc_va; + struct si_descriptors *desc = &sctx->bindless_descriptors; + struct si_resource *buf = si_resource(resource); + unsigned desc_slot_offset = desc_slot * 16; + uint32_t *desc_list = desc->list + desc_slot_offset + 4; + uint64_t old_desc_va; - assert(resource->target == PIPE_BUFFER); + assert(resource->target == PIPE_BUFFER); - /* Retrieve the old buffer addr from the descriptor. */ - old_desc_va = si_desc_extract_buffer_address(desc_list); + /* Retrieve the old buffer addr from the descriptor. */ + old_desc_va = si_desc_extract_buffer_address(desc_list); - if (old_desc_va != buf->gpu_address + offset) { - /* The buffer has been invalidated when the handle wasn't - * resident, update the descriptor and the dirty flag. - */ - si_set_buf_desc_address(buf, offset, &desc_list[0]); + if (old_desc_va != buf->gpu_address + offset) { + /* The buffer has been invalidated when the handle wasn't + * resident, update the descriptor and the dirty flag. + */ + si_set_buf_desc_address(buf, offset, &desc_list[0]); - *desc_dirty = true; - } + *desc_dirty = true; + } } static uint64_t si_create_texture_handle(struct pipe_context *ctx, - struct pipe_sampler_view *view, - const struct pipe_sampler_state *state) + struct pipe_sampler_view *view, + const struct pipe_sampler_state *state) { - struct si_sampler_view *sview = (struct si_sampler_view *)view; - struct si_context *sctx = (struct si_context *)ctx; - struct si_texture_handle *tex_handle; - struct si_sampler_state *sstate; - uint32_t desc_list[16]; - uint64_t handle; + struct si_sampler_view *sview = (struct si_sampler_view *)view; + struct si_context *sctx = (struct si_context *)ctx; + struct si_texture_handle *tex_handle; + struct si_sampler_state *sstate; + uint32_t desc_list[16]; + uint64_t handle; - tex_handle = CALLOC_STRUCT(si_texture_handle); - if (!tex_handle) - return 0; + tex_handle = CALLOC_STRUCT(si_texture_handle); + if (!tex_handle) + return 0; - memset(desc_list, 0, sizeof(desc_list)); - si_init_descriptor_list(&desc_list[0], 16, 1, null_texture_descriptor); + memset(desc_list, 0, sizeof(desc_list)); + si_init_descriptor_list(&desc_list[0], 16, 1, null_texture_descriptor); - sstate = ctx->create_sampler_state(ctx, state); - if (!sstate) { - FREE(tex_handle); - return 0; - } + sstate = ctx->create_sampler_state(ctx, state); + if (!sstate) { + FREE(tex_handle); + return 0; + } - si_set_sampler_view_desc(sctx, sview, sstate, &desc_list[0]); - memcpy(&tex_handle->sstate, sstate, sizeof(*sstate)); - ctx->delete_sampler_state(ctx, sstate); + si_set_sampler_view_desc(sctx, sview, sstate, &desc_list[0]); + memcpy(&tex_handle->sstate, sstate, sizeof(*sstate)); + ctx->delete_sampler_state(ctx, sstate); - tex_handle->desc_slot = si_create_bindless_descriptor(sctx, desc_list, - sizeof(desc_list)); - if (!tex_handle->desc_slot) { - FREE(tex_handle); - return 0; - } + tex_handle->desc_slot = si_create_bindless_descriptor(sctx, desc_list, + sizeof(desc_list)); + if (!tex_handle->desc_slot) { + FREE(tex_handle); + return 0; + } - handle = tex_handle->desc_slot; + handle = tex_handle->desc_slot; - if (!_mesa_hash_table_insert(sctx->tex_handles, - (void *)(uintptr_t)handle, - tex_handle)) { - FREE(tex_handle); - return 0; - } + if (!_mesa_hash_table_insert(sctx->tex_handles, + (void *)(uintptr_t)handle, + tex_handle)) { + FREE(tex_handle); + return 0; + } - pipe_sampler_view_reference(&tex_handle->view, view); + pipe_sampler_view_reference(&tex_handle->view, view); - si_resource(sview->base.texture)->texture_handle_allocated = true; + si_resource(sview->base.texture)->texture_handle_allocated = true; - return handle; + return handle; } static void si_delete_texture_handle(struct pipe_context *ctx, uint64_t handle) { - struct si_context *sctx = (struct si_context *)ctx; - struct si_texture_handle *tex_handle; - struct hash_entry *entry; + struct si_context *sctx = (struct si_context *)ctx; + struct si_texture_handle *tex_handle; + struct hash_entry *entry; - entry = _mesa_hash_table_search(sctx->tex_handles, - (void *)(uintptr_t)handle); - if (!entry) - return; + entry = _mesa_hash_table_search(sctx->tex_handles, + (void *)(uintptr_t)handle); + if (!entry) + return; - tex_handle = (struct si_texture_handle *)entry->data; + tex_handle = (struct si_texture_handle *)entry->data; - /* Allow this descriptor slot to be re-used. */ - util_idalloc_free(&sctx->bindless_used_slots, tex_handle->desc_slot); + /* Allow this descriptor slot to be re-used. */ + util_idalloc_free(&sctx->bindless_used_slots, tex_handle->desc_slot); - pipe_sampler_view_reference(&tex_handle->view, NULL); - _mesa_hash_table_remove(sctx->tex_handles, entry); - FREE(tex_handle); + pipe_sampler_view_reference(&tex_handle->view, NULL); + _mesa_hash_table_remove(sctx->tex_handles, entry); + FREE(tex_handle); } static void si_make_texture_handle_resident(struct pipe_context *ctx, - uint64_t handle, bool resident) + uint64_t handle, bool resident) { - struct si_context *sctx = (struct si_context *)ctx; - struct si_texture_handle *tex_handle; - struct si_sampler_view *sview; - struct hash_entry *entry; + struct si_context *sctx = (struct si_context *)ctx; + struct si_texture_handle *tex_handle; + struct si_sampler_view *sview; + struct hash_entry *entry; - entry = _mesa_hash_table_search(sctx->tex_handles, - (void *)(uintptr_t)handle); - if (!entry) - return; + entry = _mesa_hash_table_search(sctx->tex_handles, + (void *)(uintptr_t)handle); + if (!entry) + return; - tex_handle = (struct si_texture_handle *)entry->data; - sview = (struct si_sampler_view *)tex_handle->view; + tex_handle = (struct si_texture_handle *)entry->data; + sview = (struct si_sampler_view *)tex_handle->view; - if (resident) { - if (sview->base.texture->target != PIPE_BUFFER) { - struct si_texture *tex = - (struct si_texture *)sview->base.texture; + if (resident) { + if (sview->base.texture->target != PIPE_BUFFER) { + struct si_texture *tex = + (struct si_texture *)sview->base.texture; - if (depth_needs_decompression(tex)) { - util_dynarray_append( - &sctx->resident_tex_needs_depth_decompress, - struct si_texture_handle *, - tex_handle); - } + if (depth_needs_decompression(tex)) { + util_dynarray_append( + &sctx->resident_tex_needs_depth_decompress, + struct si_texture_handle *, + tex_handle); + } - if (color_needs_decompression(tex)) { - util_dynarray_append( - &sctx->resident_tex_needs_color_decompress, - struct si_texture_handle *, - tex_handle); - } + if (color_needs_decompression(tex)) { + util_dynarray_append( + &sctx->resident_tex_needs_color_decompress, + struct si_texture_handle *, + tex_handle); + } - if (tex->surface.dcc_offset && - p_atomic_read(&tex->framebuffers_bound)) - sctx->need_check_render_feedback = true; + if (tex->surface.dcc_offset && + p_atomic_read(&tex->framebuffers_bound)) + sctx->need_check_render_feedback = true; - si_update_bindless_texture_descriptor(sctx, tex_handle); - } else { - si_update_bindless_buffer_descriptor(sctx, - tex_handle->desc_slot, - sview->base.texture, - sview->base.u.buf.offset, - &tex_handle->desc_dirty); - } + si_update_bindless_texture_descriptor(sctx, tex_handle); + } else { + si_update_bindless_buffer_descriptor(sctx, + tex_handle->desc_slot, + sview->base.texture, + sview->base.u.buf.offset, + &tex_handle->desc_dirty); + } - /* Re-upload the descriptor if it has been updated while it - * wasn't resident. - */ - if (tex_handle->desc_dirty) - sctx->bindless_descriptors_dirty = true; + /* Re-upload the descriptor if it has been updated while it + * wasn't resident. + */ + if (tex_handle->desc_dirty) + sctx->bindless_descriptors_dirty = true; - /* Add the texture handle to the per-context list. */ - util_dynarray_append(&sctx->resident_tex_handles, - struct si_texture_handle *, tex_handle); + /* Add the texture handle to the per-context list. */ + util_dynarray_append(&sctx->resident_tex_handles, + struct si_texture_handle *, tex_handle); - /* Add the buffers to the current CS in case si_begin_new_cs() - * is not going to be called. - */ - si_sampler_view_add_buffer(sctx, sview->base.texture, - RADEON_USAGE_READ, - sview->is_stencil_sampler, false); - } else { - /* Remove the texture handle from the per-context list. */ - util_dynarray_delete_unordered(&sctx->resident_tex_handles, - struct si_texture_handle *, - tex_handle); + /* Add the buffers to the current CS in case si_begin_new_cs() + * is not going to be called. + */ + si_sampler_view_add_buffer(sctx, sview->base.texture, + RADEON_USAGE_READ, + sview->is_stencil_sampler, false); + } else { + /* Remove the texture handle from the per-context list. */ + util_dynarray_delete_unordered(&sctx->resident_tex_handles, + struct si_texture_handle *, + tex_handle); - if (sview->base.texture->target != PIPE_BUFFER) { - util_dynarray_delete_unordered( - &sctx->resident_tex_needs_depth_decompress, - struct si_texture_handle *, tex_handle); + if (sview->base.texture->target != PIPE_BUFFER) { + util_dynarray_delete_unordered( + &sctx->resident_tex_needs_depth_decompress, + struct si_texture_handle *, tex_handle); - util_dynarray_delete_unordered( - &sctx->resident_tex_needs_color_decompress, - struct si_texture_handle *, tex_handle); - } - } + util_dynarray_delete_unordered( + &sctx->resident_tex_needs_color_decompress, + struct si_texture_handle *, tex_handle); + } + } } static uint64_t si_create_image_handle(struct pipe_context *ctx, - const struct pipe_image_view *view) + const struct pipe_image_view *view) { - struct si_context *sctx = (struct si_context *)ctx; - struct si_image_handle *img_handle; - uint32_t desc_list[16]; - uint64_t handle; + struct si_context *sctx = (struct si_context *)ctx; + struct si_image_handle *img_handle; + uint32_t desc_list[16]; + uint64_t handle; - if (!view || !view->resource) - return 0; + if (!view || !view->resource) + return 0; - img_handle = CALLOC_STRUCT(si_image_handle); - if (!img_handle) - return 0; + img_handle = CALLOC_STRUCT(si_image_handle); + if (!img_handle) + return 0; - memset(desc_list, 0, sizeof(desc_list)); - si_init_descriptor_list(&desc_list[0], 8, 2, null_image_descriptor); + memset(desc_list, 0, sizeof(desc_list)); + si_init_descriptor_list(&desc_list[0], 8, 2, null_image_descriptor); - si_set_shader_image_desc(sctx, view, false, &desc_list[0], &desc_list[8]); + si_set_shader_image_desc(sctx, view, false, &desc_list[0], &desc_list[8]); - img_handle->desc_slot = si_create_bindless_descriptor(sctx, desc_list, - sizeof(desc_list)); - if (!img_handle->desc_slot) { - FREE(img_handle); - return 0; - } + img_handle->desc_slot = si_create_bindless_descriptor(sctx, desc_list, + sizeof(desc_list)); + if (!img_handle->desc_slot) { + FREE(img_handle); + return 0; + } - handle = img_handle->desc_slot; + handle = img_handle->desc_slot; - if (!_mesa_hash_table_insert(sctx->img_handles, - (void *)(uintptr_t)handle, - img_handle)) { - FREE(img_handle); - return 0; - } + if (!_mesa_hash_table_insert(sctx->img_handles, + (void *)(uintptr_t)handle, + img_handle)) { + FREE(img_handle); + return 0; + } - util_copy_image_view(&img_handle->view, view); + util_copy_image_view(&img_handle->view, view); - si_resource(view->resource)->image_handle_allocated = true; + si_resource(view->resource)->image_handle_allocated = true; - return handle; + return handle; } static void si_delete_image_handle(struct pipe_context *ctx, uint64_t handle) { - struct si_context *sctx = (struct si_context *)ctx; - struct si_image_handle *img_handle; - struct hash_entry *entry; + struct si_context *sctx = (struct si_context *)ctx; + struct si_image_handle *img_handle; + struct hash_entry *entry; - entry = _mesa_hash_table_search(sctx->img_handles, - (void *)(uintptr_t)handle); - if (!entry) - return; + entry = _mesa_hash_table_search(sctx->img_handles, + (void *)(uintptr_t)handle); + if (!entry) + return; - img_handle = (struct si_image_handle *)entry->data; + img_handle = (struct si_image_handle *)entry->data; - util_copy_image_view(&img_handle->view, NULL); - _mesa_hash_table_remove(sctx->img_handles, entry); - FREE(img_handle); + util_copy_image_view(&img_handle->view, NULL); + _mesa_hash_table_remove(sctx->img_handles, entry); + FREE(img_handle); } static void si_make_image_handle_resident(struct pipe_context *ctx, - uint64_t handle, unsigned access, - bool resident) + uint64_t handle, unsigned access, + bool resident) { - struct si_context *sctx = (struct si_context *)ctx; - struct si_image_handle *img_handle; - struct pipe_image_view *view; - struct si_resource *res; - struct hash_entry *entry; + struct si_context *sctx = (struct si_context *)ctx; + struct si_image_handle *img_handle; + struct pipe_image_view *view; + struct si_resource *res; + struct hash_entry *entry; - entry = _mesa_hash_table_search(sctx->img_handles, - (void *)(uintptr_t)handle); - if (!entry) - return; + entry = _mesa_hash_table_search(sctx->img_handles, + (void *)(uintptr_t)handle); + if (!entry) + return; - img_handle = (struct si_image_handle *)entry->data; - view = &img_handle->view; - res = si_resource(view->resource); + img_handle = (struct si_image_handle *)entry->data; + view = &img_handle->view; + res = si_resource(view->resource); - if (resident) { - if (res->b.b.target != PIPE_BUFFER) { - struct si_texture *tex = (struct si_texture *)res; - unsigned level = view->u.tex.level; + if (resident) { + if (res->b.b.target != PIPE_BUFFER) { + struct si_texture *tex = (struct si_texture *)res; + unsigned level = view->u.tex.level; - if (color_needs_decompression(tex)) { - util_dynarray_append( - &sctx->resident_img_needs_color_decompress, - struct si_image_handle *, - img_handle); - } + if (color_needs_decompression(tex)) { + util_dynarray_append( + &sctx->resident_img_needs_color_decompress, + struct si_image_handle *, + img_handle); + } - if (vi_dcc_enabled(tex, level) && - p_atomic_read(&tex->framebuffers_bound)) - sctx->need_check_render_feedback = true; + if (vi_dcc_enabled(tex, level) && + p_atomic_read(&tex->framebuffers_bound)) + sctx->need_check_render_feedback = true; - si_update_bindless_image_descriptor(sctx, img_handle); - } else { - si_update_bindless_buffer_descriptor(sctx, - img_handle->desc_slot, - view->resource, - view->u.buf.offset, - &img_handle->desc_dirty); - } + si_update_bindless_image_descriptor(sctx, img_handle); + } else { + si_update_bindless_buffer_descriptor(sctx, + img_handle->desc_slot, + view->resource, + view->u.buf.offset, + &img_handle->desc_dirty); + } - /* Re-upload the descriptor if it has been updated while it - * wasn't resident. - */ - if (img_handle->desc_dirty) - sctx->bindless_descriptors_dirty = true; + /* Re-upload the descriptor if it has been updated while it + * wasn't resident. + */ + if (img_handle->desc_dirty) + sctx->bindless_descriptors_dirty = true; - /* Add the image handle to the per-context list. */ - util_dynarray_append(&sctx->resident_img_handles, - struct si_image_handle *, img_handle); + /* Add the image handle to the per-context list. */ + util_dynarray_append(&sctx->resident_img_handles, + struct si_image_handle *, img_handle); - /* Add the buffers to the current CS in case si_begin_new_cs() - * is not going to be called. - */ - si_sampler_view_add_buffer(sctx, view->resource, - (access & PIPE_IMAGE_ACCESS_WRITE) ? - RADEON_USAGE_READWRITE : - RADEON_USAGE_READ, false, false); - } else { - /* Remove the image handle from the per-context list. */ - util_dynarray_delete_unordered(&sctx->resident_img_handles, - struct si_image_handle *, - img_handle); + /* Add the buffers to the current CS in case si_begin_new_cs() + * is not going to be called. + */ + si_sampler_view_add_buffer(sctx, view->resource, + (access & PIPE_IMAGE_ACCESS_WRITE) ? + RADEON_USAGE_READWRITE : + RADEON_USAGE_READ, false, false); + } else { + /* Remove the image handle from the per-context list. */ + util_dynarray_delete_unordered(&sctx->resident_img_handles, + struct si_image_handle *, + img_handle); - if (res->b.b.target != PIPE_BUFFER) { - util_dynarray_delete_unordered( - &sctx->resident_img_needs_color_decompress, - struct si_image_handle *, - img_handle); - } - } + if (res->b.b.target != PIPE_BUFFER) { + util_dynarray_delete_unordered( + &sctx->resident_img_needs_color_decompress, + struct si_image_handle *, + img_handle); + } + } } static void si_resident_buffers_add_all_to_bo_list(struct si_context *sctx) { - unsigned num_resident_tex_handles, num_resident_img_handles; + unsigned num_resident_tex_handles, num_resident_img_handles; - num_resident_tex_handles = sctx->resident_tex_handles.size / - sizeof(struct si_texture_handle *); - num_resident_img_handles = sctx->resident_img_handles.size / - sizeof(struct si_image_handle *); + num_resident_tex_handles = sctx->resident_tex_handles.size / + sizeof(struct si_texture_handle *); + num_resident_img_handles = sctx->resident_img_handles.size / + sizeof(struct si_image_handle *); - /* Add all resident texture handles. */ - util_dynarray_foreach(&sctx->resident_tex_handles, - struct si_texture_handle *, tex_handle) { - struct si_sampler_view *sview = - (struct si_sampler_view *)(*tex_handle)->view; + /* Add all resident texture handles. */ + util_dynarray_foreach(&sctx->resident_tex_handles, + struct si_texture_handle *, tex_handle) { + struct si_sampler_view *sview = + (struct si_sampler_view *)(*tex_handle)->view; - si_sampler_view_add_buffer(sctx, sview->base.texture, - RADEON_USAGE_READ, - sview->is_stencil_sampler, false); - } + si_sampler_view_add_buffer(sctx, sview->base.texture, + RADEON_USAGE_READ, + sview->is_stencil_sampler, false); + } - /* Add all resident image handles. */ - util_dynarray_foreach(&sctx->resident_img_handles, - struct si_image_handle *, img_handle) { - struct pipe_image_view *view = &(*img_handle)->view; + /* Add all resident image handles. */ + util_dynarray_foreach(&sctx->resident_img_handles, + struct si_image_handle *, img_handle) { + struct pipe_image_view *view = &(*img_handle)->view; - si_sampler_view_add_buffer(sctx, view->resource, - RADEON_USAGE_READWRITE, - false, false); - } + si_sampler_view_add_buffer(sctx, view->resource, + RADEON_USAGE_READWRITE, + false, false); + } - sctx->num_resident_handles += num_resident_tex_handles + - num_resident_img_handles; - assert(sctx->bo_list_add_all_resident_resources); - sctx->bo_list_add_all_resident_resources = false; + sctx->num_resident_handles += num_resident_tex_handles + + num_resident_img_handles; + assert(sctx->bo_list_add_all_resident_resources); + sctx->bo_list_add_all_resident_resources = false; } /* INIT/DEINIT/UPLOAD */ void si_init_all_descriptors(struct si_context *sctx) { - int i; - unsigned first_shader = - sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE; + int i; + unsigned first_shader = + sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE; - for (i = first_shader; i < SI_NUM_SHADERS; i++) { - bool is_2nd = sctx->chip_class >= GFX9 && - (i == PIPE_SHADER_TESS_CTRL || - i == PIPE_SHADER_GEOMETRY); - unsigned num_sampler_slots = SI_NUM_IMAGE_SLOTS / 2 + SI_NUM_SAMPLERS; - unsigned num_buffer_slots = SI_NUM_SHADER_BUFFERS + SI_NUM_CONST_BUFFERS; - int rel_dw_offset; - struct si_descriptors *desc; + for (i = first_shader; i < SI_NUM_SHADERS; i++) { + bool is_2nd = sctx->chip_class >= GFX9 && + (i == PIPE_SHADER_TESS_CTRL || + i == PIPE_SHADER_GEOMETRY); + unsigned num_sampler_slots = SI_NUM_IMAGE_SLOTS / 2 + SI_NUM_SAMPLERS; + unsigned num_buffer_slots = SI_NUM_SHADER_BUFFERS + SI_NUM_CONST_BUFFERS; + int rel_dw_offset; + struct si_descriptors *desc; - if (is_2nd) { - if (i == PIPE_SHADER_TESS_CTRL) { - rel_dw_offset = (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS - - R_00B430_SPI_SHADER_USER_DATA_LS_0) / 4; - } else if (sctx->chip_class >= GFX10) { /* PIPE_SHADER_GEOMETRY */ - rel_dw_offset = (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS - - R_00B230_SPI_SHADER_USER_DATA_GS_0) / 4; - } else { - rel_dw_offset = (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS - - R_00B330_SPI_SHADER_USER_DATA_ES_0) / 4; - } - } else { - rel_dw_offset = SI_SGPR_CONST_AND_SHADER_BUFFERS; - } - desc = si_const_and_shader_buffer_descriptors(sctx, i); - si_init_buffer_resources(&sctx->const_and_shader_buffers[i], desc, - num_buffer_slots, rel_dw_offset, - RADEON_PRIO_SHADER_RW_BUFFER, - RADEON_PRIO_CONST_BUFFER); - desc->slot_index_to_bind_directly = si_get_constbuf_slot(0); + if (is_2nd) { + if (i == PIPE_SHADER_TESS_CTRL) { + rel_dw_offset = (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS - + R_00B430_SPI_SHADER_USER_DATA_LS_0) / 4; + } else if (sctx->chip_class >= GFX10) { /* PIPE_SHADER_GEOMETRY */ + rel_dw_offset = (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS - + R_00B230_SPI_SHADER_USER_DATA_GS_0) / 4; + } else { + rel_dw_offset = (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS - + R_00B330_SPI_SHADER_USER_DATA_ES_0) / 4; + } + } else { + rel_dw_offset = SI_SGPR_CONST_AND_SHADER_BUFFERS; + } + desc = si_const_and_shader_buffer_descriptors(sctx, i); + si_init_buffer_resources(&sctx->const_and_shader_buffers[i], desc, + num_buffer_slots, rel_dw_offset, + RADEON_PRIO_SHADER_RW_BUFFER, + RADEON_PRIO_CONST_BUFFER); + desc->slot_index_to_bind_directly = si_get_constbuf_slot(0); - if (is_2nd) { - if (i == PIPE_SHADER_TESS_CTRL) { - rel_dw_offset = (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS - - R_00B430_SPI_SHADER_USER_DATA_LS_0) / 4; - } else if (sctx->chip_class >= GFX10) { /* PIPE_SHADER_GEOMETRY */ - rel_dw_offset = (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS - - R_00B230_SPI_SHADER_USER_DATA_GS_0) / 4; - } else { - rel_dw_offset = (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS - - R_00B330_SPI_SHADER_USER_DATA_ES_0) / 4; - } - } else { - rel_dw_offset = SI_SGPR_SAMPLERS_AND_IMAGES; - } + if (is_2nd) { + if (i == PIPE_SHADER_TESS_CTRL) { + rel_dw_offset = (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS - + R_00B430_SPI_SHADER_USER_DATA_LS_0) / 4; + } else if (sctx->chip_class >= GFX10) { /* PIPE_SHADER_GEOMETRY */ + rel_dw_offset = (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS - + R_00B230_SPI_SHADER_USER_DATA_GS_0) / 4; + } else { + rel_dw_offset = (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS - + R_00B330_SPI_SHADER_USER_DATA_ES_0) / 4; + } + } else { + rel_dw_offset = SI_SGPR_SAMPLERS_AND_IMAGES; + } - desc = si_sampler_and_image_descriptors(sctx, i); - si_init_descriptors(desc, rel_dw_offset, 16, num_sampler_slots); + desc = si_sampler_and_image_descriptors(sctx, i); + si_init_descriptors(desc, rel_dw_offset, 16, num_sampler_slots); - int j; - for (j = 0; j < SI_NUM_IMAGE_SLOTS; j++) - memcpy(desc->list + j * 8, null_image_descriptor, 8 * 4); - for (; j < SI_NUM_IMAGE_SLOTS + SI_NUM_SAMPLERS * 2; j++) - memcpy(desc->list + j * 8, null_texture_descriptor, 8 * 4); - } + int j; + for (j = 0; j < SI_NUM_IMAGE_SLOTS; j++) + memcpy(desc->list + j * 8, null_image_descriptor, 8 * 4); + for (; j < SI_NUM_IMAGE_SLOTS + SI_NUM_SAMPLERS * 2; j++) + memcpy(desc->list + j * 8, null_texture_descriptor, 8 * 4); + } - si_init_buffer_resources(&sctx->rw_buffers, - &sctx->descriptors[SI_DESCS_RW_BUFFERS], - SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS, - /* The second priority is used by - * const buffers in RW buffer slots. */ - RADEON_PRIO_SHADER_RINGS, RADEON_PRIO_CONST_BUFFER); - sctx->descriptors[SI_DESCS_RW_BUFFERS].num_active_slots = SI_NUM_RW_BUFFERS; + si_init_buffer_resources(&sctx->rw_buffers, + &sctx->descriptors[SI_DESCS_RW_BUFFERS], + SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS, + /* The second priority is used by + * const buffers in RW buffer slots. */ + RADEON_PRIO_SHADER_RINGS, RADEON_PRIO_CONST_BUFFER); + sctx->descriptors[SI_DESCS_RW_BUFFERS].num_active_slots = SI_NUM_RW_BUFFERS; - /* Initialize an array of 1024 bindless descriptors, when the limit is - * reached, just make it larger and re-upload the whole array. - */ - si_init_bindless_descriptors(sctx, &sctx->bindless_descriptors, - SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES, - 1024); + /* Initialize an array of 1024 bindless descriptors, when the limit is + * reached, just make it larger and re-upload the whole array. + */ + si_init_bindless_descriptors(sctx, &sctx->bindless_descriptors, + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES, + 1024); - sctx->descriptors_dirty = u_bit_consecutive(0, SI_NUM_DESCS); + sctx->descriptors_dirty = u_bit_consecutive(0, SI_NUM_DESCS); - /* Set pipe_context functions. */ - sctx->b.bind_sampler_states = si_bind_sampler_states; - sctx->b.set_shader_images = si_set_shader_images; - sctx->b.set_constant_buffer = si_pipe_set_constant_buffer; - sctx->b.set_shader_buffers = si_set_shader_buffers; - sctx->b.set_sampler_views = si_set_sampler_views; - sctx->b.create_texture_handle = si_create_texture_handle; - sctx->b.delete_texture_handle = si_delete_texture_handle; - sctx->b.make_texture_handle_resident = si_make_texture_handle_resident; - sctx->b.create_image_handle = si_create_image_handle; - sctx->b.delete_image_handle = si_delete_image_handle; - sctx->b.make_image_handle_resident = si_make_image_handle_resident; + /* Set pipe_context functions. */ + sctx->b.bind_sampler_states = si_bind_sampler_states; + sctx->b.set_shader_images = si_set_shader_images; + sctx->b.set_constant_buffer = si_pipe_set_constant_buffer; + sctx->b.set_shader_buffers = si_set_shader_buffers; + sctx->b.set_sampler_views = si_set_sampler_views; + sctx->b.create_texture_handle = si_create_texture_handle; + sctx->b.delete_texture_handle = si_delete_texture_handle; + sctx->b.make_texture_handle_resident = si_make_texture_handle_resident; + sctx->b.create_image_handle = si_create_image_handle; + sctx->b.delete_image_handle = si_delete_image_handle; + sctx->b.make_image_handle_resident = si_make_image_handle_resident; - if (!sctx->has_graphics) - return; + if (!sctx->has_graphics) + return; - sctx->b.set_polygon_stipple = si_set_polygon_stipple; + sctx->b.set_polygon_stipple = si_set_polygon_stipple; - /* Shader user data. */ - sctx->atoms.s.shader_pointers.emit = si_emit_graphics_shader_pointers; + /* Shader user data. */ + sctx->atoms.s.shader_pointers.emit = si_emit_graphics_shader_pointers; - /* Set default and immutable mappings. */ - if (sctx->ngg) { - assert(sctx->chip_class >= GFX10); - si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B230_SPI_SHADER_USER_DATA_GS_0); - } else { - si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0); - } + /* Set default and immutable mappings. */ + if (sctx->ngg) { + assert(sctx->chip_class >= GFX10); + si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B230_SPI_SHADER_USER_DATA_GS_0); + } else { + si_set_user_data_base(sctx, PIPE_SHADER_VERTEX, R_00B130_SPI_SHADER_USER_DATA_VS_0); + } - if (sctx->chip_class == GFX9) { - si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, - R_00B430_SPI_SHADER_USER_DATA_LS_0); - si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, - R_00B330_SPI_SHADER_USER_DATA_ES_0); - } else { - si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, - R_00B430_SPI_SHADER_USER_DATA_HS_0); - si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, - R_00B230_SPI_SHADER_USER_DATA_GS_0); - } - si_set_user_data_base(sctx, PIPE_SHADER_FRAGMENT, R_00B030_SPI_SHADER_USER_DATA_PS_0); + if (sctx->chip_class == GFX9) { + si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, + R_00B430_SPI_SHADER_USER_DATA_LS_0); + si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, + R_00B330_SPI_SHADER_USER_DATA_ES_0); + } else { + si_set_user_data_base(sctx, PIPE_SHADER_TESS_CTRL, + R_00B430_SPI_SHADER_USER_DATA_HS_0); + si_set_user_data_base(sctx, PIPE_SHADER_GEOMETRY, + R_00B230_SPI_SHADER_USER_DATA_GS_0); + } + si_set_user_data_base(sctx, PIPE_SHADER_FRAGMENT, R_00B030_SPI_SHADER_USER_DATA_PS_0); } static bool si_upload_shader_descriptors(struct si_context *sctx, unsigned mask) { - unsigned dirty = sctx->descriptors_dirty & mask; + unsigned dirty = sctx->descriptors_dirty & mask; - /* Assume nothing will go wrong: */ - sctx->shader_pointers_dirty |= dirty; + /* Assume nothing will go wrong: */ + sctx->shader_pointers_dirty |= dirty; - while (dirty) { - unsigned i = u_bit_scan(&dirty); + while (dirty) { + unsigned i = u_bit_scan(&dirty); - if (!si_upload_descriptors(sctx, &sctx->descriptors[i])) - return false; - } + if (!si_upload_descriptors(sctx, &sctx->descriptors[i])) + return false; + } - sctx->descriptors_dirty &= ~mask; + sctx->descriptors_dirty &= ~mask; - si_upload_bindless_descriptors(sctx); + si_upload_bindless_descriptors(sctx); - return true; + return true; } bool si_upload_graphics_shader_descriptors(struct si_context *sctx) { - const unsigned mask = u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE); - return si_upload_shader_descriptors(sctx, mask); + const unsigned mask = u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE); + return si_upload_shader_descriptors(sctx, mask); } bool si_upload_compute_shader_descriptors(struct si_context *sctx) { - /* Does not update rw_buffers as that is not needed for compute shaders - * and the input buffer is using the same SGPR's anyway. - */ - const unsigned mask = u_bit_consecutive(SI_DESCS_FIRST_COMPUTE, - SI_NUM_DESCS - SI_DESCS_FIRST_COMPUTE); - return si_upload_shader_descriptors(sctx, mask); + /* Does not update rw_buffers as that is not needed for compute shaders + * and the input buffer is using the same SGPR's anyway. + */ + const unsigned mask = u_bit_consecutive(SI_DESCS_FIRST_COMPUTE, + SI_NUM_DESCS - SI_DESCS_FIRST_COMPUTE); + return si_upload_shader_descriptors(sctx, mask); } void si_release_all_descriptors(struct si_context *sctx) { - int i; + int i; - for (i = 0; i < SI_NUM_SHADERS; i++) { - si_release_buffer_resources(&sctx->const_and_shader_buffers[i], - si_const_and_shader_buffer_descriptors(sctx, i)); - si_release_sampler_views(&sctx->samplers[i]); - si_release_image_views(&sctx->images[i]); - } - si_release_buffer_resources(&sctx->rw_buffers, - &sctx->descriptors[SI_DESCS_RW_BUFFERS]); - for (i = 0; i < SI_NUM_VERTEX_BUFFERS; i++) - pipe_vertex_buffer_unreference(&sctx->vertex_buffer[i]); + for (i = 0; i < SI_NUM_SHADERS; i++) { + si_release_buffer_resources(&sctx->const_and_shader_buffers[i], + si_const_and_shader_buffer_descriptors(sctx, i)); + si_release_sampler_views(&sctx->samplers[i]); + si_release_image_views(&sctx->images[i]); + } + si_release_buffer_resources(&sctx->rw_buffers, + &sctx->descriptors[SI_DESCS_RW_BUFFERS]); + for (i = 0; i < SI_NUM_VERTEX_BUFFERS; i++) + pipe_vertex_buffer_unreference(&sctx->vertex_buffer[i]); - for (i = 0; i < SI_NUM_DESCS; ++i) - si_release_descriptors(&sctx->descriptors[i]); + for (i = 0; i < SI_NUM_DESCS; ++i) + si_release_descriptors(&sctx->descriptors[i]); - si_resource_reference(&sctx->vb_descriptors_buffer, NULL); - sctx->vb_descriptors_gpu_list = NULL; /* points into a mapped buffer */ + si_resource_reference(&sctx->vb_descriptors_buffer, NULL); + sctx->vb_descriptors_gpu_list = NULL; /* points into a mapped buffer */ - si_release_bindless_descriptors(sctx); + si_release_bindless_descriptors(sctx); } void si_gfx_resources_add_all_to_bo_list(struct si_context *sctx) { - for (unsigned i = 0; i < SI_NUM_GRAPHICS_SHADERS; i++) { - si_buffer_resources_begin_new_cs(sctx, &sctx->const_and_shader_buffers[i]); - si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i]); - si_image_views_begin_new_cs(sctx, &sctx->images[i]); - } - si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers); - si_vertex_buffers_begin_new_cs(sctx); + for (unsigned i = 0; i < SI_NUM_GRAPHICS_SHADERS; i++) { + si_buffer_resources_begin_new_cs(sctx, &sctx->const_and_shader_buffers[i]); + si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i]); + si_image_views_begin_new_cs(sctx, &sctx->images[i]); + } + si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers); + si_vertex_buffers_begin_new_cs(sctx); - if (sctx->bo_list_add_all_resident_resources) - si_resident_buffers_add_all_to_bo_list(sctx); + if (sctx->bo_list_add_all_resident_resources) + si_resident_buffers_add_all_to_bo_list(sctx); - assert(sctx->bo_list_add_all_gfx_resources); - sctx->bo_list_add_all_gfx_resources = false; + assert(sctx->bo_list_add_all_gfx_resources); + sctx->bo_list_add_all_gfx_resources = false; } void si_compute_resources_add_all_to_bo_list(struct si_context *sctx) { - unsigned sh = PIPE_SHADER_COMPUTE; + unsigned sh = PIPE_SHADER_COMPUTE; - si_buffer_resources_begin_new_cs(sctx, &sctx->const_and_shader_buffers[sh]); - si_sampler_views_begin_new_cs(sctx, &sctx->samplers[sh]); - si_image_views_begin_new_cs(sctx, &sctx->images[sh]); - si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers); + si_buffer_resources_begin_new_cs(sctx, &sctx->const_and_shader_buffers[sh]); + si_sampler_views_begin_new_cs(sctx, &sctx->samplers[sh]); + si_image_views_begin_new_cs(sctx, &sctx->images[sh]); + si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers); - if (sctx->bo_list_add_all_resident_resources) - si_resident_buffers_add_all_to_bo_list(sctx); + if (sctx->bo_list_add_all_resident_resources) + si_resident_buffers_add_all_to_bo_list(sctx); - assert(sctx->bo_list_add_all_compute_resources); - sctx->bo_list_add_all_compute_resources = false; + assert(sctx->bo_list_add_all_compute_resources); + sctx->bo_list_add_all_compute_resources = false; } void si_all_descriptors_begin_new_cs(struct si_context *sctx) { - for (unsigned i = 0; i < SI_NUM_DESCS; ++i) - si_descriptors_begin_new_cs(sctx, &sctx->descriptors[i]); - si_descriptors_begin_new_cs(sctx, &sctx->bindless_descriptors); + for (unsigned i = 0; i < SI_NUM_DESCS; ++i) + si_descriptors_begin_new_cs(sctx, &sctx->descriptors[i]); + si_descriptors_begin_new_cs(sctx, &sctx->bindless_descriptors); - si_shader_pointers_begin_new_cs(sctx); + si_shader_pointers_begin_new_cs(sctx); - sctx->bo_list_add_all_resident_resources = true; - sctx->bo_list_add_all_gfx_resources = true; - sctx->bo_list_add_all_compute_resources = true; + sctx->bo_list_add_all_resident_resources = true; + sctx->bo_list_add_all_gfx_resources = true; + sctx->bo_list_add_all_compute_resources = true; } void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx, - uint64_t new_active_mask) + uint64_t new_active_mask) { - struct si_descriptors *desc = &sctx->descriptors[desc_idx]; + struct si_descriptors *desc = &sctx->descriptors[desc_idx]; - /* Ignore no-op updates and updates that disable all slots. */ - if (!new_active_mask || - new_active_mask == u_bit_consecutive64(desc->first_active_slot, - desc->num_active_slots)) - return; + /* Ignore no-op updates and updates that disable all slots. */ + if (!new_active_mask || + new_active_mask == u_bit_consecutive64(desc->first_active_slot, + desc->num_active_slots)) + return; - int first, count; - u_bit_scan_consecutive_range64(&new_active_mask, &first, &count); - assert(new_active_mask == 0); + int first, count; + u_bit_scan_consecutive_range64(&new_active_mask, &first, &count); + assert(new_active_mask == 0); - /* Upload/dump descriptors if slots are being enabled. */ - if (first < desc->first_active_slot || - first + count > desc->first_active_slot + desc->num_active_slots) - sctx->descriptors_dirty |= 1u << desc_idx; + /* Upload/dump descriptors if slots are being enabled. */ + if (first < desc->first_active_slot || + first + count > desc->first_active_slot + desc->num_active_slots) + sctx->descriptors_dirty |= 1u << desc_idx; - desc->first_active_slot = first; - desc->num_active_slots = count; + desc->first_active_slot = first; + desc->num_active_slots = count; } void si_set_active_descriptors_for_shader(struct si_context *sctx, - struct si_shader_selector *sel) + struct si_shader_selector *sel) { - if (!sel) - return; + if (!sel) + return; - si_set_active_descriptors(sctx, - si_const_and_shader_buffer_descriptors_idx(sel->type), - sel->active_const_and_shader_buffers); - si_set_active_descriptors(sctx, - si_sampler_and_image_descriptors_idx(sel->type), - sel->active_samplers_and_images); + si_set_active_descriptors(sctx, + si_const_and_shader_buffer_descriptors_idx(sel->type), + sel->active_const_and_shader_buffers); + si_set_active_descriptors(sctx, + si_sampler_and_image_descriptors_idx(sel->type), + sel->active_samplers_and_images); } diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index 0806bb00e52..cfe5d41fadd 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -42,443 +42,443 @@ static enum radeon_surf_mode si_choose_tiling(struct si_screen *sscreen, - const struct pipe_resource *templ, bool tc_compatible_htile); + const struct pipe_resource *templ, bool tc_compatible_htile); bool si_prepare_for_dma_blit(struct si_context *sctx, - struct si_texture *dst, - unsigned dst_level, unsigned dstx, - unsigned dsty, unsigned dstz, - struct si_texture *src, - unsigned src_level, - const struct pipe_box *src_box) + struct si_texture *dst, + unsigned dst_level, unsigned dstx, + unsigned dsty, unsigned dstz, + struct si_texture *src, + unsigned src_level, + const struct pipe_box *src_box) { - if (!sctx->sdma_cs) - return false; + if (!sctx->sdma_cs) + return false; - if (dst->surface.bpe != src->surface.bpe) - return false; + if (dst->surface.bpe != src->surface.bpe) + return false; - /* MSAA: Blits don't exist in the real world. */ - if (src->buffer.b.b.nr_samples > 1 || - dst->buffer.b.b.nr_samples > 1) - return false; + /* MSAA: Blits don't exist in the real world. */ + if (src->buffer.b.b.nr_samples > 1 || + dst->buffer.b.b.nr_samples > 1) + return false; - /* Depth-stencil surfaces: - * When dst is linear, the DB->CB copy preserves HTILE. - * When dst is tiled, the 3D path must be used to update HTILE. - */ - if (src->is_depth || dst->is_depth) - return false; + /* Depth-stencil surfaces: + * When dst is linear, the DB->CB copy preserves HTILE. + * When dst is tiled, the 3D path must be used to update HTILE. + */ + if (src->is_depth || dst->is_depth) + return false; - /* DCC as: - * src: Use the 3D path. DCC decompression is expensive. - * dst: Use the 3D path to compress the pixels with DCC. - */ - if (vi_dcc_enabled(src, src_level) || - vi_dcc_enabled(dst, dst_level)) - return false; + /* DCC as: + * src: Use the 3D path. DCC decompression is expensive. + * dst: Use the 3D path to compress the pixels with DCC. + */ + if (vi_dcc_enabled(src, src_level) || + vi_dcc_enabled(dst, dst_level)) + return false; - /* CMASK as: - * src: Both texture and SDMA paths need decompression. Use SDMA. - * dst: If overwriting the whole texture, discard CMASK and use - * SDMA. Otherwise, use the 3D path. - */ - if (dst->cmask_buffer && dst->dirty_level_mask & (1 << dst_level)) { - /* The CMASK clear is only enabled for the first level. */ - assert(dst_level == 0); - if (!util_texrange_covers_whole_level(&dst->buffer.b.b, dst_level, - dstx, dsty, dstz, src_box->width, - src_box->height, src_box->depth)) - return false; + /* CMASK as: + * src: Both texture and SDMA paths need decompression. Use SDMA. + * dst: If overwriting the whole texture, discard CMASK and use + * SDMA. Otherwise, use the 3D path. + */ + if (dst->cmask_buffer && dst->dirty_level_mask & (1 << dst_level)) { + /* The CMASK clear is only enabled for the first level. */ + assert(dst_level == 0); + if (!util_texrange_covers_whole_level(&dst->buffer.b.b, dst_level, + dstx, dsty, dstz, src_box->width, + src_box->height, src_box->depth)) + return false; - si_texture_discard_cmask(sctx->screen, dst); - } + si_texture_discard_cmask(sctx->screen, dst); + } - /* All requirements are met. Prepare textures for SDMA. */ - if (src->cmask_buffer && src->dirty_level_mask & (1 << src_level)) - sctx->b.flush_resource(&sctx->b, &src->buffer.b.b); + /* All requirements are met. Prepare textures for SDMA. */ + if (src->cmask_buffer && src->dirty_level_mask & (1 << src_level)) + sctx->b.flush_resource(&sctx->b, &src->buffer.b.b); - assert(!(src->dirty_level_mask & (1 << src_level))); - assert(!(dst->dirty_level_mask & (1 << dst_level))); + assert(!(src->dirty_level_mask & (1 << src_level))); + assert(!(dst->dirty_level_mask & (1 << dst_level))); - return true; + return true; } /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */ static void si_copy_region_with_blit(struct pipe_context *pipe, - struct pipe_resource *dst, - unsigned dst_level, - unsigned dstx, unsigned dsty, unsigned dstz, - struct pipe_resource *src, - unsigned src_level, - const struct pipe_box *src_box) + struct pipe_resource *dst, + unsigned dst_level, + unsigned dstx, unsigned dsty, unsigned dstz, + struct pipe_resource *src, + unsigned src_level, + const struct pipe_box *src_box) { - struct pipe_blit_info blit; + struct pipe_blit_info blit; - memset(&blit, 0, sizeof(blit)); - blit.src.resource = src; - blit.src.format = src->format; - blit.src.level = src_level; - blit.src.box = *src_box; - blit.dst.resource = dst; - blit.dst.format = dst->format; - blit.dst.level = dst_level; - blit.dst.box.x = dstx; - blit.dst.box.y = dsty; - blit.dst.box.z = dstz; - blit.dst.box.width = src_box->width; - blit.dst.box.height = src_box->height; - blit.dst.box.depth = src_box->depth; - blit.mask = util_format_get_mask(dst->format); - blit.filter = PIPE_TEX_FILTER_NEAREST; + memset(&blit, 0, sizeof(blit)); + blit.src.resource = src; + blit.src.format = src->format; + blit.src.level = src_level; + blit.src.box = *src_box; + blit.dst.resource = dst; + blit.dst.format = dst->format; + blit.dst.level = dst_level; + blit.dst.box.x = dstx; + blit.dst.box.y = dsty; + blit.dst.box.z = dstz; + blit.dst.box.width = src_box->width; + blit.dst.box.height = src_box->height; + blit.dst.box.depth = src_box->depth; + blit.mask = util_format_get_mask(dst->format); + blit.filter = PIPE_TEX_FILTER_NEAREST; - if (blit.mask) { - pipe->blit(pipe, &blit); - } + if (blit.mask) { + pipe->blit(pipe, &blit); + } } /* Copy from a full GPU texture to a transfer's staging one. */ static void si_copy_to_staging_texture(struct pipe_context *ctx, struct si_transfer *stransfer) { - struct si_context *sctx = (struct si_context*)ctx; - struct pipe_transfer *transfer = (struct pipe_transfer*)stransfer; - struct pipe_resource *dst = &stransfer->staging->b.b; - struct pipe_resource *src = transfer->resource; + struct si_context *sctx = (struct si_context*)ctx; + struct pipe_transfer *transfer = (struct pipe_transfer*)stransfer; + struct pipe_resource *dst = &stransfer->staging->b.b; + struct pipe_resource *src = transfer->resource; - if (src->nr_samples > 1 || ((struct si_texture*)src)->is_depth) { - si_copy_region_with_blit(ctx, dst, 0, 0, 0, 0, - src, transfer->level, &transfer->box); - return; - } + if (src->nr_samples > 1 || ((struct si_texture*)src)->is_depth) { + si_copy_region_with_blit(ctx, dst, 0, 0, 0, 0, + src, transfer->level, &transfer->box); + return; + } - sctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level, - &transfer->box); + sctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level, + &transfer->box); } /* Copy from a transfer's staging texture to a full GPU one. */ static void si_copy_from_staging_texture(struct pipe_context *ctx, struct si_transfer *stransfer) { - struct si_context *sctx = (struct si_context*)ctx; - struct pipe_transfer *transfer = (struct pipe_transfer*)stransfer; - struct pipe_resource *dst = transfer->resource; - struct pipe_resource *src = &stransfer->staging->b.b; - struct pipe_box sbox; + struct si_context *sctx = (struct si_context*)ctx; + struct pipe_transfer *transfer = (struct pipe_transfer*)stransfer; + struct pipe_resource *dst = transfer->resource; + struct pipe_resource *src = &stransfer->staging->b.b; + struct pipe_box sbox; - u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox); + u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox); - if (dst->nr_samples > 1 || ((struct si_texture*)dst)->is_depth) { - si_copy_region_with_blit(ctx, dst, transfer->level, - transfer->box.x, transfer->box.y, transfer->box.z, - src, 0, &sbox); - return; - } + if (dst->nr_samples > 1 || ((struct si_texture*)dst)->is_depth) { + si_copy_region_with_blit(ctx, dst, transfer->level, + transfer->box.x, transfer->box.y, transfer->box.z, + src, 0, &sbox); + return; + } - if (util_format_is_compressed(dst->format)) { - sbox.width = util_format_get_nblocksx(dst->format, sbox.width); - sbox.height = util_format_get_nblocksx(dst->format, sbox.height); - } + if (util_format_is_compressed(dst->format)) { + sbox.width = util_format_get_nblocksx(dst->format, sbox.width); + sbox.height = util_format_get_nblocksx(dst->format, sbox.height); + } - sctx->dma_copy(ctx, dst, transfer->level, - transfer->box.x, transfer->box.y, transfer->box.z, - src, 0, &sbox); + sctx->dma_copy(ctx, dst, transfer->level, + transfer->box.x, transfer->box.y, transfer->box.z, + src, 0, &sbox); } static unsigned si_texture_get_offset(struct si_screen *sscreen, - struct si_texture *tex, unsigned level, - const struct pipe_box *box, - unsigned *stride, - unsigned *layer_stride) + struct si_texture *tex, unsigned level, + const struct pipe_box *box, + unsigned *stride, + unsigned *layer_stride) { - if (sscreen->info.chip_class >= GFX9) { - *stride = tex->surface.u.gfx9.surf_pitch * tex->surface.bpe; - *layer_stride = tex->surface.u.gfx9.surf_slice_size; + if (sscreen->info.chip_class >= GFX9) { + *stride = tex->surface.u.gfx9.surf_pitch * tex->surface.bpe; + *layer_stride = tex->surface.u.gfx9.surf_slice_size; - if (!box) - return 0; + if (!box) + return 0; - /* Each texture is an array of slices. Each slice is an array - * of mipmap levels. */ - return tex->surface.u.gfx9.surf_offset + - box->z * tex->surface.u.gfx9.surf_slice_size + - tex->surface.u.gfx9.offset[level] + - (box->y / tex->surface.blk_h * - tex->surface.u.gfx9.surf_pitch + - box->x / tex->surface.blk_w) * tex->surface.bpe; - } else { - *stride = tex->surface.u.legacy.level[level].nblk_x * - tex->surface.bpe; - assert((uint64_t)tex->surface.u.legacy.level[level].slice_size_dw * 4 <= UINT_MAX); - *layer_stride = (uint64_t)tex->surface.u.legacy.level[level].slice_size_dw * 4; + /* Each texture is an array of slices. Each slice is an array + * of mipmap levels. */ + return tex->surface.u.gfx9.surf_offset + + box->z * tex->surface.u.gfx9.surf_slice_size + + tex->surface.u.gfx9.offset[level] + + (box->y / tex->surface.blk_h * + tex->surface.u.gfx9.surf_pitch + + box->x / tex->surface.blk_w) * tex->surface.bpe; + } else { + *stride = tex->surface.u.legacy.level[level].nblk_x * + tex->surface.bpe; + assert((uint64_t)tex->surface.u.legacy.level[level].slice_size_dw * 4 <= UINT_MAX); + *layer_stride = (uint64_t)tex->surface.u.legacy.level[level].slice_size_dw * 4; - if (!box) - return tex->surface.u.legacy.level[level].offset; + if (!box) + return tex->surface.u.legacy.level[level].offset; - /* Each texture is an array of mipmap levels. Each level is - * an array of slices. */ - return tex->surface.u.legacy.level[level].offset + - box->z * (uint64_t)tex->surface.u.legacy.level[level].slice_size_dw * 4 + - (box->y / tex->surface.blk_h * - tex->surface.u.legacy.level[level].nblk_x + - box->x / tex->surface.blk_w) * tex->surface.bpe; - } + /* Each texture is an array of mipmap levels. Each level is + * an array of slices. */ + return tex->surface.u.legacy.level[level].offset + + box->z * (uint64_t)tex->surface.u.legacy.level[level].slice_size_dw * 4 + + (box->y / tex->surface.blk_h * + tex->surface.u.legacy.level[level].nblk_x + + box->x / tex->surface.blk_w) * tex->surface.bpe; + } } static int si_init_surface(struct si_screen *sscreen, - struct radeon_surf *surface, - const struct pipe_resource *ptex, - enum radeon_surf_mode array_mode, - unsigned pitch_in_bytes_override, - bool is_imported, - bool is_scanout, - bool is_flushed_depth, - bool tc_compatible_htile) + struct radeon_surf *surface, + const struct pipe_resource *ptex, + enum radeon_surf_mode array_mode, + unsigned pitch_in_bytes_override, + bool is_imported, + bool is_scanout, + bool is_flushed_depth, + bool tc_compatible_htile) { - const struct util_format_description *desc = - util_format_description(ptex->format); - bool is_depth, is_stencil; - int r; - unsigned bpe, flags = 0; + const struct util_format_description *desc = + util_format_description(ptex->format); + bool is_depth, is_stencil; + int r; + unsigned bpe, flags = 0; - is_depth = util_format_has_depth(desc); - is_stencil = util_format_has_stencil(desc); + is_depth = util_format_has_depth(desc); + is_stencil = util_format_has_stencil(desc); - if (!is_flushed_depth && - ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) { - bpe = 4; /* stencil is allocated separately */ - } else { - bpe = util_format_get_blocksize(ptex->format); - assert(util_is_power_of_two_or_zero(bpe)); - } + if (!is_flushed_depth && + ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) { + bpe = 4; /* stencil is allocated separately */ + } else { + bpe = util_format_get_blocksize(ptex->format); + assert(util_is_power_of_two_or_zero(bpe)); + } - if (!is_flushed_depth && is_depth) { - flags |= RADEON_SURF_ZBUFFER; + if (!is_flushed_depth && is_depth) { + flags |= RADEON_SURF_ZBUFFER; - if (sscreen->debug_flags & DBG(NO_HYPERZ)) { - flags |= RADEON_SURF_NO_HTILE; - } else if (tc_compatible_htile && - (sscreen->info.chip_class >= GFX9 || - array_mode == RADEON_SURF_MODE_2D)) { - /* TC-compatible HTILE only supports Z32_FLOAT. - * GFX9 also supports Z16_UNORM. - * On GFX8, promote Z16 to Z32. DB->CB copies will convert - * the format for transfers. - */ - if (sscreen->info.chip_class == GFX8) - bpe = 4; + if (sscreen->debug_flags & DBG(NO_HYPERZ)) { + flags |= RADEON_SURF_NO_HTILE; + } else if (tc_compatible_htile && + (sscreen->info.chip_class >= GFX9 || + array_mode == RADEON_SURF_MODE_2D)) { + /* TC-compatible HTILE only supports Z32_FLOAT. + * GFX9 also supports Z16_UNORM. + * On GFX8, promote Z16 to Z32. DB->CB copies will convert + * the format for transfers. + */ + if (sscreen->info.chip_class == GFX8) + bpe = 4; - flags |= RADEON_SURF_TC_COMPATIBLE_HTILE; - } + flags |= RADEON_SURF_TC_COMPATIBLE_HTILE; + } - if (is_stencil) - flags |= RADEON_SURF_SBUFFER; - } + if (is_stencil) + flags |= RADEON_SURF_SBUFFER; + } - if (sscreen->info.chip_class >= GFX8 && - (ptex->flags & SI_RESOURCE_FLAG_DISABLE_DCC || - ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT || - (ptex->nr_samples >= 2 && !sscreen->dcc_msaa_allowed))) - flags |= RADEON_SURF_DISABLE_DCC; + if (sscreen->info.chip_class >= GFX8 && + (ptex->flags & SI_RESOURCE_FLAG_DISABLE_DCC || + ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT || + (ptex->nr_samples >= 2 && !sscreen->dcc_msaa_allowed))) + flags |= RADEON_SURF_DISABLE_DCC; - /* Stoney: 128bpp MSAA textures randomly fail piglit tests with DCC. */ - if (sscreen->info.family == CHIP_STONEY && - bpe == 16 && ptex->nr_samples >= 2) - flags |= RADEON_SURF_DISABLE_DCC; + /* Stoney: 128bpp MSAA textures randomly fail piglit tests with DCC. */ + if (sscreen->info.family == CHIP_STONEY && + bpe == 16 && ptex->nr_samples >= 2) + flags |= RADEON_SURF_DISABLE_DCC; - /* GFX8: DCC clear for 4x and 8x MSAA array textures unimplemented. */ - if (sscreen->info.chip_class == GFX8 && - ptex->nr_storage_samples >= 4 && - ptex->array_size > 1) - flags |= RADEON_SURF_DISABLE_DCC; + /* GFX8: DCC clear for 4x and 8x MSAA array textures unimplemented. */ + if (sscreen->info.chip_class == GFX8 && + ptex->nr_storage_samples >= 4 && + ptex->array_size > 1) + flags |= RADEON_SURF_DISABLE_DCC; - /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */ - if (sscreen->info.chip_class == GFX9 && - (ptex->nr_storage_samples >= 4 || - (sscreen->info.family == CHIP_RAVEN && - ptex->nr_storage_samples >= 2 && bpe < 4))) - flags |= RADEON_SURF_DISABLE_DCC; + /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */ + if (sscreen->info.chip_class == GFX9 && + (ptex->nr_storage_samples >= 4 || + (sscreen->info.family == CHIP_RAVEN && + ptex->nr_storage_samples >= 2 && bpe < 4))) + flags |= RADEON_SURF_DISABLE_DCC; - /* TODO: GFX10: DCC causes corruption with MSAA. */ - if (sscreen->info.chip_class >= GFX10 && - ptex->nr_storage_samples >= 2) - flags |= RADEON_SURF_DISABLE_DCC; + /* TODO: GFX10: DCC causes corruption with MSAA. */ + if (sscreen->info.chip_class >= GFX10 && + ptex->nr_storage_samples >= 2) + flags |= RADEON_SURF_DISABLE_DCC; - /* Shared textures must always set up DCC. - * If it's not present, it will be disabled by - * si_get_opaque_metadata later. - */ - if (!is_imported && (sscreen->debug_flags & DBG(NO_DCC))) - flags |= RADEON_SURF_DISABLE_DCC; + /* Shared textures must always set up DCC. + * If it's not present, it will be disabled by + * si_get_opaque_metadata later. + */ + if (!is_imported && (sscreen->debug_flags & DBG(NO_DCC))) + flags |= RADEON_SURF_DISABLE_DCC; - if (is_scanout) { - /* This should catch bugs in gallium users setting incorrect flags. */ - assert(ptex->nr_samples <= 1 && - ptex->array_size == 1 && - ptex->depth0 == 1 && - ptex->last_level == 0 && - !(flags & RADEON_SURF_Z_OR_SBUFFER)); + if (is_scanout) { + /* This should catch bugs in gallium users setting incorrect flags. */ + assert(ptex->nr_samples <= 1 && + ptex->array_size == 1 && + ptex->depth0 == 1 && + ptex->last_level == 0 && + !(flags & RADEON_SURF_Z_OR_SBUFFER)); - flags |= RADEON_SURF_SCANOUT; - } + flags |= RADEON_SURF_SCANOUT; + } - if (ptex->bind & PIPE_BIND_SHARED) - flags |= RADEON_SURF_SHAREABLE; - if (is_imported) - flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE; - if (!(ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING)) - flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE; - if (sscreen->debug_flags & DBG(NO_FMASK)) - flags |= RADEON_SURF_NO_FMASK; + if (ptex->bind & PIPE_BIND_SHARED) + flags |= RADEON_SURF_SHAREABLE; + if (is_imported) + flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE; + if (!(ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING)) + flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE; + if (sscreen->debug_flags & DBG(NO_FMASK)) + flags |= RADEON_SURF_NO_FMASK; - if (sscreen->info.chip_class == GFX9 && - (ptex->flags & SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE)) { - flags |= RADEON_SURF_FORCE_MICRO_TILE_MODE; - surface->micro_tile_mode = SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(ptex->flags); - } + if (sscreen->info.chip_class == GFX9 && + (ptex->flags & SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE)) { + flags |= RADEON_SURF_FORCE_MICRO_TILE_MODE; + surface->micro_tile_mode = SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(ptex->flags); + } - if (sscreen->info.chip_class >= GFX10 && - (ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING)) { - flags |= RADEON_SURF_FORCE_SWIZZLE_MODE; - surface->u.gfx9.surf.swizzle_mode = ADDR_SW_64KB_R_X; - } + if (sscreen->info.chip_class >= GFX10 && + (ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING)) { + flags |= RADEON_SURF_FORCE_SWIZZLE_MODE; + surface->u.gfx9.surf.swizzle_mode = ADDR_SW_64KB_R_X; + } - r = sscreen->ws->surface_init(sscreen->ws, ptex, flags, bpe, - array_mode, surface); - if (r) { - return r; - } + r = sscreen->ws->surface_init(sscreen->ws, ptex, flags, bpe, + array_mode, surface); + if (r) { + return r; + } - unsigned pitch = pitch_in_bytes_override / bpe; + unsigned pitch = pitch_in_bytes_override / bpe; - if (sscreen->info.chip_class >= GFX9) { - if (pitch) { - surface->u.gfx9.surf_pitch = pitch; - if (ptex->last_level == 0) - surface->u.gfx9.surf.epitch = pitch - 1; - surface->u.gfx9.surf_slice_size = - (uint64_t)pitch * surface->u.gfx9.surf_height * bpe; - } - } else { - if (pitch) { - surface->u.legacy.level[0].nblk_x = pitch; - surface->u.legacy.level[0].slice_size_dw = - ((uint64_t)pitch * surface->u.legacy.level[0].nblk_y * bpe) / 4; - } - } - return 0; + if (sscreen->info.chip_class >= GFX9) { + if (pitch) { + surface->u.gfx9.surf_pitch = pitch; + if (ptex->last_level == 0) + surface->u.gfx9.surf.epitch = pitch - 1; + surface->u.gfx9.surf_slice_size = + (uint64_t)pitch * surface->u.gfx9.surf_height * bpe; + } + } else { + if (pitch) { + surface->u.legacy.level[0].nblk_x = pitch; + surface->u.legacy.level[0].slice_size_dw = + ((uint64_t)pitch * surface->u.legacy.level[0].nblk_y * bpe) / 4; + } + } + return 0; } static void si_get_display_metadata(struct si_screen *sscreen, - struct radeon_surf *surf, - struct radeon_bo_metadata *metadata, - enum radeon_surf_mode *array_mode, - bool *is_scanout) + struct radeon_surf *surf, + struct radeon_bo_metadata *metadata, + enum radeon_surf_mode *array_mode, + bool *is_scanout) { - if (sscreen->info.chip_class >= GFX9) { - if (metadata->u.gfx9.swizzle_mode > 0) - *array_mode = RADEON_SURF_MODE_2D; - else - *array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED; + if (sscreen->info.chip_class >= GFX9) { + if (metadata->u.gfx9.swizzle_mode > 0) + *array_mode = RADEON_SURF_MODE_2D; + else + *array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED; - surf->u.gfx9.surf.swizzle_mode = metadata->u.gfx9.swizzle_mode; - *is_scanout = metadata->u.gfx9.scanout; + surf->u.gfx9.surf.swizzle_mode = metadata->u.gfx9.swizzle_mode; + *is_scanout = metadata->u.gfx9.scanout; - if (metadata->u.gfx9.dcc_offset_256B) { - surf->u.gfx9.display_dcc_pitch_max = metadata->u.gfx9.dcc_pitch_max; - assert(metadata->u.gfx9.dcc_independent_64B == 1); - } - } else { - surf->u.legacy.pipe_config = metadata->u.legacy.pipe_config; - surf->u.legacy.bankw = metadata->u.legacy.bankw; - surf->u.legacy.bankh = metadata->u.legacy.bankh; - surf->u.legacy.tile_split = metadata->u.legacy.tile_split; - surf->u.legacy.mtilea = metadata->u.legacy.mtilea; - surf->u.legacy.num_banks = metadata->u.legacy.num_banks; + if (metadata->u.gfx9.dcc_offset_256B) { + surf->u.gfx9.display_dcc_pitch_max = metadata->u.gfx9.dcc_pitch_max; + assert(metadata->u.gfx9.dcc_independent_64B == 1); + } + } else { + surf->u.legacy.pipe_config = metadata->u.legacy.pipe_config; + surf->u.legacy.bankw = metadata->u.legacy.bankw; + surf->u.legacy.bankh = metadata->u.legacy.bankh; + surf->u.legacy.tile_split = metadata->u.legacy.tile_split; + surf->u.legacy.mtilea = metadata->u.legacy.mtilea; + surf->u.legacy.num_banks = metadata->u.legacy.num_banks; - if (metadata->u.legacy.macrotile == RADEON_LAYOUT_TILED) - *array_mode = RADEON_SURF_MODE_2D; - else if (metadata->u.legacy.microtile == RADEON_LAYOUT_TILED) - *array_mode = RADEON_SURF_MODE_1D; - else - *array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED; + if (metadata->u.legacy.macrotile == RADEON_LAYOUT_TILED) + *array_mode = RADEON_SURF_MODE_2D; + else if (metadata->u.legacy.microtile == RADEON_LAYOUT_TILED) + *array_mode = RADEON_SURF_MODE_1D; + else + *array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED; - *is_scanout = metadata->u.legacy.scanout; - } + *is_scanout = metadata->u.legacy.scanout; + } } void si_eliminate_fast_color_clear(struct si_context *sctx, - struct si_texture *tex) + struct si_texture *tex) { - struct si_screen *sscreen = sctx->screen; - struct pipe_context *ctx = &sctx->b; + struct si_screen *sscreen = sctx->screen; + struct pipe_context *ctx = &sctx->b; - if (ctx == sscreen->aux_context) - simple_mtx_lock(&sscreen->aux_context_lock); + if (ctx == sscreen->aux_context) + simple_mtx_lock(&sscreen->aux_context_lock); - unsigned n = sctx->num_decompress_calls; - ctx->flush_resource(ctx, &tex->buffer.b.b); + unsigned n = sctx->num_decompress_calls; + ctx->flush_resource(ctx, &tex->buffer.b.b); - /* Flush only if any fast clear elimination took place. */ - if (n != sctx->num_decompress_calls) - ctx->flush(ctx, NULL, 0); + /* Flush only if any fast clear elimination took place. */ + if (n != sctx->num_decompress_calls) + ctx->flush(ctx, NULL, 0); - if (ctx == sscreen->aux_context) - simple_mtx_unlock(&sscreen->aux_context_lock); + if (ctx == sscreen->aux_context) + simple_mtx_unlock(&sscreen->aux_context_lock); } void si_texture_discard_cmask(struct si_screen *sscreen, - struct si_texture *tex) + struct si_texture *tex) { - if (!tex->cmask_buffer) - return; + if (!tex->cmask_buffer) + return; - assert(tex->buffer.b.b.nr_samples <= 1); + assert(tex->buffer.b.b.nr_samples <= 1); - /* Disable CMASK. */ - tex->cmask_base_address_reg = tex->buffer.gpu_address >> 8; - tex->dirty_level_mask = 0; + /* Disable CMASK. */ + tex->cmask_base_address_reg = tex->buffer.gpu_address >> 8; + tex->dirty_level_mask = 0; - tex->cb_color_info &= ~S_028C70_FAST_CLEAR(1); + tex->cb_color_info &= ~S_028C70_FAST_CLEAR(1); - if (tex->cmask_buffer != &tex->buffer) - si_resource_reference(&tex->cmask_buffer, NULL); + if (tex->cmask_buffer != &tex->buffer) + si_resource_reference(&tex->cmask_buffer, NULL); - tex->cmask_buffer = NULL; + tex->cmask_buffer = NULL; - /* Notify all contexts about the change. */ - p_atomic_inc(&sscreen->dirty_tex_counter); - p_atomic_inc(&sscreen->compressed_colortex_counter); + /* Notify all contexts about the change. */ + p_atomic_inc(&sscreen->dirty_tex_counter); + p_atomic_inc(&sscreen->compressed_colortex_counter); } static bool si_can_disable_dcc(struct si_texture *tex) { - /* We can't disable DCC if it can be written by another process. */ - return tex->surface.dcc_offset && - (!tex->buffer.b.is_shared || - !(tex->buffer.external_usage & PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE)); + /* We can't disable DCC if it can be written by another process. */ + return tex->surface.dcc_offset && + (!tex->buffer.b.is_shared || + !(tex->buffer.external_usage & PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE)); } static void si_texture_zero_dcc_fields(struct si_texture *tex) { - tex->surface.dcc_offset = 0; - tex->surface.display_dcc_offset = 0; - tex->surface.dcc_retile_map_offset = 0; + tex->surface.dcc_offset = 0; + tex->surface.display_dcc_offset = 0; + tex->surface.dcc_retile_map_offset = 0; } static bool si_texture_discard_dcc(struct si_screen *sscreen, - struct si_texture *tex) + struct si_texture *tex) { - if (!si_can_disable_dcc(tex)) - return false; + if (!si_can_disable_dcc(tex)) + return false; - assert(tex->dcc_separate_buffer == NULL); + assert(tex->dcc_separate_buffer == NULL); - /* Disable DCC. */ - si_texture_zero_dcc_fields(tex); + /* Disable DCC. */ + si_texture_zero_dcc_fields(tex); - /* Notify all contexts about the change. */ - p_atomic_inc(&sscreen->dirty_tex_counter); - return true; + /* Notify all contexts about the change. */ + p_atomic_inc(&sscreen->dirty_tex_counter); + return true; } /** @@ -503,1403 +503,1403 @@ static bool si_texture_discard_dcc(struct si_screen *sscreen, * if you don't. */ bool si_texture_disable_dcc(struct si_context *sctx, - struct si_texture *tex) + struct si_texture *tex) { - struct si_screen *sscreen = sctx->screen; + struct si_screen *sscreen = sctx->screen; - if (!sctx->has_graphics) - return si_texture_discard_dcc(sscreen, tex); + if (!sctx->has_graphics) + return si_texture_discard_dcc(sscreen, tex); - if (!si_can_disable_dcc(tex)) - return false; + if (!si_can_disable_dcc(tex)) + return false; - if (&sctx->b == sscreen->aux_context) - simple_mtx_lock(&sscreen->aux_context_lock); + if (&sctx->b == sscreen->aux_context) + simple_mtx_lock(&sscreen->aux_context_lock); - /* Decompress DCC. */ - si_decompress_dcc(sctx, tex); - sctx->b.flush(&sctx->b, NULL, 0); + /* Decompress DCC. */ + si_decompress_dcc(sctx, tex); + sctx->b.flush(&sctx->b, NULL, 0); - if (&sctx->b == sscreen->aux_context) - simple_mtx_unlock(&sscreen->aux_context_lock); + if (&sctx->b == sscreen->aux_context) + simple_mtx_unlock(&sscreen->aux_context_lock); - return si_texture_discard_dcc(sscreen, tex); + return si_texture_discard_dcc(sscreen, tex); } static void si_reallocate_texture_inplace(struct si_context *sctx, - struct si_texture *tex, - unsigned new_bind_flag, - bool invalidate_storage) + struct si_texture *tex, + unsigned new_bind_flag, + bool invalidate_storage) { - struct pipe_screen *screen = sctx->b.screen; - struct si_texture *new_tex; - struct pipe_resource templ = tex->buffer.b.b; - unsigned i; + struct pipe_screen *screen = sctx->b.screen; + struct si_texture *new_tex; + struct pipe_resource templ = tex->buffer.b.b; + unsigned i; - templ.bind |= new_bind_flag; + templ.bind |= new_bind_flag; - if (tex->buffer.b.is_shared || tex->num_planes > 1) - return; + if (tex->buffer.b.is_shared || tex->num_planes > 1) + return; - if (new_bind_flag == PIPE_BIND_LINEAR) { - if (tex->surface.is_linear) - return; + if (new_bind_flag == PIPE_BIND_LINEAR) { + if (tex->surface.is_linear) + return; - /* This fails with MSAA, depth, and compressed textures. */ - if (si_choose_tiling(sctx->screen, &templ, false) != - RADEON_SURF_MODE_LINEAR_ALIGNED) - return; - } + /* This fails with MSAA, depth, and compressed textures. */ + if (si_choose_tiling(sctx->screen, &templ, false) != + RADEON_SURF_MODE_LINEAR_ALIGNED) + return; + } - new_tex = (struct si_texture*)screen->resource_create(screen, &templ); - if (!new_tex) - return; + new_tex = (struct si_texture*)screen->resource_create(screen, &templ); + if (!new_tex) + return; - /* Copy the pixels to the new texture. */ - if (!invalidate_storage) { - for (i = 0; i <= templ.last_level; i++) { - struct pipe_box box; + /* Copy the pixels to the new texture. */ + if (!invalidate_storage) { + for (i = 0; i <= templ.last_level; i++) { + struct pipe_box box; - u_box_3d(0, 0, 0, - u_minify(templ.width0, i), u_minify(templ.height0, i), - util_num_layers(&templ, i), &box); + u_box_3d(0, 0, 0, + u_minify(templ.width0, i), u_minify(templ.height0, i), + util_num_layers(&templ, i), &box); - sctx->dma_copy(&sctx->b, &new_tex->buffer.b.b, i, 0, 0, 0, - &tex->buffer.b.b, i, &box); - } - } + sctx->dma_copy(&sctx->b, &new_tex->buffer.b.b, i, 0, 0, 0, + &tex->buffer.b.b, i, &box); + } + } - if (new_bind_flag == PIPE_BIND_LINEAR) { - si_texture_discard_cmask(sctx->screen, tex); - si_texture_discard_dcc(sctx->screen, tex); - } + if (new_bind_flag == PIPE_BIND_LINEAR) { + si_texture_discard_cmask(sctx->screen, tex); + si_texture_discard_dcc(sctx->screen, tex); + } - /* Replace the structure fields of tex. */ - tex->buffer.b.b.bind = templ.bind; - pb_reference(&tex->buffer.buf, new_tex->buffer.buf); - tex->buffer.gpu_address = new_tex->buffer.gpu_address; - tex->buffer.vram_usage = new_tex->buffer.vram_usage; - tex->buffer.gart_usage = new_tex->buffer.gart_usage; - tex->buffer.bo_size = new_tex->buffer.bo_size; - tex->buffer.bo_alignment = new_tex->buffer.bo_alignment; - tex->buffer.domains = new_tex->buffer.domains; - tex->buffer.flags = new_tex->buffer.flags; + /* Replace the structure fields of tex. */ + tex->buffer.b.b.bind = templ.bind; + pb_reference(&tex->buffer.buf, new_tex->buffer.buf); + tex->buffer.gpu_address = new_tex->buffer.gpu_address; + tex->buffer.vram_usage = new_tex->buffer.vram_usage; + tex->buffer.gart_usage = new_tex->buffer.gart_usage; + tex->buffer.bo_size = new_tex->buffer.bo_size; + tex->buffer.bo_alignment = new_tex->buffer.bo_alignment; + tex->buffer.domains = new_tex->buffer.domains; + tex->buffer.flags = new_tex->buffer.flags; - tex->surface = new_tex->surface; - si_texture_reference(&tex->flushed_depth_texture, - new_tex->flushed_depth_texture); + tex->surface = new_tex->surface; + si_texture_reference(&tex->flushed_depth_texture, + new_tex->flushed_depth_texture); - tex->surface.fmask_offset = new_tex->surface.fmask_offset; - tex->surface.cmask_offset = new_tex->surface.cmask_offset; - tex->cmask_base_address_reg = new_tex->cmask_base_address_reg; + tex->surface.fmask_offset = new_tex->surface.fmask_offset; + tex->surface.cmask_offset = new_tex->surface.cmask_offset; + tex->cmask_base_address_reg = new_tex->cmask_base_address_reg; - if (tex->cmask_buffer == &tex->buffer) - tex->cmask_buffer = NULL; - else - si_resource_reference(&tex->cmask_buffer, NULL); + if (tex->cmask_buffer == &tex->buffer) + tex->cmask_buffer = NULL; + else + si_resource_reference(&tex->cmask_buffer, NULL); - if (new_tex->cmask_buffer == &new_tex->buffer) - tex->cmask_buffer = &tex->buffer; - else - si_resource_reference(&tex->cmask_buffer, new_tex->cmask_buffer); + if (new_tex->cmask_buffer == &new_tex->buffer) + tex->cmask_buffer = &tex->buffer; + else + si_resource_reference(&tex->cmask_buffer, new_tex->cmask_buffer); - tex->surface.dcc_offset = new_tex->surface.dcc_offset; - tex->cb_color_info = new_tex->cb_color_info; - memcpy(tex->color_clear_value, new_tex->color_clear_value, - sizeof(tex->color_clear_value)); - tex->last_msaa_resolve_target_micro_mode = new_tex->last_msaa_resolve_target_micro_mode; + tex->surface.dcc_offset = new_tex->surface.dcc_offset; + tex->cb_color_info = new_tex->cb_color_info; + memcpy(tex->color_clear_value, new_tex->color_clear_value, + sizeof(tex->color_clear_value)); + tex->last_msaa_resolve_target_micro_mode = new_tex->last_msaa_resolve_target_micro_mode; - tex->surface.htile_offset = new_tex->surface.htile_offset; - tex->depth_clear_value = new_tex->depth_clear_value; - tex->dirty_level_mask = new_tex->dirty_level_mask; - tex->stencil_dirty_level_mask = new_tex->stencil_dirty_level_mask; - tex->db_render_format = new_tex->db_render_format; - tex->stencil_clear_value = new_tex->stencil_clear_value; - tex->tc_compatible_htile = new_tex->tc_compatible_htile; - tex->depth_cleared = new_tex->depth_cleared; - tex->stencil_cleared = new_tex->stencil_cleared; - tex->upgraded_depth = new_tex->upgraded_depth; - tex->db_compatible = new_tex->db_compatible; - tex->can_sample_z = new_tex->can_sample_z; - tex->can_sample_s = new_tex->can_sample_s; + tex->surface.htile_offset = new_tex->surface.htile_offset; + tex->depth_clear_value = new_tex->depth_clear_value; + tex->dirty_level_mask = new_tex->dirty_level_mask; + tex->stencil_dirty_level_mask = new_tex->stencil_dirty_level_mask; + tex->db_render_format = new_tex->db_render_format; + tex->stencil_clear_value = new_tex->stencil_clear_value; + tex->tc_compatible_htile = new_tex->tc_compatible_htile; + tex->depth_cleared = new_tex->depth_cleared; + tex->stencil_cleared = new_tex->stencil_cleared; + tex->upgraded_depth = new_tex->upgraded_depth; + tex->db_compatible = new_tex->db_compatible; + tex->can_sample_z = new_tex->can_sample_z; + tex->can_sample_s = new_tex->can_sample_s; - tex->separate_dcc_dirty = new_tex->separate_dcc_dirty; - tex->displayable_dcc_dirty = new_tex->displayable_dcc_dirty; - tex->dcc_gather_statistics = new_tex->dcc_gather_statistics; - si_resource_reference(&tex->dcc_separate_buffer, - new_tex->dcc_separate_buffer); - si_resource_reference(&tex->last_dcc_separate_buffer, - new_tex->last_dcc_separate_buffer); + tex->separate_dcc_dirty = new_tex->separate_dcc_dirty; + tex->displayable_dcc_dirty = new_tex->displayable_dcc_dirty; + tex->dcc_gather_statistics = new_tex->dcc_gather_statistics; + si_resource_reference(&tex->dcc_separate_buffer, + new_tex->dcc_separate_buffer); + si_resource_reference(&tex->last_dcc_separate_buffer, + new_tex->last_dcc_separate_buffer); - if (new_bind_flag == PIPE_BIND_LINEAR) { - assert(!tex->surface.htile_offset); - assert(!tex->cmask_buffer); - assert(!tex->surface.fmask_size); - assert(!tex->surface.dcc_offset); - assert(!tex->is_depth); - } + if (new_bind_flag == PIPE_BIND_LINEAR) { + assert(!tex->surface.htile_offset); + assert(!tex->cmask_buffer); + assert(!tex->surface.fmask_size); + assert(!tex->surface.dcc_offset); + assert(!tex->is_depth); + } - si_texture_reference(&new_tex, NULL); + si_texture_reference(&new_tex, NULL); - p_atomic_inc(&sctx->screen->dirty_tex_counter); + p_atomic_inc(&sctx->screen->dirty_tex_counter); } static uint32_t si_get_bo_metadata_word1(struct si_screen *sscreen) { - return (ATI_VENDOR_ID << 16) | sscreen->info.pci_id; + return (ATI_VENDOR_ID << 16) | sscreen->info.pci_id; } static void si_set_tex_bo_metadata(struct si_screen *sscreen, - struct si_texture *tex) + struct si_texture *tex) { - struct radeon_surf *surface = &tex->surface; - struct pipe_resource *res = &tex->buffer.b.b; - struct radeon_bo_metadata md; + struct radeon_surf *surface = &tex->surface; + struct pipe_resource *res = &tex->buffer.b.b; + struct radeon_bo_metadata md; - memset(&md, 0, sizeof(md)); + memset(&md, 0, sizeof(md)); - if (sscreen->info.chip_class >= GFX9) { - md.u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode; - md.u.gfx9.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0; + if (sscreen->info.chip_class >= GFX9) { + md.u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode; + md.u.gfx9.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0; - if (tex->surface.dcc_offset && !tex->dcc_separate_buffer) { - uint64_t dcc_offset = - tex->surface.display_dcc_offset ? tex->surface.display_dcc_offset - : tex->surface.dcc_offset; + if (tex->surface.dcc_offset && !tex->dcc_separate_buffer) { + uint64_t dcc_offset = + tex->surface.display_dcc_offset ? tex->surface.display_dcc_offset + : tex->surface.dcc_offset; - assert((dcc_offset >> 8) != 0 && (dcc_offset >> 8) < (1 << 24)); - md.u.gfx9.dcc_offset_256B = dcc_offset >> 8; - md.u.gfx9.dcc_pitch_max = tex->surface.u.gfx9.display_dcc_pitch_max; - md.u.gfx9.dcc_independent_64B = 1; - } - } else { - md.u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ? - RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR; - md.u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ? - RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR; - md.u.legacy.pipe_config = surface->u.legacy.pipe_config; - md.u.legacy.bankw = surface->u.legacy.bankw; - md.u.legacy.bankh = surface->u.legacy.bankh; - md.u.legacy.tile_split = surface->u.legacy.tile_split; - md.u.legacy.mtilea = surface->u.legacy.mtilea; - md.u.legacy.num_banks = surface->u.legacy.num_banks; - md.u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe; - md.u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0; - } + assert((dcc_offset >> 8) != 0 && (dcc_offset >> 8) < (1 << 24)); + md.u.gfx9.dcc_offset_256B = dcc_offset >> 8; + md.u.gfx9.dcc_pitch_max = tex->surface.u.gfx9.display_dcc_pitch_max; + md.u.gfx9.dcc_independent_64B = 1; + } + } else { + md.u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ? + RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR; + md.u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ? + RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR; + md.u.legacy.pipe_config = surface->u.legacy.pipe_config; + md.u.legacy.bankw = surface->u.legacy.bankw; + md.u.legacy.bankh = surface->u.legacy.bankh; + md.u.legacy.tile_split = surface->u.legacy.tile_split; + md.u.legacy.mtilea = surface->u.legacy.mtilea; + md.u.legacy.num_banks = surface->u.legacy.num_banks; + md.u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe; + md.u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0; + } - assert(tex->dcc_separate_buffer == NULL); - assert(tex->surface.fmask_size == 0); + assert(tex->dcc_separate_buffer == NULL); + assert(tex->surface.fmask_size == 0); - /* Metadata image format format version 1: - * [0] = 1 (metadata format identifier) - * [1] = (VENDOR_ID << 16) | PCI_ID - * [2:9] = image descriptor for the whole resource - * [2] is always 0, because the base address is cleared - * [9] is the DCC offset bits [39:8] from the beginning of - * the buffer - * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level - */ + /* Metadata image format format version 1: + * [0] = 1 (metadata format identifier) + * [1] = (VENDOR_ID << 16) | PCI_ID + * [2:9] = image descriptor for the whole resource + * [2] is always 0, because the base address is cleared + * [9] is the DCC offset bits [39:8] from the beginning of + * the buffer + * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level + */ - md.metadata[0] = 1; /* metadata image format version 1 */ + md.metadata[0] = 1; /* metadata image format version 1 */ - /* TILE_MODE_INDEX is ambiguous without a PCI ID. */ - md.metadata[1] = si_get_bo_metadata_word1(sscreen); + /* TILE_MODE_INDEX is ambiguous without a PCI ID. */ + md.metadata[1] = si_get_bo_metadata_word1(sscreen); - static const unsigned char swizzle[] = { - PIPE_SWIZZLE_X, - PIPE_SWIZZLE_Y, - PIPE_SWIZZLE_Z, - PIPE_SWIZZLE_W - }; - bool is_array = util_texture_is_array(res->target); - uint32_t desc[8]; + static const unsigned char swizzle[] = { + PIPE_SWIZZLE_X, + PIPE_SWIZZLE_Y, + PIPE_SWIZZLE_Z, + PIPE_SWIZZLE_W + }; + bool is_array = util_texture_is_array(res->target); + uint32_t desc[8]; - sscreen->make_texture_descriptor(sscreen, tex, true, - res->target, res->format, - swizzle, 0, res->last_level, 0, - is_array ? res->array_size - 1 : 0, - res->width0, res->height0, res->depth0, - desc, NULL); + sscreen->make_texture_descriptor(sscreen, tex, true, + res->target, res->format, + swizzle, 0, res->last_level, 0, + is_array ? res->array_size - 1 : 0, + res->width0, res->height0, res->depth0, + desc, NULL); - si_set_mutable_tex_desc_fields(sscreen, tex, &tex->surface.u.legacy.level[0], - 0, 0, tex->surface.blk_w, false, desc); + si_set_mutable_tex_desc_fields(sscreen, tex, &tex->surface.u.legacy.level[0], + 0, 0, tex->surface.blk_w, false, desc); - /* Clear the base address and set the relative DCC offset. */ - desc[0] = 0; - desc[1] &= C_008F14_BASE_ADDRESS_HI; + /* Clear the base address and set the relative DCC offset. */ + desc[0] = 0; + desc[1] &= C_008F14_BASE_ADDRESS_HI; - switch (sscreen->info.chip_class) { - case GFX6: - case GFX7: - break; - case GFX8: - desc[7] = tex->surface.dcc_offset >> 8; - break; - case GFX9: - desc[7] = tex->surface.dcc_offset >> 8; - desc[5] &= C_008F24_META_DATA_ADDRESS; - desc[5] |= S_008F24_META_DATA_ADDRESS(tex->surface.dcc_offset >> 40); - break; - case GFX10: - desc[6] &= C_00A018_META_DATA_ADDRESS_LO; - desc[6] |= S_00A018_META_DATA_ADDRESS_LO(tex->surface.dcc_offset >> 8); - desc[7] = tex->surface.dcc_offset >> 16; - break; - default: - assert(0); - } + switch (sscreen->info.chip_class) { + case GFX6: + case GFX7: + break; + case GFX8: + desc[7] = tex->surface.dcc_offset >> 8; + break; + case GFX9: + desc[7] = tex->surface.dcc_offset >> 8; + desc[5] &= C_008F24_META_DATA_ADDRESS; + desc[5] |= S_008F24_META_DATA_ADDRESS(tex->surface.dcc_offset >> 40); + break; + case GFX10: + desc[6] &= C_00A018_META_DATA_ADDRESS_LO; + desc[6] |= S_00A018_META_DATA_ADDRESS_LO(tex->surface.dcc_offset >> 8); + desc[7] = tex->surface.dcc_offset >> 16; + break; + default: + assert(0); + } - /* Dwords [2:9] contain the image descriptor. */ - memcpy(&md.metadata[2], desc, sizeof(desc)); - md.size_metadata = 10 * 4; + /* Dwords [2:9] contain the image descriptor. */ + memcpy(&md.metadata[2], desc, sizeof(desc)); + md.size_metadata = 10 * 4; - /* Dwords [10:..] contain the mipmap level offsets. */ - if (sscreen->info.chip_class <= GFX8) { - for (unsigned i = 0; i <= res->last_level; i++) - md.metadata[10+i] = tex->surface.u.legacy.level[i].offset >> 8; + /* Dwords [10:..] contain the mipmap level offsets. */ + if (sscreen->info.chip_class <= GFX8) { + for (unsigned i = 0; i <= res->last_level; i++) + md.metadata[10+i] = tex->surface.u.legacy.level[i].offset >> 8; - md.size_metadata += (1 + res->last_level) * 4; - } + md.size_metadata += (1 + res->last_level) * 4; + } - sscreen->ws->buffer_set_metadata(tex->buffer.buf, &md); + sscreen->ws->buffer_set_metadata(tex->buffer.buf, &md); } static bool si_read_tex_bo_metadata(struct si_screen *sscreen, - struct si_texture *tex, - uint64_t offset, - struct radeon_bo_metadata *md) + struct si_texture *tex, + uint64_t offset, + struct radeon_bo_metadata *md) { - uint32_t *desc = &md->metadata[2]; + uint32_t *desc = &md->metadata[2]; - if (offset || /* Non-zero planes ignore metadata. */ - md->size_metadata < 10 * 4 || /* at least 2(header) + 8(desc) dwords */ - md->metadata[0] == 0 || /* invalid version number */ - md->metadata[1] != si_get_bo_metadata_word1(sscreen)) /* invalid PCI ID */ { - /* Disable DCC because it might not be enabled. */ - si_texture_zero_dcc_fields(tex); + if (offset || /* Non-zero planes ignore metadata. */ + md->size_metadata < 10 * 4 || /* at least 2(header) + 8(desc) dwords */ + md->metadata[0] == 0 || /* invalid version number */ + md->metadata[1] != si_get_bo_metadata_word1(sscreen)) /* invalid PCI ID */ { + /* Disable DCC because it might not be enabled. */ + si_texture_zero_dcc_fields(tex); - /* Don't report an error if the texture comes from an incompatible driver, - * but this might not work. - */ - return true; - } + /* Don't report an error if the texture comes from an incompatible driver, + * but this might not work. + */ + return true; + } - /* Validate that sample counts and the number of mipmap levels match. */ - unsigned last_level = G_008F1C_LAST_LEVEL(desc[3]); - unsigned type = G_008F1C_TYPE(desc[3]); + /* Validate that sample counts and the number of mipmap levels match. */ + unsigned last_level = G_008F1C_LAST_LEVEL(desc[3]); + unsigned type = G_008F1C_TYPE(desc[3]); - if (type == V_008F1C_SQ_RSRC_IMG_2D_MSAA || - type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) { - unsigned log_samples = - util_logbase2(MAX2(1, tex->buffer.b.b.nr_storage_samples)); + if (type == V_008F1C_SQ_RSRC_IMG_2D_MSAA || + type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) { + unsigned log_samples = + util_logbase2(MAX2(1, tex->buffer.b.b.nr_storage_samples)); - if (last_level != log_samples) { - fprintf(stderr, "radeonsi: invalid MSAA texture import, " - "metadata has log2(samples) = %u, the caller set %u\n", - last_level, log_samples); - return false; - } - } else { - if (last_level != tex->buffer.b.b.last_level) { - fprintf(stderr, "radeonsi: invalid mipmapped texture import, " - "metadata has last_level = %u, the caller set %u\n", - last_level, tex->buffer.b.b.last_level); - return false; - } - } + if (last_level != log_samples) { + fprintf(stderr, "radeonsi: invalid MSAA texture import, " + "metadata has log2(samples) = %u, the caller set %u\n", + last_level, log_samples); + return false; + } + } else { + if (last_level != tex->buffer.b.b.last_level) { + fprintf(stderr, "radeonsi: invalid mipmapped texture import, " + "metadata has last_level = %u, the caller set %u\n", + last_level, tex->buffer.b.b.last_level); + return false; + } + } - if (sscreen->info.chip_class >= GFX8 && - G_008F28_COMPRESSION_EN(desc[6])) { - /* Read DCC information. */ - switch (sscreen->info.chip_class) { - case GFX8: - tex->surface.dcc_offset = (uint64_t)desc[7] << 8; - break; + if (sscreen->info.chip_class >= GFX8 && + G_008F28_COMPRESSION_EN(desc[6])) { + /* Read DCC information. */ + switch (sscreen->info.chip_class) { + case GFX8: + tex->surface.dcc_offset = (uint64_t)desc[7] << 8; + break; - case GFX9: - tex->surface.dcc_offset = - ((uint64_t)desc[7] << 8) | - ((uint64_t)G_008F24_META_DATA_ADDRESS(desc[5]) << 40); - tex->surface.u.gfx9.dcc.pipe_aligned = - G_008F24_META_PIPE_ALIGNED(desc[5]); - tex->surface.u.gfx9.dcc.rb_aligned = - G_008F24_META_RB_ALIGNED(desc[5]); + case GFX9: + tex->surface.dcc_offset = + ((uint64_t)desc[7] << 8) | + ((uint64_t)G_008F24_META_DATA_ADDRESS(desc[5]) << 40); + tex->surface.u.gfx9.dcc.pipe_aligned = + G_008F24_META_PIPE_ALIGNED(desc[5]); + tex->surface.u.gfx9.dcc.rb_aligned = + G_008F24_META_RB_ALIGNED(desc[5]); - /* If DCC is unaligned, this can only be a displayable image. */ - if (!tex->surface.u.gfx9.dcc.pipe_aligned && - !tex->surface.u.gfx9.dcc.rb_aligned) - assert(tex->surface.is_displayable); - break; + /* If DCC is unaligned, this can only be a displayable image. */ + if (!tex->surface.u.gfx9.dcc.pipe_aligned && + !tex->surface.u.gfx9.dcc.rb_aligned) + assert(tex->surface.is_displayable); + break; - case GFX10: - tex->surface.dcc_offset = - ((uint64_t)G_00A018_META_DATA_ADDRESS_LO(desc[6]) << 8) | - ((uint64_t)desc[7] << 16); - tex->surface.u.gfx9.dcc.pipe_aligned = - G_00A018_META_PIPE_ALIGNED(desc[6]); - break; + case GFX10: + tex->surface.dcc_offset = + ((uint64_t)G_00A018_META_DATA_ADDRESS_LO(desc[6]) << 8) | + ((uint64_t)desc[7] << 16); + tex->surface.u.gfx9.dcc.pipe_aligned = + G_00A018_META_PIPE_ALIGNED(desc[6]); + break; - default: - assert(0); - return false; - } - } else { - /* Disable DCC. dcc_offset is always set by texture_from_handle - * and must be cleared here. - */ - si_texture_zero_dcc_fields(tex); - } + default: + assert(0); + return false; + } + } else { + /* Disable DCC. dcc_offset is always set by texture_from_handle + * and must be cleared here. + */ + si_texture_zero_dcc_fields(tex); + } - return true; + return true; } static bool si_has_displayable_dcc(struct si_texture *tex) { - struct si_screen *sscreen = (struct si_screen*)tex->buffer.b.b.screen; + struct si_screen *sscreen = (struct si_screen*)tex->buffer.b.b.screen; - if (sscreen->info.chip_class <= GFX8) - return false; + if (sscreen->info.chip_class <= GFX8) + return false; - /* This needs a cache flush before scanout. - * (it can't be scanned out and rendered to simultaneously) - */ - if (sscreen->info.use_display_dcc_unaligned && - tex->surface.dcc_offset && - !tex->surface.u.gfx9.dcc.pipe_aligned && - !tex->surface.u.gfx9.dcc.rb_aligned) - return true; + /* This needs a cache flush before scanout. + * (it can't be scanned out and rendered to simultaneously) + */ + if (sscreen->info.use_display_dcc_unaligned && + tex->surface.dcc_offset && + !tex->surface.u.gfx9.dcc.pipe_aligned && + !tex->surface.u.gfx9.dcc.rb_aligned) + return true; - /* This needs an explicit flush (flush_resource). */ - if (sscreen->info.use_display_dcc_with_retile_blit && - tex->surface.display_dcc_offset) - return true; + /* This needs an explicit flush (flush_resource). */ + if (sscreen->info.use_display_dcc_with_retile_blit && + tex->surface.display_dcc_offset) + return true; - return false; + return false; } static bool si_resource_get_param(struct pipe_screen *screen, - struct pipe_context *context, - struct pipe_resource *resource, - unsigned plane, - unsigned layer, - enum pipe_resource_param param, - unsigned handle_usage, - uint64_t *value) + struct pipe_context *context, + struct pipe_resource *resource, + unsigned plane, + unsigned layer, + enum pipe_resource_param param, + unsigned handle_usage, + uint64_t *value) { - for (unsigned i = 0; i < plane; i++) - resource = resource->next; + for (unsigned i = 0; i < plane; i++) + resource = resource->next; - struct si_screen *sscreen = (struct si_screen*)screen; - struct si_texture *tex = (struct si_texture*)resource; - struct winsys_handle whandle; + struct si_screen *sscreen = (struct si_screen*)screen; + struct si_texture *tex = (struct si_texture*)resource; + struct winsys_handle whandle; - switch (param) { - case PIPE_RESOURCE_PARAM_NPLANES: - *value = resource->target == PIPE_BUFFER ? 1 : tex->num_planes; - return true; + switch (param) { + case PIPE_RESOURCE_PARAM_NPLANES: + *value = resource->target == PIPE_BUFFER ? 1 : tex->num_planes; + return true; - case PIPE_RESOURCE_PARAM_STRIDE: - if (resource->target == PIPE_BUFFER) - *value = 0; - else if (sscreen->info.chip_class >= GFX9) - *value = tex->surface.u.gfx9.surf_pitch * tex->surface.bpe; - else - *value = tex->surface.u.legacy.level[0].nblk_x * tex->surface.bpe; - return true; + case PIPE_RESOURCE_PARAM_STRIDE: + if (resource->target == PIPE_BUFFER) + *value = 0; + else if (sscreen->info.chip_class >= GFX9) + *value = tex->surface.u.gfx9.surf_pitch * tex->surface.bpe; + else + *value = tex->surface.u.legacy.level[0].nblk_x * tex->surface.bpe; + return true; - case PIPE_RESOURCE_PARAM_OFFSET: - if (resource->target == PIPE_BUFFER) - *value = 0; - else if (sscreen->info.chip_class >= GFX9) - *value = tex->surface.u.gfx9.surf_offset + - layer * tex->surface.u.gfx9.surf_slice_size; - else - *value = tex->surface.u.legacy.level[0].offset + - layer * (uint64_t)tex->surface.u.legacy.level[0].slice_size_dw * 4; - return true; + case PIPE_RESOURCE_PARAM_OFFSET: + if (resource->target == PIPE_BUFFER) + *value = 0; + else if (sscreen->info.chip_class >= GFX9) + *value = tex->surface.u.gfx9.surf_offset + + layer * tex->surface.u.gfx9.surf_slice_size; + else + *value = tex->surface.u.legacy.level[0].offset + + layer * (uint64_t)tex->surface.u.legacy.level[0].slice_size_dw * 4; + return true; - case PIPE_RESOURCE_PARAM_MODIFIER: - *value = DRM_FORMAT_MOD_INVALID; - return true; + case PIPE_RESOURCE_PARAM_MODIFIER: + *value = DRM_FORMAT_MOD_INVALID; + return true; - case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED: - case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS: - case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD: - memset(&whandle, 0, sizeof(whandle)); + case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED: + case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS: + case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD: + memset(&whandle, 0, sizeof(whandle)); - if (param == PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED) - whandle.type = WINSYS_HANDLE_TYPE_SHARED; - else if (param == PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS) - whandle.type = WINSYS_HANDLE_TYPE_KMS; - else if (param == PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD) - whandle.type = WINSYS_HANDLE_TYPE_FD; + if (param == PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED) + whandle.type = WINSYS_HANDLE_TYPE_SHARED; + else if (param == PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS) + whandle.type = WINSYS_HANDLE_TYPE_KMS; + else if (param == PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD) + whandle.type = WINSYS_HANDLE_TYPE_FD; - if (!screen->resource_get_handle(screen, context, resource, - &whandle, handle_usage)) - return false; + if (!screen->resource_get_handle(screen, context, resource, + &whandle, handle_usage)) + return false; - *value = whandle.handle; - return true; - } - return false; + *value = whandle.handle; + return true; + } + return false; } static void si_texture_get_info(struct pipe_screen* screen, - struct pipe_resource *resource, - unsigned *pstride, - unsigned *poffset) + struct pipe_resource *resource, + unsigned *pstride, + unsigned *poffset) { - uint64_t value; + uint64_t value; - if (pstride) { - si_resource_get_param(screen, NULL, resource, 0, 0, - PIPE_RESOURCE_PARAM_STRIDE, 0, &value); - *pstride = value; - } + if (pstride) { + si_resource_get_param(screen, NULL, resource, 0, 0, + PIPE_RESOURCE_PARAM_STRIDE, 0, &value); + *pstride = value; + } - if (poffset) { - si_resource_get_param(screen, NULL, resource, 0, 0, - PIPE_RESOURCE_PARAM_OFFSET, 0, &value); - *poffset = value; - } + if (poffset) { + si_resource_get_param(screen, NULL, resource, 0, 0, + PIPE_RESOURCE_PARAM_OFFSET, 0, &value); + *poffset = value; + } } static bool si_texture_get_handle(struct pipe_screen* screen, - struct pipe_context *ctx, - struct pipe_resource *resource, - struct winsys_handle *whandle, - unsigned usage) + struct pipe_context *ctx, + struct pipe_resource *resource, + struct winsys_handle *whandle, + unsigned usage) { - struct si_screen *sscreen = (struct si_screen*)screen; - struct si_context *sctx; - struct si_resource *res = si_resource(resource); - struct si_texture *tex = (struct si_texture*)resource; - bool update_metadata = false; - unsigned stride, offset, slice_size; - bool flush = false; + struct si_screen *sscreen = (struct si_screen*)screen; + struct si_context *sctx; + struct si_resource *res = si_resource(resource); + struct si_texture *tex = (struct si_texture*)resource; + bool update_metadata = false; + unsigned stride, offset, slice_size; + bool flush = false; - ctx = threaded_context_unwrap_sync(ctx); - sctx = (struct si_context*)(ctx ? ctx : sscreen->aux_context); + ctx = threaded_context_unwrap_sync(ctx); + sctx = (struct si_context*)(ctx ? ctx : sscreen->aux_context); - if (resource->target != PIPE_BUFFER) { - /* Individual planes are chained pipe_resource instances. */ - for (unsigned i = 0; i < whandle->plane; i++) { - resource = resource->next; - res = si_resource(resource); - tex = (struct si_texture*)resource; - } + if (resource->target != PIPE_BUFFER) { + /* Individual planes are chained pipe_resource instances. */ + for (unsigned i = 0; i < whandle->plane; i++) { + resource = resource->next; + res = si_resource(resource); + tex = (struct si_texture*)resource; + } - /* This is not supported now, but it might be required for OpenCL - * interop in the future. - */ - if (resource->nr_samples > 1 || tex->is_depth) - return false; + /* This is not supported now, but it might be required for OpenCL + * interop in the future. + */ + if (resource->nr_samples > 1 || tex->is_depth) + return false; - /* Move a suballocated texture into a non-suballocated allocation. */ - if (sscreen->ws->buffer_is_suballocated(res->buf) || - tex->surface.tile_swizzle || - (tex->buffer.flags & RADEON_FLAG_NO_INTERPROCESS_SHARING && - sscreen->info.has_local_buffers)) { - assert(!res->b.is_shared); - si_reallocate_texture_inplace(sctx, tex, - PIPE_BIND_SHARED, false); - flush = true; - assert(res->b.b.bind & PIPE_BIND_SHARED); - assert(res->flags & RADEON_FLAG_NO_SUBALLOC); - assert(!(res->flags & RADEON_FLAG_NO_INTERPROCESS_SHARING)); - assert(tex->surface.tile_swizzle == 0); - } + /* Move a suballocated texture into a non-suballocated allocation. */ + if (sscreen->ws->buffer_is_suballocated(res->buf) || + tex->surface.tile_swizzle || + (tex->buffer.flags & RADEON_FLAG_NO_INTERPROCESS_SHARING && + sscreen->info.has_local_buffers)) { + assert(!res->b.is_shared); + si_reallocate_texture_inplace(sctx, tex, + PIPE_BIND_SHARED, false); + flush = true; + assert(res->b.b.bind & PIPE_BIND_SHARED); + assert(res->flags & RADEON_FLAG_NO_SUBALLOC); + assert(!(res->flags & RADEON_FLAG_NO_INTERPROCESS_SHARING)); + assert(tex->surface.tile_swizzle == 0); + } - /* Since shader image stores don't support DCC on GFX8, - * disable it for external clients that want write - * access. - */ - if ((usage & PIPE_HANDLE_USAGE_SHADER_WRITE && tex->surface.dcc_offset) || - /* Displayable DCC requires an explicit flush. */ - (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) && - si_has_displayable_dcc(tex))) { - if (si_texture_disable_dcc(sctx, tex)) { - update_metadata = true; - /* si_texture_disable_dcc flushes the context */ - flush = false; - } - } + /* Since shader image stores don't support DCC on GFX8, + * disable it for external clients that want write + * access. + */ + if ((usage & PIPE_HANDLE_USAGE_SHADER_WRITE && tex->surface.dcc_offset) || + /* Displayable DCC requires an explicit flush. */ + (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) && + si_has_displayable_dcc(tex))) { + if (si_texture_disable_dcc(sctx, tex)) { + update_metadata = true; + /* si_texture_disable_dcc flushes the context */ + flush = false; + } + } - if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) && - (tex->cmask_buffer || tex->surface.dcc_offset)) { - /* Eliminate fast clear (both CMASK and DCC) */ - si_eliminate_fast_color_clear(sctx, tex); - /* eliminate_fast_color_clear flushes the context */ - flush = false; + if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) && + (tex->cmask_buffer || tex->surface.dcc_offset)) { + /* Eliminate fast clear (both CMASK and DCC) */ + si_eliminate_fast_color_clear(sctx, tex); + /* eliminate_fast_color_clear flushes the context */ + flush = false; - /* Disable CMASK if flush_resource isn't going - * to be called. - */ - if (tex->cmask_buffer) - si_texture_discard_cmask(sscreen, tex); - } + /* Disable CMASK if flush_resource isn't going + * to be called. + */ + if (tex->cmask_buffer) + si_texture_discard_cmask(sscreen, tex); + } - /* Set metadata. */ - if ((!res->b.is_shared || update_metadata) && whandle->offset == 0) - si_set_tex_bo_metadata(sscreen, tex); + /* Set metadata. */ + if ((!res->b.is_shared || update_metadata) && whandle->offset == 0) + si_set_tex_bo_metadata(sscreen, tex); - if (sscreen->info.chip_class >= GFX9) { - slice_size = tex->surface.u.gfx9.surf_slice_size; - } else { - slice_size = (uint64_t)tex->surface.u.legacy.level[0].slice_size_dw * 4; - } - } else { - /* Buffer exports are for the OpenCL interop. */ - /* Move a suballocated buffer into a non-suballocated allocation. */ - if (sscreen->ws->buffer_is_suballocated(res->buf) || - /* A DMABUF export always fails if the BO is local. */ - (tex->buffer.flags & RADEON_FLAG_NO_INTERPROCESS_SHARING && - sscreen->info.has_local_buffers)) { - assert(!res->b.is_shared); + if (sscreen->info.chip_class >= GFX9) { + slice_size = tex->surface.u.gfx9.surf_slice_size; + } else { + slice_size = (uint64_t)tex->surface.u.legacy.level[0].slice_size_dw * 4; + } + } else { + /* Buffer exports are for the OpenCL interop. */ + /* Move a suballocated buffer into a non-suballocated allocation. */ + if (sscreen->ws->buffer_is_suballocated(res->buf) || + /* A DMABUF export always fails if the BO is local. */ + (tex->buffer.flags & RADEON_FLAG_NO_INTERPROCESS_SHARING && + sscreen->info.has_local_buffers)) { + assert(!res->b.is_shared); - /* Allocate a new buffer with PIPE_BIND_SHARED. */ - struct pipe_resource templ = res->b.b; - templ.bind |= PIPE_BIND_SHARED; + /* Allocate a new buffer with PIPE_BIND_SHARED. */ + struct pipe_resource templ = res->b.b; + templ.bind |= PIPE_BIND_SHARED; - struct pipe_resource *newb = - screen->resource_create(screen, &templ); - if (!newb) - return false; + struct pipe_resource *newb = + screen->resource_create(screen, &templ); + if (!newb) + return false; - /* Copy the old buffer contents to the new one. */ - struct pipe_box box; - u_box_1d(0, newb->width0, &box); - sctx->b.resource_copy_region(&sctx->b, newb, 0, 0, 0, 0, - &res->b.b, 0, &box); - flush = true; - /* Move the new buffer storage to the old pipe_resource. */ - si_replace_buffer_storage(&sctx->b, &res->b.b, newb); - pipe_resource_reference(&newb, NULL); + /* Copy the old buffer contents to the new one. */ + struct pipe_box box; + u_box_1d(0, newb->width0, &box); + sctx->b.resource_copy_region(&sctx->b, newb, 0, 0, 0, 0, + &res->b.b, 0, &box); + flush = true; + /* Move the new buffer storage to the old pipe_resource. */ + si_replace_buffer_storage(&sctx->b, &res->b.b, newb); + pipe_resource_reference(&newb, NULL); - assert(res->b.b.bind & PIPE_BIND_SHARED); - assert(res->flags & RADEON_FLAG_NO_SUBALLOC); - } + assert(res->b.b.bind & PIPE_BIND_SHARED); + assert(res->flags & RADEON_FLAG_NO_SUBALLOC); + } - /* Buffers */ - slice_size = 0; - } + /* Buffers */ + slice_size = 0; + } - si_texture_get_info(screen, resource, &stride, &offset); + si_texture_get_info(screen, resource, &stride, &offset); - if (flush) - sctx->b.flush(&sctx->b, NULL, 0); + if (flush) + sctx->b.flush(&sctx->b, NULL, 0); - if (res->b.is_shared) { - /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user - * doesn't set it. - */ - res->external_usage |= usage & ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH; - if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH)) - res->external_usage &= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH; - } else { - res->b.is_shared = true; - res->external_usage = usage; - } + if (res->b.is_shared) { + /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user + * doesn't set it. + */ + res->external_usage |= usage & ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH; + if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH)) + res->external_usage &= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH; + } else { + res->b.is_shared = true; + res->external_usage = usage; + } - whandle->stride = stride; - whandle->offset = offset + slice_size * whandle->layer; + whandle->stride = stride; + whandle->offset = offset + slice_size * whandle->layer; - return sscreen->ws->buffer_get_handle(sscreen->ws, res->buf, whandle); + return sscreen->ws->buffer_get_handle(sscreen->ws, res->buf, whandle); } static void si_texture_destroy(struct pipe_screen *screen, - struct pipe_resource *ptex) + struct pipe_resource *ptex) { - struct si_screen *sscreen = (struct si_screen*)screen; - struct si_texture *tex = (struct si_texture*)ptex; - struct si_resource *resource = &tex->buffer; + struct si_screen *sscreen = (struct si_screen*)screen; + struct si_texture *tex = (struct si_texture*)ptex; + struct si_resource *resource = &tex->buffer; - if (sscreen->info.chip_class >= GFX9) - free(tex->surface.u.gfx9.dcc_retile_map); + if (sscreen->info.chip_class >= GFX9) + free(tex->surface.u.gfx9.dcc_retile_map); - si_texture_reference(&tex->flushed_depth_texture, NULL); + si_texture_reference(&tex->flushed_depth_texture, NULL); - if (tex->cmask_buffer != &tex->buffer) { - si_resource_reference(&tex->cmask_buffer, NULL); - } - pb_reference(&resource->buf, NULL); - si_resource_reference(&tex->dcc_separate_buffer, NULL); - si_resource_reference(&tex->last_dcc_separate_buffer, NULL); - FREE(tex); + if (tex->cmask_buffer != &tex->buffer) { + si_resource_reference(&tex->cmask_buffer, NULL); + } + pb_reference(&resource->buf, NULL); + si_resource_reference(&tex->dcc_separate_buffer, NULL); + si_resource_reference(&tex->last_dcc_separate_buffer, NULL); + FREE(tex); } static const struct u_resource_vtbl si_texture_vtbl; void si_print_texture_info(struct si_screen *sscreen, - struct si_texture *tex, struct u_log_context *log) + struct si_texture *tex, struct u_log_context *log) { - int i; + int i; - /* Common parameters. */ - u_log_printf(log, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, " - "blk_h=%u, array_size=%u, last_level=%u, " - "bpe=%u, nsamples=%u, flags=0x%x, %s\n", - tex->buffer.b.b.width0, tex->buffer.b.b.height0, - tex->buffer.b.b.depth0, tex->surface.blk_w, - tex->surface.blk_h, - tex->buffer.b.b.array_size, tex->buffer.b.b.last_level, - tex->surface.bpe, tex->buffer.b.b.nr_samples, - tex->surface.flags, util_format_short_name(tex->buffer.b.b.format)); + /* Common parameters. */ + u_log_printf(log, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, " + "blk_h=%u, array_size=%u, last_level=%u, " + "bpe=%u, nsamples=%u, flags=0x%x, %s\n", + tex->buffer.b.b.width0, tex->buffer.b.b.height0, + tex->buffer.b.b.depth0, tex->surface.blk_w, + tex->surface.blk_h, + tex->buffer.b.b.array_size, tex->buffer.b.b.last_level, + tex->surface.bpe, tex->buffer.b.b.nr_samples, + tex->surface.flags, util_format_short_name(tex->buffer.b.b.format)); - if (sscreen->info.chip_class >= GFX9) { - u_log_printf(log, " Surf: size=%"PRIu64", slice_size=%"PRIu64", " - "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n", - tex->surface.surf_size, - tex->surface.u.gfx9.surf_slice_size, - tex->surface.surf_alignment, - tex->surface.u.gfx9.surf.swizzle_mode, - tex->surface.u.gfx9.surf.epitch, - tex->surface.u.gfx9.surf_pitch); + if (sscreen->info.chip_class >= GFX9) { + u_log_printf(log, " Surf: size=%"PRIu64", slice_size=%"PRIu64", " + "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n", + tex->surface.surf_size, + tex->surface.u.gfx9.surf_slice_size, + tex->surface.surf_alignment, + tex->surface.u.gfx9.surf.swizzle_mode, + tex->surface.u.gfx9.surf.epitch, + tex->surface.u.gfx9.surf_pitch); - if (tex->surface.fmask_offset) { - u_log_printf(log, " FMASK: offset=%"PRIu64", size=%"PRIu64", " - "alignment=%u, swmode=%u, epitch=%u\n", - tex->surface.fmask_offset, - tex->surface.fmask_size, - tex->surface.fmask_alignment, - tex->surface.u.gfx9.fmask.swizzle_mode, - tex->surface.u.gfx9.fmask.epitch); - } + if (tex->surface.fmask_offset) { + u_log_printf(log, " FMASK: offset=%"PRIu64", size=%"PRIu64", " + "alignment=%u, swmode=%u, epitch=%u\n", + tex->surface.fmask_offset, + tex->surface.fmask_size, + tex->surface.fmask_alignment, + tex->surface.u.gfx9.fmask.swizzle_mode, + tex->surface.u.gfx9.fmask.epitch); + } - if (tex->cmask_buffer) { - u_log_printf(log, " CMask: offset=%"PRIu64", size=%u, " - "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n", - tex->surface.cmask_offset, - tex->surface.cmask_size, - tex->surface.cmask_alignment, - tex->surface.u.gfx9.cmask.rb_aligned, - tex->surface.u.gfx9.cmask.pipe_aligned); - } + if (tex->cmask_buffer) { + u_log_printf(log, " CMask: offset=%"PRIu64", size=%u, " + "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n", + tex->surface.cmask_offset, + tex->surface.cmask_size, + tex->surface.cmask_alignment, + tex->surface.u.gfx9.cmask.rb_aligned, + tex->surface.u.gfx9.cmask.pipe_aligned); + } - if (tex->surface.htile_offset) { - u_log_printf(log, " HTile: offset=%"PRIu64", size=%u, alignment=%u, " - "rb_aligned=%u, pipe_aligned=%u\n", - tex->surface.htile_offset, - tex->surface.htile_size, - tex->surface.htile_alignment, - tex->surface.u.gfx9.htile.rb_aligned, - tex->surface.u.gfx9.htile.pipe_aligned); - } + if (tex->surface.htile_offset) { + u_log_printf(log, " HTile: offset=%"PRIu64", size=%u, alignment=%u, " + "rb_aligned=%u, pipe_aligned=%u\n", + tex->surface.htile_offset, + tex->surface.htile_size, + tex->surface.htile_alignment, + tex->surface.u.gfx9.htile.rb_aligned, + tex->surface.u.gfx9.htile.pipe_aligned); + } - if (tex->surface.dcc_offset) { - u_log_printf(log, " DCC: offset=%"PRIu64", size=%u, " - "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n", - tex->surface.dcc_offset, tex->surface.dcc_size, - tex->surface.dcc_alignment, - tex->surface.u.gfx9.display_dcc_pitch_max, - tex->surface.num_dcc_levels); - } + if (tex->surface.dcc_offset) { + u_log_printf(log, " DCC: offset=%"PRIu64", size=%u, " + "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n", + tex->surface.dcc_offset, tex->surface.dcc_size, + tex->surface.dcc_alignment, + tex->surface.u.gfx9.display_dcc_pitch_max, + tex->surface.num_dcc_levels); + } - if (tex->surface.u.gfx9.stencil_offset) { - u_log_printf(log, " Stencil: offset=%"PRIu64", swmode=%u, epitch=%u\n", - tex->surface.u.gfx9.stencil_offset, - tex->surface.u.gfx9.stencil.swizzle_mode, - tex->surface.u.gfx9.stencil.epitch); - } - return; - } + if (tex->surface.u.gfx9.stencil_offset) { + u_log_printf(log, " Stencil: offset=%"PRIu64", swmode=%u, epitch=%u\n", + tex->surface.u.gfx9.stencil_offset, + tex->surface.u.gfx9.stencil.swizzle_mode, + tex->surface.u.gfx9.stencil.epitch); + } + return; + } - u_log_printf(log, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, " - "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n", - tex->surface.surf_size, tex->surface.surf_alignment, tex->surface.u.legacy.bankw, - tex->surface.u.legacy.bankh, tex->surface.u.legacy.num_banks, tex->surface.u.legacy.mtilea, - tex->surface.u.legacy.tile_split, tex->surface.u.legacy.pipe_config, - (tex->surface.flags & RADEON_SURF_SCANOUT) != 0); + u_log_printf(log, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, " + "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n", + tex->surface.surf_size, tex->surface.surf_alignment, tex->surface.u.legacy.bankw, + tex->surface.u.legacy.bankh, tex->surface.u.legacy.num_banks, tex->surface.u.legacy.mtilea, + tex->surface.u.legacy.tile_split, tex->surface.u.legacy.pipe_config, + (tex->surface.flags & RADEON_SURF_SCANOUT) != 0); - if (tex->surface.fmask_offset) - u_log_printf(log, " FMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, pitch_in_pixels=%u, " - "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n", - tex->surface.fmask_offset, tex->surface.fmask_size, tex->surface.fmask_alignment, - tex->surface.u.legacy.fmask.pitch_in_pixels, - tex->surface.u.legacy.fmask.bankh, - tex->surface.u.legacy.fmask.slice_tile_max, - tex->surface.u.legacy.fmask.tiling_index); + if (tex->surface.fmask_offset) + u_log_printf(log, " FMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, pitch_in_pixels=%u, " + "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n", + tex->surface.fmask_offset, tex->surface.fmask_size, tex->surface.fmask_alignment, + tex->surface.u.legacy.fmask.pitch_in_pixels, + tex->surface.u.legacy.fmask.bankh, + tex->surface.u.legacy.fmask.slice_tile_max, + tex->surface.u.legacy.fmask.tiling_index); - if (tex->cmask_buffer) - u_log_printf(log, " CMask: offset=%"PRIu64", size=%u, alignment=%u, " - "slice_tile_max=%u\n", - tex->surface.cmask_offset, tex->surface.cmask_size, tex->surface.cmask_alignment, - tex->surface.u.legacy.cmask_slice_tile_max); + if (tex->cmask_buffer) + u_log_printf(log, " CMask: offset=%"PRIu64", size=%u, alignment=%u, " + "slice_tile_max=%u\n", + tex->surface.cmask_offset, tex->surface.cmask_size, tex->surface.cmask_alignment, + tex->surface.u.legacy.cmask_slice_tile_max); - if (tex->surface.htile_offset) - u_log_printf(log, " HTile: offset=%"PRIu64", size=%u, " - "alignment=%u, TC_compatible = %u\n", - tex->surface.htile_offset, tex->surface.htile_size, - tex->surface.htile_alignment, - tex->tc_compatible_htile); + if (tex->surface.htile_offset) + u_log_printf(log, " HTile: offset=%"PRIu64", size=%u, " + "alignment=%u, TC_compatible = %u\n", + tex->surface.htile_offset, tex->surface.htile_size, + tex->surface.htile_alignment, + tex->tc_compatible_htile); - if (tex->surface.dcc_offset) { - u_log_printf(log, " DCC: offset=%"PRIu64", size=%u, alignment=%u\n", - tex->surface.dcc_offset, tex->surface.dcc_size, - tex->surface.dcc_alignment); - for (i = 0; i <= tex->buffer.b.b.last_level; i++) - u_log_printf(log, " DCCLevel[%i]: enabled=%u, offset=%u, " - "fast_clear_size=%u\n", - i, i < tex->surface.num_dcc_levels, - tex->surface.u.legacy.level[i].dcc_offset, - tex->surface.u.legacy.level[i].dcc_fast_clear_size); - } + if (tex->surface.dcc_offset) { + u_log_printf(log, " DCC: offset=%"PRIu64", size=%u, alignment=%u\n", + tex->surface.dcc_offset, tex->surface.dcc_size, + tex->surface.dcc_alignment); + for (i = 0; i <= tex->buffer.b.b.last_level; i++) + u_log_printf(log, " DCCLevel[%i]: enabled=%u, offset=%u, " + "fast_clear_size=%u\n", + i, i < tex->surface.num_dcc_levels, + tex->surface.u.legacy.level[i].dcc_offset, + tex->surface.u.legacy.level[i].dcc_fast_clear_size); + } - for (i = 0; i <= tex->buffer.b.b.last_level; i++) - u_log_printf(log, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", " - "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " - "mode=%u, tiling_index = %u\n", - i, tex->surface.u.legacy.level[i].offset, - (uint64_t)tex->surface.u.legacy.level[i].slice_size_dw * 4, - u_minify(tex->buffer.b.b.width0, i), - u_minify(tex->buffer.b.b.height0, i), - u_minify(tex->buffer.b.b.depth0, i), - tex->surface.u.legacy.level[i].nblk_x, - tex->surface.u.legacy.level[i].nblk_y, - tex->surface.u.legacy.level[i].mode, - tex->surface.u.legacy.tiling_index[i]); + for (i = 0; i <= tex->buffer.b.b.last_level; i++) + u_log_printf(log, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", " + "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " + "mode=%u, tiling_index = %u\n", + i, tex->surface.u.legacy.level[i].offset, + (uint64_t)tex->surface.u.legacy.level[i].slice_size_dw * 4, + u_minify(tex->buffer.b.b.width0, i), + u_minify(tex->buffer.b.b.height0, i), + u_minify(tex->buffer.b.b.depth0, i), + tex->surface.u.legacy.level[i].nblk_x, + tex->surface.u.legacy.level[i].nblk_y, + tex->surface.u.legacy.level[i].mode, + tex->surface.u.legacy.tiling_index[i]); - if (tex->surface.has_stencil) { - u_log_printf(log, " StencilLayout: tilesplit=%u\n", - tex->surface.u.legacy.stencil_tile_split); - for (i = 0; i <= tex->buffer.b.b.last_level; i++) { - u_log_printf(log, " StencilLevel[%i]: offset=%"PRIu64", " - "slice_size=%"PRIu64", npix_x=%u, " - "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " - "mode=%u, tiling_index = %u\n", - i, tex->surface.u.legacy.stencil_level[i].offset, - (uint64_t)tex->surface.u.legacy.stencil_level[i].slice_size_dw * 4, - u_minify(tex->buffer.b.b.width0, i), - u_minify(tex->buffer.b.b.height0, i), - u_minify(tex->buffer.b.b.depth0, i), - tex->surface.u.legacy.stencil_level[i].nblk_x, - tex->surface.u.legacy.stencil_level[i].nblk_y, - tex->surface.u.legacy.stencil_level[i].mode, - tex->surface.u.legacy.stencil_tiling_index[i]); - } - } + if (tex->surface.has_stencil) { + u_log_printf(log, " StencilLayout: tilesplit=%u\n", + tex->surface.u.legacy.stencil_tile_split); + for (i = 0; i <= tex->buffer.b.b.last_level; i++) { + u_log_printf(log, " StencilLevel[%i]: offset=%"PRIu64", " + "slice_size=%"PRIu64", npix_x=%u, " + "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " + "mode=%u, tiling_index = %u\n", + i, tex->surface.u.legacy.stencil_level[i].offset, + (uint64_t)tex->surface.u.legacy.stencil_level[i].slice_size_dw * 4, + u_minify(tex->buffer.b.b.width0, i), + u_minify(tex->buffer.b.b.height0, i), + u_minify(tex->buffer.b.b.depth0, i), + tex->surface.u.legacy.stencil_level[i].nblk_x, + tex->surface.u.legacy.stencil_level[i].nblk_y, + tex->surface.u.legacy.stencil_level[i].mode, + tex->surface.u.legacy.stencil_tiling_index[i]); + } + } } /** * Common function for si_texture_create and si_texture_from_handle. * - * \param screen screen - * \param base resource template - * \param surface radeon_surf - * \param plane0 if a non-zero plane is being created, this is the first plane - * \param imported_buf from si_texture_from_handle - * \param offset offset for non-zero planes or imported buffers - * \param alloc_size the size to allocate if plane0 != NULL - * \param alignment alignment for the allocation + * \param screen screen + * \param base resource template + * \param surface radeon_surf + * \param plane0 if a non-zero plane is being created, this is the first plane + * \param imported_buf from si_texture_from_handle + * \param offset offset for non-zero planes or imported buffers + * \param alloc_size the size to allocate if plane0 != NULL + * \param alignment alignment for the allocation */ static struct si_texture * si_texture_create_object(struct pipe_screen *screen, - const struct pipe_resource *base, - const struct radeon_surf *surface, - const struct si_texture *plane0, - struct pb_buffer *imported_buf, - uint64_t offset, - uint64_t alloc_size, - unsigned alignment) + const struct pipe_resource *base, + const struct radeon_surf *surface, + const struct si_texture *plane0, + struct pb_buffer *imported_buf, + uint64_t offset, + uint64_t alloc_size, + unsigned alignment) { - struct si_texture *tex; - struct si_resource *resource; - struct si_screen *sscreen = (struct si_screen*)screen; + struct si_texture *tex; + struct si_resource *resource; + struct si_screen *sscreen = (struct si_screen*)screen; - tex = CALLOC_STRUCT(si_texture); - if (!tex) - goto error; + tex = CALLOC_STRUCT(si_texture); + if (!tex) + goto error; - resource = &tex->buffer; - resource->b.b = *base; - resource->b.b.next = NULL; - resource->b.vtbl = &si_texture_vtbl; - pipe_reference_init(&resource->b.b.reference, 1); - resource->b.b.screen = screen; + resource = &tex->buffer; + resource->b.b = *base; + resource->b.b.next = NULL; + resource->b.vtbl = &si_texture_vtbl; + pipe_reference_init(&resource->b.b.reference, 1); + resource->b.b.screen = screen; - /* don't include stencil-only formats which we don't support for rendering */ - tex->is_depth = util_format_has_depth(util_format_description(tex->buffer.b.b.format)); - tex->surface = *surface; - tex->tc_compatible_htile = tex->surface.htile_size != 0 && - (tex->surface.flags & - RADEON_SURF_TC_COMPATIBLE_HTILE); + /* don't include stencil-only formats which we don't support for rendering */ + tex->is_depth = util_format_has_depth(util_format_description(tex->buffer.b.b.format)); + tex->surface = *surface; + tex->tc_compatible_htile = tex->surface.htile_size != 0 && + (tex->surface.flags & + RADEON_SURF_TC_COMPATIBLE_HTILE); - /* TC-compatible HTILE: - * - GFX8 only supports Z32_FLOAT. - * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */ - if (tex->tc_compatible_htile) { - if (sscreen->info.chip_class >= GFX9 && - base->format == PIPE_FORMAT_Z16_UNORM) - tex->db_render_format = base->format; - else { - tex->db_render_format = PIPE_FORMAT_Z32_FLOAT; - tex->upgraded_depth = base->format != PIPE_FORMAT_Z32_FLOAT && - base->format != PIPE_FORMAT_Z32_FLOAT_S8X24_UINT; - } - } else { - tex->db_render_format = base->format; - } + /* TC-compatible HTILE: + * - GFX8 only supports Z32_FLOAT. + * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */ + if (tex->tc_compatible_htile) { + if (sscreen->info.chip_class >= GFX9 && + base->format == PIPE_FORMAT_Z16_UNORM) + tex->db_render_format = base->format; + else { + tex->db_render_format = PIPE_FORMAT_Z32_FLOAT; + tex->upgraded_depth = base->format != PIPE_FORMAT_Z32_FLOAT && + base->format != PIPE_FORMAT_Z32_FLOAT_S8X24_UINT; + } + } else { + tex->db_render_format = base->format; + } - /* Applies to GCN. */ - tex->last_msaa_resolve_target_micro_mode = tex->surface.micro_tile_mode; + /* Applies to GCN. */ + tex->last_msaa_resolve_target_micro_mode = tex->surface.micro_tile_mode; - /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers - * between frames, so the only thing that can enable separate DCC - * with DRI2 is multiple slow clears within a frame. - */ - tex->ps_draw_ratio = 0; + /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers + * between frames, so the only thing that can enable separate DCC + * with DRI2 is multiple slow clears within a frame. + */ + tex->ps_draw_ratio = 0; - if (sscreen->info.chip_class >= GFX9) { - tex->surface.u.gfx9.surf_offset = offset; - } else { - for (unsigned i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i) - tex->surface.u.legacy.level[i].offset += offset; - } + if (sscreen->info.chip_class >= GFX9) { + tex->surface.u.gfx9.surf_offset = offset; + } else { + for (unsigned i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i) + tex->surface.u.legacy.level[i].offset += offset; + } - if (tex->is_depth) { - if (sscreen->info.chip_class >= GFX9) { - tex->can_sample_z = true; - tex->can_sample_s = true; + if (tex->is_depth) { + if (sscreen->info.chip_class >= GFX9) { + tex->can_sample_z = true; + tex->can_sample_s = true; - /* Stencil texturing with HTILE doesn't work - * with mipmapping on Navi10-14. */ - if ((sscreen->info.family == CHIP_NAVI10 || - sscreen->info.family == CHIP_NAVI12 || - sscreen->info.family == CHIP_NAVI14) && - base->last_level > 0) - tex->htile_stencil_disabled = true; - } else { - tex->can_sample_z = !tex->surface.u.legacy.depth_adjusted; - tex->can_sample_s = !tex->surface.u.legacy.stencil_adjusted; - } + /* Stencil texturing with HTILE doesn't work + * with mipmapping on Navi10-14. */ + if ((sscreen->info.family == CHIP_NAVI10 || + sscreen->info.family == CHIP_NAVI12 || + sscreen->info.family == CHIP_NAVI14) && + base->last_level > 0) + tex->htile_stencil_disabled = true; + } else { + tex->can_sample_z = !tex->surface.u.legacy.depth_adjusted; + tex->can_sample_s = !tex->surface.u.legacy.stencil_adjusted; + } - tex->db_compatible = surface->flags & RADEON_SURF_ZBUFFER; - } else { - if (tex->surface.cmask_offset) { - tex->cb_color_info |= S_028C70_FAST_CLEAR(1); - tex->cmask_buffer = &tex->buffer; - } - } + tex->db_compatible = surface->flags & RADEON_SURF_ZBUFFER; + } else { + if (tex->surface.cmask_offset) { + tex->cb_color_info |= S_028C70_FAST_CLEAR(1); + tex->cmask_buffer = &tex->buffer; + } + } - if (plane0) { - /* The buffer is shared with the first plane. */ - resource->bo_size = plane0->buffer.bo_size; - resource->bo_alignment = plane0->buffer.bo_alignment; - resource->flags = plane0->buffer.flags; - resource->domains = plane0->buffer.domains; - resource->vram_usage = plane0->buffer.vram_usage; - resource->gart_usage = plane0->buffer.gart_usage; + if (plane0) { + /* The buffer is shared with the first plane. */ + resource->bo_size = plane0->buffer.bo_size; + resource->bo_alignment = plane0->buffer.bo_alignment; + resource->flags = plane0->buffer.flags; + resource->domains = plane0->buffer.domains; + resource->vram_usage = plane0->buffer.vram_usage; + resource->gart_usage = plane0->buffer.gart_usage; - pb_reference(&resource->buf, plane0->buffer.buf); - resource->gpu_address = plane0->buffer.gpu_address; - } else if (!(surface->flags & RADEON_SURF_IMPORTED)) { - /* Create the backing buffer. */ - si_init_resource_fields(sscreen, resource, alloc_size, alignment); + pb_reference(&resource->buf, plane0->buffer.buf); + resource->gpu_address = plane0->buffer.gpu_address; + } else if (!(surface->flags & RADEON_SURF_IMPORTED)) { + /* Create the backing buffer. */ + si_init_resource_fields(sscreen, resource, alloc_size, alignment); - if (!si_alloc_resource(sscreen, resource)) - goto error; - } else { - resource->buf = imported_buf; - resource->gpu_address = sscreen->ws->buffer_get_virtual_address(resource->buf); - resource->bo_size = imported_buf->size; - resource->bo_alignment = imported_buf->alignment; - resource->domains = sscreen->ws->buffer_get_initial_domain(resource->buf); - if (resource->domains & RADEON_DOMAIN_VRAM) - resource->vram_usage = resource->bo_size; - else if (resource->domains & RADEON_DOMAIN_GTT) - resource->gart_usage = resource->bo_size; + if (!si_alloc_resource(sscreen, resource)) + goto error; + } else { + resource->buf = imported_buf; + resource->gpu_address = sscreen->ws->buffer_get_virtual_address(resource->buf); + resource->bo_size = imported_buf->size; + resource->bo_alignment = imported_buf->alignment; + resource->domains = sscreen->ws->buffer_get_initial_domain(resource->buf); + if (resource->domains & RADEON_DOMAIN_VRAM) + resource->vram_usage = resource->bo_size; + else if (resource->domains & RADEON_DOMAIN_GTT) + resource->gart_usage = resource->bo_size; if (sscreen->ws->buffer_get_flags) resource->flags = sscreen->ws->buffer_get_flags(resource->buf); - } + } - if (tex->cmask_buffer) { - /* Initialize the cmask to 0xCC (= compressed state). */ - si_screen_clear_buffer(sscreen, &tex->cmask_buffer->b.b, - tex->surface.cmask_offset, tex->surface.cmask_size, - 0xCCCCCCCC); - } - if (tex->surface.htile_offset) { - uint32_t clear_value = 0; + if (tex->cmask_buffer) { + /* Initialize the cmask to 0xCC (= compressed state). */ + si_screen_clear_buffer(sscreen, &tex->cmask_buffer->b.b, + tex->surface.cmask_offset, tex->surface.cmask_size, + 0xCCCCCCCC); + } + if (tex->surface.htile_offset) { + uint32_t clear_value = 0; - if (sscreen->info.chip_class >= GFX9 || tex->tc_compatible_htile) - clear_value = 0x0000030F; + if (sscreen->info.chip_class >= GFX9 || tex->tc_compatible_htile) + clear_value = 0x0000030F; - si_screen_clear_buffer(sscreen, &tex->buffer.b.b, - tex->surface.htile_offset, - tex->surface.htile_size, - clear_value); - } + si_screen_clear_buffer(sscreen, &tex->buffer.b.b, + tex->surface.htile_offset, + tex->surface.htile_size, + clear_value); + } - /* Initialize DCC only if the texture is not being imported. */ - if (!(surface->flags & RADEON_SURF_IMPORTED) && tex->surface.dcc_offset) { - /* Clear DCC to black for all tiles with DCC enabled. - * - * This fixes corruption in 3DMark Slingshot Extreme, which - * uses uninitialized textures, causing corruption. - */ - if (tex->surface.num_dcc_levels == tex->buffer.b.b.last_level + 1 && - tex->buffer.b.b.nr_samples <= 2) { - /* Simple case - all tiles have DCC enabled. */ - si_screen_clear_buffer(sscreen, &tex->buffer.b.b, - tex->surface.dcc_offset, - tex->surface.dcc_size, - DCC_CLEAR_COLOR_0000); - } else if (sscreen->info.chip_class >= GFX9) { - /* Clear to uncompressed. Clearing this to black is complicated. */ - si_screen_clear_buffer(sscreen, &tex->buffer.b.b, - tex->surface.dcc_offset, - tex->surface.dcc_size, - DCC_UNCOMPRESSED); - } else { - /* GFX8: Initialize mipmap levels and multisamples separately. */ - if (tex->buffer.b.b.nr_samples >= 2) { - /* Clearing this to black is complicated. */ - si_screen_clear_buffer(sscreen, &tex->buffer.b.b, - tex->surface.dcc_offset, - tex->surface.dcc_size, - DCC_UNCOMPRESSED); - } else { - /* Clear the enabled mipmap levels to black. */ - unsigned size = 0; + /* Initialize DCC only if the texture is not being imported. */ + if (!(surface->flags & RADEON_SURF_IMPORTED) && tex->surface.dcc_offset) { + /* Clear DCC to black for all tiles with DCC enabled. + * + * This fixes corruption in 3DMark Slingshot Extreme, which + * uses uninitialized textures, causing corruption. + */ + if (tex->surface.num_dcc_levels == tex->buffer.b.b.last_level + 1 && + tex->buffer.b.b.nr_samples <= 2) { + /* Simple case - all tiles have DCC enabled. */ + si_screen_clear_buffer(sscreen, &tex->buffer.b.b, + tex->surface.dcc_offset, + tex->surface.dcc_size, + DCC_CLEAR_COLOR_0000); + } else if (sscreen->info.chip_class >= GFX9) { + /* Clear to uncompressed. Clearing this to black is complicated. */ + si_screen_clear_buffer(sscreen, &tex->buffer.b.b, + tex->surface.dcc_offset, + tex->surface.dcc_size, + DCC_UNCOMPRESSED); + } else { + /* GFX8: Initialize mipmap levels and multisamples separately. */ + if (tex->buffer.b.b.nr_samples >= 2) { + /* Clearing this to black is complicated. */ + si_screen_clear_buffer(sscreen, &tex->buffer.b.b, + tex->surface.dcc_offset, + tex->surface.dcc_size, + DCC_UNCOMPRESSED); + } else { + /* Clear the enabled mipmap levels to black. */ + unsigned size = 0; - for (unsigned i = 0; i < tex->surface.num_dcc_levels; i++) { - if (!tex->surface.u.legacy.level[i].dcc_fast_clear_size) - break; + for (unsigned i = 0; i < tex->surface.num_dcc_levels; i++) { + if (!tex->surface.u.legacy.level[i].dcc_fast_clear_size) + break; - size = tex->surface.u.legacy.level[i].dcc_offset + - tex->surface.u.legacy.level[i].dcc_fast_clear_size; - } + size = tex->surface.u.legacy.level[i].dcc_offset + + tex->surface.u.legacy.level[i].dcc_fast_clear_size; + } - /* Mipmap levels with DCC. */ - if (size) { - si_screen_clear_buffer(sscreen, &tex->buffer.b.b, - tex->surface.dcc_offset, size, - DCC_CLEAR_COLOR_0000); - } - /* Mipmap levels without DCC. */ - if (size != tex->surface.dcc_size) { - si_screen_clear_buffer(sscreen, &tex->buffer.b.b, - tex->surface.dcc_offset + size, - tex->surface.dcc_size - size, - DCC_UNCOMPRESSED); - } - } - } + /* Mipmap levels with DCC. */ + if (size) { + si_screen_clear_buffer(sscreen, &tex->buffer.b.b, + tex->surface.dcc_offset, size, + DCC_CLEAR_COLOR_0000); + } + /* Mipmap levels without DCC. */ + if (size != tex->surface.dcc_size) { + si_screen_clear_buffer(sscreen, &tex->buffer.b.b, + tex->surface.dcc_offset + size, + tex->surface.dcc_size - size, + DCC_UNCOMPRESSED); + } + } + } - /* Initialize displayable DCC that requires the retile blit. */ - if (tex->surface.dcc_retile_map_offset) { - /* Uninitialized DCC can hang the display hw. - * Clear to white to indicate that. */ - si_screen_clear_buffer(sscreen, &tex->buffer.b.b, - tex->surface.display_dcc_offset, - tex->surface.u.gfx9.display_dcc_size, - DCC_CLEAR_COLOR_1111); + /* Initialize displayable DCC that requires the retile blit. */ + if (tex->surface.dcc_retile_map_offset) { + /* Uninitialized DCC can hang the display hw. + * Clear to white to indicate that. */ + si_screen_clear_buffer(sscreen, &tex->buffer.b.b, + tex->surface.display_dcc_offset, + tex->surface.u.gfx9.display_dcc_size, + DCC_CLEAR_COLOR_1111); - /* Upload the DCC retile map. - * Use a staging buffer for the upload, because - * the buffer backing the texture is unmappable. - */ - bool use_uint16 = tex->surface.u.gfx9.dcc_retile_use_uint16; - unsigned num_elements = tex->surface.u.gfx9.dcc_retile_num_elements; - struct si_resource *buf = - si_aligned_buffer_create(screen, 0, PIPE_USAGE_STREAM, - num_elements * (use_uint16 ? 2 : 4), - sscreen->info.tcc_cache_line_size); - uint32_t *ui = (uint32_t*)sscreen->ws->buffer_map(buf->buf, NULL, - PIPE_TRANSFER_WRITE); - uint16_t *us = (uint16_t*)ui; + /* Upload the DCC retile map. + * Use a staging buffer for the upload, because + * the buffer backing the texture is unmappable. + */ + bool use_uint16 = tex->surface.u.gfx9.dcc_retile_use_uint16; + unsigned num_elements = tex->surface.u.gfx9.dcc_retile_num_elements; + struct si_resource *buf = + si_aligned_buffer_create(screen, 0, PIPE_USAGE_STREAM, + num_elements * (use_uint16 ? 2 : 4), + sscreen->info.tcc_cache_line_size); + uint32_t *ui = (uint32_t*)sscreen->ws->buffer_map(buf->buf, NULL, + PIPE_TRANSFER_WRITE); + uint16_t *us = (uint16_t*)ui; - /* Upload the retile map into a staging buffer. */ - if (use_uint16) { - for (unsigned i = 0; i < num_elements; i++) - us[i] = tex->surface.u.gfx9.dcc_retile_map[i]; - } else { - for (unsigned i = 0; i < num_elements; i++) - ui[i] = tex->surface.u.gfx9.dcc_retile_map[i]; - } + /* Upload the retile map into a staging buffer. */ + if (use_uint16) { + for (unsigned i = 0; i < num_elements; i++) + us[i] = tex->surface.u.gfx9.dcc_retile_map[i]; + } else { + for (unsigned i = 0; i < num_elements; i++) + ui[i] = tex->surface.u.gfx9.dcc_retile_map[i]; + } - /* Copy the staging buffer to the buffer backing the texture. */ - struct si_context *sctx = (struct si_context*)sscreen->aux_context; + /* Copy the staging buffer to the buffer backing the texture. */ + struct si_context *sctx = (struct si_context*)sscreen->aux_context; - assert(tex->surface.dcc_retile_map_offset <= UINT_MAX); - simple_mtx_lock(&sscreen->aux_context_lock); - si_sdma_copy_buffer(sctx, &tex->buffer.b.b, &buf->b.b, - tex->surface.dcc_retile_map_offset, - 0, buf->b.b.width0); - sscreen->aux_context->flush(sscreen->aux_context, NULL, 0); - simple_mtx_unlock(&sscreen->aux_context_lock); + assert(tex->surface.dcc_retile_map_offset <= UINT_MAX); + simple_mtx_lock(&sscreen->aux_context_lock); + si_sdma_copy_buffer(sctx, &tex->buffer.b.b, &buf->b.b, + tex->surface.dcc_retile_map_offset, + 0, buf->b.b.width0); + sscreen->aux_context->flush(sscreen->aux_context, NULL, 0); + simple_mtx_unlock(&sscreen->aux_context_lock); - si_resource_reference(&buf, NULL); - } - } + si_resource_reference(&buf, NULL); + } + } - /* Initialize the CMASK base register value. */ - tex->cmask_base_address_reg = - (tex->buffer.gpu_address + tex->surface.cmask_offset) >> 8; + /* Initialize the CMASK base register value. */ + tex->cmask_base_address_reg = + (tex->buffer.gpu_address + tex->surface.cmask_offset) >> 8; - if (sscreen->debug_flags & DBG(VM)) { - fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n", - tex->buffer.gpu_address, - tex->buffer.gpu_address + tex->buffer.buf->size, - base->width0, base->height0, util_num_layers(base, 0), base->last_level+1, - base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format)); - } + if (sscreen->debug_flags & DBG(VM)) { + fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n", + tex->buffer.gpu_address, + tex->buffer.gpu_address + tex->buffer.buf->size, + base->width0, base->height0, util_num_layers(base, 0), base->last_level+1, + base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format)); + } - if (sscreen->debug_flags & DBG(TEX)) { - puts("Texture:"); - struct u_log_context log; - u_log_context_init(&log); - si_print_texture_info(sscreen, tex, &log); - u_log_new_page_print(&log, stdout); - fflush(stdout); - u_log_context_destroy(&log); - } + if (sscreen->debug_flags & DBG(TEX)) { + puts("Texture:"); + struct u_log_context log; + u_log_context_init(&log); + si_print_texture_info(sscreen, tex, &log); + u_log_new_page_print(&log, stdout); + fflush(stdout); + u_log_context_destroy(&log); + } - return tex; + return tex; error: - FREE(tex); - if (sscreen->info.chip_class >= GFX9) - free(surface->u.gfx9.dcc_retile_map); - return NULL; + FREE(tex); + if (sscreen->info.chip_class >= GFX9) + free(surface->u.gfx9.dcc_retile_map); + return NULL; } static enum radeon_surf_mode si_choose_tiling(struct si_screen *sscreen, - const struct pipe_resource *templ, bool tc_compatible_htile) + const struct pipe_resource *templ, bool tc_compatible_htile) { - const struct util_format_description *desc = util_format_description(templ->format); - bool force_tiling = templ->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING; - bool is_depth_stencil = util_format_is_depth_or_stencil(templ->format) && - !(templ->flags & SI_RESOURCE_FLAG_FLUSHED_DEPTH); + const struct util_format_description *desc = util_format_description(templ->format); + bool force_tiling = templ->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING; + bool is_depth_stencil = util_format_is_depth_or_stencil(templ->format) && + !(templ->flags & SI_RESOURCE_FLAG_FLUSHED_DEPTH); - /* MSAA resources must be 2D tiled. */ - if (templ->nr_samples > 1) - return RADEON_SURF_MODE_2D; + /* MSAA resources must be 2D tiled. */ + if (templ->nr_samples > 1) + return RADEON_SURF_MODE_2D; - /* Transfer resources should be linear. */ - if (templ->flags & SI_RESOURCE_FLAG_TRANSFER) - return RADEON_SURF_MODE_LINEAR_ALIGNED; + /* Transfer resources should be linear. */ + if (templ->flags & SI_RESOURCE_FLAG_TRANSFER) + return RADEON_SURF_MODE_LINEAR_ALIGNED; - /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on GFX8, - * which requires 2D tiling. - */ - if (sscreen->info.chip_class == GFX8 && tc_compatible_htile) - return RADEON_SURF_MODE_2D; + /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on GFX8, + * which requires 2D tiling. + */ + if (sscreen->info.chip_class == GFX8 && tc_compatible_htile) + return RADEON_SURF_MODE_2D; - /* Handle common candidates for the linear mode. - * Compressed textures and DB surfaces must always be tiled. - */ - if (!force_tiling && - !is_depth_stencil && - !util_format_is_compressed(templ->format)) { - if (sscreen->debug_flags & DBG(NO_TILING)) - return RADEON_SURF_MODE_LINEAR_ALIGNED; + /* Handle common candidates for the linear mode. + * Compressed textures and DB surfaces must always be tiled. + */ + if (!force_tiling && + !is_depth_stencil && + !util_format_is_compressed(templ->format)) { + if (sscreen->debug_flags & DBG(NO_TILING)) + return RADEON_SURF_MODE_LINEAR_ALIGNED; - /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. */ - if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) - return RADEON_SURF_MODE_LINEAR_ALIGNED; + /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. */ + if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) + return RADEON_SURF_MODE_LINEAR_ALIGNED; - /* Cursors are linear on AMD GCN. - * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */ - if (templ->bind & PIPE_BIND_CURSOR) - return RADEON_SURF_MODE_LINEAR_ALIGNED; + /* Cursors are linear on AMD GCN. + * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */ + if (templ->bind & PIPE_BIND_CURSOR) + return RADEON_SURF_MODE_LINEAR_ALIGNED; - if (templ->bind & PIPE_BIND_LINEAR) - return RADEON_SURF_MODE_LINEAR_ALIGNED; + if (templ->bind & PIPE_BIND_LINEAR) + return RADEON_SURF_MODE_LINEAR_ALIGNED; - /* Textures with a very small height are recommended to be linear. */ - if (templ->target == PIPE_TEXTURE_1D || - templ->target == PIPE_TEXTURE_1D_ARRAY || - /* Only very thin and long 2D textures should benefit from - * linear_aligned. */ - (templ->width0 > 8 && templ->height0 <= 2)) - return RADEON_SURF_MODE_LINEAR_ALIGNED; + /* Textures with a very small height are recommended to be linear. */ + if (templ->target == PIPE_TEXTURE_1D || + templ->target == PIPE_TEXTURE_1D_ARRAY || + /* Only very thin and long 2D textures should benefit from + * linear_aligned. */ + (templ->width0 > 8 && templ->height0 <= 2)) + return RADEON_SURF_MODE_LINEAR_ALIGNED; - /* Textures likely to be mapped often. */ - if (templ->usage == PIPE_USAGE_STAGING || - templ->usage == PIPE_USAGE_STREAM) - return RADEON_SURF_MODE_LINEAR_ALIGNED; - } + /* Textures likely to be mapped often. */ + if (templ->usage == PIPE_USAGE_STAGING || + templ->usage == PIPE_USAGE_STREAM) + return RADEON_SURF_MODE_LINEAR_ALIGNED; + } - /* Make small textures 1D tiled. */ - if (templ->width0 <= 16 || templ->height0 <= 16 || - (sscreen->debug_flags & DBG(NO_2D_TILING))) - return RADEON_SURF_MODE_1D; + /* Make small textures 1D tiled. */ + if (templ->width0 <= 16 || templ->height0 <= 16 || + (sscreen->debug_flags & DBG(NO_2D_TILING))) + return RADEON_SURF_MODE_1D; - /* The allocator will switch to 1D if needed. */ - return RADEON_SURF_MODE_2D; + /* The allocator will switch to 1D if needed. */ + return RADEON_SURF_MODE_2D; } struct pipe_resource *si_texture_create(struct pipe_screen *screen, - const struct pipe_resource *templ) + const struct pipe_resource *templ) { - struct si_screen *sscreen = (struct si_screen*)screen; - bool is_zs = util_format_is_depth_or_stencil(templ->format); + struct si_screen *sscreen = (struct si_screen*)screen; + bool is_zs = util_format_is_depth_or_stencil(templ->format); - if (templ->nr_samples >= 2) { - /* This is hackish (overwriting the const pipe_resource template), - * but should be harmless and state trackers can also see - * the overriden number of samples in the created pipe_resource. - */ - if (is_zs && sscreen->eqaa_force_z_samples) { - ((struct pipe_resource*)templ)->nr_samples = - ((struct pipe_resource*)templ)->nr_storage_samples = - sscreen->eqaa_force_z_samples; - } else if (!is_zs && sscreen->eqaa_force_color_samples) { - ((struct pipe_resource*)templ)->nr_samples = - sscreen->eqaa_force_coverage_samples; - ((struct pipe_resource*)templ)->nr_storage_samples = - sscreen->eqaa_force_color_samples; - } - } + if (templ->nr_samples >= 2) { + /* This is hackish (overwriting the const pipe_resource template), + * but should be harmless and state trackers can also see + * the overriden number of samples in the created pipe_resource. + */ + if (is_zs && sscreen->eqaa_force_z_samples) { + ((struct pipe_resource*)templ)->nr_samples = + ((struct pipe_resource*)templ)->nr_storage_samples = + sscreen->eqaa_force_z_samples; + } else if (!is_zs && sscreen->eqaa_force_color_samples) { + ((struct pipe_resource*)templ)->nr_samples = + sscreen->eqaa_force_coverage_samples; + ((struct pipe_resource*)templ)->nr_storage_samples = + sscreen->eqaa_force_color_samples; + } + } - bool is_flushed_depth = templ->flags & SI_RESOURCE_FLAG_FLUSHED_DEPTH || - templ->flags & SI_RESOURCE_FLAG_TRANSFER; - bool tc_compatible_htile = - sscreen->info.chip_class >= GFX8 && - /* There are issues with TC-compatible HTILE on Tonga (and - * Iceland is the same design), and documented bug workarounds - * don't help. For example, this fails: - * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow -auto - */ - sscreen->info.family != CHIP_TONGA && - sscreen->info.family != CHIP_ICELAND && - (templ->flags & PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY) && - !(sscreen->debug_flags & DBG(NO_HYPERZ)) && - !is_flushed_depth && - templ->nr_samples <= 1 && /* TC-compat HTILE is less efficient with MSAA */ - is_zs; - enum radeon_surf_mode tile_mode = si_choose_tiling(sscreen, templ, - tc_compatible_htile); + bool is_flushed_depth = templ->flags & SI_RESOURCE_FLAG_FLUSHED_DEPTH || + templ->flags & SI_RESOURCE_FLAG_TRANSFER; + bool tc_compatible_htile = + sscreen->info.chip_class >= GFX8 && + /* There are issues with TC-compatible HTILE on Tonga (and + * Iceland is the same design), and documented bug workarounds + * don't help. For example, this fails: + * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow -auto + */ + sscreen->info.family != CHIP_TONGA && + sscreen->info.family != CHIP_ICELAND && + (templ->flags & PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY) && + !(sscreen->debug_flags & DBG(NO_HYPERZ)) && + !is_flushed_depth && + templ->nr_samples <= 1 && /* TC-compat HTILE is less efficient with MSAA */ + is_zs; + enum radeon_surf_mode tile_mode = si_choose_tiling(sscreen, templ, + tc_compatible_htile); - /* This allocates textures with multiple planes like NV12 in 1 buffer. */ - enum { SI_TEXTURE_MAX_PLANES = 3 }; - struct radeon_surf surface[SI_TEXTURE_MAX_PLANES] = {}; - struct pipe_resource plane_templ[SI_TEXTURE_MAX_PLANES]; - uint64_t plane_offset[SI_TEXTURE_MAX_PLANES] = {}; - uint64_t total_size = 0; - unsigned max_alignment = 0; - unsigned num_planes = util_format_get_num_planes(templ->format); - assert(num_planes <= SI_TEXTURE_MAX_PLANES); + /* This allocates textures with multiple planes like NV12 in 1 buffer. */ + enum { SI_TEXTURE_MAX_PLANES = 3 }; + struct radeon_surf surface[SI_TEXTURE_MAX_PLANES] = {}; + struct pipe_resource plane_templ[SI_TEXTURE_MAX_PLANES]; + uint64_t plane_offset[SI_TEXTURE_MAX_PLANES] = {}; + uint64_t total_size = 0; + unsigned max_alignment = 0; + unsigned num_planes = util_format_get_num_planes(templ->format); + assert(num_planes <= SI_TEXTURE_MAX_PLANES); - /* Compute texture or plane layouts and offsets. */ - for (unsigned i = 0; i < num_planes; i++) { - plane_templ[i] = *templ; - plane_templ[i].format = util_format_get_plane_format(templ->format, i); - plane_templ[i].width0 = util_format_get_plane_width(templ->format, i, templ->width0); - plane_templ[i].height0 = util_format_get_plane_height(templ->format, i, templ->height0); + /* Compute texture or plane layouts and offsets. */ + for (unsigned i = 0; i < num_planes; i++) { + plane_templ[i] = *templ; + plane_templ[i].format = util_format_get_plane_format(templ->format, i); + plane_templ[i].width0 = util_format_get_plane_width(templ->format, i, templ->width0); + plane_templ[i].height0 = util_format_get_plane_height(templ->format, i, templ->height0); - /* Multi-plane allocations need PIPE_BIND_SHARED, because we can't - * reallocate the storage to add PIPE_BIND_SHARED, because it's - * shared by 3 pipe_resources. - */ - if (num_planes > 1) - plane_templ[i].bind |= PIPE_BIND_SHARED; + /* Multi-plane allocations need PIPE_BIND_SHARED, because we can't + * reallocate the storage to add PIPE_BIND_SHARED, because it's + * shared by 3 pipe_resources. + */ + if (num_planes > 1) + plane_templ[i].bind |= PIPE_BIND_SHARED; - if (si_init_surface(sscreen, &surface[i], &plane_templ[i], - tile_mode, 0, false, - plane_templ[i].bind & PIPE_BIND_SCANOUT, - is_flushed_depth, tc_compatible_htile)) - return NULL; + if (si_init_surface(sscreen, &surface[i], &plane_templ[i], + tile_mode, 0, false, + plane_templ[i].bind & PIPE_BIND_SCANOUT, + is_flushed_depth, tc_compatible_htile)) + return NULL; - plane_offset[i] = align64(total_size, surface[i].surf_alignment); - total_size = plane_offset[i] + surface[i].total_size; - max_alignment = MAX2(max_alignment, surface[i].surf_alignment); - } + plane_offset[i] = align64(total_size, surface[i].surf_alignment); + total_size = plane_offset[i] + surface[i].total_size; + max_alignment = MAX2(max_alignment, surface[i].surf_alignment); + } - struct si_texture *plane0 = NULL, *last_plane = NULL; + struct si_texture *plane0 = NULL, *last_plane = NULL; - for (unsigned i = 0; i < num_planes; i++) { - struct si_texture *tex = - si_texture_create_object(screen, &plane_templ[i], &surface[i], - plane0, NULL, plane_offset[i], - total_size, max_alignment); - if (!tex) { - si_texture_reference(&plane0, NULL); - return NULL; - } + for (unsigned i = 0; i < num_planes; i++) { + struct si_texture *tex = + si_texture_create_object(screen, &plane_templ[i], &surface[i], + plane0, NULL, plane_offset[i], + total_size, max_alignment); + if (!tex) { + si_texture_reference(&plane0, NULL); + return NULL; + } - tex->plane_index = i; - tex->num_planes = num_planes; + tex->plane_index = i; + tex->num_planes = num_planes; - if (!plane0) { - plane0 = last_plane = tex; - } else { - last_plane->buffer.b.b.next = &tex->buffer.b.b; - last_plane = tex; - } - } + if (!plane0) { + plane0 = last_plane = tex; + } else { + last_plane->buffer.b.b.next = &tex->buffer.b.b; + last_plane = tex; + } + } - return (struct pipe_resource *)plane0; + return (struct pipe_resource *)plane0; } static struct pipe_resource *si_texture_from_winsys_buffer(struct si_screen *sscreen, - const struct pipe_resource *templ, - struct pb_buffer *buf, - unsigned stride, - unsigned offset, - unsigned usage, - bool dedicated) + const struct pipe_resource *templ, + struct pb_buffer *buf, + unsigned stride, + unsigned offset, + unsigned usage, + bool dedicated) { - enum radeon_surf_mode array_mode; - struct radeon_surf surface = {}; - struct radeon_bo_metadata metadata = {}; - struct si_texture *tex; - bool is_scanout; - int r; + enum radeon_surf_mode array_mode; + struct radeon_surf surface = {}; + struct radeon_bo_metadata metadata = {}; + struct si_texture *tex; + bool is_scanout; + int r; - /* Ignore metadata for non-zero planes. */ - if (offset != 0) - dedicated = false; + /* Ignore metadata for non-zero planes. */ + if (offset != 0) + dedicated = false; - if (dedicated) { - sscreen->ws->buffer_get_metadata(buf, &metadata); - si_get_display_metadata(sscreen, &surface, &metadata, - &array_mode, &is_scanout); - } else { - /** - * The bo metadata is unset for un-dedicated images. So we fall - * back to linear. See answer to question 5 of the - * VK_KHX_external_memory spec for some details. - * - * It is possible that this case isn't going to work if the - * surface pitch isn't correctly aligned by default. - * - * In order to support it correctly we require multi-image - * metadata to be syncrhonized between radv and radeonsi. The - * semantics of associating multiple image metadata to a memory - * object on the vulkan export side are not concretely defined - * either. - * - * All the use cases we are aware of at the moment for memory - * objects use dedicated allocations. So lets keep the initial - * implementation simple. - * - * A possible alternative is to attempt to reconstruct the - * tiling information when the TexParameter TEXTURE_TILING_EXT - * is set. - */ - array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED; - is_scanout = false; - } + if (dedicated) { + sscreen->ws->buffer_get_metadata(buf, &metadata); + si_get_display_metadata(sscreen, &surface, &metadata, + &array_mode, &is_scanout); + } else { + /** + * The bo metadata is unset for un-dedicated images. So we fall + * back to linear. See answer to question 5 of the + * VK_KHX_external_memory spec for some details. + * + * It is possible that this case isn't going to work if the + * surface pitch isn't correctly aligned by default. + * + * In order to support it correctly we require multi-image + * metadata to be syncrhonized between radv and radeonsi. The + * semantics of associating multiple image metadata to a memory + * object on the vulkan export side are not concretely defined + * either. + * + * All the use cases we are aware of at the moment for memory + * objects use dedicated allocations. So lets keep the initial + * implementation simple. + * + * A possible alternative is to attempt to reconstruct the + * tiling information when the TexParameter TEXTURE_TILING_EXT + * is set. + */ + array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED; + is_scanout = false; + } - r = si_init_surface(sscreen, &surface, templ, - array_mode, stride, true, is_scanout, - false, false); - if (r) - return NULL; + r = si_init_surface(sscreen, &surface, templ, + array_mode, stride, true, is_scanout, + false, false); + if (r) + return NULL; - tex = si_texture_create_object(&sscreen->b, templ, &surface, NULL, buf, - offset, 0, 0); - if (!tex) - return NULL; + tex = si_texture_create_object(&sscreen->b, templ, &surface, NULL, buf, + offset, 0, 0); + if (!tex) + return NULL; - tex->buffer.b.is_shared = true; - tex->buffer.external_usage = usage; - tex->num_planes = 1; + tex->buffer.b.is_shared = true; + tex->buffer.external_usage = usage; + tex->num_planes = 1; - if (!si_read_tex_bo_metadata(sscreen, tex, offset, &metadata)) { - si_texture_reference(&tex, NULL); - return NULL; - } + if (!si_read_tex_bo_metadata(sscreen, tex, offset, &metadata)) { + si_texture_reference(&tex, NULL); + return NULL; + } - /* Displayable DCC requires an explicit flush. */ - if (dedicated && offset == 0 && - !(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) && - si_has_displayable_dcc(tex)) { - /* TODO: do we need to decompress DCC? */ - if (si_texture_discard_dcc(sscreen, tex)) { - /* Update BO metadata after disabling DCC. */ - si_set_tex_bo_metadata(sscreen, tex); - } - } + /* Displayable DCC requires an explicit flush. */ + if (dedicated && offset == 0 && + !(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) && + si_has_displayable_dcc(tex)) { + /* TODO: do we need to decompress DCC? */ + if (si_texture_discard_dcc(sscreen, tex)) { + /* Update BO metadata after disabling DCC. */ + si_set_tex_bo_metadata(sscreen, tex); + } + } - assert(tex->surface.tile_swizzle == 0); - return &tex->buffer.b.b; + assert(tex->surface.tile_swizzle == 0); + return &tex->buffer.b.b; } static struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen, - const struct pipe_resource *templ, - struct winsys_handle *whandle, - unsigned usage) + const struct pipe_resource *templ, + struct winsys_handle *whandle, + unsigned usage) { - struct si_screen *sscreen = (struct si_screen*)screen; - struct pb_buffer *buf = NULL; + struct si_screen *sscreen = (struct si_screen*)screen; + struct pb_buffer *buf = NULL; - /* Support only 2D textures without mipmaps */ - if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT && - templ->target != PIPE_TEXTURE_2D_ARRAY) || - templ->last_level != 0) - return NULL; + /* Support only 2D textures without mipmaps */ + if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT && + templ->target != PIPE_TEXTURE_2D_ARRAY) || + templ->last_level != 0) + return NULL; - buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle, - sscreen->info.max_alignment); - if (!buf) - return NULL; + buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle, + sscreen->info.max_alignment); + if (!buf) + return NULL; - return si_texture_from_winsys_buffer(sscreen, templ, buf, - whandle->stride, whandle->offset, - usage, true); + return si_texture_from_winsys_buffer(sscreen, templ, buf, + whandle->stride, whandle->offset, + usage, true); } bool si_init_flushed_depth_texture(struct pipe_context *ctx, - struct pipe_resource *texture) + struct pipe_resource *texture) { - struct si_texture *tex = (struct si_texture*)texture; - struct pipe_resource resource; - enum pipe_format pipe_format = texture->format; + struct si_texture *tex = (struct si_texture*)texture; + struct pipe_resource resource; + enum pipe_format pipe_format = texture->format; - assert(!tex->flushed_depth_texture); + assert(!tex->flushed_depth_texture); - if (!tex->can_sample_z && tex->can_sample_s) { - switch (pipe_format) { - case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: - /* Save memory by not allocating the S plane. */ - pipe_format = PIPE_FORMAT_Z32_FLOAT; - break; - case PIPE_FORMAT_Z24_UNORM_S8_UINT: - case PIPE_FORMAT_S8_UINT_Z24_UNORM: - /* Save memory bandwidth by not copying the - * stencil part during flush. - * - * This potentially increases memory bandwidth - * if an application uses both Z and S texturing - * simultaneously (a flushed Z24S8 texture - * would be stored compactly), but how often - * does that really happen? - */ - pipe_format = PIPE_FORMAT_Z24X8_UNORM; - break; - default:; - } - } else if (!tex->can_sample_s && tex->can_sample_z) { - assert(util_format_has_stencil(util_format_description(pipe_format))); + if (!tex->can_sample_z && tex->can_sample_s) { + switch (pipe_format) { + case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: + /* Save memory by not allocating the S plane. */ + pipe_format = PIPE_FORMAT_Z32_FLOAT; + break; + case PIPE_FORMAT_Z24_UNORM_S8_UINT: + case PIPE_FORMAT_S8_UINT_Z24_UNORM: + /* Save memory bandwidth by not copying the + * stencil part during flush. + * + * This potentially increases memory bandwidth + * if an application uses both Z and S texturing + * simultaneously (a flushed Z24S8 texture + * would be stored compactly), but how often + * does that really happen? + */ + pipe_format = PIPE_FORMAT_Z24X8_UNORM; + break; + default:; + } + } else if (!tex->can_sample_s && tex->can_sample_z) { + assert(util_format_has_stencil(util_format_description(pipe_format))); - /* DB->CB copies to an 8bpp surface don't work. */ - pipe_format = PIPE_FORMAT_X24S8_UINT; - } + /* DB->CB copies to an 8bpp surface don't work. */ + pipe_format = PIPE_FORMAT_X24S8_UINT; + } - memset(&resource, 0, sizeof(resource)); - resource.target = texture->target; - resource.format = pipe_format; - resource.width0 = texture->width0; - resource.height0 = texture->height0; - resource.depth0 = texture->depth0; - resource.array_size = texture->array_size; - resource.last_level = texture->last_level; - resource.nr_samples = texture->nr_samples; - resource.usage = PIPE_USAGE_DEFAULT; - resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL; - resource.flags = texture->flags | SI_RESOURCE_FLAG_FLUSHED_DEPTH; + memset(&resource, 0, sizeof(resource)); + resource.target = texture->target; + resource.format = pipe_format; + resource.width0 = texture->width0; + resource.height0 = texture->height0; + resource.depth0 = texture->depth0; + resource.array_size = texture->array_size; + resource.last_level = texture->last_level; + resource.nr_samples = texture->nr_samples; + resource.usage = PIPE_USAGE_DEFAULT; + resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL; + resource.flags = texture->flags | SI_RESOURCE_FLAG_FLUSHED_DEPTH; - tex->flushed_depth_texture = (struct si_texture *)ctx->screen->resource_create(ctx->screen, &resource); - if (!tex->flushed_depth_texture) { - PRINT_ERR("failed to create temporary texture to hold flushed depth\n"); - return false; - } - return true; + tex->flushed_depth_texture = (struct si_texture *)ctx->screen->resource_create(ctx->screen, &resource); + if (!tex->flushed_depth_texture) { + PRINT_ERR("failed to create temporary texture to hold flushed depth\n"); + return false; + } + return true; } /** @@ -1908,678 +1908,678 @@ bool si_init_flushed_depth_texture(struct pipe_context *ctx, * mipmap level. */ static void si_init_temp_resource_from_box(struct pipe_resource *res, - struct pipe_resource *orig, - const struct pipe_box *box, - unsigned level, unsigned flags) + struct pipe_resource *orig, + const struct pipe_box *box, + unsigned level, unsigned flags) { - memset(res, 0, sizeof(*res)); - res->format = orig->format; - res->width0 = box->width; - res->height0 = box->height; - res->depth0 = 1; - res->array_size = 1; - res->usage = flags & SI_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT; - res->flags = flags; + memset(res, 0, sizeof(*res)); + res->format = orig->format; + res->width0 = box->width; + res->height0 = box->height; + res->depth0 = 1; + res->array_size = 1; + res->usage = flags & SI_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT; + res->flags = flags; - if (flags & SI_RESOURCE_FLAG_TRANSFER && - util_format_is_compressed(orig->format)) { - /* Transfer resources are allocated with linear tiling, which is - * not supported for compressed formats. - */ - unsigned blocksize = - util_format_get_blocksize(orig->format); + if (flags & SI_RESOURCE_FLAG_TRANSFER && + util_format_is_compressed(orig->format)) { + /* Transfer resources are allocated with linear tiling, which is + * not supported for compressed formats. + */ + unsigned blocksize = + util_format_get_blocksize(orig->format); - if (blocksize == 8) { - res->format = PIPE_FORMAT_R16G16B16A16_UINT; - } else { - assert(blocksize == 16); - res->format = PIPE_FORMAT_R32G32B32A32_UINT; - } + if (blocksize == 8) { + res->format = PIPE_FORMAT_R16G16B16A16_UINT; + } else { + assert(blocksize == 16); + res->format = PIPE_FORMAT_R32G32B32A32_UINT; + } - res->width0 = util_format_get_nblocksx(orig->format, box->width); - res->height0 = util_format_get_nblocksy(orig->format, box->height); - } + res->width0 = util_format_get_nblocksx(orig->format, box->width); + res->height0 = util_format_get_nblocksy(orig->format, box->height); + } - /* We must set the correct texture target and dimensions for a 3D box. */ - if (box->depth > 1 && util_max_layer(orig, level) > 0) { - res->target = PIPE_TEXTURE_2D_ARRAY; - res->array_size = box->depth; - } else { - res->target = PIPE_TEXTURE_2D; - } + /* We must set the correct texture target and dimensions for a 3D box. */ + if (box->depth > 1 && util_max_layer(orig, level) > 0) { + res->target = PIPE_TEXTURE_2D_ARRAY; + res->array_size = box->depth; + } else { + res->target = PIPE_TEXTURE_2D; + } } static bool si_can_invalidate_texture(struct si_screen *sscreen, - struct si_texture *tex, - unsigned transfer_usage, - const struct pipe_box *box) + struct si_texture *tex, + unsigned transfer_usage, + const struct pipe_box *box) { - return !tex->buffer.b.is_shared && - !(tex->surface.flags & RADEON_SURF_IMPORTED) && - !(transfer_usage & PIPE_TRANSFER_READ) && - tex->buffer.b.b.last_level == 0 && - util_texrange_covers_whole_level(&tex->buffer.b.b, 0, - box->x, box->y, box->z, - box->width, box->height, - box->depth); + return !tex->buffer.b.is_shared && + !(tex->surface.flags & RADEON_SURF_IMPORTED) && + !(transfer_usage & PIPE_TRANSFER_READ) && + tex->buffer.b.b.last_level == 0 && + util_texrange_covers_whole_level(&tex->buffer.b.b, 0, + box->x, box->y, box->z, + box->width, box->height, + box->depth); } static void si_texture_invalidate_storage(struct si_context *sctx, - struct si_texture *tex) + struct si_texture *tex) { - struct si_screen *sscreen = sctx->screen; + struct si_screen *sscreen = sctx->screen; - /* There is no point in discarding depth and tiled buffers. */ - assert(!tex->is_depth); - assert(tex->surface.is_linear); + /* There is no point in discarding depth and tiled buffers. */ + assert(!tex->is_depth); + assert(tex->surface.is_linear); - /* Reallocate the buffer in the same pipe_resource. */ - si_alloc_resource(sscreen, &tex->buffer); + /* Reallocate the buffer in the same pipe_resource. */ + si_alloc_resource(sscreen, &tex->buffer); - /* Initialize the CMASK base address (needed even without CMASK). */ - tex->cmask_base_address_reg = - (tex->buffer.gpu_address + tex->surface.cmask_offset) >> 8; + /* Initialize the CMASK base address (needed even without CMASK). */ + tex->cmask_base_address_reg = + (tex->buffer.gpu_address + tex->surface.cmask_offset) >> 8; - p_atomic_inc(&sscreen->dirty_tex_counter); + p_atomic_inc(&sscreen->dirty_tex_counter); - sctx->num_alloc_tex_transfer_bytes += tex->surface.total_size; + sctx->num_alloc_tex_transfer_bytes += tex->surface.total_size; } static void *si_texture_transfer_map(struct pipe_context *ctx, - struct pipe_resource *texture, - unsigned level, - unsigned usage, - const struct pipe_box *box, - struct pipe_transfer **ptransfer) + struct pipe_resource *texture, + unsigned level, + unsigned usage, + const struct pipe_box *box, + struct pipe_transfer **ptransfer) { - struct si_context *sctx = (struct si_context*)ctx; - struct si_texture *tex = (struct si_texture*)texture; - struct si_transfer *trans; - struct si_resource *buf; - unsigned offset = 0; - char *map; - bool use_staging_texture = false; + struct si_context *sctx = (struct si_context*)ctx; + struct si_texture *tex = (struct si_texture*)texture; + struct si_transfer *trans; + struct si_resource *buf; + unsigned offset = 0; + char *map; + bool use_staging_texture = false; - assert(!(texture->flags & SI_RESOURCE_FLAG_TRANSFER)); - assert(box->width && box->height && box->depth); + assert(!(texture->flags & SI_RESOURCE_FLAG_TRANSFER)); + assert(box->width && box->height && box->depth); - if (tex->is_depth) { - /* Depth textures use staging unconditionally. */ - use_staging_texture = true; - } else { - /* Degrade the tile mode if we get too many transfers on APUs. - * On dGPUs, the staging texture is always faster. - * Only count uploads that are at least 4x4 pixels large. - */ - if (!sctx->screen->info.has_dedicated_vram && - level == 0 && - box->width >= 4 && box->height >= 4 && - p_atomic_inc_return(&tex->num_level0_transfers) == 10) { - bool can_invalidate = - si_can_invalidate_texture(sctx->screen, tex, - usage, box); + if (tex->is_depth) { + /* Depth textures use staging unconditionally. */ + use_staging_texture = true; + } else { + /* Degrade the tile mode if we get too many transfers on APUs. + * On dGPUs, the staging texture is always faster. + * Only count uploads that are at least 4x4 pixels large. + */ + if (!sctx->screen->info.has_dedicated_vram && + level == 0 && + box->width >= 4 && box->height >= 4 && + p_atomic_inc_return(&tex->num_level0_transfers) == 10) { + bool can_invalidate = + si_can_invalidate_texture(sctx->screen, tex, + usage, box); - si_reallocate_texture_inplace(sctx, tex, - PIPE_BIND_LINEAR, - can_invalidate); - } + si_reallocate_texture_inplace(sctx, tex, + PIPE_BIND_LINEAR, + can_invalidate); + } - /* Tiled textures need to be converted into a linear texture for CPU - * access. The staging texture is always linear and is placed in GART. - * - * Reading from VRAM or GTT WC is slow, always use the staging - * texture in this case. - * - * Use the staging texture for uploads if the underlying BO - * is busy. - */ - if (!tex->surface.is_linear) - use_staging_texture = true; - else if (usage & PIPE_TRANSFER_READ) - use_staging_texture = - tex->buffer.domains & RADEON_DOMAIN_VRAM || - tex->buffer.flags & RADEON_FLAG_GTT_WC; - /* Write & linear only: */ - else if (si_rings_is_buffer_referenced(sctx, tex->buffer.buf, - RADEON_USAGE_READWRITE) || - !sctx->ws->buffer_wait(tex->buffer.buf, 0, - RADEON_USAGE_READWRITE)) { - /* It's busy. */ - if (si_can_invalidate_texture(sctx->screen, tex, - usage, box)) - si_texture_invalidate_storage(sctx, tex); - else - use_staging_texture = true; - } - } + /* Tiled textures need to be converted into a linear texture for CPU + * access. The staging texture is always linear and is placed in GART. + * + * Reading from VRAM or GTT WC is slow, always use the staging + * texture in this case. + * + * Use the staging texture for uploads if the underlying BO + * is busy. + */ + if (!tex->surface.is_linear) + use_staging_texture = true; + else if (usage & PIPE_TRANSFER_READ) + use_staging_texture = + tex->buffer.domains & RADEON_DOMAIN_VRAM || + tex->buffer.flags & RADEON_FLAG_GTT_WC; + /* Write & linear only: */ + else if (si_rings_is_buffer_referenced(sctx, tex->buffer.buf, + RADEON_USAGE_READWRITE) || + !sctx->ws->buffer_wait(tex->buffer.buf, 0, + RADEON_USAGE_READWRITE)) { + /* It's busy. */ + if (si_can_invalidate_texture(sctx->screen, tex, + usage, box)) + si_texture_invalidate_storage(sctx, tex); + else + use_staging_texture = true; + } + } - trans = CALLOC_STRUCT(si_transfer); - if (!trans) - return NULL; - pipe_resource_reference(&trans->b.b.resource, texture); - trans->b.b.level = level; - trans->b.b.usage = usage; - trans->b.b.box = *box; + trans = CALLOC_STRUCT(si_transfer); + if (!trans) + return NULL; + pipe_resource_reference(&trans->b.b.resource, texture); + trans->b.b.level = level; + trans->b.b.usage = usage; + trans->b.b.box = *box; - if (use_staging_texture) { - struct pipe_resource resource; - struct si_texture *staging; + if (use_staging_texture) { + struct pipe_resource resource; + struct si_texture *staging; - si_init_temp_resource_from_box(&resource, texture, box, level, - SI_RESOURCE_FLAG_TRANSFER); - resource.usage = (usage & PIPE_TRANSFER_READ) ? - PIPE_USAGE_STAGING : PIPE_USAGE_STREAM; + si_init_temp_resource_from_box(&resource, texture, box, level, + SI_RESOURCE_FLAG_TRANSFER); + resource.usage = (usage & PIPE_TRANSFER_READ) ? + PIPE_USAGE_STAGING : PIPE_USAGE_STREAM; - /* Since depth-stencil textures don't support linear tiling, - * blit from ZS to color and vice versa. u_blitter will do - * the packing for these formats. - */ - if (tex->is_depth) - resource.format = util_blitter_get_color_format_for_zs(resource.format); + /* Since depth-stencil textures don't support linear tiling, + * blit from ZS to color and vice versa. u_blitter will do + * the packing for these formats. + */ + if (tex->is_depth) + resource.format = util_blitter_get_color_format_for_zs(resource.format); - /* Create the temporary texture. */ - staging = (struct si_texture*)ctx->screen->resource_create(ctx->screen, &resource); - if (!staging) { - PRINT_ERR("failed to create temporary texture to hold untiled copy\n"); - goto fail_trans; - } - trans->staging = &staging->buffer; + /* Create the temporary texture. */ + staging = (struct si_texture*)ctx->screen->resource_create(ctx->screen, &resource); + if (!staging) { + PRINT_ERR("failed to create temporary texture to hold untiled copy\n"); + goto fail_trans; + } + trans->staging = &staging->buffer; - /* Just get the strides. */ - si_texture_get_offset(sctx->screen, staging, 0, NULL, - &trans->b.b.stride, - &trans->b.b.layer_stride); + /* Just get the strides. */ + si_texture_get_offset(sctx->screen, staging, 0, NULL, + &trans->b.b.stride, + &trans->b.b.layer_stride); - if (usage & PIPE_TRANSFER_READ) - si_copy_to_staging_texture(ctx, trans); - else - usage |= PIPE_TRANSFER_UNSYNCHRONIZED; + if (usage & PIPE_TRANSFER_READ) + si_copy_to_staging_texture(ctx, trans); + else + usage |= PIPE_TRANSFER_UNSYNCHRONIZED; - buf = trans->staging; - } else { - /* the resource is mapped directly */ - offset = si_texture_get_offset(sctx->screen, tex, level, box, - &trans->b.b.stride, - &trans->b.b.layer_stride); - buf = &tex->buffer; - } + buf = trans->staging; + } else { + /* the resource is mapped directly */ + offset = si_texture_get_offset(sctx->screen, tex, level, box, + &trans->b.b.stride, + &trans->b.b.layer_stride); + buf = &tex->buffer; + } - /* Always unmap texture CPU mappings on 32-bit architectures, so that - * we don't run out of the CPU address space. - */ - if (sizeof(void*) == 4) - usage |= RADEON_TRANSFER_TEMPORARY; + /* Always unmap texture CPU mappings on 32-bit architectures, so that + * we don't run out of the CPU address space. + */ + if (sizeof(void*) == 4) + usage |= RADEON_TRANSFER_TEMPORARY; - if (!(map = si_buffer_map_sync_with_rings(sctx, buf, usage))) - goto fail_trans; + if (!(map = si_buffer_map_sync_with_rings(sctx, buf, usage))) + goto fail_trans; - *ptransfer = &trans->b.b; - return map + offset; + *ptransfer = &trans->b.b; + return map + offset; fail_trans: - si_resource_reference(&trans->staging, NULL); - pipe_resource_reference(&trans->b.b.resource, NULL); - FREE(trans); - return NULL; + si_resource_reference(&trans->staging, NULL); + pipe_resource_reference(&trans->b.b.resource, NULL); + FREE(trans); + return NULL; } static void si_texture_transfer_unmap(struct pipe_context *ctx, - struct pipe_transfer* transfer) + struct pipe_transfer* transfer) { - struct si_context *sctx = (struct si_context*)ctx; - struct si_transfer *stransfer = (struct si_transfer*)transfer; - struct pipe_resource *texture = transfer->resource; - struct si_texture *tex = (struct si_texture*)texture; + struct si_context *sctx = (struct si_context*)ctx; + struct si_transfer *stransfer = (struct si_transfer*)transfer; + struct pipe_resource *texture = transfer->resource; + struct si_texture *tex = (struct si_texture*)texture; - /* Always unmap texture CPU mappings on 32-bit architectures, so that - * we don't run out of the CPU address space. - */ - if (sizeof(void*) == 4) { - struct si_resource *buf = - stransfer->staging ? stransfer->staging : &tex->buffer; + /* Always unmap texture CPU mappings on 32-bit architectures, so that + * we don't run out of the CPU address space. + */ + if (sizeof(void*) == 4) { + struct si_resource *buf = + stransfer->staging ? stransfer->staging : &tex->buffer; - sctx->ws->buffer_unmap(buf->buf); - } + sctx->ws->buffer_unmap(buf->buf); + } - if ((transfer->usage & PIPE_TRANSFER_WRITE) && stransfer->staging) - si_copy_from_staging_texture(ctx, stransfer); + if ((transfer->usage & PIPE_TRANSFER_WRITE) && stransfer->staging) + si_copy_from_staging_texture(ctx, stransfer); - if (stransfer->staging) { - sctx->num_alloc_tex_transfer_bytes += stransfer->staging->buf->size; - si_resource_reference(&stransfer->staging, NULL); - } + if (stransfer->staging) { + sctx->num_alloc_tex_transfer_bytes += stransfer->staging->buf->size; + si_resource_reference(&stransfer->staging, NULL); + } - /* Heuristic for {upload, draw, upload, draw, ..}: - * - * Flush the gfx IB if we've allocated too much texture storage. - * - * The idea is that we don't want to build IBs that use too much - * memory and put pressure on the kernel memory manager and we also - * want to make temporary and invalidated buffers go idle ASAP to - * decrease the total memory usage or make them reusable. The memory - * usage will be slightly higher than given here because of the buffer - * cache in the winsys. - * - * The result is that the kernel memory manager is never a bottleneck. - */ - if (sctx->num_alloc_tex_transfer_bytes > sctx->screen->info.gart_size / 4) { - si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL); - sctx->num_alloc_tex_transfer_bytes = 0; - } + /* Heuristic for {upload, draw, upload, draw, ..}: + * + * Flush the gfx IB if we've allocated too much texture storage. + * + * The idea is that we don't want to build IBs that use too much + * memory and put pressure on the kernel memory manager and we also + * want to make temporary and invalidated buffers go idle ASAP to + * decrease the total memory usage or make them reusable. The memory + * usage will be slightly higher than given here because of the buffer + * cache in the winsys. + * + * The result is that the kernel memory manager is never a bottleneck. + */ + if (sctx->num_alloc_tex_transfer_bytes > sctx->screen->info.gart_size / 4) { + si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL); + sctx->num_alloc_tex_transfer_bytes = 0; + } - pipe_resource_reference(&transfer->resource, NULL); - FREE(transfer); + pipe_resource_reference(&transfer->resource, NULL); + FREE(transfer); } static const struct u_resource_vtbl si_texture_vtbl = { - NULL, /* get_handle */ - si_texture_destroy, /* resource_destroy */ - si_texture_transfer_map, /* transfer_map */ - u_default_transfer_flush_region, /* transfer_flush_region */ - si_texture_transfer_unmap, /* transfer_unmap */ + NULL, /* get_handle */ + si_texture_destroy, /* resource_destroy */ + si_texture_transfer_map, /* transfer_map */ + u_default_transfer_flush_region, /* transfer_flush_region */ + si_texture_transfer_unmap, /* transfer_unmap */ }; /* Return if it's allowed to reinterpret one format as another with DCC enabled. */ bool vi_dcc_formats_compatible(struct si_screen *sscreen, - enum pipe_format format1, - enum pipe_format format2) + enum pipe_format format1, + enum pipe_format format2) { - const struct util_format_description *desc1, *desc2; + const struct util_format_description *desc1, *desc2; - /* No format change - exit early. */ - if (format1 == format2) - return true; + /* No format change - exit early. */ + if (format1 == format2) + return true; - format1 = si_simplify_cb_format(format1); - format2 = si_simplify_cb_format(format2); + format1 = si_simplify_cb_format(format1); + format2 = si_simplify_cb_format(format2); - /* Check again after format adjustments. */ - if (format1 == format2) - return true; + /* Check again after format adjustments. */ + if (format1 == format2) + return true; - desc1 = util_format_description(format1); - desc2 = util_format_description(format2); + desc1 = util_format_description(format1); + desc2 = util_format_description(format2); - if (desc1->layout != UTIL_FORMAT_LAYOUT_PLAIN || - desc2->layout != UTIL_FORMAT_LAYOUT_PLAIN) - return false; + if (desc1->layout != UTIL_FORMAT_LAYOUT_PLAIN || + desc2->layout != UTIL_FORMAT_LAYOUT_PLAIN) + return false; - /* Float and non-float are totally incompatible. */ - if ((desc1->channel[0].type == UTIL_FORMAT_TYPE_FLOAT) != - (desc2->channel[0].type == UTIL_FORMAT_TYPE_FLOAT)) - return false; + /* Float and non-float are totally incompatible. */ + if ((desc1->channel[0].type == UTIL_FORMAT_TYPE_FLOAT) != + (desc2->channel[0].type == UTIL_FORMAT_TYPE_FLOAT)) + return false; - /* Channel sizes must match across DCC formats. - * Comparing just the first 2 channels should be enough. - */ - if (desc1->channel[0].size != desc2->channel[0].size || - (desc1->nr_channels >= 2 && - desc1->channel[1].size != desc2->channel[1].size)) - return false; + /* Channel sizes must match across DCC formats. + * Comparing just the first 2 channels should be enough. + */ + if (desc1->channel[0].size != desc2->channel[0].size || + (desc1->nr_channels >= 2 && + desc1->channel[1].size != desc2->channel[1].size)) + return false; - /* Everything below is not needed if the driver never uses the DCC - * clear code with the value of 1. - */ + /* Everything below is not needed if the driver never uses the DCC + * clear code with the value of 1. + */ - /* If the clear values are all 1 or all 0, this constraint can be - * ignored. */ - if (vi_alpha_is_on_msb(sscreen, format1) != vi_alpha_is_on_msb(sscreen, format2)) - return false; + /* If the clear values are all 1 or all 0, this constraint can be + * ignored. */ + if (vi_alpha_is_on_msb(sscreen, format1) != vi_alpha_is_on_msb(sscreen, format2)) + return false; - /* Channel types must match if the clear value of 1 is used. - * The type categories are only float, signed, unsigned. - * NORM and INT are always compatible. - */ - if (desc1->channel[0].type != desc2->channel[0].type || - (desc1->nr_channels >= 2 && - desc1->channel[1].type != desc2->channel[1].type)) - return false; + /* Channel types must match if the clear value of 1 is used. + * The type categories are only float, signed, unsigned. + * NORM and INT are always compatible. + */ + if (desc1->channel[0].type != desc2->channel[0].type || + (desc1->nr_channels >= 2 && + desc1->channel[1].type != desc2->channel[1].type)) + return false; - return true; + return true; } bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex, - unsigned level, - enum pipe_format view_format) + unsigned level, + enum pipe_format view_format) { - struct si_texture *stex = (struct si_texture *)tex; + struct si_texture *stex = (struct si_texture *)tex; - return vi_dcc_enabled(stex, level) && - !vi_dcc_formats_compatible((struct si_screen*)tex->screen, - tex->format, view_format); + return vi_dcc_enabled(stex, level) && + !vi_dcc_formats_compatible((struct si_screen*)tex->screen, + tex->format, view_format); } /* This can't be merged with the above function, because * vi_dcc_formats_compatible should be called only when DCC is enabled. */ void vi_disable_dcc_if_incompatible_format(struct si_context *sctx, - struct pipe_resource *tex, - unsigned level, - enum pipe_format view_format) + struct pipe_resource *tex, + unsigned level, + enum pipe_format view_format) { - struct si_texture *stex = (struct si_texture *)tex; + struct si_texture *stex = (struct si_texture *)tex; - if (vi_dcc_formats_are_incompatible(tex, level, view_format)) - if (!si_texture_disable_dcc(sctx, stex)) - si_decompress_dcc(sctx, stex); + if (vi_dcc_formats_are_incompatible(tex, level, view_format)) + if (!si_texture_disable_dcc(sctx, stex)) + si_decompress_dcc(sctx, stex); } struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe, - struct pipe_resource *texture, - const struct pipe_surface *templ, - unsigned width0, unsigned height0, - unsigned width, unsigned height) + struct pipe_resource *texture, + const struct pipe_surface *templ, + unsigned width0, unsigned height0, + unsigned width, unsigned height) { - struct si_surface *surface = CALLOC_STRUCT(si_surface); + struct si_surface *surface = CALLOC_STRUCT(si_surface); - if (!surface) - return NULL; + if (!surface) + return NULL; - assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level)); - assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level)); + assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level)); + assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level)); - pipe_reference_init(&surface->base.reference, 1); - pipe_resource_reference(&surface->base.texture, texture); - surface->base.context = pipe; - surface->base.format = templ->format; - surface->base.width = width; - surface->base.height = height; - surface->base.u = templ->u; + pipe_reference_init(&surface->base.reference, 1); + pipe_resource_reference(&surface->base.texture, texture); + surface->base.context = pipe; + surface->base.format = templ->format; + surface->base.width = width; + surface->base.height = height; + surface->base.u = templ->u; - surface->width0 = width0; - surface->height0 = height0; + surface->width0 = width0; + surface->height0 = height0; - surface->dcc_incompatible = - texture->target != PIPE_BUFFER && - vi_dcc_formats_are_incompatible(texture, templ->u.tex.level, - templ->format); - return &surface->base; + surface->dcc_incompatible = + texture->target != PIPE_BUFFER && + vi_dcc_formats_are_incompatible(texture, templ->u.tex.level, + templ->format); + return &surface->base; } static struct pipe_surface *si_create_surface(struct pipe_context *pipe, - struct pipe_resource *tex, - const struct pipe_surface *templ) + struct pipe_resource *tex, + const struct pipe_surface *templ) { - unsigned level = templ->u.tex.level; - unsigned width = u_minify(tex->width0, level); - unsigned height = u_minify(tex->height0, level); - unsigned width0 = tex->width0; - unsigned height0 = tex->height0; + unsigned level = templ->u.tex.level; + unsigned width = u_minify(tex->width0, level); + unsigned height = u_minify(tex->height0, level); + unsigned width0 = tex->width0; + unsigned height0 = tex->height0; - if (tex->target != PIPE_BUFFER && templ->format != tex->format) { - const struct util_format_description *tex_desc - = util_format_description(tex->format); - const struct util_format_description *templ_desc - = util_format_description(templ->format); + if (tex->target != PIPE_BUFFER && templ->format != tex->format) { + const struct util_format_description *tex_desc + = util_format_description(tex->format); + const struct util_format_description *templ_desc + = util_format_description(templ->format); - assert(tex_desc->block.bits == templ_desc->block.bits); + assert(tex_desc->block.bits == templ_desc->block.bits); - /* Adjust size of surface if and only if the block width or - * height is changed. */ - if (tex_desc->block.width != templ_desc->block.width || - tex_desc->block.height != templ_desc->block.height) { - unsigned nblks_x = util_format_get_nblocksx(tex->format, width); - unsigned nblks_y = util_format_get_nblocksy(tex->format, height); + /* Adjust size of surface if and only if the block width or + * height is changed. */ + if (tex_desc->block.width != templ_desc->block.width || + tex_desc->block.height != templ_desc->block.height) { + unsigned nblks_x = util_format_get_nblocksx(tex->format, width); + unsigned nblks_y = util_format_get_nblocksy(tex->format, height); - width = nblks_x * templ_desc->block.width; - height = nblks_y * templ_desc->block.height; + width = nblks_x * templ_desc->block.width; + height = nblks_y * templ_desc->block.height; - width0 = util_format_get_nblocksx(tex->format, width0); - height0 = util_format_get_nblocksy(tex->format, height0); - } - } + width0 = util_format_get_nblocksx(tex->format, width0); + height0 = util_format_get_nblocksy(tex->format, height0); + } + } - return si_create_surface_custom(pipe, tex, templ, - width0, height0, - width, height); + return si_create_surface_custom(pipe, tex, templ, + width0, height0, + width, height); } static void si_surface_destroy(struct pipe_context *pipe, - struct pipe_surface *surface) + struct pipe_surface *surface) { - pipe_resource_reference(&surface->texture, NULL); - FREE(surface); + pipe_resource_reference(&surface->texture, NULL); + FREE(surface); } unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap) { - const struct util_format_description *desc = util_format_description(format); + const struct util_format_description *desc = util_format_description(format); #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz) - if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */ - return V_028C70_SWAP_STD; + if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */ + return V_028C70_SWAP_STD; - if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) - return ~0U; + if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) + return ~0U; - switch (desc->nr_channels) { - case 1: - if (HAS_SWIZZLE(0,X)) - return V_028C70_SWAP_STD; /* X___ */ - else if (HAS_SWIZZLE(3,X)) - return V_028C70_SWAP_ALT_REV; /* ___X */ - break; - case 2: - if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) || - (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) || - (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y))) - return V_028C70_SWAP_STD; /* XY__ */ - else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) || - (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) || - (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X))) - /* YX__ */ - return (do_endian_swap ? V_028C70_SWAP_STD : V_028C70_SWAP_STD_REV); - else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y)) - return V_028C70_SWAP_ALT; /* X__Y */ - else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X)) - return V_028C70_SWAP_ALT_REV; /* Y__X */ - break; - case 3: - if (HAS_SWIZZLE(0,X)) - return (do_endian_swap ? V_028C70_SWAP_STD_REV : V_028C70_SWAP_STD); - else if (HAS_SWIZZLE(0,Z)) - return V_028C70_SWAP_STD_REV; /* ZYX */ - break; - case 4: - /* check the middle channels, the 1st and 4th channel can be NONE */ - if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z)) { - return V_028C70_SWAP_STD; /* XYZW */ - } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y)) { - return V_028C70_SWAP_STD_REV; /* WZYX */ - } else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X)) { - return V_028C70_SWAP_ALT; /* ZYXW */ - } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W)) { - /* YZWX */ - if (desc->is_array) - return V_028C70_SWAP_ALT_REV; - else - return (do_endian_swap ? V_028C70_SWAP_ALT : V_028C70_SWAP_ALT_REV); - } - break; - } - return ~0U; + switch (desc->nr_channels) { + case 1: + if (HAS_SWIZZLE(0,X)) + return V_028C70_SWAP_STD; /* X___ */ + else if (HAS_SWIZZLE(3,X)) + return V_028C70_SWAP_ALT_REV; /* ___X */ + break; + case 2: + if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) || + (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) || + (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y))) + return V_028C70_SWAP_STD; /* XY__ */ + else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) || + (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) || + (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X))) + /* YX__ */ + return (do_endian_swap ? V_028C70_SWAP_STD : V_028C70_SWAP_STD_REV); + else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y)) + return V_028C70_SWAP_ALT; /* X__Y */ + else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X)) + return V_028C70_SWAP_ALT_REV; /* Y__X */ + break; + case 3: + if (HAS_SWIZZLE(0,X)) + return (do_endian_swap ? V_028C70_SWAP_STD_REV : V_028C70_SWAP_STD); + else if (HAS_SWIZZLE(0,Z)) + return V_028C70_SWAP_STD_REV; /* ZYX */ + break; + case 4: + /* check the middle channels, the 1st and 4th channel can be NONE */ + if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z)) { + return V_028C70_SWAP_STD; /* XYZW */ + } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y)) { + return V_028C70_SWAP_STD_REV; /* WZYX */ + } else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X)) { + return V_028C70_SWAP_ALT; /* ZYXW */ + } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W)) { + /* YZWX */ + if (desc->is_array) + return V_028C70_SWAP_ALT_REV; + else + return (do_endian_swap ? V_028C70_SWAP_ALT : V_028C70_SWAP_ALT_REV); + } + break; + } + return ~0U; } /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */ static void vi_dcc_clean_up_context_slot(struct si_context *sctx, - int slot) + int slot) { - int i; + int i; - if (sctx->dcc_stats[slot].query_active) - vi_separate_dcc_stop_query(sctx, - sctx->dcc_stats[slot].tex); + if (sctx->dcc_stats[slot].query_active) + vi_separate_dcc_stop_query(sctx, + sctx->dcc_stats[slot].tex); - for (i = 0; i < ARRAY_SIZE(sctx->dcc_stats[slot].ps_stats); i++) - if (sctx->dcc_stats[slot].ps_stats[i]) { - sctx->b.destroy_query(&sctx->b, - sctx->dcc_stats[slot].ps_stats[i]); - sctx->dcc_stats[slot].ps_stats[i] = NULL; - } + for (i = 0; i < ARRAY_SIZE(sctx->dcc_stats[slot].ps_stats); i++) + if (sctx->dcc_stats[slot].ps_stats[i]) { + sctx->b.destroy_query(&sctx->b, + sctx->dcc_stats[slot].ps_stats[i]); + sctx->dcc_stats[slot].ps_stats[i] = NULL; + } - si_texture_reference(&sctx->dcc_stats[slot].tex, NULL); + si_texture_reference(&sctx->dcc_stats[slot].tex, NULL); } /** * Return the per-context slot where DCC statistics queries for the texture live. */ static unsigned vi_get_context_dcc_stats_index(struct si_context *sctx, - struct si_texture *tex) + struct si_texture *tex) { - int i, empty_slot = -1; + int i, empty_slot = -1; - /* Remove zombie textures (textures kept alive by this array only). */ - for (i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) - if (sctx->dcc_stats[i].tex && - sctx->dcc_stats[i].tex->buffer.b.b.reference.count == 1) - vi_dcc_clean_up_context_slot(sctx, i); + /* Remove zombie textures (textures kept alive by this array only). */ + for (i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) + if (sctx->dcc_stats[i].tex && + sctx->dcc_stats[i].tex->buffer.b.b.reference.count == 1) + vi_dcc_clean_up_context_slot(sctx, i); - /* Find the texture. */ - for (i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) { - /* Return if found. */ - if (sctx->dcc_stats[i].tex == tex) { - sctx->dcc_stats[i].last_use_timestamp = os_time_get(); - return i; - } + /* Find the texture. */ + for (i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) { + /* Return if found. */ + if (sctx->dcc_stats[i].tex == tex) { + sctx->dcc_stats[i].last_use_timestamp = os_time_get(); + return i; + } - /* Record the first seen empty slot. */ - if (empty_slot == -1 && !sctx->dcc_stats[i].tex) - empty_slot = i; - } + /* Record the first seen empty slot. */ + if (empty_slot == -1 && !sctx->dcc_stats[i].tex) + empty_slot = i; + } - /* Not found. Remove the oldest member to make space in the array. */ - if (empty_slot == -1) { - int oldest_slot = 0; + /* Not found. Remove the oldest member to make space in the array. */ + if (empty_slot == -1) { + int oldest_slot = 0; - /* Find the oldest slot. */ - for (i = 1; i < ARRAY_SIZE(sctx->dcc_stats); i++) - if (sctx->dcc_stats[oldest_slot].last_use_timestamp > - sctx->dcc_stats[i].last_use_timestamp) - oldest_slot = i; + /* Find the oldest slot. */ + for (i = 1; i < ARRAY_SIZE(sctx->dcc_stats); i++) + if (sctx->dcc_stats[oldest_slot].last_use_timestamp > + sctx->dcc_stats[i].last_use_timestamp) + oldest_slot = i; - /* Clean up the oldest slot. */ - vi_dcc_clean_up_context_slot(sctx, oldest_slot); - empty_slot = oldest_slot; - } + /* Clean up the oldest slot. */ + vi_dcc_clean_up_context_slot(sctx, oldest_slot); + empty_slot = oldest_slot; + } - /* Add the texture to the new slot. */ - si_texture_reference(&sctx->dcc_stats[empty_slot].tex, tex); - sctx->dcc_stats[empty_slot].last_use_timestamp = os_time_get(); - return empty_slot; + /* Add the texture to the new slot. */ + si_texture_reference(&sctx->dcc_stats[empty_slot].tex, tex); + sctx->dcc_stats[empty_slot].last_use_timestamp = os_time_get(); + return empty_slot; } static struct pipe_query * vi_create_resuming_pipestats_query(struct si_context *sctx) { - struct si_query_hw *query = (struct si_query_hw*) - sctx->b.create_query(&sctx->b, PIPE_QUERY_PIPELINE_STATISTICS, 0); + struct si_query_hw *query = (struct si_query_hw*) + sctx->b.create_query(&sctx->b, PIPE_QUERY_PIPELINE_STATISTICS, 0); - query->flags |= SI_QUERY_HW_FLAG_BEGIN_RESUMES; - return (struct pipe_query*)query; + query->flags |= SI_QUERY_HW_FLAG_BEGIN_RESUMES; + return (struct pipe_query*)query; } /** * Called when binding a color buffer. */ void vi_separate_dcc_start_query(struct si_context *sctx, - struct si_texture *tex) + struct si_texture *tex) { - unsigned i = vi_get_context_dcc_stats_index(sctx, tex); + unsigned i = vi_get_context_dcc_stats_index(sctx, tex); - assert(!sctx->dcc_stats[i].query_active); + assert(!sctx->dcc_stats[i].query_active); - if (!sctx->dcc_stats[i].ps_stats[0]) - sctx->dcc_stats[i].ps_stats[0] = vi_create_resuming_pipestats_query(sctx); + if (!sctx->dcc_stats[i].ps_stats[0]) + sctx->dcc_stats[i].ps_stats[0] = vi_create_resuming_pipestats_query(sctx); - /* begin or resume the query */ - sctx->b.begin_query(&sctx->b, sctx->dcc_stats[i].ps_stats[0]); - sctx->dcc_stats[i].query_active = true; + /* begin or resume the query */ + sctx->b.begin_query(&sctx->b, sctx->dcc_stats[i].ps_stats[0]); + sctx->dcc_stats[i].query_active = true; } /** * Called when unbinding a color buffer. */ void vi_separate_dcc_stop_query(struct si_context *sctx, - struct si_texture *tex) + struct si_texture *tex) { - unsigned i = vi_get_context_dcc_stats_index(sctx, tex); + unsigned i = vi_get_context_dcc_stats_index(sctx, tex); - assert(sctx->dcc_stats[i].query_active); - assert(sctx->dcc_stats[i].ps_stats[0]); + assert(sctx->dcc_stats[i].query_active); + assert(sctx->dcc_stats[i].ps_stats[0]); - /* pause or end the query */ - sctx->b.end_query(&sctx->b, sctx->dcc_stats[i].ps_stats[0]); - sctx->dcc_stats[i].query_active = false; + /* pause or end the query */ + sctx->b.end_query(&sctx->b, sctx->dcc_stats[i].ps_stats[0]); + sctx->dcc_stats[i].query_active = false; } static bool vi_should_enable_separate_dcc(struct si_texture *tex) { - /* The minimum number of fullscreen draws per frame that is required - * to enable DCC. */ - return tex->ps_draw_ratio + tex->num_slow_clears >= 5; + /* The minimum number of fullscreen draws per frame that is required + * to enable DCC. */ + return tex->ps_draw_ratio + tex->num_slow_clears >= 5; } /* Called by fast clear. */ void vi_separate_dcc_try_enable(struct si_context *sctx, - struct si_texture *tex) + struct si_texture *tex) { - /* The intent is to use this with shared displayable back buffers, - * but it's not strictly limited only to them. - */ - if (!tex->buffer.b.is_shared || - !(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) || - tex->buffer.b.b.target != PIPE_TEXTURE_2D || - tex->buffer.b.b.last_level > 0 || - !tex->surface.dcc_size || - sctx->screen->debug_flags & DBG(NO_DCC) || - sctx->screen->debug_flags & DBG(NO_DCC_FB)) - return; + /* The intent is to use this with shared displayable back buffers, + * but it's not strictly limited only to them. + */ + if (!tex->buffer.b.is_shared || + !(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) || + tex->buffer.b.b.target != PIPE_TEXTURE_2D || + tex->buffer.b.b.last_level > 0 || + !tex->surface.dcc_size || + sctx->screen->debug_flags & DBG(NO_DCC) || + sctx->screen->debug_flags & DBG(NO_DCC_FB)) + return; - assert(sctx->chip_class >= GFX8); + assert(sctx->chip_class >= GFX8); - if (tex->surface.dcc_offset) - return; /* already enabled */ + if (tex->surface.dcc_offset) + return; /* already enabled */ - /* Enable the DCC stat gathering. */ - if (!tex->dcc_gather_statistics) { - tex->dcc_gather_statistics = true; - vi_separate_dcc_start_query(sctx, tex); - } + /* Enable the DCC stat gathering. */ + if (!tex->dcc_gather_statistics) { + tex->dcc_gather_statistics = true; + vi_separate_dcc_start_query(sctx, tex); + } - if (!vi_should_enable_separate_dcc(tex)) - return; /* stats show that DCC decompression is too expensive */ + if (!vi_should_enable_separate_dcc(tex)) + return; /* stats show that DCC decompression is too expensive */ - assert(tex->surface.num_dcc_levels); - assert(!tex->dcc_separate_buffer); + assert(tex->surface.num_dcc_levels); + assert(!tex->dcc_separate_buffer); - si_texture_discard_cmask(sctx->screen, tex); + si_texture_discard_cmask(sctx->screen, tex); - /* Get a DCC buffer. */ - if (tex->last_dcc_separate_buffer) { - assert(tex->dcc_gather_statistics); - assert(!tex->dcc_separate_buffer); - tex->dcc_separate_buffer = tex->last_dcc_separate_buffer; - tex->last_dcc_separate_buffer = NULL; - } else { - tex->dcc_separate_buffer = - si_aligned_buffer_create(sctx->b.screen, - SI_RESOURCE_FLAG_UNMAPPABLE, - PIPE_USAGE_DEFAULT, - tex->surface.dcc_size, - tex->surface.dcc_alignment); - if (!tex->dcc_separate_buffer) - return; - } + /* Get a DCC buffer. */ + if (tex->last_dcc_separate_buffer) { + assert(tex->dcc_gather_statistics); + assert(!tex->dcc_separate_buffer); + tex->dcc_separate_buffer = tex->last_dcc_separate_buffer; + tex->last_dcc_separate_buffer = NULL; + } else { + tex->dcc_separate_buffer = + si_aligned_buffer_create(sctx->b.screen, + SI_RESOURCE_FLAG_UNMAPPABLE, + PIPE_USAGE_DEFAULT, + tex->surface.dcc_size, + tex->surface.dcc_alignment); + if (!tex->dcc_separate_buffer) + return; + } - /* dcc_offset is the absolute GPUVM address. */ - tex->surface.dcc_offset = tex->dcc_separate_buffer->gpu_address; + /* dcc_offset is the absolute GPUVM address. */ + tex->surface.dcc_offset = tex->dcc_separate_buffer->gpu_address; - /* no need to flag anything since this is called by fast clear that - * flags framebuffer state - */ + /* no need to flag anything since this is called by fast clear that + * flags framebuffer state + */ } /** @@ -2587,156 +2587,156 @@ void vi_separate_dcc_try_enable(struct si_context *sctx, * takes place. */ void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx, - struct si_texture *tex) + struct si_texture *tex) { - struct si_context *sctx = (struct si_context*)ctx; - struct pipe_query *tmp; - unsigned i = vi_get_context_dcc_stats_index(sctx, tex); - bool query_active = sctx->dcc_stats[i].query_active; - bool disable = false; + struct si_context *sctx = (struct si_context*)ctx; + struct pipe_query *tmp; + unsigned i = vi_get_context_dcc_stats_index(sctx, tex); + bool query_active = sctx->dcc_stats[i].query_active; + bool disable = false; - if (sctx->dcc_stats[i].ps_stats[2]) { - union pipe_query_result result; + if (sctx->dcc_stats[i].ps_stats[2]) { + union pipe_query_result result; - /* Read the results. */ - struct pipe_query *query = sctx->dcc_stats[i].ps_stats[2]; - ctx->get_query_result(ctx, query, - true, &result); - si_query_buffer_reset(sctx, &((struct si_query_hw*)query)->buffer); + /* Read the results. */ + struct pipe_query *query = sctx->dcc_stats[i].ps_stats[2]; + ctx->get_query_result(ctx, query, + true, &result); + si_query_buffer_reset(sctx, &((struct si_query_hw*)query)->buffer); - /* Compute the approximate number of fullscreen draws. */ - tex->ps_draw_ratio = - result.pipeline_statistics.ps_invocations / - (tex->buffer.b.b.width0 * tex->buffer.b.b.height0); - sctx->last_tex_ps_draw_ratio = tex->ps_draw_ratio; + /* Compute the approximate number of fullscreen draws. */ + tex->ps_draw_ratio = + result.pipeline_statistics.ps_invocations / + (tex->buffer.b.b.width0 * tex->buffer.b.b.height0); + sctx->last_tex_ps_draw_ratio = tex->ps_draw_ratio; - disable = tex->dcc_separate_buffer && - !vi_should_enable_separate_dcc(tex); - } + disable = tex->dcc_separate_buffer && + !vi_should_enable_separate_dcc(tex); + } - tex->num_slow_clears = 0; + tex->num_slow_clears = 0; - /* stop the statistics query for ps_stats[0] */ - if (query_active) - vi_separate_dcc_stop_query(sctx, tex); + /* stop the statistics query for ps_stats[0] */ + if (query_active) + vi_separate_dcc_stop_query(sctx, tex); - /* Move the queries in the queue by one. */ - tmp = sctx->dcc_stats[i].ps_stats[2]; - sctx->dcc_stats[i].ps_stats[2] = sctx->dcc_stats[i].ps_stats[1]; - sctx->dcc_stats[i].ps_stats[1] = sctx->dcc_stats[i].ps_stats[0]; - sctx->dcc_stats[i].ps_stats[0] = tmp; + /* Move the queries in the queue by one. */ + tmp = sctx->dcc_stats[i].ps_stats[2]; + sctx->dcc_stats[i].ps_stats[2] = sctx->dcc_stats[i].ps_stats[1]; + sctx->dcc_stats[i].ps_stats[1] = sctx->dcc_stats[i].ps_stats[0]; + sctx->dcc_stats[i].ps_stats[0] = tmp; - /* create and start a new query as ps_stats[0] */ - if (query_active) - vi_separate_dcc_start_query(sctx, tex); + /* create and start a new query as ps_stats[0] */ + if (query_active) + vi_separate_dcc_start_query(sctx, tex); - if (disable) { - assert(!tex->last_dcc_separate_buffer); - tex->last_dcc_separate_buffer = tex->dcc_separate_buffer; - tex->dcc_separate_buffer = NULL; - tex->surface.dcc_offset = 0; - /* no need to flag anything since this is called after - * decompression that re-sets framebuffer state - */ - } + if (disable) { + assert(!tex->last_dcc_separate_buffer); + tex->last_dcc_separate_buffer = tex->dcc_separate_buffer; + tex->dcc_separate_buffer = NULL; + tex->surface.dcc_offset = 0; + /* no need to flag anything since this is called after + * decompression that re-sets framebuffer state + */ + } } static struct pipe_memory_object * si_memobj_from_handle(struct pipe_screen *screen, - struct winsys_handle *whandle, - bool dedicated) + struct winsys_handle *whandle, + bool dedicated) { - struct si_screen *sscreen = (struct si_screen*)screen; - struct si_memory_object *memobj = CALLOC_STRUCT(si_memory_object); - struct pb_buffer *buf = NULL; + struct si_screen *sscreen = (struct si_screen*)screen; + struct si_memory_object *memobj = CALLOC_STRUCT(si_memory_object); + struct pb_buffer *buf = NULL; - if (!memobj) - return NULL; + if (!memobj) + return NULL; - buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle, - sscreen->info.max_alignment); - if (!buf) { - free(memobj); - return NULL; - } + buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle, + sscreen->info.max_alignment); + if (!buf) { + free(memobj); + return NULL; + } - memobj->b.dedicated = dedicated; - memobj->buf = buf; - memobj->stride = whandle->stride; + memobj->b.dedicated = dedicated; + memobj->buf = buf; + memobj->stride = whandle->stride; - return (struct pipe_memory_object *)memobj; + return (struct pipe_memory_object *)memobj; } static void si_memobj_destroy(struct pipe_screen *screen, - struct pipe_memory_object *_memobj) + struct pipe_memory_object *_memobj) { - struct si_memory_object *memobj = (struct si_memory_object *)_memobj; + struct si_memory_object *memobj = (struct si_memory_object *)_memobj; - pb_reference(&memobj->buf, NULL); - free(memobj); + pb_reference(&memobj->buf, NULL); + free(memobj); } static struct pipe_resource * si_texture_from_memobj(struct pipe_screen *screen, - const struct pipe_resource *templ, - struct pipe_memory_object *_memobj, - uint64_t offset) + const struct pipe_resource *templ, + struct pipe_memory_object *_memobj, + uint64_t offset) { - struct si_screen *sscreen = (struct si_screen*)screen; - struct si_memory_object *memobj = (struct si_memory_object *)_memobj; - struct pipe_resource *tex = - si_texture_from_winsys_buffer(sscreen, templ, memobj->buf, - memobj->stride, offset, - PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE | - PIPE_HANDLE_USAGE_SHADER_WRITE, - memobj->b.dedicated); - if (!tex) - return NULL; + struct si_screen *sscreen = (struct si_screen*)screen; + struct si_memory_object *memobj = (struct si_memory_object *)_memobj; + struct pipe_resource *tex = + si_texture_from_winsys_buffer(sscreen, templ, memobj->buf, + memobj->stride, offset, + PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE | + PIPE_HANDLE_USAGE_SHADER_WRITE, + memobj->b.dedicated); + if (!tex) + return NULL; - /* si_texture_from_winsys_buffer doesn't increment refcount of - * memobj->buf, so increment it here. - */ - struct pb_buffer *buf = NULL; - pb_reference(&buf, memobj->buf); - return tex; + /* si_texture_from_winsys_buffer doesn't increment refcount of + * memobj->buf, so increment it here. + */ + struct pb_buffer *buf = NULL; + pb_reference(&buf, memobj->buf); + return tex; } static bool si_check_resource_capability(struct pipe_screen *screen, - struct pipe_resource *resource, - unsigned bind) + struct pipe_resource *resource, + unsigned bind) { - struct si_texture *tex = (struct si_texture*)resource; + struct si_texture *tex = (struct si_texture*)resource; - /* Buffers only support the linear flag. */ - if (resource->target == PIPE_BUFFER) - return (bind & ~PIPE_BIND_LINEAR) == 0; + /* Buffers only support the linear flag. */ + if (resource->target == PIPE_BUFFER) + return (bind & ~PIPE_BIND_LINEAR) == 0; - if (bind & PIPE_BIND_LINEAR && !tex->surface.is_linear) - return false; + if (bind & PIPE_BIND_LINEAR && !tex->surface.is_linear) + return false; - if (bind & PIPE_BIND_SCANOUT && !tex->surface.is_displayable) - return false; + if (bind & PIPE_BIND_SCANOUT && !tex->surface.is_displayable) + return false; - /* TODO: PIPE_BIND_CURSOR - do we care? */ - return true; + /* TODO: PIPE_BIND_CURSOR - do we care? */ + return true; } void si_init_screen_texture_functions(struct si_screen *sscreen) { - sscreen->b.resource_from_handle = si_texture_from_handle; - sscreen->b.resource_get_handle = si_texture_get_handle; - sscreen->b.resource_get_param = si_resource_get_param; - sscreen->b.resource_get_info = si_texture_get_info; - sscreen->b.resource_from_memobj = si_texture_from_memobj; - sscreen->b.memobj_create_from_handle = si_memobj_from_handle; - sscreen->b.memobj_destroy = si_memobj_destroy; - sscreen->b.check_resource_capability = si_check_resource_capability; + sscreen->b.resource_from_handle = si_texture_from_handle; + sscreen->b.resource_get_handle = si_texture_get_handle; + sscreen->b.resource_get_param = si_resource_get_param; + sscreen->b.resource_get_info = si_texture_get_info; + sscreen->b.resource_from_memobj = si_texture_from_memobj; + sscreen->b.memobj_create_from_handle = si_memobj_from_handle; + sscreen->b.memobj_destroy = si_memobj_destroy; + sscreen->b.check_resource_capability = si_check_resource_capability; } void si_init_context_texture_functions(struct si_context *sctx) { - sctx->b.create_surface = si_create_surface; - sctx->b.surface_destroy = si_surface_destroy; + sctx->b.create_surface = si_create_surface; + sctx->b.surface_destroy = si_surface_destroy; }