diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 3796c0c2f38..1654fbe6220 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1721,6 +1721,26 @@ radv_pipeline_init_rasterization_info(struct radv_graphics_pipeline *pipeline,
    return info;
 }
 
+static struct radv_discard_rectangle_info
+radv_pipeline_init_discard_rectangle_info(struct radv_graphics_pipeline *pipeline,
+                                          const VkGraphicsPipelineCreateInfo *pCreateInfo)
+{
+   const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
+      vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
+   struct radv_discard_rectangle_info info = {0};
+
+   if (discard_rectangle_info) {
+      info.mode = discard_rectangle_info->discardRectangleMode;
+      if (!(pipeline->dynamic_states & RADV_DYNAMIC_DISCARD_RECTANGLE)) {
+         typed_memcpy(info.rects, discard_rectangle_info->pDiscardRectangles,
+                      discard_rectangle_info->discardRectangleCount);
+      }
+      info.count = discard_rectangle_info->discardRectangleCount;
+   }
+
+   return info;
+}
+
 static struct radv_multisample_info
 radv_pipeline_init_multisample_info(struct radv_graphics_pipeline *pipeline,
                                     const VkGraphicsPipelineCreateInfo *pCreateInfo)
@@ -1898,6 +1918,7 @@ radv_pipeline_init_graphics_info(struct radv_graphics_pipeline *pipeline,
    info.ts = radv_pipeline_init_tessellation_info(pipeline, pCreateInfo);
    info.vp = radv_pipeline_init_viewport_info(pipeline, pCreateInfo);
    info.rs = radv_pipeline_init_rasterization_info(pipeline, pCreateInfo);
+   info.dr = radv_pipeline_init_discard_rectangle_info(pipeline, pCreateInfo);
 
    info.ms = radv_pipeline_init_multisample_info(pipeline, pCreateInfo);
    info.ds = radv_pipeline_init_depth_stencil_info(pipeline, pCreateInfo);
@@ -2071,14 +2092,10 @@ radv_pipeline_init_dynamic_state(struct radv_graphics_pipeline *pipeline,
       }
    }
 
-   const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
-      vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
    if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
-      dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
+      dynamic->discard_rectangle.count = info->dr.count;
       if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
-         typed_memcpy(dynamic->discard_rectangle.rectangles,
-                      discard_rectangle_info->pDiscardRectangles,
-                      discard_rectangle_info->discardRectangleCount);
+         typed_memcpy(dynamic->discard_rectangle.rectangles, info->dr.rects, info->dr.count);
       }
    }
 
@@ -6521,13 +6538,11 @@ radv_pipeline_emit_vgt_shader_config(struct radeon_cmdbuf *ctx_cs,
 
 static void
 radv_pipeline_emit_cliprect_rule(struct radeon_cmdbuf *ctx_cs,
-                                 const VkGraphicsPipelineCreateInfo *pCreateInfo)
+                                 const struct radv_graphics_pipeline_info *info)
 {
-   const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
-      vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
    uint32_t cliprect_rule = 0;
 
-   if (!discard_rectangle_info) {
+   if (!info->dr.count) {
       cliprect_rule = 0xffff;
    } else {
       for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
@@ -6536,16 +6551,12 @@ radv_pipeline_emit_cliprect_rule(struct radeon_cmdbuf *ctx_cs,
           * the pixel is contained should pass the cliprect
           * test.
           */
-         unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
+         unsigned relevant_subset = i & ((1u << info->dr.count) - 1);
 
-         if (discard_rectangle_info->discardRectangleMode ==
-                VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
-             !relevant_subset)
+         if (info->dr.mode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT && !relevant_subset)
             continue;
 
-         if (discard_rectangle_info->discardRectangleMode ==
-                VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
-             relevant_subset)
+         if (info->dr.mode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT && relevant_subset)
             continue;
 
          cliprect_rule |= 1u << i;
@@ -6721,7 +6732,7 @@ radv_pipeline_emit_pm4(struct radv_graphics_pipeline *pipeline,
    radv_pipeline_emit_ps_inputs(ctx_cs, pipeline);
    radv_pipeline_emit_vgt_vertex_reuse(ctx_cs, pipeline);
    radv_pipeline_emit_vgt_shader_config(ctx_cs, pipeline);
-   radv_pipeline_emit_cliprect_rule(ctx_cs, pCreateInfo);
+   radv_pipeline_emit_cliprect_rule(ctx_cs, info);
    radv_pipeline_emit_vgt_gs_out(ctx_cs, pipeline, vgt_gs_out_prim_type);
 
    if (pdevice->rad_info.gfx_level >= GFX10 && !radv_pipeline_has_ngg(pipeline))
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 05c5b976b4b..092e2eb9988 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1920,6 +1920,12 @@ struct radv_rasterization_info {
    VkRasterizationOrderAMD order;
 };
 
+struct radv_discard_rectangle_info {
+   VkDiscardRectangleModeEXT mode;
+   VkRect2D rects[MAX_DISCARD_RECTANGLES];
+   uint32_t count;
+};
+
 struct radv_multisample_info {
    bool sample_shading_enable;
    bool alpha_to_coverage_enable;
@@ -1990,6 +1996,7 @@ struct radv_graphics_pipeline_info {
    struct radv_tessellation_info ts;
    struct radv_viewport_info vp;
    struct radv_rasterization_info rs;
+   struct radv_discard_rectangle_info dr;
 
    struct radv_multisample_info ms;
    struct radv_depth_stencil_info ds;