fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-23 09:00:10 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

radv: Use access helpers for flushing with meta operations.

Browse source 
This way we're properly using the vulkan barrier paradigm instead
of adhoc guessing what caches need to be flushed. This is more robust
for cache policy changes as we now don't have to revisit all the meta
operations all the time.

Note that a barrier has both a src and dst part though. So

barrier:
   flush src
   meta op
   flush dst

becomes

barrier:
  flush barrier src
  flush meta op dst
  meta op
  flush meta op src
  flush barrier dst

And there are some places where we've been able to replace a CB flush
with a shader flush because that is what we'd need according to vulkan rules
(and it turns out that in the cases the CB flush mattered the app will set the
bit in one of the relevant flushes or it was needed as a result of an optimization
that we counter-acted in the previous patch.)

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7202>
This commit is contained in:
Bas Nieuwenhuizen 2020-10-06 03:23:06 +02:00 • committed by Marge Bot
parent dba0a523a0
commit 8f8d72af55
10 changed files with 96 additions and 72 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

47
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -3267,10 +3267,10 @@ static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
} }
} }
static enum radv_cmd_flush_bits enum radv_cmd_flush_bits
radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer, radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
VkAccessFlags src_flags, VkAccessFlags src_flags,
struct radv_image *image) const struct radv_image *image)
{ {
bool flush_CB_meta = true, flush_DB_meta = true; bool flush_CB_meta = true, flush_DB_meta = true;
enum radv_cmd_flush_bits flush_bits = 0; enum radv_cmd_flush_bits flush_bits = 0;
@ -3339,10 +3339,10 @@ radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
return flush_bits; return flush_bits;
} }
static enum radv_cmd_flush_bits enum radv_cmd_flush_bits
radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer, radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
VkAccessFlags dst_flags, VkAccessFlags dst_flags,
struct radv_image *image) const struct radv_image *image)
{ {
bool flush_CB_meta = true, flush_DB_meta = true; bool flush_CB_meta = true, flush_DB_meta = true;
enum radv_cmd_flush_bits flush_bits = 0; enum radv_cmd_flush_bits flush_bits = 0;
@ -6029,15 +6029,14 @@ static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
VkClearDepthStencilValue value = {0}; VkClearDepthStencilValue value = {0};
struct radv_barrier_data barrier = {0}; struct radv_barrier_data barrier = {0};
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
barrier.layout_transitions.init_mask_ram = 1; barrier.layout_transitions.init_mask_ram = 1;
radv_describe_layout_transition(cmd_buffer, &barrier); radv_describe_layout_transition(cmd_buffer, &barrier);
state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value); /* Transitioning from LAYOUT_UNDEFINED layout not everyone is consistent
* in considering previous rendering work for WAW hazards. */
state->flush_bits |= radv_src_access_flush(cmd_buffer, VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT, image);
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META; state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
if (vk_format_is_stencil(image->vk_format)) if (vk_format_is_stencil(image->vk_format))
aspects |= VK_IMAGE_ASPECT_STENCIL_BIT; aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
@ -6096,15 +6095,14 @@ static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
struct radv_cmd_state *state = &cmd_buffer->state; struct radv_cmd_state *state = &cmd_buffer->state;
struct radv_barrier_data barrier = {0}; struct radv_barrier_data barrier = {0};
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
barrier.layout_transitions.init_mask_ram = 1; barrier.layout_transitions.init_mask_ram = 1;
radv_describe_layout_transition(cmd_buffer, &barrier); radv_describe_layout_transition(cmd_buffer, &barrier);
state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value); /* Transitioning from LAYOUT_UNDEFINED layout not everyone is consistent
* in considering previous rendering work for WAW hazards. */
state->flush_bits |= radv_src_access_flush(cmd_buffer, VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT, image);
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META; state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
} }
void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer, void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
@ -6122,15 +6120,14 @@ void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
uint32_t value = fmask_clear_values[log2_samples]; uint32_t value = fmask_clear_values[log2_samples];
struct radv_barrier_data barrier = {0}; struct radv_barrier_data barrier = {0};
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
barrier.layout_transitions.init_mask_ram = 1; barrier.layout_transitions.init_mask_ram = 1;
radv_describe_layout_transition(cmd_buffer, &barrier); radv_describe_layout_transition(cmd_buffer, &barrier);
state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value); /* Transitioning from LAYOUT_UNDEFINED layout not everyone is consistent
* in considering previous rendering work for WAW hazards. */
state->flush_bits |= radv_src_access_flush(cmd_buffer, VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT, image);
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META; state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
} }
void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer, void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
@ -6141,12 +6138,13 @@ void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
struct radv_barrier_data barrier = {0}; struct radv_barrier_data barrier = {0};
unsigned size = 0; unsigned size = 0;
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
barrier.layout_transitions.init_mask_ram = 1; barrier.layout_transitions.init_mask_ram = 1;
radv_describe_layout_transition(cmd_buffer, &barrier); radv_describe_layout_transition(cmd_buffer, &barrier);
/* Transitioning from LAYOUT_UNDEFINED layout not everyone is consistent
* in considering previous rendering work for WAW hazards. */
state->flush_bits |= radv_src_access_flush(cmd_buffer, VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT, image);
state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value); state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) { if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
@ -6170,15 +6168,12 @@ void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
/* Initialize the mipmap levels without DCC. */ /* Initialize the mipmap levels without DCC. */
if (size != image->planes[0].surface.dcc_size) { if (size != image->planes[0].surface.dcc_size) {
state->flush_bits |= state->flush_bits |=
radv_fill_buffer(cmd_buffer, image->bo, radv_fill_buffer(cmd_buffer, image, image->bo,
image->offset + image->planes[0].surface.dcc_offset + size, image->offset + image->planes[0].surface.dcc_offset + size,
image->planes[0].surface.dcc_size - size, image->planes[0].surface.dcc_size - size,
0xffffffff); 0xffffffff);
} }
} }
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
} }
/** /**

11
src/amd/vulkan/radv_meta_buffer.c
View file

@ -351,8 +351,8 @@ static void copy_buffer_shader(struct radv_cmd_buffer *cmd_buffer,
radv_meta_restore(&saved_state, cmd_buffer); radv_meta_restore(&saved_state, cmd_buffer);
} }
uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer, uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
const struct radv_image *image,
struct radeon_winsys_bo *bo, struct radeon_winsys_bo *bo,
uint64_t offset, uint64_t size, uint32_t value) uint64_t offset, uint64_t size, uint32_t value)
{ {
@ -362,10 +362,13 @@ uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
assert(!(size & 3)); assert(!(size & 3));
if (size >= RADV_BUFFER_OPS_CS_THRESHOLD) { if (size >= RADV_BUFFER_OPS_CS_THRESHOLD) {
cmd_buffer->state.flush_bits |=
radv_dst_access_flush(cmd_buffer, VK_ACCESS_SHADER_WRITE_BIT, image);
fill_buffer_shader(cmd_buffer, bo, offset, size, value); fill_buffer_shader(cmd_buffer, bo, offset, size, value);
flush_bits = RADV_CMD_FLAG_CS_PARTIAL_FLUSH | flush_bits = RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
RADV_CMD_FLAG_INV_VCACHE | radv_src_access_flush(cmd_buffer, VK_ACCESS_SHADER_WRITE_BIT, image);
RADV_CMD_FLAG_WB_L2;
} else if (size) { } else if (size) {
uint64_t va = radv_buffer_get_va(bo); uint64_t va = radv_buffer_get_va(bo);
va += offset; va += offset;
@ -412,7 +415,7 @@ void radv_CmdFillBuffer(
if (fillSize == VK_WHOLE_SIZE) if (fillSize == VK_WHOLE_SIZE)
fillSize = (dst_buffer->size - dstOffset) & ~3ull; fillSize = (dst_buffer->size - dstOffset) & ~3ull;
radv_fill_buffer(cmd_buffer, dst_buffer->bo, dst_buffer->offset + dstOffset, radv_fill_buffer(cmd_buffer, NULL, dst_buffer->bo, dst_buffer->offset + dstOffset,
fillSize, data); fillSize, data);
} }

27
src/amd/vulkan/radv_meta_clear.c
View file

@ -882,7 +882,7 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
} }
static uint32_t static uint32_t
clear_htile_mask(struct radv_cmd_buffer *cmd_buffer, clear_htile_mask(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *image,
struct radeon_winsys_bo *bo, uint64_t offset, uint64_t size, struct radeon_winsys_bo *bo, uint64_t offset, uint64_t size,
uint32_t htile_value, uint32_t htile_mask) uint32_t htile_value, uint32_t htile_mask)
{ {
@ -940,8 +940,7 @@ clear_htile_mask(struct radv_cmd_buffer *cmd_buffer,
radv_meta_restore(&saved_state, cmd_buffer); radv_meta_restore(&saved_state, cmd_buffer);
return RADV_CMD_FLAG_CS_PARTIAL_FLUSH | return RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
RADV_CMD_FLAG_INV_VCACHE | radv_src_access_flush(cmd_buffer, VK_ACCESS_SHADER_WRITE_BIT, image);
RADV_CMD_FLAG_WB_L2;
} }
static uint32_t static uint32_t
@ -1046,8 +1045,10 @@ radv_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer,
clear_word = radv_get_htile_fast_clear_value(cmd_buffer->device, iview->image, clear_value); clear_word = radv_get_htile_fast_clear_value(cmd_buffer->device, iview->image, clear_value);
if (pre_flush) { if (pre_flush) {
cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB | enum radv_cmd_flush_bits bits =
RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) & ~ *pre_flush; radv_src_access_flush(cmd_buffer, VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT, iview->image) |
radv_dst_access_flush(cmd_buffer, VK_ACCESS_SHADER_WRITE_BIT, iview->image);
cmd_buffer->state.flush_bits |= bits & ~ *pre_flush;
*pre_flush |= cmd_buffer->state.flush_bits; *pre_flush |= cmd_buffer->state.flush_bits;
} }
@ -1372,7 +1373,7 @@ radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
size = cmask_slice_size * radv_get_layerCount(image, range); size = cmask_slice_size * radv_get_layerCount(image, range);
} }
return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value); return radv_fill_buffer(cmd_buffer, image, image->bo, offset, size, value);
} }
@ -1392,7 +1393,7 @@ radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
offset += slice_size * range->baseArrayLayer; offset += slice_size * range->baseArrayLayer;
size = slice_size * radv_get_layerCount(image, range); size = slice_size * radv_get_layerCount(image, range);
return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value); return radv_fill_buffer(cmd_buffer, image, image->bo, offset, size, value);
} }
uint32_t uint32_t
@ -1440,7 +1441,7 @@ radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
if (!size) if (!size)
continue; continue;
flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset, flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bo, offset,
size, value); size, value);
} }
@ -1463,11 +1464,11 @@ radv_clear_htile(struct radv_cmd_buffer *cmd_buffer,
if (htile_mask == UINT_MAX) { if (htile_mask == UINT_MAX) {
/* Clear the whole HTILE buffer. */ /* Clear the whole HTILE buffer. */
flush_bits = radv_fill_buffer(cmd_buffer, image->bo, offset, flush_bits = radv_fill_buffer(cmd_buffer, image, image->bo, offset,
size, value); size, value);
} else { } else {
/* Only clear depth or stencil bytes in the HTILE buffer. */ /* Only clear depth or stencil bytes in the HTILE buffer. */
flush_bits = clear_htile_mask(cmd_buffer, image->bo, offset, flush_bits = clear_htile_mask(cmd_buffer, image, image->bo, offset,
size, value, htile_mask); size, value, htile_mask);
} }
@ -1670,8 +1671,10 @@ radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
}; };
if (pre_flush) { if (pre_flush) {
cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB | enum radv_cmd_flush_bits bits =
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) & ~ *pre_flush; radv_src_access_flush(cmd_buffer, VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT, iview->image) |
radv_dst_access_flush(cmd_buffer, VK_ACCESS_SHADER_WRITE_BIT, iview->image);
cmd_buffer->state.flush_bits |= bits & ~ *pre_flush;
*pre_flush |= cmd_buffer->state.flush_bits; *pre_flush |= cmd_buffer->state.flush_bits;
} }

15
src/amd/vulkan/radv_meta_fast_clear.c
View file

@ -633,14 +633,14 @@ radv_process_color_image_layer(struct radv_cmd_buffer *cmd_buffer,
&cmd_buffer->state.pass->subpasses[0]); &cmd_buffer->state.pass->subpasses[0]);
if (flush_cb) if (flush_cb)
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB | cmd_buffer->state.flush_bits |=
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META; radv_dst_access_flush(cmd_buffer, VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT, image);
radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0); radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
if (flush_cb) if (flush_cb)
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB | cmd_buffer->state.flush_bits |=
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META; radv_src_access_flush(cmd_buffer, VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT, image);
radv_cmd_buffer_end_render_pass(cmd_buffer); radv_cmd_buffer_end_render_pass(cmd_buffer);
@ -841,8 +841,8 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer,
struct radv_image_view store_iview = {0}; struct radv_image_view store_iview = {0};
struct radv_device *device = cmd_buffer->device; struct radv_device *device = cmd_buffer->device;
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB | cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, VK_ACCESS_SHADER_WRITE_BIT,
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META; image);
if (!cmd_buffer->device->meta_state.fast_clear_flush.cmask_eliminate_pipeline) { if (!cmd_buffer->device->meta_state.fast_clear_flush.cmask_eliminate_pipeline) {
VkResult ret = radv_device_init_meta_fast_clear_flush_state_internal(cmd_buffer->device); VkResult ret = radv_device_init_meta_fast_clear_flush_state_internal(cmd_buffer->device);
@ -948,9 +948,8 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer,
radv_meta_restore(&saved_state, cmd_buffer); radv_meta_restore(&saved_state, cmd_buffer);
/* Make sure the image is decompressed before fixup up DCC. */
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
RADV_CMD_FLAG_INV_VCACHE; radv_src_access_flush(cmd_buffer, VK_ACCESS_SHADER_WRITE_BIT, image);
/* Initialize the DCC metadata as "fully expanded". */ /* Initialize the DCC metadata as "fully expanded". */
radv_initialize_dcc(cmd_buffer, image, subresourceRange, 0xffffffff); radv_initialize_dcc(cmd_buffer, image, subresourceRange, 0xffffffff);

4
src/amd/vulkan/radv_meta_fmask_expand.c
View file

@ -114,6 +114,8 @@ radv_expand_fmask_image_inplace(struct radv_cmd_buffer *cmd_buffer,
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
VK_PIPELINE_BIND_POINT_COMPUTE, pipeline); VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, VK_ACCESS_SHADER_WRITE_BIT, image);
for (unsigned l = 0; l < radv_get_layerCount(image, subresourceRange); l++) { for (unsigned l = 0; l < radv_get_layerCount(image, subresourceRange); l++) {
struct radv_image_view iview; struct radv_image_view iview;
@ -160,7 +162,7 @@ radv_expand_fmask_image_inplace(struct radv_cmd_buffer *cmd_buffer,
radv_meta_restore(&saved_state, cmd_buffer); radv_meta_restore(&saved_state, cmd_buffer);
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
RADV_CMD_FLAG_INV_L2; radv_src_access_flush(cmd_buffer, VK_ACCESS_SHADER_WRITE_BIT, image);
/* Re-initialize FMASK in fully expanded mode. */ /* Re-initialize FMASK in fully expanded mode. */
radv_initialize_fmask(cmd_buffer, image, subresourceRange); radv_initialize_fmask(cmd_buffer, image, subresourceRange);

17
src/amd/vulkan/radv_meta_resolve.c
View file

@ -310,6 +310,8 @@ cleanup:
static void static void
emit_resolve(struct radv_cmd_buffer *cmd_buffer, emit_resolve(struct radv_cmd_buffer *cmd_buffer,
const struct radv_image *src_image,
const struct radv_image *dst_image,
VkFormat vk_format, VkFormat vk_format,
const VkOffset2D *dest_offset, const VkOffset2D *dest_offset,
const VkExtent2D *resolve_extent) const VkExtent2D *resolve_extent)
@ -318,7 +320,10 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer,
VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer); VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
unsigned fs_key = radv_format_meta_fs_key(device, vk_format); unsigned fs_key = radv_format_meta_fs_key(device, vk_format);
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB; cmd_buffer->state.flush_bits |=
radv_src_access_flush(cmd_buffer, VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT, src_image) |
radv_dst_access_flush(cmd_buffer, VK_ACCESS_COLOR_ATTACHMENT_READ_BIT, src_image) |
radv_dst_access_flush(cmd_buffer, VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT, dst_image);
radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS, radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
device->meta_state.resolve.pipeline[fs_key]); device->meta_state.resolve.pipeline[fs_key]);
@ -338,7 +343,8 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer,
}); });
radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0); radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0);
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB; cmd_buffer->state.flush_bits |=
radv_src_access_flush(cmd_buffer, VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT, dst_image);
} }
enum radv_resolve_method { enum radv_resolve_method {
@ -581,7 +587,7 @@ radv_meta_resolve_hardware_image(struct radv_cmd_buffer *cmd_buffer,
radv_cmd_buffer_set_subpass(cmd_buffer, radv_cmd_buffer_set_subpass(cmd_buffer,
&cmd_buffer->state.pass->subpasses[0]); &cmd_buffer->state.pass->subpasses[0]);
emit_resolve(cmd_buffer, emit_resolve(cmd_buffer, src_image, dst_image,
dst_iview.vk_format, dst_iview.vk_format,
&(VkOffset2D) { &(VkOffset2D) {
.x = dstOffset.x, .x = dstOffset.x,
@ -860,6 +866,9 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer)
if (dest_att.attachment == VK_ATTACHMENT_UNUSED) if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
continue; continue;
struct radv_image_view *src_iview = cmd_buffer->state.attachments[src_att.attachment].iview;
struct radv_image *src_img = src_iview->image;
struct radv_image_view *dest_iview = cmd_buffer->state.attachments[dest_att.attachment].iview; struct radv_image_view *dest_iview = cmd_buffer->state.attachments[dest_att.attachment].iview;
struct radv_image *dst_img = dest_iview->image; struct radv_image *dst_img = dest_iview->image;
@ -890,7 +899,7 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer)
continue; continue;
} }
emit_resolve(cmd_buffer, emit_resolve(cmd_buffer, src_img, dst_img,
dest_iview->vk_format, dest_iview->vk_format,
&(VkOffset2D) { 0, 0 }, &(VkOffset2D) { 0, 0 },
&(VkExtent2D) { fb->width, fb->height }); &(VkExtent2D) { fb->width, fb->height });

22
src/amd/vulkan/radv_meta_resolve_cs.c
View file

@ -898,7 +898,8 @@ radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer)
*/ */
barrier.src_stage_mask = VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT; barrier.src_stage_mask = VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT;
barrier.src_access_mask = VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT; barrier.src_access_mask = VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT;
barrier.dst_access_mask = VK_ACCESS_INPUT_ATTACHMENT_READ_BIT; barrier.dst_access_mask = VK_ACCESS_SHADER_READ_BIT |
VK_ACCESS_SHADER_WRITE_BIT;
radv_subpass_barrier(cmd_buffer, &barrier); radv_subpass_barrier(cmd_buffer, &barrier);
for (uint32_t i = 0; i < subpass->color_count; ++i) { for (uint32_t i = 0; i < subpass->color_count; ++i) {
@ -940,8 +941,9 @@ radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer)
&region); &region);
} }
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | cmd_buffer->state.flush_bits |=
RADV_CMD_FLAG_INV_VCACHE; RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
radv_src_access_flush(cmd_buffer, VK_ACCESS_SHADER_WRITE_BIT, NULL);
} }
void void
@ -952,7 +954,6 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
struct radv_framebuffer *fb = cmd_buffer->state.framebuffer; struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
const struct radv_subpass *subpass = cmd_buffer->state.subpass; const struct radv_subpass *subpass = cmd_buffer->state.subpass;
struct radv_meta_saved_state saved_state; struct radv_meta_saved_state saved_state;
struct radv_subpass_barrier barrier;
uint32_t layer_count = fb->layers; uint32_t layer_count = fb->layers;
if (subpass->view_mask) if (subpass->view_mask)
@ -961,10 +962,10 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
/* Resolves happen before the end-of-subpass barriers get executed, so /* Resolves happen before the end-of-subpass barriers get executed, so
* we have to make the attachment shader-readable. * we have to make the attachment shader-readable.
*/ */
barrier.src_stage_mask = VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT; cmd_buffer->state.flush_bits |=
barrier.src_access_mask = VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT; radv_src_access_flush(cmd_buffer, VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT, NULL) |
barrier.dst_access_mask = VK_ACCESS_INPUT_ATTACHMENT_READ_BIT; radv_dst_access_flush(cmd_buffer, VK_ACCESS_SHADER_READ_BIT, NULL) |
radv_subpass_barrier(cmd_buffer, &barrier); radv_dst_access_flush(cmd_buffer, VK_ACCESS_SHADER_WRITE_BIT, NULL);
radv_decompress_resolve_subpass_src(cmd_buffer); radv_decompress_resolve_subpass_src(cmd_buffer);
@ -1019,8 +1020,9 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
&(VkExtent3D) { fb->width, fb->height, layer_count }, &(VkExtent3D) { fb->width, fb->height, layer_count },
aspects, resolve_mode); aspects, resolve_mode);
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | cmd_buffer->state.flush_bits |=
RADV_CMD_FLAG_INV_VCACHE; RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
radv_src_access_flush(cmd_buffer, VK_ACCESS_SHADER_WRITE_BIT, NULL);
VkImageLayout layout = VkImageLayout layout =
cmd_buffer->state.attachments[dest_att.attachment].current_layout; cmd_buffer->state.attachments[dest_att.attachment].current_layout;

7
src/amd/vulkan/radv_meta_resolve_fs.c
View file

@ -858,7 +858,9 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer,
}, },
}); });
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB; cmd_buffer->state.flush_bits |=
radv_dst_access_flush(cmd_buffer, VK_ACCESS_SHADER_READ_BIT, src_iview->image) |
radv_dst_access_flush(cmd_buffer, VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT, dest_iview->image);
unsigned push_constants[2] = { unsigned push_constants[2] = {
src_offset->x - dest_offset->x, src_offset->x - dest_offset->x,
@ -889,7 +891,8 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer,
}); });
radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0); radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0);
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB; cmd_buffer->state.flush_bits |=
radv_src_access_flush(cmd_buffer, VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT, dest_iview->image);
} }
static void static void

10
src/amd/vulkan/radv_private.h
View file

@ -1583,8 +1583,16 @@ void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer, void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image, struct radv_image *image,
const VkImageSubresourceRange *range, bool value); const VkImageSubresourceRange *range, bool value);
enum radv_cmd_flush_bits
radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
VkAccessFlags src_flags,
const struct radv_image *image);
enum radv_cmd_flush_bits
radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
VkAccessFlags dst_flags,
const struct radv_image *image);
uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer, uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
const struct radv_image *image,
struct radeon_winsys_bo *bo, struct radeon_winsys_bo *bo,
uint64_t offset, uint64_t size, uint32_t value); uint64_t offset, uint64_t size, uint32_t value);
void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer); void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);

4
src/amd/vulkan/radv_query.c
View file

@ -1428,12 +1428,12 @@ void radv_CmdResetQueryPool(
*/ */
cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits; cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
flush_bits |= radv_fill_buffer(cmd_buffer, pool->bo, flush_bits |= radv_fill_buffer(cmd_buffer, NULL, pool->bo,
firstQuery * pool->stride, firstQuery * pool->stride,
queryCount * pool->stride, value); queryCount * pool->stride, value);
if (pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS) { if (pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS) {
flush_bits |= radv_fill_buffer(cmd_buffer, pool->bo, flush_bits |= radv_fill_buffer(cmd_buffer, NULL, pool->bo,
pool->availability_offset + firstQuery * 4, pool->availability_offset + firstQuery * 4,
queryCount * 4, 0); queryCount * 4, 0);
} }