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freedreno/ir3: add IDIV/UDIV support
Logic shamelessly copied from nv50 lowering pass. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
This commit is contained in:
Ilia Mirkin
Rob Clark
parent
ed03747e6a
commit
8f7d01c2cb
1 changed files with 197 additions and 3 deletions
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@ -91,7 +91,7 @@ struct ir3_compile_context {
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unsigned next_inloc;
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unsigned num_internal_temps;
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struct tgsi_src_register internal_temps[6];
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struct tgsi_src_register internal_temps[8];
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/* idx/slot for last compiler generated immediate */
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unsigned immediate_idx;
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@ -305,10 +305,10 @@ push_block(struct ir3_compile_context *ctx)
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#define SCALAR_REGS(file) (4 * (ctx->info.file_max[TGSI_FILE_ ## file] + 1))
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/* hmm, give ourselves room to create 4 extra temporaries (vec4):
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/* hmm, give ourselves room to create 8 extra temporaries (vec4):
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*/
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ntmp = SCALAR_REGS(TEMPORARY);
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ntmp += 4 * 4;
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ntmp += 8 * 4;
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nout = SCALAR_REGS(OUTPUT);
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nin = SCALAR_REGS(INPUT);
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@ -775,6 +775,12 @@ get_utype(struct ir3_compile_context *ctx)
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return TYPE_U32;
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}
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static type_t
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get_stype(struct ir3_compile_context *ctx)
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{
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return TYPE_S32;
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}
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static unsigned
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src_swiz(struct tgsi_src_register *src, int chan)
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{
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@ -1988,6 +1994,192 @@ trans_umul(const struct instr_translater *t,
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put_dst(ctx, inst, dst);
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}
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/*
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* IDIV / UDIV
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*
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* See NV50LegalizeSSA::handleDIV for the origin of this implementation.
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*/
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static void
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trans_idiv(const struct instr_translater *t,
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struct ir3_compile_context *ctx,
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struct tgsi_full_instruction *inst)
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{
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struct ir3_instruction *instr;
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struct tgsi_dst_register *dst = get_dst(ctx, inst);
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struct tgsi_src_register *a = &inst->Src[0].Register;
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struct tgsi_src_register *b = &inst->Src[1].Register;
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struct tgsi_dst_register af_dst, bf_dst, q_dst, r_dst, a_dst, b_dst;
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struct tgsi_src_register *af_src, *bf_src, *q_src, *r_src, *a_src, *b_src;
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struct tgsi_src_register negative_2, thirty_one;
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type_t src_type = t->tgsi_opc == TGSI_OPCODE_IDIV ?
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get_stype(ctx) : get_utype(ctx);
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af_src = get_internal_temp(ctx, &af_dst);
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bf_src = get_internal_temp(ctx, &bf_dst);
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q_src = get_internal_temp(ctx, &q_dst);
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r_src = get_internal_temp(ctx, &r_dst);
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a_src = get_internal_temp(ctx, &a_dst);
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b_src = get_internal_temp(ctx, &b_dst);
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get_immediate(ctx, &negative_2, -2);
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get_immediate(ctx, &thirty_one, 31);
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/* cov.[us]32f32 af, numerator */
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instr = instr_create(ctx, 1, 0);
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instr->cat1.src_type = src_type;
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instr->cat1.dst_type = get_ftype(ctx);
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vectorize(ctx, instr, &af_dst, 1, a, 0);
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/* cov.[us]32f32 bf, denominator */
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instr = instr_create(ctx, 1, 0);
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instr->cat1.src_type = src_type;
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instr->cat1.dst_type = get_ftype(ctx);
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vectorize(ctx, instr, &bf_dst, 1, b, 0);
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/* Get the absolute values for IDIV */
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if (t->tgsi_opc == TGSI_OPCODE_IDIV) {
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/* absneg.f af, (abs)af */
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instr = instr_create(ctx, 2, OPC_ABSNEG_F);
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vectorize(ctx, instr, &af_dst, 1, af_src, IR3_REG_ABS);
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/* absneg.f bf, (abs)bf */
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instr = instr_create(ctx, 2, OPC_ABSNEG_F);
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vectorize(ctx, instr, &bf_dst, 1, bf_src, IR3_REG_ABS);
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/* absneg.s a, (abs)numerator */
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instr = instr_create(ctx, 2, OPC_ABSNEG_S);
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vectorize(ctx, instr, &a_dst, 1, a, IR3_REG_ABS);
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/* absneg.s b, (abs)denominator */
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instr = instr_create(ctx, 2, OPC_ABSNEG_S);
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vectorize(ctx, instr, &b_dst, 1, b, IR3_REG_ABS);
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} else {
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/* mov.u32u32 a, numerator */
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instr = instr_create(ctx, 1, 0);
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instr->cat1.src_type = src_type;
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instr->cat1.dst_type = src_type;
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vectorize(ctx, instr, &a_dst, 1, a, 0);
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/* mov.u32u32 b, denominator */
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instr = instr_create(ctx, 1, 0);
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instr->cat1.src_type = src_type;
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instr->cat1.dst_type = src_type;
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vectorize(ctx, instr, &b_dst, 1, b, 0);
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}
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/* rcp.f bf, bf */
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instr = instr_create(ctx, 4, OPC_RCP);
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vectorize(ctx, instr, &bf_dst, 1, bf_src, 0);
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/* That's right, subtract 2 as an integer from the float */
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/* add.u bf, bf, -2 */
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instr = instr_create(ctx, 2, OPC_ADD_U);
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vectorize(ctx, instr, &bf_dst, 2, bf_src, 0, &negative_2, 0);
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/* mul.f q, af, bf */
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instr = instr_create(ctx, 2, OPC_MUL_F);
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vectorize(ctx, instr, &q_dst, 2, af_src, 0, bf_src, 0);
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/* cov.f32[us]32 q, q */
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instr = instr_create(ctx, 1, 0);
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instr->cat1.src_type = get_ftype(ctx);
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instr->cat1.dst_type = src_type;
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vectorize(ctx, instr, &q_dst, 1, q_src, 0);
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/* integer multiply q by b */
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/* mull.u r, q, b */
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instr = instr_create(ctx, 2, OPC_MULL_U);
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vectorize(ctx, instr, &r_dst, 2, q_src, 0, b_src, 0);
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/* madsh.m16 r, q, b, r */
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instr = instr_create(ctx, 3, OPC_MADSH_M16);
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vectorize(ctx, instr, &r_dst, 3, q_src, 0, b_src, 0, r_src, 0);
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/* madsh.m16, r, b, q, r */
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instr = instr_create(ctx, 3, OPC_MADSH_M16);
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vectorize(ctx, instr, &r_dst, 3, b_src, 0, q_src, 0, r_src, 0);
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/* sub.u r, a, r */
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instr = instr_create(ctx, 2, OPC_SUB_U);
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vectorize(ctx, instr, &r_dst, 2, a_src, 0, r_src, 0);
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/* cov.u32f32, r, r */
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instr = instr_create(ctx, 1, 0);
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instr->cat1.src_type = get_utype(ctx);
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instr->cat1.dst_type = get_ftype(ctx);
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vectorize(ctx, instr, &r_dst, 1, r_src, 0);
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/* mul.f r, r, bf */
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instr = instr_create(ctx, 2, OPC_MUL_F);
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vectorize(ctx, instr, &r_dst, 2, r_src, 0, bf_src, 0);
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/* cov.f32u32 r, r */
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instr = instr_create(ctx, 1, 0);
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instr->cat1.src_type = get_ftype(ctx);
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instr->cat1.dst_type = get_utype(ctx);
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vectorize(ctx, instr, &r_dst, 1, r_src, 0);
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/* add.u q, q, r */
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instr = instr_create(ctx, 2, OPC_ADD_U);
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vectorize(ctx, instr, &q_dst, 2, q_src, 0, r_src, 0);
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/* mull.u r, q, b */
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instr = instr_create(ctx, 2, OPC_MULL_U);
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vectorize(ctx, instr, &r_dst, 2, q_src, 0, b_src, 0);
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/* madsh.m16 r, q, b, r */
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instr = instr_create(ctx, 3, OPC_MADSH_M16);
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vectorize(ctx, instr, &r_dst, 3, q_src, 0, b_src, 0, r_src, 0);
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/* madsh.m16 r, b, q, r */
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instr = instr_create(ctx, 3, OPC_MADSH_M16);
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vectorize(ctx, instr, &r_dst, 3, b_src, 0, q_src, 0, r_src, 0);
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/* sub.u r, a, r */
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instr = instr_create(ctx, 2, OPC_SUB_U);
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vectorize(ctx, instr, &r_dst, 2, a_src, 0, r_src, 0);
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/* cmps.u.ge r, r, b */
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instr = instr_create(ctx, 2, OPC_CMPS_U);
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instr->cat2.condition = IR3_COND_GE;
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vectorize(ctx, instr, &r_dst, 2, r_src, 0, b_src, 0);
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if (t->tgsi_opc == TGSI_OPCODE_UDIV) {
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/* add.u dst, q, r */
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instr = instr_create(ctx, 2, OPC_ADD_U);
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vectorize(ctx, instr, dst, 2, q_src, 0, r_src, 0);
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} else {
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/* add.u q, q, r */
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instr = instr_create(ctx, 2, OPC_ADD_U);
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vectorize(ctx, instr, &q_dst, 2, q_src, 0, r_src, 0);
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/* negate result based on the original arguments */
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if (is_const(a) && is_const(b))
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a = get_unconst(ctx, a);
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/* xor.b r, numerator, denominator */
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instr = instr_create(ctx, 2, OPC_XOR_B);
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vectorize(ctx, instr, &r_dst, 2, a, 0, b, 0);
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/* shr.b r, r, 31 */
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instr = instr_create(ctx, 2, OPC_SHR_B);
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vectorize(ctx, instr, &r_dst, 2, r_src, 0, &thirty_one, 0);
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/* absneg.s b, (neg)q */
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instr = instr_create(ctx, 2, OPC_ABSNEG_S);
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vectorize(ctx, instr, &b_dst, 1, q_src, IR3_REG_NEGATE);
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/* sel.b dst, b, r, q */
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instr = instr_create(ctx, 3, OPC_SEL_B32);
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vectorize(ctx, instr, dst, 3, b_src, 0, r_src, 0, q_src, 0);
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}
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put_dst(ctx, inst, dst);
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}
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/*
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* Handlers for TGSI instructions which do have 1:1 mapping to native
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* instructions:
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@ -2147,6 +2339,8 @@ static const struct instr_translater translaters[TGSI_OPCODE_LAST] = {
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INSTR(NOT, instr_cat2, .opc = OPC_NOT_B),
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INSTR(XOR, instr_cat2, .opc = OPC_XOR_B),
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INSTR(UMUL, trans_umul),
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INSTR(UDIV, trans_idiv),
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INSTR(IDIV, trans_idiv),
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INSTR(SHL, instr_cat2, .opc = OPC_SHL_B),
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INSTR(USHR, instr_cat2, .opc = OPC_SHR_B),
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INSTR(ISHR, instr_cat2, .opc = OPC_ASHR_B),
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