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freedreno: Convert fd_dev_info to const pointer

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Split out from previous patch to reduce churn.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11790>
This commit is contained in:
Rob Clark 2021-07-07 18:37:09 -07:00 • committed by Marge Bot
parent 78c8a8af80
commit 8f6715862f
11 changed files with 37 additions and 39 deletions
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2
src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
View file

@ -584,7 +584,7 @@ fd2_emit_tile_init(struct fd_batch *batch) assert_dt
if (cf->opc == ALLOC)
cf++;
assert(cf->opc == EXEC);
assert(cf[ctx->screen->info.num_vsc_pipes * 2 - 2].opc == EXEC_END);
assert(cf[ctx->screen->info->num_vsc_pipes * 2 - 2].opc == EXEC_END);
cf[2 * (gmem->num_vsc_pipes - 1)].opc = EXEC_END;
}

10
src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
View file

@ -412,7 +412,7 @@ emit_blit_buffer(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_WFI5(ring);
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
OUT_RING(ring, ctx->screen->info.a6xx.magic.RB_UNKNOWN_8E04_blit);
OUT_RING(ring, ctx->screen->info->a6xx.magic.RB_UNKNOWN_8E04_blit);
OUT_PKT7(ring, CP_BLIT, 1);
OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
@ -507,7 +507,7 @@ fd6_clear_ubwc(struct fd_batch *batch, struct fd_resource *rsc) assert_dt
OUT_WFI5(ring);
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
OUT_RING(ring, batch->ctx->screen->info.a6xx.magic.RB_UNKNOWN_8E04_blit);
OUT_RING(ring, batch->ctx->screen->info->a6xx.magic.RB_UNKNOWN_8E04_blit);
OUT_PKT7(ring, CP_BLIT, 1);
OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
@ -684,7 +684,7 @@ emit_blit_texture(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_WFI5(ring);
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
OUT_RING(ring, ctx->screen->info.a6xx.magic.RB_UNKNOWN_8E04_blit);
OUT_RING(ring, ctx->screen->info->a6xx.magic.RB_UNKNOWN_8E04_blit);
OUT_PKT7(ring, CP_BLIT, 1);
OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
@ -812,7 +812,7 @@ fd6_clear_surface(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_WFI5(ring);
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
OUT_RING(ring, ctx->screen->info.a6xx.magic.RB_UNKNOWN_8E04_blit);
OUT_RING(ring, ctx->screen->info->a6xx.magic.RB_UNKNOWN_8E04_blit);
OUT_PKT7(ring, CP_BLIT, 1);
OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
@ -1062,7 +1062,7 @@ handle_zs_blit(struct fd_context *ctx,
/* non-UBWC Z24_UNORM_S8_UINT_AS_R8G8B8A8 is broken on a630, fall back to
* 8888_unorm.
*/
if (!ctx->screen->info.a6xx.has_z24uint_s8uint) {
if (!ctx->screen->info->a6xx.has_z24uint_s8uint) {
if (!src->layout.ubwc)
blit.src.format = PIPE_FORMAT_RGBA8888_UNORM;
if (!dst->layout.ubwc)

2
src/gallium/drivers/freedreno/a6xx/fd6_draw.c
View file

@ -457,7 +457,7 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
OUT_WFI5(ring);
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
OUT_RING(ring, screen->info.a6xx.magic.RB_UNKNOWN_8E04_blit);
OUT_RING(ring, screen->info->a6xx.magic.RB_UNKNOWN_8E04_blit);
OUT_PKT7(ring, CP_BLIT, 1);
OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));

12
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
View file

@ -689,10 +689,10 @@ emit_binning_pass(struct fd_batch *batch) assert_dt
update_vsc_pipe(batch);
OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
OUT_RING(ring, screen->info.a6xx.magic.PC_UNKNOWN_9805);
OUT_RING(ring, screen->info->a6xx.magic.PC_UNKNOWN_9805);
OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
OUT_RING(ring, screen->info.a6xx.magic.SP_UNKNOWN_A0F8);
OUT_RING(ring, screen->info->a6xx.magic.SP_UNKNOWN_A0F8);
OUT_PKT7(ring, CP_EVENT_WRITE, 1);
OUT_RING(ring, UNK_2C);
@ -742,7 +742,7 @@ emit_binning_pass(struct fd_batch *batch) assert_dt
OUT_REG(ring,
A6XX_RB_CCU_CNTL(.color_offset = screen->ccu_offset_gmem,
.gmem = true,
.unk2 = screen->info.a6xx.ccu_cntl_gmem_unk2));
.unk2 = screen->info->a6xx.ccu_cntl_gmem_unk2));
}
static void
@ -810,7 +810,7 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt
OUT_REG(ring,
A6XX_RB_CCU_CNTL(.color_offset = screen->ccu_offset_gmem,
.gmem = true,
.unk2 = screen->info.a6xx.ccu_cntl_gmem_unk2));
.unk2 = screen->info->a6xx.ccu_cntl_gmem_unk2));
emit_zs(ring, pfb->zsbuf, batch->gmem_state);
emit_mrt(ring, pfb, batch->gmem_state);
@ -845,10 +845,10 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt
OUT_RING(ring, 0x0);
OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
OUT_RING(ring, screen->info.a6xx.magic.PC_UNKNOWN_9805);
OUT_RING(ring, screen->info->a6xx.magic.PC_UNKNOWN_9805);
OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
OUT_RING(ring, screen->info.a6xx.magic.SP_UNKNOWN_A0F8);
OUT_RING(ring, screen->info->a6xx.magic.SP_UNKNOWN_A0F8);
OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
OUT_RING(ring, 0x1);

4
src/gallium/drivers/freedreno/a6xx/fd6_program.c
View file

@ -103,8 +103,8 @@ fd6_emit_shader(struct fd_context *ctx, struct fd_ringbuffer *ring,
fd_emit_string5(ring, name, strlen(name));
#endif
uint32_t fibers_per_sp = ctx->screen->info.a6xx.fibers_per_sp;
uint32_t num_sp_cores = ctx->screen->info.num_sp_cores;
uint32_t fibers_per_sp = ctx->screen->info->a6xx.fibers_per_sp;
uint32_t num_sp_cores = ctx->screen->info->num_sp_cores;
uint32_t per_fiber_size = ALIGN(so->pvtmem_size, 512);
if (per_fiber_size > ctx->pvtmem[so->pvtmem_per_wave].per_fiber_size) {

2
src/gallium/drivers/freedreno/a6xx/fd6_resource.c
View file

@ -47,7 +47,7 @@ ok_ubwc_format(struct pipe_screen *pscreen, enum pipe_format pfmt)
* fd_resource_uncompress() at the point of stencil sampling because
* that itself uses stencil sampling in the fd_blitter_blit path.
*/
return fd_screen(pscreen)->info.a6xx.has_z24uint_s8uint;
return fd_screen(pscreen)->info->a6xx.has_z24uint_s8uint;
case PIPE_FORMAT_R8_G8B8_420_UNORM:
return true;

24
src/gallium/drivers/freedreno/freedreno_gmem.c
View file

@ -178,13 +178,13 @@ layout_gmem(struct gmem_key *key, uint32_t nbins_x, uint32_t nbins_y,
return false;
uint32_t bin_w, bin_h;
bin_w = div_align(key->width, nbins_x, screen->info.tile_align_w);
bin_h = div_align(key->height, nbins_y, screen->info.tile_align_h);
bin_w = div_align(key->width, nbins_x, screen->info->tile_align_w);
bin_h = div_align(key->height, nbins_y, screen->info->tile_align_h);
if (bin_w > screen->info.tile_max_w)
if (bin_w > screen->info->tile_max_w)
return false;
if (bin_h > screen->info.tile_max_h)
if (bin_h > screen->info->tile_max_h)
return false;
gmem->bin_w = bin_w;
@ -221,8 +221,8 @@ calc_nbins(struct gmem_key *key, struct fd_gmem_stateobj *gmem)
{
struct fd_screen *screen = gmem->screen;
uint32_t nbins_x = 1, nbins_y = 1;
uint32_t max_width = screen->info.tile_max_w;
uint32_t max_height = screen->info.tile_max_h;
uint32_t max_width = screen->info->tile_max_w;
uint32_t max_height = screen->info->tile_max_h;
if (FD_DBG(MSGS)) {
debug_printf("binning input: cbuf cpp:");
@ -235,12 +235,12 @@ calc_nbins(struct gmem_key *key, struct fd_gmem_stateobj *gmem)
/* first, find a bin size that satisfies the maximum width/
* height restrictions:
*/
while (div_align(key->width, nbins_x, screen->info.tile_align_w) >
while (div_align(key->width, nbins_x, screen->info->tile_align_w) >
max_width) {
nbins_x++;
}
while (div_align(key->height, nbins_y, screen->info.tile_align_h) >
while (div_align(key->height, nbins_y, screen->info->tile_align_h) >
max_height) {
nbins_y++;
}
@ -282,7 +282,7 @@ gmem_stateobj_init(struct fd_screen *screen, struct gmem_key *key)
gmem->key = key;
list_inithead(&gmem->node);
const unsigned npipes = screen->info.num_vsc_pipes;
const unsigned npipes = screen->info->num_vsc_pipes;
uint32_t i, j, t, xoff, yoff;
uint32_t tpp_x, tpp_y;
int tile_n[npipes];
@ -504,8 +504,8 @@ gmem_key_init(struct fd_batch *batch, bool assume_zs, bool no_scis_opt)
}
/* round down to multiple of alignment: */
key->minx = scissor->minx & ~(screen->info.gmem_align_w - 1);
key->miny = scissor->miny & ~(screen->info.gmem_align_h - 1);
key->minx = scissor->minx & ~(screen->info->gmem_align_w - 1);
key->miny = scissor->miny & ~(screen->info->gmem_align_h - 1);
key->width = scissor->maxx - key->minx;
key->height = scissor->maxy - key->miny;
}
@ -516,7 +516,7 @@ gmem_key_init(struct fd_batch *batch, bool assume_zs, bool no_scis_opt)
*/
key->gmem_page_align = 8;
} else if (is_a6xx(screen)) {
key->gmem_page_align = (screen->info.tile_align_w == 96) ? 3 : 1;
key->gmem_page_align = (screen->info->tile_align_w == 96) ? 3 : 1;
} else {
// TODO re-check this across gens.. maybe it should only
// be a single page in some cases:

4
src/gallium/drivers/freedreno/freedreno_resource.c
View file

@ -1258,7 +1258,7 @@ fd_resource_create_with_modifiers(struct pipe_screen *pscreen,
struct winsys_handle handle;
/* note: alignment is wrong for a6xx */
scanout_templat.width0 = align(tmpl->width0, screen->info.gmem_align_w);
scanout_templat.width0 = align(tmpl->width0, screen->info->gmem_align_w);
scanout =
renderonly_scanout_for_resource(&scanout_templat, screen->ro, &handle);
@ -1344,7 +1344,7 @@ fd_resource_from_handle(struct pipe_screen *pscreen,
* validate the pitch and set the right pitchalign
*/
rsc->layout.pitchalign =
fdl_cpp_shift(&rsc->layout) + util_logbase2(screen->info.gmem_align_w);
fdl_cpp_shift(&rsc->layout) + util_logbase2(screen->info->gmem_align_w);
/* apply the minimum pitchalign (note: actually 4 for a3xx but doesn't
* matter) */

7
src/gallium/drivers/freedreno/freedreno_screen.c
View file

@ -1058,13 +1058,12 @@ fd_screen_create(struct fd_device *dev, struct renderonly *ro)
goto fail;
}
// TODO change to pointer:
screen->info = *info;
screen->info = info;
if (is_a6xx(screen)) {
screen->ccu_offset_bypass = screen->info.num_ccu * A6XX_CCU_DEPTH_SIZE;
screen->ccu_offset_bypass = screen->info->num_ccu * A6XX_CCU_DEPTH_SIZE;
screen->ccu_offset_gmem = (screen->gmemsize_bytes -
screen->info.num_ccu * A6XX_CCU_GMEM_COLOR_SIZE);
screen->info->num_ccu * A6XX_CCU_GMEM_COLOR_SIZE);
}
if (FD_DBG(PERFC)) {

2
src/gallium/drivers/freedreno/freedreno_screen.h
View file

@ -91,7 +91,7 @@ struct fd_screen {
bool has_robustness;
bool has_syncobj;
struct fd_dev_info info;
const struct fd_dev_info *info;
uint32_t ccu_offset_gmem;
uint32_t ccu_offset_bypass;

7
src/gallium/drivers/freedreno/gmemtool.c
View file

@ -167,8 +167,7 @@ main(int argc, char **argv)
.gmemsize_bytes = gpu_info->gmemsize_bytes,
};
// TODO change to pointer:
screen.info = *fd_dev_info(gpu_info->gpu_id);
screen.info = fd_dev_info(gpu_info->gpu_id);
/* And finally run thru all the GMEM keys: */
for (int i = 0; i < ARRAY_SIZE(keys); i++) {
@ -179,8 +178,8 @@ main(int argc, char **argv)
assert((gmem->bin_w * gmem->nbins_x) >= key.width);
assert((gmem->bin_h * gmem->nbins_y) >= key.height);
assert(gmem->bin_w < screen.info.tile_max_w);
assert(gmem->bin_h < screen.info.tile_max_h);
assert(gmem->bin_w < screen.info->tile_max_w);
assert(gmem->bin_h < screen.info->tile_max_h);
ralloc_free(gmem);
}