diff --git a/src/amd/compiler/README-ISA.md b/src/amd/compiler/README-ISA.md
index 3bd7dfeb873..20a5d9b1ec6 100644
--- a/src/amd/compiler/README-ISA.md
+++ b/src/amd/compiler/README-ISA.md
@@ -372,7 +372,7 @@ A va_vdst=0 wait: `s_waitcnt_deptr 0x0fff`
 ### VALUMaskWriteHazard
 
 Triggered by:
-SALU writing then reading a SGPR that was previously used as a lane mask for a VALU.
+SALU writing then SALU or VALU reading a SGPR that was previously used as a lane mask for a VALU.
 
 Mitigated by:
 A VALU instruction reading a non-exec SGPR before the SALU write, or a sa_sdst=0 wait:
diff --git a/src/amd/compiler/aco_insert_NOPs.cpp b/src/amd/compiler/aco_insert_NOPs.cpp
index b9744434fd5..2c506da584b 100644
--- a/src/amd/compiler/aco_insert_NOPs.cpp
+++ b/src/amd/compiler/aco_insert_NOPs.cpp
@@ -1449,13 +1449,14 @@ handle_instruction_gfx11(State& state, NOP_ctx_gfx11& ctx, aco_ptr<Instruction>&
 
    if (state.program->gfx_level < GFX12) {
       /* VALUMaskWriteHazard
-       * VALU reads SGPR as a lane mask and later written by SALU cannot safely be read by SALU.
+       * VALU reads SGPR as a lane mask and later written by SALU cannot safely be read by SALU or
+       * VALU.
        */
       if (state.program->wave_size == 64 && instr->isSALU() &&
           check_written_regs(instr, ctx.sgpr_read_by_valu_as_lanemask)) {
          ctx.sgpr_read_by_valu_as_lanemask_then_wr_by_salu = ctx.sgpr_read_by_valu_as_lanemask;
          ctx.sgpr_read_by_valu_as_lanemask.reset();
-      } else if (state.program->wave_size == 64 && instr->isSALU() &&
+      } else if (state.program->wave_size == 64 && (instr->isSALU() || instr->isVALU()) &&
                  check_read_regs(instr, ctx.sgpr_read_by_valu_as_lanemask_then_wr_by_salu)) {
          bld.sopp(aco_opcode::s_waitcnt_depctr, 0xfffe);
          sa_sdst = 0;