From 8f33896822f37bbdb166473dc2f13839b58cc06e Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 12 Mar 2026 14:34:49 +0100 Subject: [PATCH] radv: pre-compute the primitive restart index Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 49 ++++++++++++++++---------------- src/amd/vulkan/radv_cmd_buffer.h | 3 +- 2 files changed, 27 insertions(+), 25 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 3ea60bc681d..3b6cde8c419 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -4391,22 +4391,6 @@ radv_emit_fsr_state(struct radv_cmd_buffer *cmd_buffer) radeon_end(); } -static uint32_t -radv_get_primitive_reset_index(const struct radv_cmd_buffer *cmd_buffer) -{ - const uint32_t index_type = G_028A7C_INDEX_TYPE(cmd_buffer->state.index_type); - switch (index_type) { - case V_028A7C_VGT_INDEX_8: - return 0xffu; - case V_028A7C_VGT_INDEX_16: - return 0xffffu; - case V_028A7C_VGT_INDEX_32: - return 0xffffffffu; - default: - UNREACHABLE("invalid index type"); - } -} - static void radv_emit_ls_hs_config(struct radv_cmd_buffer *cmd_buffer) { @@ -7283,10 +7267,8 @@ radv_emit_primitive_restart(struct radv_cmd_buffer *cmd_buffer, bool enable) * GFX9+: Default is same as GFX8, MATCH_ALL_BITS=1 selects GFX6-7 behavior */ if (enable && gfx_level <= GFX7) { - const uint32_t primitive_reset_index = radv_get_primitive_reset_index(cmd_buffer); - radeon_opt_set_context_reg(R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, AC_TRACKED_VGT_MULTI_PRIM_IB_RESET_INDX, - primitive_reset_index); + cmd_buffer->state.primitive_restart_index); } } @@ -7301,7 +7283,6 @@ radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, const struct radv_d const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; const bool primitive_restart_en = (draw_info->indexed || pdev->info.gfx_level >= GFX11) && d->vk.ia.primitive_restart_enable; - const uint32_t primitive_reset_index = radv_get_primitive_reset_index(cmd_buffer); const struct radeon_info *gpu_info = &pdev->info; struct radv_cmd_state *state = &cmd_buffer->state; struct radv_cmd_stream *cs = cmd_buffer->cs; @@ -7348,10 +7329,10 @@ radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, const struct radv_d } if (primitive_restart_en != state->last_primitive_restart_en || - (pdev->info.gfx_level <= GFX7 && primitive_reset_index != state->last_primitive_reset_index)) { + (pdev->info.gfx_level <= GFX7 && state->primitive_restart_index != state->last_primitive_restart_index)) { radv_emit_primitive_restart(cmd_buffer, primitive_restart_en); state->last_primitive_restart_en = primitive_restart_en; - state->last_primitive_reset_index = primitive_reset_index; + state->last_primitive_restart_index = state->primitive_restart_index; } } @@ -8019,6 +8000,21 @@ vk_to_index_type(VkIndexType type) } } +static uint32_t +radv_get_primitive_restart_index(VkIndexType type) +{ + switch (type) { + case VK_INDEX_TYPE_UINT8: + return 0xffu; + case VK_INDEX_TYPE_UINT16: + return 0xffffu; + case VK_INDEX_TYPE_UINT32: + return 0xffffffffu; + default: + UNREACHABLE("invalid index type"); + } +} + static uint32_t radv_get_vgt_index_size(uint32_t type) { @@ -8067,6 +8063,7 @@ radv_CmdBindIndexBuffer3KHR(VkCommandBuffer commandBuffer, const VkBindIndexBuff VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); cmd_buffer->state.index_type = vk_to_index_type(pInfo->indexType); + cmd_buffer->state.primitive_restart_index = radv_get_primitive_restart_index(pInfo->indexType); if (pInfo->addressRange.size) { cmd_buffer->state.index_va = pInfo->addressRange.address; @@ -9921,8 +9918,12 @@ radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCou primary->state.last_primitive_restart_en = secondary->state.last_primitive_restart_en; } - if (secondary->state.last_primitive_reset_index) { - primary->state.last_primitive_reset_index = secondary->state.last_primitive_reset_index; + if (secondary->state.primitive_restart_index) { + primary->state.primitive_restart_index = secondary->state.primitive_restart_index; + } + + if (secondary->state.last_primitive_restart_index) { + primary->state.last_primitive_restart_index = secondary->state.last_primitive_restart_index; } primary->state.rb_noncoherent_dirty |= secondary->state.rb_noncoherent_dirty; diff --git a/src/amd/vulkan/radv_cmd_buffer.h b/src/amd/vulkan/radv_cmd_buffer.h index 2cd9b196ace..a6665713ae2 100644 --- a/src/amd/vulkan/radv_cmd_buffer.h +++ b/src/amd/vulkan/radv_cmd_buffer.h @@ -356,7 +356,8 @@ struct radv_cmd_state { /* Primitive restart */ int32_t last_primitive_restart_en; - uint32_t last_primitive_reset_index; + uint32_t primitive_restart_index; + uint32_t last_primitive_restart_index; enum radv_cmd_flush_bits flush_bits; unsigned active_occlusion_queries;