diff --git a/src/amd/common/ac_cmdbuf_video.c b/src/amd/common/ac_cmdbuf_video.c
new file mode 100644
index 00000000000..2ea3cc23435
--- /dev/null
+++ b/src/amd/common/ac_cmdbuf_video.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#include "ac_cmdbuf.h"
+#include "ac_cmdbuf_video.h"
+#include "ac_vcn.h"
+#include "ac_vcn_dec.h"
+
+static void *
+vcn_common_cmd(struct ac_cmdbuf *cs, uint32_t type, uint32_t size)
+{
+   struct rvcn_sq_var sq;
+
+   ac_vcn_sq_header(cs, &sq, RADEON_VCN_ENGINE_TYPE_COMMON);
+   struct rvcn_cmn_engine_ib_package *ib_header = (struct rvcn_cmn_engine_ib_package *)&(cs->buf[cs->cdw]);
+   ib_header->package_size = sizeof(struct rvcn_cmn_engine_ib_package) + size;
+   cs->cdw++;
+   ib_header->package_type = type;
+   cs->cdw++;
+
+   void *ret = &(cs->buf[cs->cdw]);
+   cs->cdw += size / 4;
+   ac_vcn_sq_tail(cs, &sq);
+
+   return ret;
+}
+
+void
+ac_emit_video_write_memory(struct ac_cmdbuf *cs, const struct radeon_info *info,
+                           enum amd_ip_type ip_type, uint64_t va, uint64_t value)
+{
+   if (ip_type == AMD_IP_VCN_DEC) {
+      struct ac_vcn_dec_reg reg;
+      ac_vcn_dec_init_regs(&reg, info->vcn_ip_version);
+      if (reg.data2) {
+         ac_cmdbuf_begin(cs);
+         ac_cmdbuf_emit(RDECODE_PKT0(reg.data0 >> 2, 0));
+         ac_cmdbuf_emit(va);
+         ac_cmdbuf_emit(RDECODE_PKT0(reg.data1 >> 2, 0));
+         ac_cmdbuf_emit(va >> 32);
+         ac_cmdbuf_emit(RDECODE_PKT0(reg.data2 >> 2, 0));
+         ac_cmdbuf_emit(value);
+         ac_cmdbuf_emit(RDECODE_PKT0(reg.cmd >> 2, 0));
+         ac_cmdbuf_emit(RDECODE_CMD_WRITE_MEMORY << 1);
+         ac_cmdbuf_end();
+      }
+   } else if (ip_type == AMD_IP_VCN_ENC) {
+      struct rvcn_cmn_engine_op_writememory *write_memory =
+         vcn_common_cmd(cs, RADEON_VCN_IB_COMMON_OP_WRITEMEMORY, sizeof(struct rvcn_cmn_engine_op_writememory));
+      write_memory->dest_addr_lo = va;
+      write_memory->dest_addr_hi = va >> 32;
+      write_memory->data = value;
+   }
+}
diff --git a/src/amd/common/ac_cmdbuf_video.h b/src/amd/common/ac_cmdbuf_video.h
new file mode 100644
index 00000000000..43c5b28f013
--- /dev/null
+++ b/src/amd/common/ac_cmdbuf_video.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#ifndef AC_CMDBUF_VIDEO_H
+#define AC_CMDBUF_VIDEO_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+struct radeon_info;
+struct ac_cmdbuf;
+enum amd_ip_type;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void
+ac_emit_video_write_memory(struct ac_cmdbuf *cs, const struct radeon_info *info,
+                           enum amd_ip_type ip_type, uint64_t va, uint64_t value);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/amd/common/meson.build b/src/amd/common/meson.build
index 369705e88d0..e7b58dc7acf 100644
--- a/src/amd/common/meson.build
+++ b/src/amd/common/meson.build
@@ -103,6 +103,8 @@ amd_common_files = files(
   'ac_cmdbuf_cp.h',
   'ac_cmdbuf_sdma.c',
   'ac_cmdbuf_sdma.h',
+  'ac_cmdbuf_video.c',
+  'ac_cmdbuf_video.h',
   'ac_shader_args.c',
   'ac_shader_args.h',
   'ac_shader_util.c',