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intel/fs: Fix "packed word exception" condition for register regioning

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Fixes: a6bf5f88 ("i965/fs: Enforce common regioning restrictions by SIMD splitting.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9432
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25378>
This commit is contained in:
Sviatoslav Peleshko 2023-09-25 19:16:50 +03:00 • committed by Marge Bot
parent 922bd13152
commit 8f23b45252
2 changed files with 11 additions and 22 deletions
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21
src/intel/ci/hasvk-hsw-fails.txt
View file

@ -1738,24 +1738,3 @@ dEQP-VK.pipeline.monolithic.sampler.view_type.3d.format.d32_sfloat_s8_uint.addre
dEQP-VK.pipeline.monolithic.sampler.view_type.3d.format.d32_sfloat_s8_uint.address_modes.uvw_mode_mirrored_repeat_mode_repeat_mode_clamp_to_border_stencil,Fail
dEQP-VK.pipeline.monolithic.sampler.view_type.3d.format.d32_sfloat_s8_uint.address_modes.uvw_mode_repeat_mode_clamp_to_border_mode_clamp_to_edge_stencil,Fail
dEQP-VK.pipeline.monolithic.sampler.view_type.3d.format.d32_sfloat_s8_uint.address_modes.uvw_mode_repeat_mode_mirrored_repeat_mode_clamp_to_border_stencil,Fail
# https://gitlab.freedesktop.org/mesa/mesa/-/issues/9432
dEQP-VK.graphicsfuzz.spv-access-chains,Fail
dEQP-VK.graphicsfuzz.spv-copy-object,Fail
dEQP-VK.graphicsfuzz.spv-dead-break-and-unroll,Fail
dEQP-VK.graphicsfuzz.spv-stable-maze-O-dead-code,Fail
dEQP-VK.graphicsfuzz.spv-stable-maze-O-memory-accesses,Fail
dEQP-VK.graphicsfuzz.spv-stable-maze-flatten-copy-composite,Fail
dEQP-VK.reconvergence.subgroup_uniform_control_flow_ballot.compute.nesting4.6.49,Fail
dEQP-VK.reconvergence.subgroup_uniform_control_flow_ballot.compute.nesting4.7.31,Fail
dEQP-VK.reconvergence.subgroup_uniform_control_flow_elect.compute.nesting2.1.17,Fail
dEQP-VK.reconvergence.workgroup_uniform_control_flow_ballot.compute.nesting4.1.36,Fail
dEQP-VK.reconvergence.workgroup_uniform_control_flow_elect.compute.nesting3.1.35,Fail
dEQP-VK.reconvergence.workgroup_uniform_control_flow_elect.compute.nesting3.2.33,Fail
dEQP-VK.reconvergence.workgroup_uniform_control_flow_elect.compute.nesting3.5.17,Fail
dEQP-VK.reconvergence.workgroup_uniform_control_flow_elect.compute.nesting4.7.24,Fail
dEQP-VK.transform_feedback.primitives_generated_query.copy.queue_reset.32bit.geom.xfb.rast.line_strip_with_adjacency.pgq_default_xfb_0.single_draw,Fail
dEQP-VK.transform_feedback.simple.query_copy_stride_zero_triangle_strip_0_6_64bits,Fail
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_251_64bits,Fail
dEQP-VK.transform_feedback.simple.winding_line_strip_with_adjacency_8,Fail
dEQP-VK.transform_feedback.simple.xfb_clipdistance_beginqueryindexed_streamid_0_1_512,Fail

12
src/intel/compiler/brw_fs.cpp
View file

@ -4918,13 +4918,23 @@ get_fpu_lowered_simd_width(const struct brw_compiler *compiler,
* restrictions. The code below intentionally doesn't check whether the
* destination type is integer because empirically the hardware doesn't
* seem to care what the actual type is as long as it's dword-aligned.
*
* HSW PRMs also add a note to the second exception:
* "When lower 8 channels are disabled, the sub register of source1
* operand is not incremented. If the lower 8 channels are expected
* to be disabled, say by predication, the instruction must be split
* into pair of simd8 operations."
*
* We can't reliably know if the channels won't be disabled due to,
* for example, IMASK. So, play it safe and disallow packed-word exception
* for src1.
*/
if (devinfo->ver < 8) {
for (unsigned i = 0; i < inst->sources; i++) {
/* IVB implements DF scalars as <0;2,1> regions. */
const bool is_scalar_exception = is_uniform(inst->src[i]) &&
(devinfo->platform == INTEL_PLATFORM_HSW || type_sz(inst->src[i].type) != 8);
const bool is_packed_word_exception =
const bool is_packed_word_exception = i != 1 &&
type_sz(inst->dst.type) == 4 && inst->dst.stride == 1 &&
type_sz(inst->src[i].type) == 2 && inst->src[i].stride == 1;