diff --git a/.pick_status.json b/.pick_status.json
index 1f934f79fad..a91cd5bd113 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -1714,7 +1714,7 @@
         "description": "aco: fix reserving VGPRs for 64-bit attributes in VS prologs",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null,
         "notes": null
diff --git a/src/amd/compiler/instruction_selection/aco_select_vs_prolog.cpp b/src/amd/compiler/instruction_selection/aco_select_vs_prolog.cpp
index 76782c586d2..3638fbc03a5 100644
--- a/src/amd/compiler/instruction_selection/aco_select_vs_prolog.cpp
+++ b/src/amd/compiler/instruction_selection/aco_select_vs_prolog.cpp
@@ -338,6 +338,22 @@ load_unaligned_vs_attrib(Builder& bld, PhysReg dst, Operand desc, Operand index,
    state->current_loads.push_back(load);
 }
 
+bool
+is_last_attribute_large(const struct aco_vs_prolog_info* pinfo)
+{
+   const struct ac_vtx_format_info* vtx_info_table =
+      ac_get_vtx_format_info_table(GFX8, CHIP_POLARIS10);
+   unsigned last_attribute = pinfo->num_attributes - 1;
+
+   if ((pinfo->misaligned_mask & (1u << last_attribute))) {
+      const struct ac_vtx_format_info* vtx_info = &vtx_info_table[pinfo->formats[last_attribute]];
+      if (vtx_info->chan_byte_size == 8 && vtx_info->num_channels > 2)
+         return true;
+   }
+
+   return false;
+}
+
 } // namespace
 
 void
@@ -393,9 +409,11 @@ select_vs_prolog(Program* program, const struct aco_vs_prolog_info* pinfo, ac_sh
       has_nontrivial_divisors && (program->gfx_level <= GFX8 || program->gfx_level >= GFX11);
 
    int vgpr_offset = pinfo->misaligned_mask & (1u << (pinfo->num_attributes - 1)) ? 0 : -4;
+   const bool is_last_attr_large = is_last_attribute_large(pinfo);
 
    unsigned num_vgprs = args->num_vgprs_used;
-   PhysReg attributes_start = get_next_vgpr(pinfo->num_attributes * 4, &num_vgprs);
+   PhysReg attributes_start =
+      get_next_vgpr(pinfo->num_attributes * 4 + (is_last_attr_large ? 4 : 0), &num_vgprs);
    PhysReg vertex_index, instance_index, start_instance_vgpr, nontrivial_tmp_vgpr0,
       nontrivial_tmp_vgpr1;
    if (needs_vertex_index)