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freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
Rob Clark
parent
219440ddeb
commit
8ecbcbf0aa
6 changed files with 65 additions and 18 deletions
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@ -14,7 +14,7 @@ The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15076 bytes, from 2014-12-01 22:40:01)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 64344 bytes, from 2014-12-03 14:14:54)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 49060 bytes, from 2014-12-03 22:36:15)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 50255 bytes, from 2014-12-07 18:43:56)
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Copyright (C) 2013-2014 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@ -14,7 +14,7 @@ The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15076 bytes, from 2014-12-01 22:40:01)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 64344 bytes, from 2014-12-03 14:14:54)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 49060 bytes, from 2014-12-03 22:36:15)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 50255 bytes, from 2014-12-07 18:43:56)
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Copyright (C) 2013-2014 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@ -14,7 +14,7 @@ The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15076 bytes, from 2014-12-01 22:40:01)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 64344 bytes, from 2014-12-03 14:14:54)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 49060 bytes, from 2014-12-03 22:36:15)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 50255 bytes, from 2014-12-07 18:43:56)
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Copyright (C) 2013-2014 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@ -91,6 +91,7 @@ enum a4xx_vtx_fmt {
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VFMT4_16_16_UNORM = 29,
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VFMT4_16_16_16_UNORM = 30,
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VFMT4_16_16_16_16_UNORM = 31,
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VFMT4_32_32_SINT = 37,
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VFMT4_8_UINT = 40,
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VFMT4_8_8_UINT = 41,
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VFMT4_8_8_8_UINT = 42,
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@ -132,6 +133,14 @@ enum a4xx_tex_fmt {
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TFMT4_32_32_32_32_FLOAT = 63,
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};
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enum a4xx_tex_fetchsize {
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TFETCH4_1_BYTE = 0,
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TFETCH4_2_BYTE = 1,
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TFETCH4_4_BYTE = 2,
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TFETCH4_8_BYTE = 3,
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TFETCH4_16_BYTE = 4,
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};
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enum a4xx_depth_format {
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DEPTH4_NONE = 0,
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DEPTH4_16 = 1,
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@ -265,14 +274,19 @@ static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)
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return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK;
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}
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#define REG_A4XX_RB_MSAA_CONTROL2 0x000020a3
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#define A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES__MASK 0x00000380
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#define A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES__SHIFT 7
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static inline uint32_t A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES(uint32_t val)
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#define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3
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#define A4XX_RB_RENDER_CONTROL2_XCOORD 0x00000001
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#define A4XX_RB_RENDER_CONTROL2_YCOORD 0x00000002
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#define A4XX_RB_RENDER_CONTROL2_ZCOORD 0x00000004
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#define A4XX_RB_RENDER_CONTROL2_WCOORD 0x00000008
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#define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020
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#define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380
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#define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7
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static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val)
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{
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return ((val) << A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES__MASK;
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return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK;
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}
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#define A4XX_RB_MSAA_CONTROL2_VARYING 0x00001000
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#define A4XX_RB_RENDER_CONTROL2_VARYING 0x00001000
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static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
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@ -1122,7 +1136,9 @@ static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
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{
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return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
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}
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#define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000
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#define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000
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#define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000
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#define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea
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#define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
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@ -1447,6 +1463,7 @@ static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val)
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{
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return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK;
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}
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#define A4XX_VFD_DECODE_INSTR_INT 0x00100000
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#define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000
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#define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22
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static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
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@ -1743,6 +1760,12 @@ static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize
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}
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#define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
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#define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200
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#define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000
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#define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16
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static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK;
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}
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#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORD 0x02000000
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#define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2
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@ -1752,6 +1775,12 @@ static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
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}
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#define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc
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#define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2
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static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
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}
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#define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3
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#define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff
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@ -2107,6 +2136,12 @@ static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val)
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}
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#define REG_A4XX_TEX_CONST_2 0x00000002
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#define A4XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
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#define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
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static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val)
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{
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return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK;
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}
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#define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00
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#define A4XX_TEX_CONST_2_PITCH__SHIFT 9
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static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val)
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@ -2121,19 +2156,31 @@ static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
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}
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#define REG_A4XX_TEX_CONST_3 0x00000003
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#define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x0000000f
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#define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff
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#define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0
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static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val)
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{
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return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK;
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}
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#define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000
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#define A4XX_TEX_CONST_3_DEPTH__SHIFT 18
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static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val)
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{
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return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK;
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}
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#define REG_A4XX_TEX_CONST_4 0x00000004
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#define A4XX_TEX_CONST_4_BASE__MASK 0xffffffff
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#define A4XX_TEX_CONST_4_BASE__SHIFT 0
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#define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f
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#define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0
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static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val)
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{
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return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK;
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}
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#define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0
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#define A4XX_TEX_CONST_4_BASE__SHIFT 5
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static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val)
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{
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return ((val) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK;
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return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK;
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}
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#define REG_A4XX_TEX_CONST_5 0x00000005
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@ -371,9 +371,9 @@ fd4_program_emit(struct fd_ringbuffer *ring, struct fd4_emit *emit)
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OUT_RING(ring, A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
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A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[GS].instroff));
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OUT_PKT0(ring, REG_A4XX_RB_MSAA_CONTROL2, 1);
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OUT_RING(ring, A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES(0) |
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COND(s[FS].v->total_in > 0, A4XX_RB_MSAA_CONTROL2_VARYING));
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OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL2, 1);
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OUT_RING(ring, A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(0) |
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COND(s[FS].v->total_in > 0, A4XX_RB_RENDER_CONTROL2_VARYING));
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OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT_REG, 1);
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OUT_RING(ring, A4XX_RB_FS_OUTPUT_REG_COLOR_PIPE_ENABLE |
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@ -14,7 +14,7 @@ The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15076 bytes, from 2014-12-01 22:40:01)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 64344 bytes, from 2014-12-03 14:14:54)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 49060 bytes, from 2014-12-03 22:36:15)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 50255 bytes, from 2014-12-07 18:43:56)
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Copyright (C) 2013-2014 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@ -14,7 +14,7 @@ The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15076 bytes, from 2014-12-01 22:40:01)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 64344 bytes, from 2014-12-03 14:14:54)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 49060 bytes, from 2014-12-03 22:36:15)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 50255 bytes, from 2014-12-07 18:43:56)
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Copyright (C) 2013-2014 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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