fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-05 20:28:04 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

ac: Fix typo RENCDOE -> RENCODE

Browse source 
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31113>
This commit is contained in:
David Rosca 2024-09-16 17:10:13 +02:00 • committed by Marge Bot
parent d6cf36b4d2
commit 8ecad47695
5 changed files with 16 additions and 16 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
src/amd/common/ac_vcn_enc.h
View file

@ -135,8 +135,8 @@
#define RENCODE_AV1_DELTA_FRAME_ID_LENGTH 15
#define RENCODE_AV1_ADDITIONAL_FRAME_ID_LENGTH 1
#define RENCDOE_AV1_NUM_REF_FRAMES 8
#define RENCDOE_AV1_REFS_PER_FRAME 7
#define RENCODE_AV1_NUM_REF_FRAMES 8
#define RENCODE_AV1_REFS_PER_FRAME 7
#define RENCODE_AV1_SDB_FRAME_CONTEXT_SIZE 947200
#define RENCODE_AV1_FRAME_CONTEXT_CDF_TABLE_SIZE 22528
#define RENCODE_AV1_CDEF_ALGORITHM_FRAME_CONTEXT_SIZE (64 * 8 * 3)
@ -475,7 +475,7 @@ typedef struct rvcn_enc_hevc_encode_params_s {
} rvcn_enc_hevc_encode_params_t;
typedef struct rvcn_enc_av1_encode_params_s {
uint32_t ref_frames[RENCDOE_AV1_REFS_PER_FRAME];
uint32_t ref_frames[RENCODE_AV1_REFS_PER_FRAME];
uint32_t lsm_reference_frame_index[2];
} rvcn_enc_av1_encode_params_t;

4
src/gallium/drivers/radeonsi/radeon_vcn_enc.c
View file

@ -906,10 +906,10 @@ static void radeon_vcn_enc_av1_get_param(struct radeon_encoder *enc,
/* 1, 2 layer needs 1 reference, and 3, 4 layer needs 2 references */
enc->base.max_references = (enc_pic->num_temporal_layers + 1) / 2
+ RENCODE_VCN4_AV1_MAX_NUM_LTR;
for (int i = 0; i < RENCDOE_AV1_REFS_PER_FRAME; i++)
for (int i = 0; i < RENCODE_AV1_REFS_PER_FRAME; i++)
enc_pic->av1_ref_frame_idx[i] = pic->ref_frame_idx[i];
for (int i = 0; i < RENCDOE_AV1_NUM_REF_FRAMES; i++)
for (int i = 0; i < RENCODE_AV1_NUM_REF_FRAMES; i++)
enc_pic->av1_ref_list[i] = pic->ref_list[i];
enc_pic->av1_recon_frame = pic->recon_frame;

10
src/gallium/drivers/radeonsi/radeon_vcn_enc.h
View file

@ -125,7 +125,7 @@ struct radeon_enc_pic {
uint32_t refresh_frame_flags;
uint32_t reference_delta_frame_id;
uint32_t reference_frame_index;
uint32_t reference_order_hint[RENCDOE_AV1_NUM_REF_FRAMES];
uint32_t reference_order_hint[RENCODE_AV1_NUM_REF_FRAMES];
uint32_t *copy_start;
};
rvcn_enc_av1_spec_misc_t av1_spec_misc;
@ -133,10 +133,10 @@ struct radeon_enc_pic {
rvcn_enc_av1_timing_info_t av1_timing_info;
rvcn_enc_av1_color_description_t av1_color_description;
uint32_t count_last_layer;
rvcn_enc_av1_ref_frame_t frames[RENCDOE_AV1_NUM_REF_FRAMES];
rvcn_enc_av1_recon_slot_t recon_slots[RENCDOE_AV1_NUM_REF_FRAMES + 1];
uint8_t av1_ref_frame_idx[RENCDOE_AV1_REFS_PER_FRAME];
void *av1_ref_list[RENCDOE_AV1_NUM_REF_FRAMES];
rvcn_enc_av1_ref_frame_t frames[RENCODE_AV1_NUM_REF_FRAMES];
rvcn_enc_av1_recon_slot_t recon_slots[RENCODE_AV1_NUM_REF_FRAMES + 1];
uint8_t av1_ref_frame_idx[RENCODE_AV1_REFS_PER_FRAME];
void *av1_ref_list[RENCODE_AV1_NUM_REF_FRAMES];
void *av1_recon_frame;
uint32_t av1_ref_frame_ctrl_l0;
uint32_t av1_ref_frame_ctrl_l1;

6
src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c
View file

@ -320,7 +320,7 @@ static bool radeon_enc_av1_search_requested_reference(
enc->enc_pic.av1_ref_frame_idx[marked_ref_frame_idx - 1];
void *request_signature = NULL;
if (requested_frame_idx >= RENCDOE_AV1_NUM_REF_FRAMES)
if (requested_frame_idx >= RENCODE_AV1_NUM_REF_FRAMES)
goto end;
request_signature = enc->enc_pic.av1_ref_list[requested_frame_idx];
@ -828,7 +828,7 @@ static void radeon_enc_av1_frame_header(struct radeon_encoder *enc, bool frame_h
if ((!frame_is_intra || enc->enc_pic.refresh_frame_flags != 0xff) &&
error_resilient_mode && enc->enc_pic.enable_order_hint)
for (i = 0; i < RENCDOE_AV1_NUM_REF_FRAMES; i++)
for (i = 0; i < RENCODE_AV1_NUM_REF_FRAMES; i++)
/* ref_order_hint */
radeon_enc_code_fixed_bits(enc, enc->enc_pic.reference_order_hint[i], enc->enc_pic.order_hint_bits);
@ -849,7 +849,7 @@ static void radeon_enc_av1_frame_header(struct radeon_encoder *enc, bool frame_h
if (enc->enc_pic.enable_order_hint)
/* frame_refs_short_signaling */
radeon_enc_code_fixed_bits(enc, 0, 1);
for (i = 0; i < RENCDOE_AV1_REFS_PER_FRAME; i++) {
for (i = 0; i < RENCODE_AV1_REFS_PER_FRAME; i++) {
/* ref_frame_idx */
radeon_enc_code_fixed_bits(enc, enc->enc_pic.reference_frame_index, 3);
if (enc->enc_pic.frame_id_numbers_present)

6
src/gallium/drivers/radeonsi/radeon_vcn_enc_5_0.c
View file

@ -394,7 +394,7 @@ static void radeon_enc_encode_params_av1(struct radeon_encoder *enc)
RADEON_ENC_BEGIN(enc->cmd.enc_params_av1);
RADEON_ENC_CS(enc->enc_pic.av1_enc_params.ref_frames[0]);
for (int i = 1; i < RENCDOE_AV1_REFS_PER_FRAME; i++)
for (int i = 1; i < RENCODE_AV1_REFS_PER_FRAME; i++)
RADEON_ENC_CS(0xFFFFFFFF);
RADEON_ENC_CS(enc->enc_pic.av1_enc_params.lsm_reference_frame_index[0]);
RADEON_ENC_CS(0xFFFFFFFF);
@ -841,7 +841,7 @@ static void radeon_enc_av1_frame_header(struct radeon_encoder *enc, bool frame_h
if ((!frame_is_intra || enc->enc_pic.refresh_frame_flags != 0xff) &&
error_resilient_mode && enc->enc_pic.enable_order_hint)
for (i = 0; i < RENCDOE_AV1_NUM_REF_FRAMES; i++)
for (i = 0; i < RENCODE_AV1_NUM_REF_FRAMES; i++)
/* ref_order_hint */
radeon_enc_code_fixed_bits(enc, enc->enc_pic.reference_order_hint[i], enc->enc_pic.order_hint_bits);
@ -862,7 +862,7 @@ static void radeon_enc_av1_frame_header(struct radeon_encoder *enc, bool frame_h
if (enc->enc_pic.enable_order_hint)
/* frame_refs_short_signaling */
radeon_enc_code_fixed_bits(enc, 0, 1);
for (i = 0; i < RENCDOE_AV1_REFS_PER_FRAME; i++) {
for (i = 0; i < RENCODE_AV1_REFS_PER_FRAME; i++) {
/* ref_frame_idx */
radeon_enc_code_fixed_bits(enc, enc->enc_pic.reference_frame_index, 3);
if (enc->enc_pic.frame_id_numbers_present)