From 8e96b516ca4ed4e81d288f730d1931e1ce663118 Mon Sep 17 00:00:00 2001 From: Nanley Chery Date: Tue, 14 May 2024 12:57:20 -0400 Subject: [PATCH] intel/isl: Assert alignments of surface addresses In the import paths in iris, there are several cases where surface VMAs are created without relying on the calculated surface alignment. Asserting the alignments of surface addresses, should help catch any cases where we end up with the wrong alignment. This found a couple issues during development. One which required a change to existing code is that when creating uncompressed surfaces from compressed ones, ISL will sometimes increase the image alignment as a result of the new format supporting CCS. This patch adds the usage flag to disable that behavior. Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/isl/isl.c | 15 +++++++++++++-- src/intel/isl/isl_emit_cpb.c | 2 ++ src/intel/isl/isl_emit_depth_stencil.c | 3 +++ src/intel/isl/isl_surface_state.c | 2 ++ 4 files changed, 20 insertions(+), 2 deletions(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 36d5d3f6842..3222f4baba3 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -4057,11 +4057,22 @@ isl_surf_get_uncompressed_surf(const struct isl_device *dev, x_offset_el, y_offset_el); + isl_surf_usage_flags_t usage = surf->usage; + /* Even for cube maps there will be only single face, therefore drop * the corresponding flag if present. */ - const isl_surf_usage_flags_t usage = - surf->usage & (~ISL_SURF_USAGE_CUBE_BIT); + usage &= ~ISL_SURF_USAGE_CUBE_BIT; + + /* CCS-enabled surfaces can have different layout requirements than + * surfaces without CCS support. So, for accuracy, disable CCS + * support if the original surface lacked it. + */ + if (_isl_surf_info_supports_ccs(dev, surf->format, surf->usage) != + _isl_surf_info_supports_ccs(dev, view_format, usage)) { + assert(_isl_surf_info_supports_ccs(dev, view_format, usage)); + usage |= ISL_SURF_USAGE_DISABLE_AUX_BIT; + } bool ok UNUSED; ok = isl_surf_init(dev, ucompr_surf, diff --git a/src/intel/isl/isl_emit_cpb.c b/src/intel/isl/isl_emit_cpb.c index a546b5bb909..e53055d13d0 100644 --- a/src/intel/isl/isl_emit_cpb.c +++ b/src/intel/isl/isl_emit_cpb.c @@ -100,6 +100,8 @@ isl_genX(emit_cpb_control_s)(const struct isl_device *dev, void *batch, cpb.MOCS = info->mocs; cpb.SurfaceQPitch = isl_surf_get_array_pitch_sa_rows(info->surf) >> 2; cpb.TiledMode = isl_encode_tiling[info->surf->tiling]; + + assert(info->address % info->surf->alignment_B == 0); cpb.SurfaceBaseAddress = info->address; cpb.MipTailStartLOD = info->surf->miptail_start_level; diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c index d7d2f24c43a..0e66aa5720b 100644 --- a/src/intel/isl/isl_emit_depth_stencil.c +++ b/src/intel/isl/isl_emit_depth_stencil.c @@ -167,6 +167,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, #if GFX_VER >= 7 db.DepthWriteEnable = true; #endif + assert(info->depth_address % info->depth_surf->alignment_B == 0); db.SurfaceBaseAddress = info->depth_address; #if GFX_VERx10 >= 125 @@ -269,6 +270,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, #elif GFX_VERx10 >= 75 sb.StencilBufferEnable = true; #endif + assert(info->stencil_address % info->stencil_surf->alignment_B == 0); sb.SurfaceBaseAddress = info->stencil_address; sb.SurfacePitch = info->stencil_surf->row_pitch_B - 1; #if GFX_VER >= 8 @@ -310,6 +312,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, assert(GFX_VER >= 12 || info->hiz_usage == ISL_AUX_USAGE_HIZ); db.HierarchicalDepthBufferEnable = true; + assert(info->hiz_address % info->hiz_surf->alignment_B == 0); hiz.SurfaceBaseAddress = info->hiz_address; hiz.SurfacePitch = info->hiz_surf->row_pitch_B - 1; diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index ec338529b01..f3516fe9bb2 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -611,6 +611,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, assert(isl_swizzle_is_identity(info->view->swizzle)); #endif + assert(info->address % info->surf->alignment_B == 0); s.SurfaceBaseAddress = info->address; #if GFX_VER >= 6 @@ -824,6 +825,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, uint32_t pitch_in_tiles = info->aux_surf->row_pitch_B / tile_info.phys_extent_B.width; + assert(info->aux_address % info->aux_surf->alignment_B == 0); s.AuxiliarySurfaceBaseAddress = info->aux_address; s.AuxiliarySurfacePitch = pitch_in_tiles - 1;