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radv: implement fullyCoveredFragmentShaderInputVariable

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1 means INNER_COVERAGE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21497>
This commit is contained in:
Samuel Pitoiset 2023-02-22 16:34:55 +01:00 • committed by Marge Bot
parent ebbb0d3f1b
commit 8e84251cc7
3 changed files with 18 additions and 3 deletions
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13
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -1877,6 +1877,9 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
cmd_buffer->state.emitted_graphics_pipeline->db_render_control != pipeline->db_render_control ||
cmd_buffer->state.emitted_graphics_pipeline->rast_prim != pipeline->rast_prim)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES;
if (cmd_buffer->state.emitted_graphics_pipeline->uses_inner_coverage != pipeline->uses_inner_coverage)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_CONSERVATIVE_RAST_MODE;
}
radeon_emit_array(cmd_buffer->cs, pipeline->base.cs.buf, pipeline->base.cs.cdw);
@ -2473,6 +2476,7 @@ radv_emit_patch_control_points(struct radv_cmd_buffer *cmd_buffer)
static void
radv_emit_conservative_rast_mode(struct radv_cmd_buffer *cmd_buffer)
{
const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
const struct radv_physical_device *pdevice = cmd_buffer->device->physical_device;
const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
@ -2483,13 +2487,13 @@ radv_emit_conservative_rast_mode(struct radv_cmd_buffer *cmd_buffer)
pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) | S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
if (d->vk.rs.conservative_mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
/* Inner coverage requires underestimate conservative rasterization. */
if (d->vk.rs.conservative_mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT &&
!pipeline->uses_inner_coverage) {
pa_sc_conservative_rast |= S_028C4C_OVER_RAST_ENABLE(1) |
S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
} else {
assert(d->vk.rs.conservative_mode ==
VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
pa_sc_conservative_rast |=
S_028C4C_OVER_RAST_SAMPLE_SELECT(1) | S_028C4C_UNDER_RAST_ENABLE(1);
}
@ -4224,6 +4228,7 @@ lookup_ps_epilog(struct radv_cmd_buffer *cmd_buffer)
static void
radv_emit_msaa_state(struct radv_cmd_buffer *cmd_buffer)
{
const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
const struct radv_physical_device *pdevice = cmd_buffer->device->physical_device;
unsigned rasterization_samples = radv_get_rasterization_samples(cmd_buffer);
const struct radv_rendering_state *render = &cmd_buffer->state.render;
@ -4283,6 +4288,8 @@ radv_emit_msaa_state(struct radv_cmd_buffer *cmd_buffer)
S_028BE0_COVERED_CENTROID_IS_CENTER(pdevice->rad_info.gfx_level >= GFX10_3);
}
pa_sc_aa_config |= S_028BE0_COVERAGE_TO_SHADER_SELECT(pipeline->uses_inner_coverage);
radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, db_eqaa);
radeon_set_context_reg(cmd_buffer->cs, R_028BE0_PA_SC_AA_CONFIG, pa_sc_aa_config);
radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,

2
src/amd/vulkan/radv_pipeline.c
View file

@ -4973,6 +4973,8 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
pipeline->force_vrs_per_vertex =
pipeline->base.shaders[pipeline->last_vgt_api_stage]->info.force_vrs_per_vertex;
pipeline->uses_user_sample_locations = state.ms && state.ms->sample_locations_enable;
pipeline->uses_inner_coverage =
pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.ps.reads_fully_covered;
pipeline->rast_prim = vgt_gs_out_prim_type;
pipeline->last_vgt_api_stage_locs = pipeline->base.shaders[pipeline->last_vgt_api_stage]->info.user_sgprs_locs.shader_data;

6
src/amd/vulkan/radv_private.h
View file

@ -2190,6 +2190,12 @@ struct radv_graphics_pipeline {
bool use_per_attribute_vb_descs;
bool can_use_simple_input;
bool uses_user_sample_locations;
/* Whether the pipeline uses inner coverage which means that a fragment has all of its pixel
* squares fully covered by the generating primitive.
*/
bool uses_inner_coverage;
bool need_null_export_workaround;
/* Whether the pipeline forces per-vertex VRS (GFX10.3+). */
bool force_vrs_per_vertex;