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iris: Emit STATE_SYSTEM_MEM_FENCE_ADDRESS

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According to HAS it is necessary to emit this instruction once per
context so MI_MEM_FENCE works properly.

Fixes: 86813c60a4 ("mi-builder: add read/write memory fencing support on Gfx20+")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32680>
This commit is contained in:
José Roberto de Souza 2024-12-16 11:12:11 -08:00 • committed by Marge Bot
parent 2bd3df75e5
commit 8e8097245f
3 changed files with 43 additions and 2 deletions
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28
src/gallium/drivers/iris/iris_bufmgr.c
View file

@ -242,6 +242,7 @@ struct iris_bufmgr {
struct iris_border_color_pool border_color_pool;
struct iris_bo *dummy_aux_bo;
struct iris_bo *mem_fence_bo;
};
static simple_mtx_t global_bufmgr_list_mutex = SIMPLE_MTX_INITIALIZER;
@ -1829,6 +1830,7 @@ static void
iris_bufmgr_destroy(struct iris_bufmgr *bufmgr)
{
iris_bo_unreference(bufmgr->dummy_aux_bo);
iris_bo_unreference(bufmgr->mem_fence_bo);
iris_destroy_border_color_pool(&bufmgr->border_color_pool);
@ -2463,12 +2465,28 @@ iris_bufmgr_create(struct intel_device_info *devinfo, int fd, bool bo_reuse)
bufmgr->dummy_aux_bo = iris_bo_alloc(bufmgr, "dummy_aux", 4096, 4096,
IRIS_MEMZONE_OTHER, BO_ALLOC_PLAIN);
if (!bufmgr->dummy_aux_bo)
goto error_dummy_aux;
goto error_alloc_bo;
}
/* Programming note from MI_MEM_FENCE specification:
*
* Software must ensure STATE_SYSTEM_MEM_FENCE_ADDRESS command is
* programmed prior to programming this command.
*
* HAS 1607240579 then provides the size information: 4K
*/
if (devinfo->verx10 >= 200) {
bufmgr->mem_fence_bo = iris_bo_alloc(bufmgr, "mem_fence", 4096, 4096,
IRIS_MEMZONE_OTHER, BO_ALLOC_SMEM);
if (!bufmgr->dummy_aux_bo)
goto error_alloc_bo;
}
return bufmgr;
error_dummy_aux:
error_alloc_bo:
iris_bo_unreference(bufmgr->dummy_aux_bo);
iris_bo_unreference(bufmgr->mem_fence_bo);
iris_destroy_border_color_pool(&bufmgr->border_color_pool);
intel_aux_map_finish(bufmgr->aux_map_ctx);
_mesa_hash_table_destroy(bufmgr->handle_table, NULL);
@ -2663,3 +2681,9 @@ iris_bufmgr_get_dummy_aux_address(struct iris_bufmgr *bufmgr)
{
return bufmgr->dummy_aux_bo ? bufmgr->dummy_aux_bo->address : 0;
}
struct iris_bo *
iris_bufmgr_get_mem_fence_bo(struct iris_bufmgr *bufmgr)
{
return bufmgr->mem_fence_bo;
}

1
src/gallium/drivers/iris/iris_bufmgr.h
View file

@ -665,6 +665,7 @@ bool iris_bufmgr_use_global_vm_id(struct iris_bufmgr *bufmgr);
struct intel_bind_timeline *iris_bufmgr_get_bind_timeline(struct iris_bufmgr *bufmgr);
bool iris_bufmgr_compute_engine_supported(struct iris_bufmgr *bufmgr);
uint64_t iris_bufmgr_get_dummy_aux_address(struct iris_bufmgr *bufmgr);
struct iris_bo *iris_bufmgr_get_mem_fence_bo(struct iris_bufmgr *bufmgr);
enum iris_madvice {
IRIS_MADVICE_WILL_NEED = 0,

16
src/gallium/drivers/iris/iris_state.c
View file

@ -1148,6 +1148,18 @@ iris_disable_rhwo_optimization(struct iris_batch *batch, bool disable)
#endif
}
static void
state_system_mem_fence_address_emit(struct iris_batch *batch)
{
#if GFX_VERx10 >= 200
struct iris_screen *screen = batch->screen;
struct iris_address addr = { .bo = iris_bufmgr_get_mem_fence_bo(screen->bufmgr) };
iris_emit_cmd(batch, GENX(STATE_SYSTEM_MEM_FENCE_ADDRESS), mem_fence_addr) {
mem_fence_addr.SystemMemoryFenceAddress = addr;
}
#endif
}
/**
* Upload initial GPU state for any kind of context.
*
@ -1196,6 +1208,8 @@ iris_init_common_context(struct iris_batch *batch)
reg.CrossTilePartialWriteMergeEnable = true;
}
#endif
state_system_mem_fence_address_emit(batch);
}
static void
@ -1543,6 +1557,8 @@ iris_init_copy_context(struct iris_batch *batch)
init_aux_map_state(batch);
#endif
state_system_mem_fence_address_emit(batch);
iris_batch_sync_region_end(batch);
}