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intel/eu: Provide single descriptor argument to brw_send_indirect_surface_message().

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Instead of the current message_len, response_len and header_present
arguments.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Francisco Jerez 2018-06-07 15:19:49 -07:00
parent b10b4e7c45
commit 8e707fc2af
1 changed files with 36 additions and 29 deletions
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65
src/intel/compiler/brw_eu_emit.c
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@ -2483,11 +2483,8 @@ brw_send_indirect_surface_message(struct brw_codegen *p,
struct brw_reg dst,
struct brw_reg payload,
struct brw_reg surface,
unsigned message_len,
unsigned response_len,
bool header_present)
unsigned desc_imm)
{
const struct gen_device_info *devinfo = p->devinfo;
struct brw_inst *insn;
if (surface.file != BRW_IMMEDIATE_VALUE) {
@ -2512,10 +2509,7 @@ brw_send_indirect_surface_message(struct brw_codegen *p,
surface = addr;
}
insn = brw_send_indirect_message(p, sfid, dst, payload, surface, 0);
brw_inst_set_mlen(devinfo, insn, message_len);
brw_inst_set_rlen(devinfo, insn, response_len);
brw_inst_set_header_present(devinfo, insn, header_present);
insn = brw_send_indirect_message(p, sfid, dst, payload, surface, desc_imm);
return insn;
}
@ -2805,6 +2799,10 @@ brw_untyped_atomic(struct brw_codegen *p,
const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN7_SFID_DATAPORT_DATA_CACHE);
const unsigned response_length = brw_surface_payload_size(
p, response_expected, devinfo->gen >= 8 || devinfo->is_haswell, true);
const unsigned desc =
brw_message_desc(devinfo, msg_length, response_length, header_present);
const bool align1 = brw_get_default_access_mode(p) == BRW_ALIGN_1;
/* Mask out unused components -- This is especially important in Align16
* mode on generations that don't have native support for SIMD4x2 atomics,
@ -2814,10 +2812,7 @@ brw_untyped_atomic(struct brw_codegen *p,
*/
const unsigned mask = align1 ? WRITEMASK_XYZW : WRITEMASK_X;
struct brw_inst *insn = brw_send_indirect_surface_message(
p, sfid, brw_writemask(dst, mask), payload, surface, msg_length,
brw_surface_payload_size(p, response_expected,
devinfo->gen >= 8 || devinfo->is_haswell, true),
header_present);
p, sfid, brw_writemask(dst, mask), payload, surface, desc);
brw_set_dp_untyped_atomic_message(
p, insn, atomic_op, response_expected);
@ -2858,10 +2853,12 @@ brw_untyped_surface_read(struct brw_codegen *p,
const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN7_SFID_DATAPORT_DATA_CACHE);
const unsigned response_length =
brw_surface_payload_size(p, num_channels, true, true);
const unsigned desc =
brw_message_desc(devinfo, msg_length, response_length, false);
struct brw_inst *insn = brw_send_indirect_surface_message(
p, sfid, dst, payload, surface, msg_length,
brw_surface_payload_size(p, num_channels, true, true),
false);
p, sfid, dst, payload, surface, desc);
brw_set_dp_untyped_surface_read_message(
p, insn, num_channels);
@ -2907,13 +2904,15 @@ brw_untyped_surface_write(struct brw_codegen *p,
const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN7_SFID_DATAPORT_DATA_CACHE);
const unsigned desc =
brw_message_desc(devinfo, msg_length, 0, header_present);
const bool align1 = brw_get_default_access_mode(p) == BRW_ALIGN_1;
/* Mask out unused components -- See comment in brw_untyped_atomic(). */
const unsigned mask = devinfo->gen == 7 && !devinfo->is_haswell && !align1 ?
WRITEMASK_X : WRITEMASK_XYZW;
struct brw_inst *insn = brw_send_indirect_surface_message(
p, sfid, brw_writemask(brw_null_reg(), mask),
payload, surface, msg_length, 0, header_present);
payload, surface, desc);
brw_set_dp_untyped_surface_write_message(
p, insn, num_channels);
@ -2947,11 +2946,13 @@ brw_byte_scattered_read(struct brw_codegen *p,
assert(devinfo->gen > 7 || devinfo->is_haswell);
assert(brw_get_default_access_mode(p) == BRW_ALIGN_1);
const unsigned sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
const unsigned response_length =
brw_surface_payload_size(p, 1, true, true);
const unsigned desc =
brw_message_desc(devinfo, msg_length, response_length, false);
struct brw_inst *insn = brw_send_indirect_surface_message(
p, sfid, dst, payload, surface, msg_length,
brw_surface_payload_size(p, 1, true, true),
false);
p, sfid, dst, payload, surface, desc);
unsigned msg_control =
brw_byte_scattered_data_element_from_bit_size(bit_size) << 2;
@ -2978,10 +2979,12 @@ brw_byte_scattered_write(struct brw_codegen *p,
assert(devinfo->gen > 7 || devinfo->is_haswell);
assert(brw_get_default_access_mode(p) == BRW_ALIGN_1);
const unsigned sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
const unsigned desc =
brw_message_desc(devinfo, msg_length, 0, header_present);
struct brw_inst *insn = brw_send_indirect_surface_message(
p, sfid, brw_writemask(brw_null_reg(), WRITEMASK_XYZW),
payload, surface, msg_length, 0, header_present);
payload, surface, desc);
unsigned msg_control =
brw_byte_scattered_data_element_from_bit_size(bit_size) << 2;
@ -3043,14 +3046,15 @@ brw_typed_atomic(struct brw_codegen *p,
const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN6_SFID_DATAPORT_RENDER_CACHE);
const unsigned response_length = brw_surface_payload_size(
p, response_expected, devinfo->gen >= 8 || devinfo->is_haswell, false);
const unsigned desc =
brw_message_desc(devinfo, msg_length, response_length, header_present);
const bool align1 = brw_get_default_access_mode(p) == BRW_ALIGN_1;
/* Mask out unused components -- See comment in brw_untyped_atomic(). */
const unsigned mask = align1 ? WRITEMASK_XYZW : WRITEMASK_X;
struct brw_inst *insn = brw_send_indirect_surface_message(
p, sfid, brw_writemask(dst, mask), payload, surface, msg_length,
brw_surface_payload_size(p, response_expected,
devinfo->gen >= 8 || devinfo->is_haswell, false),
header_present);
p, sfid, brw_writemask(dst, mask), payload, surface, desc);
brw_set_dp_typed_atomic_message(
p, insn, atomic_op, response_expected);
@ -3101,11 +3105,12 @@ brw_typed_surface_read(struct brw_codegen *p,
const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN6_SFID_DATAPORT_RENDER_CACHE);
const unsigned response_length = brw_surface_payload_size(
p, num_channels, devinfo->gen >= 8 || devinfo->is_haswell, false);
const unsigned desc =
brw_message_desc(devinfo, msg_length, response_length, header_present);
struct brw_inst *insn = brw_send_indirect_surface_message(
p, sfid, dst, payload, surface, msg_length,
brw_surface_payload_size(p, num_channels,
devinfo->gen >= 8 || devinfo->is_haswell, false),
header_present);
p, sfid, dst, payload, surface, desc);
brw_set_dp_typed_surface_read_message(
p, insn, num_channels);
@ -3156,13 +3161,15 @@ brw_typed_surface_write(struct brw_codegen *p,
const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN6_SFID_DATAPORT_RENDER_CACHE);
const unsigned desc =
brw_message_desc(devinfo, msg_length, 0, header_present);
const bool align1 = brw_get_default_access_mode(p) == BRW_ALIGN_1;
/* Mask out unused components -- See comment in brw_untyped_atomic(). */
const unsigned mask = (devinfo->gen == 7 && !devinfo->is_haswell && !align1 ?
WRITEMASK_X : WRITEMASK_XYZW);
struct brw_inst *insn = brw_send_indirect_surface_message(
p, sfid, brw_writemask(brw_null_reg(), mask),
payload, surface, msg_length, 0, header_present);
payload, surface, desc);
brw_set_dp_typed_surface_write_message(
p, insn, num_channels);