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radv: use vk_image::array_layers instead of radv_image::info::array_size

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22816>
This commit is contained in:
Samuel Pitoiset 2023-05-03 08:21:04 +02:00 • committed by Marge Bot
parent b7b9657a70
commit 8e62bb0dfe
8 changed files with 29 additions and 29 deletions
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12
src/amd/vulkan/meta/radv_meta_clear.c
View file

@ -793,12 +793,12 @@ radv_can_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer, const struct radv_
clear_rect->rect.extent.height != iview->image->info.height)
return false;
if (view_mask && (iview->image->info.array_size >= 32 ||
(1u << iview->image->info.array_size) - 1u != view_mask))
if (view_mask && (iview->image->vk.array_layers >= 32 ||
(1u << iview->image->vk.array_layers) - 1u != view_mask))
return false;
if (!view_mask && clear_rect->baseArrayLayer != 0)
return false;
if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
if (!view_mask && clear_rect->layerCount != iview->image->vk.array_layers)
return false;
if (cmd_buffer->device->vk.enabled_extensions.EXT_depth_range_unrestricted &&
@ -1731,12 +1731,12 @@ radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, const struct radv_
clear_rect->rect.extent.height != iview->image->info.height)
return false;
if (view_mask && (iview->image->info.array_size >= 32 ||
(1u << iview->image->info.array_size) - 1u != view_mask))
if (view_mask && (iview->image->vk.array_layers >= 32 ||
(1u << iview->image->vk.array_layers) - 1u != view_mask))
return false;
if (!view_mask && clear_rect->baseArrayLayer != 0)
return false;
if (!view_mask && clear_rect->layerCount != iview->image->info.array_size)
if (!view_mask && clear_rect->layerCount != iview->image->vk.array_layers)
return false;
/* DCC */

2
src/amd/vulkan/meta/radv_meta_dcc_retile.c
View file

@ -185,7 +185,7 @@ radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image)
struct radv_buffer buffer;
assert(image->vk.image_type == VK_IMAGE_TYPE_2D);
assert(image->info.array_size == 1 && image->vk.mip_levels == 1);
assert(image->vk.array_layers == 1 && image->vk.mip_levels == 1);
struct radv_cmd_state *state = &cmd_buffer->state;

2
src/amd/vulkan/meta/radv_meta_fast_clear.c
View file

@ -571,7 +571,7 @@ radv_process_color_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *
}
if (radv_dcc_enabled(image, subresourceRange->baseMipLevel) &&
(image->info.array_size != vk_image_subresource_layer_count(&image->vk, subresourceRange) ||
(image->vk.array_layers != vk_image_subresource_layer_count(&image->vk, subresourceRange) ||
subresourceRange->baseArrayLayer != 0)) {
/* Only use predication if the image has DCC with mipmaps or
* if the range of layers covers the whole image because the

2
src/amd/vulkan/meta/radv_meta_fmask_copy.c
View file

@ -248,7 +248,7 @@ radv_can_use_fmask_copy(struct radv_cmd_buffer *cmd_buffer,
return false;
/* TODO: Add support for layers. */
if (src_image->info.array_size != 1 || dst_image->info.array_size != 1)
if (src_image->vk.array_layers != 1 || dst_image->vk.array_layers != 1)
return false;
/* Source/destination images must have FMASK. */

4
src/amd/vulkan/meta/radv_meta_resolve.c
View file

@ -301,10 +301,10 @@ radv_pick_resolve_method_images(struct radv_device *device, struct radv_image *s
*method = RESOLVE_COMPUTE;
else if (vk_format_is_int(src_format))
*method = RESOLVE_COMPUTE;
else if (src_image->info.array_size > 1 || dst_image->info.array_size > 1)
else if (src_image->vk.array_layers > 1 || dst_image->vk.array_layers > 1)
*method = RESOLVE_COMPUTE;
} else {
if (src_image->info.array_size > 1 || dst_image->info.array_size > 1 ||
if (src_image->vk.array_layers > 1 || dst_image->vk.array_layers > 1 ||
(dst_image->planes[0].surface.flags & RADEON_SURF_NO_RENDER_TARGET))
*method = RESOLVE_COMPUTE;
else

2
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -10217,7 +10217,7 @@ radv_init_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
for (unsigned i = 0; i < image->planes[0].surface.num_meta_levels; i++) {
struct legacy_surf_dcc_level *dcc_level = &image->planes[0].surface.u.legacy.color.dcc_level[i];
unsigned dcc_fast_clear_size =
dcc_level->dcc_slice_fast_clear_size * image->info.array_size;
dcc_level->dcc_slice_fast_clear_size * image->vk.array_layers;
if (!dcc_fast_clear_size)
break;

2
src/amd/vulkan/radv_device.c
View file

@ -1667,7 +1667,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
if (device->physical_device->rad_info.gfx_level >= GFX9) {
unsigned mip0_depth = iview->image->vk.image_type == VK_IMAGE_TYPE_3D
? (iview->extent.depth - 1)
: (iview->image->info.array_size - 1);
: (iview->image->vk.array_layers - 1);
unsigned width =
vk_format_get_plane_width(iview->image->vk.format, iview->plane_id, iview->extent.width);
unsigned height =

32
src/amd/vulkan/radv_image.c
View file

@ -358,7 +358,7 @@ radv_use_htile_for_image(const struct radv_device *device, const struct radv_ima
* - Enable on other gens.
*/
bool use_htile_for_mips =
image->info.array_size == 1 && device->physical_device->rad_info.gfx_level >= GFX10;
image->vk.array_layers == 1 && device->physical_device->rad_info.gfx_level >= GFX10;
/* Stencil texturing with HTILE doesn't work with mipmapping on Navi10-14. */
if (device->physical_device->rad_info.gfx_level == GFX10 &&
@ -1049,18 +1049,18 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima
assert(image->vk.image_type == VK_IMAGE_TYPE_3D);
type = V_008F1C_SQ_RSRC_IMG_3D;
} else {
type = radv_tex_dim(image->vk.image_type, view_type, image->info.array_size, image->info.samples,
type = radv_tex_dim(image->vk.image_type, view_type, image->vk.array_layers, image->info.samples,
is_storage_image, device->physical_device->rad_info.gfx_level == GFX9);
}
if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
height = 1;
depth = image->info.array_size;
depth = image->vk.array_layers;
} else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY || type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
if (view_type != VK_IMAGE_VIEW_TYPE_3D)
depth = image->info.array_size;
depth = image->vk.array_layers;
} else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
depth = image->info.array_size / 6;
depth = image->vk.array_layers / 6;
state[0] = 0;
state[1] = S_00A004_FORMAT(img_format) |
@ -1171,7 +1171,7 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima
S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) | S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
S_00A00C_SW_MODE(image->planes[0].surface.u.gfx9.color.fmask_swizzle_mode) |
S_00A00C_TYPE(
radv_tex_dim(image->vk.image_type, view_type, image->info.array_size, 0, false, false));
radv_tex_dim(image->vk.image_type, view_type, image->vk.array_layers, 0, false, false));
fmask_state[4] = S_00A010_DEPTH(last_layer) | S_00A010_BASE_ARRAY(first_layer);
fmask_state[5] = 0;
fmask_state[6] = S_00A018_META_PIPE_ALIGNED(1);
@ -1247,18 +1247,18 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image,
assert(image->vk.image_type == VK_IMAGE_TYPE_3D);
type = V_008F1C_SQ_RSRC_IMG_3D;
} else {
type = radv_tex_dim(image->vk.image_type, view_type, image->info.array_size, image->info.samples,
type = radv_tex_dim(image->vk.image_type, view_type, image->vk.array_layers, image->info.samples,
is_storage_image, device->physical_device->rad_info.gfx_level == GFX9);
}
if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
height = 1;
depth = image->info.array_size;
depth = image->vk.array_layers;
} else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY || type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
if (view_type != VK_IMAGE_VIEW_TYPE_3D)
depth = image->info.array_size;
depth = image->vk.array_layers;
} else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
depth = image->info.array_size / 6;
depth = image->vk.array_layers / 6;
state[0] = 0;
state[1] = (S_008F14_MIN_LOD(radv_float_to_ufixed(CLAMP(min_lod, 0, 15), 8)) |
@ -1367,7 +1367,7 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image,
S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) | S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) | S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
S_008F1C_TYPE(
radv_tex_dim(image->vk.image_type, view_type, image->info.array_size, 0, false, false));
radv_tex_dim(image->vk.image_type, view_type, image->vk.array_layers, 0, false, false));
fmask_state[4] = 0;
fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
fmask_state[6] = 0;
@ -1439,7 +1439,7 @@ radv_query_opaque_metadata(struct radv_device *device, struct radv_image *image,
radv_make_texture_descriptor(device, image, false, (VkImageViewType)image->vk.image_type,
image->vk.format, &fixedmapping, 0, image->vk.mip_levels - 1, 0,
image->info.array_size - 1, image->info.width, image->info.height,
image->vk.array_layers - 1, image->info.width, image->info.height,
image->info.depth, 0.0f, desc, NULL, 0, NULL, NULL);
si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0,
@ -1568,7 +1568,7 @@ radv_image_is_pipe_misaligned(const struct radv_device *device, const struct rad
if (rad_info->gfx_level >= GFX10_3) {
log2_bpp_and_samples = log2_bpp + log2_samples;
} else {
if (vk_format_has_depth(image->vk.format) && image->info.array_size >= 8) {
if (vk_format_has_depth(image->vk.format) && image->vk.array_layers >= 8) {
log2_bpp = 2;
}
@ -1853,7 +1853,7 @@ radv_image_print_info(struct radv_device *device, struct radv_image *image)
"width=%" PRIu32 ", height=%" PRIu32 ", depth=%" PRIu32 ", "
"array_size=%" PRIu32 ", levels=%" PRIu32 "\n",
image->size, image->alignment, image->info.width, image->info.height, image->info.depth,
image->info.array_size, image->vk.mip_levels);
image->vk.array_layers, image->vk.mip_levels);
for (unsigned i = 0; i < image->plane_count; ++i) {
const struct radv_image_plane *plane = &image->planes[i];
const struct radeon_surf *surf = &plane->surface;
@ -2166,7 +2166,7 @@ radv_image_view_can_fast_clear(const struct radv_device *device,
return false;
/* Only fast clear if all layers are bound. */
if (iview->vk.base_array_layer > 0 || iview->vk.layer_count != image->info.array_size)
if (iview->vk.base_array_layer > 0 || iview->vk.layer_count != image->vk.array_layers)
return false;
/* Only fast clear if the view covers the whole image. */
@ -2203,7 +2203,7 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device,
case VK_IMAGE_TYPE_1D:
case VK_IMAGE_TYPE_2D:
assert(range->baseArrayLayer + vk_image_subresource_layer_count(&image->vk, range) - 1 <=
image->info.array_size);
image->vk.array_layers);
break;
case VK_IMAGE_TYPE_3D:
assert(range->baseArrayLayer + vk_image_subresource_layer_count(&image->vk, range) - 1 <=