From 8e1cad8d8f89d54ce08dd2e699911782ee4308aa Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Sat, 14 Dec 2024 01:46:28 +0200 Subject: [PATCH] isl: centralize supported tilings in a single function Signed-off-by: Lionel Landwerlin Reviewed-by: Nanley Chery Part-of: --- src/intel/isl/isl.c | 63 +++++++++++++++++++++++++++++++++++++++ src/intel/isl/isl.h | 3 ++ src/intel/isl/isl_gfx12.c | 5 +--- src/intel/isl/isl_gfx20.c | 5 +--- src/intel/isl/isl_gfx4.c | 3 +- src/intel/isl/isl_gfx7.c | 28 ++--------------- 6 files changed, 71 insertions(+), 36 deletions(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 533bb77c592..3f36c57a1c1 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -428,6 +428,69 @@ isl_device_init(struct isl_device *dev, dev->emit_cpb_control_s = isl_emit_cpb_control_s_get_func(dev); } +/** + * @brief Query the supported tilings by the device. + * + * This function always returns non-zero as ISL_TILING_LINEAR_BIT is always + * supported. + */ +isl_tiling_flags_t +isl_device_get_supported_tilings(const struct isl_device *dev) +{ + isl_tiling_flags_t flags; + + if (ISL_GFX_VERX10(dev) >= 200) { + flags = + ISL_TILING_LINEAR_BIT | + ISL_TILING_X_BIT | + ISL_TILING_4_BIT | + ISL_TILING_64_XE2_BIT; + } else if (ISL_GFX_VERX10(dev) >= 125) { + flags = + ISL_TILING_LINEAR_BIT | + ISL_TILING_X_BIT | + ISL_TILING_4_BIT | + ISL_TILING_64_BIT; + } else if (ISL_GFX_VER(dev) >= 12) { + flags = + ISL_TILING_LINEAR_BIT | + ISL_TILING_X_BIT | + ISL_TILING_Y0_BIT | + ISL_TILING_ICL_Yf_BIT | + ISL_TILING_ICL_Ys_BIT; + } else if (ISL_GFX_VER(dev) >= 11) { + flags = + ISL_TILING_LINEAR_BIT | + ISL_TILING_X_BIT | + ISL_TILING_W_BIT | + ISL_TILING_Y0_BIT | + ISL_TILING_ICL_Yf_BIT | + ISL_TILING_ICL_Ys_BIT; + } else if (ISL_GFX_VER(dev) >= 9) { + flags = + ISL_TILING_LINEAR_BIT | + ISL_TILING_X_BIT | + ISL_TILING_W_BIT | + ISL_TILING_Y0_BIT | + ISL_TILING_SKL_Yf_BIT | + ISL_TILING_SKL_Ys_BIT; + } else if (ISL_GFX_VER(dev) >= 6) { + flags = + ISL_TILING_LINEAR_BIT | + ISL_TILING_X_BIT | + ISL_TILING_W_BIT | + ISL_TILING_Y0_BIT; + } else { + /* Gfx4-5 only support linear, X, and Y-tiling. */ + flags = + ISL_TILING_LINEAR_BIT | + ISL_TILING_X_BIT | + ISL_TILING_Y0_BIT; + } + + return flags; +} + /** * @brief Query the set of multisamples supported by the device. * diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index 07ae03d75df..9d51dd3c8d4 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -2029,6 +2029,9 @@ void isl_device_init(struct isl_device *dev, const struct intel_device_info *info); +isl_tiling_flags_t +isl_device_get_supported_tilings(const struct isl_device *dev); + isl_sample_count_mask_t ATTRIBUTE_CONST isl_device_get_sample_counts(const struct isl_device *dev); diff --git a/src/intel/isl/isl_gfx12.c b/src/intel/isl/isl_gfx12.c index 96e16dc09bc..cba84fea7e8 100644 --- a/src/intel/isl/isl_gfx12.c +++ b/src/intel/isl/isl_gfx12.c @@ -44,10 +44,7 @@ isl_gfx125_filter_tiling(const struct isl_device *dev, /* Clear flags unsupported on this hardware */ assert(ISL_GFX_VERX10(dev) == 125); - *flags &= ISL_TILING_LINEAR_BIT | - ISL_TILING_X_BIT | - ISL_TILING_4_BIT | - ISL_TILING_64_BIT; + *flags &= isl_device_get_supported_tilings(dev); if (isl_surf_usage_is_depth_or_stencil(info->usage)) { *flags &= ISL_TILING_4_BIT | ISL_TILING_64_BIT; diff --git a/src/intel/isl/isl_gfx20.c b/src/intel/isl/isl_gfx20.c index 3044bc2df85..d20365d4d8c 100644 --- a/src/intel/isl/isl_gfx20.c +++ b/src/intel/isl/isl_gfx20.c @@ -44,10 +44,7 @@ isl_gfx20_filter_tiling(const struct isl_device *dev, /* Clear flags unsupported on this hardware */ assert(ISL_GFX_VERX10(dev) >= 200); - *flags &= ISL_TILING_LINEAR_BIT | - ISL_TILING_X_BIT | - ISL_TILING_4_BIT | - ISL_TILING_64_XE2_BIT; + *flags &= isl_device_get_supported_tilings(dev); if (isl_surf_usage_is_depth_or_stencil(info->usage)) { *flags &= ISL_TILING_4_BIT | ISL_TILING_64_XE2_BIT; diff --git a/src/intel/isl/isl_gfx4.c b/src/intel/isl/isl_gfx4.c index 8b716c615ec..fc3022cbbae 100644 --- a/src/intel/isl/isl_gfx4.c +++ b/src/intel/isl/isl_gfx4.c @@ -42,8 +42,7 @@ isl_gfx4_filter_tiling(const struct isl_device *dev, const struct isl_surf_init_info *restrict info, isl_tiling_flags_t *flags) { - /* Gfx4-5 only support linear, X, and Y-tiling. */ - *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT | ISL_TILING_Y0_BIT); + *flags &= isl_device_get_supported_tilings(dev);; if (isl_surf_usage_is_depth_or_stencil(info->usage)) { assert(!ISL_DEV_USE_SEPARATE_STENCIL(dev)); diff --git a/src/intel/isl/isl_gfx7.c b/src/intel/isl/isl_gfx7.c index aeabbfd8752..aa07fa9806c 100644 --- a/src/intel/isl/isl_gfx7.c +++ b/src/intel/isl/isl_gfx7.c @@ -198,32 +198,8 @@ isl_gfx6_filter_tiling(const struct isl_device *dev, /* Clear flags unsupported on this hardware */ assert(ISL_GFX_VERX10(dev) < 125); - if (ISL_GFX_VER(dev) >= 12) { - *flags &= ISL_TILING_LINEAR_BIT | - ISL_TILING_X_BIT | - ISL_TILING_Y0_BIT | - ISL_TILING_ICL_Yf_BIT | - ISL_TILING_ICL_Ys_BIT; - } else if (ISL_GFX_VER(dev) >= 11) { - *flags &= ISL_TILING_LINEAR_BIT | - ISL_TILING_X_BIT | - ISL_TILING_W_BIT | - ISL_TILING_Y0_BIT | - ISL_TILING_ICL_Yf_BIT | - ISL_TILING_ICL_Ys_BIT; - } else if (ISL_GFX_VER(dev) >= 9) { - *flags &= ISL_TILING_LINEAR_BIT | - ISL_TILING_X_BIT | - ISL_TILING_W_BIT | - ISL_TILING_Y0_BIT | - ISL_TILING_SKL_Yf_BIT | - ISL_TILING_SKL_Ys_BIT; - } else { - *flags &= ISL_TILING_LINEAR_BIT | - ISL_TILING_X_BIT | - ISL_TILING_W_BIT | - ISL_TILING_Y0_BIT; - } + + *flags &= isl_device_get_supported_tilings(dev); /* TODO: Investigate Yf failures (~5000 VK CTS failures at the time of this * writing).