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freedreno: prefer float immediates when float values are involved

Browse source 
Using double immediates can cause a natively-float value to have to get
upgraded to a double unnecessarily. Use float immediates where possible.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13764>
This commit is contained in:
Ilia Mirkin 2021-11-11 20:07:08 -05:00 • committed by Marge Bot
parent 4e83584092
commit 8db29109be
26 changed files with 100 additions and 100 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
src/gallium/drivers/freedreno/a2xx/fd2_context.c
View file

@ -48,17 +48,17 @@ create_solid_vertexbuf(struct pipe_context *pctx)
/* clang-format off */
static const float init_shader_const[] = {
/* for clear/gmem2mem/mem2gmem (vertices): */
-1.000000, +1.000000, +1.000000,
+1.000000, +1.000000, +1.000000,
-1.000000, -1.000000, +1.000000,
-1.000000f, +1.000000f, +1.000000f,
+1.000000f, +1.000000f, +1.000000f,
-1.000000f, -1.000000f, +1.000000f,
/* for mem2gmem: (tex coords) */
+0.000000, +0.000000,
+1.000000, +0.000000,
+0.000000, +1.000000,
+0.000000f, +0.000000f,
+1.000000f, +0.000000f,
+0.000000f, +1.000000f,
/* SCREEN_SCISSOR_BR value (must be at 60 byte offset in page) */
0.0,
0.0f,
/* zero indices dummy draw workaround (3 16-bit zeros) */
0.0, 0.0,
0.0f, 0.0f,
};
/* clang-format on */

16
src/gallium/drivers/freedreno/a2xx/fd2_draw.c
View file

@ -484,10 +484,10 @@ fd2_clear_fast(struct fd_context *ctx, unsigned buffers,
/* make sure we fill all "pixels" (in SCREEN_SCISSOR) */
OUT_PKT3(ring, CP_SET_CONSTANT, 5);
OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE));
OUT_RING(ring, fui(4096.0));
OUT_RING(ring, fui(4096.0));
OUT_RING(ring, fui(4096.0));
OUT_RING(ring, fui(4096.0));
OUT_RING(ring, fui(4096.0f));
OUT_RING(ring, fui(4096.0f));
OUT_RING(ring, fui(4096.0f));
OUT_RING(ring, fui(4096.0f));
clear_state(batch, ring, ~0u, true);
@ -612,10 +612,10 @@ fd2_clear(struct fd_context *ctx, unsigned buffers,
/* viewport state */
OUT_PKT3(ring, CP_SET_CONSTANT, 5);
OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE));
OUT_RING(ring, fui((float)fb->width / 2.0));
OUT_RING(ring, fui((float)fb->width / 2.0));
OUT_RING(ring, fui((float)fb->height / 2.0));
OUT_RING(ring, fui((float)fb->height / 2.0));
OUT_RING(ring, fui((float)fb->width / 2.0f));
OUT_RING(ring, fui((float)fb->width / 2.0f));
OUT_RING(ring, fui((float)fb->height / 2.0f));
OUT_RING(ring, fui((float)fb->height / 2.0f));
/* common state */
clear_state(ctx->batch, ring, buffers, false);

8
src/gallium/drivers/freedreno/a2xx/fd2_emit.c
View file

@ -291,10 +291,10 @@ fd2_emit_state(struct fd_context *ctx, const enum fd_dirty_3d_state dirty)
OUT_PKT3(ring, CP_SET_CONSTANT, 6);
OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_VTX_CNTL));
OUT_RING(ring, rasterizer->pa_su_vtx_cntl);
OUT_RING(ring, fui(1.0)); /* PA_CL_GB_VERT_CLIP_ADJ */
OUT_RING(ring, fui(1.0)); /* PA_CL_GB_VERT_DISC_ADJ */
OUT_RING(ring, fui(1.0)); /* PA_CL_GB_HORZ_CLIP_ADJ */
OUT_RING(ring, fui(1.0)); /* PA_CL_GB_HORZ_DISC_ADJ */
OUT_RING(ring, fui(1.0f)); /* PA_CL_GB_VERT_CLIP_ADJ */
OUT_RING(ring, fui(1.0f)); /* PA_CL_GB_VERT_DISC_ADJ */
OUT_RING(ring, fui(1.0f)); /* PA_CL_GB_HORZ_CLIP_ADJ */
OUT_RING(ring, fui(1.0f)); /* PA_CL_GB_HORZ_DISC_ADJ */
if (rasterizer->base.offset_tri) {
/* TODO: why multiply scale by 2 ? without it deqp test fails

20
src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
View file

@ -194,10 +194,10 @@ prepare_tile_fini_ib(struct fd_batch *batch) assert_dt
OUT_PKT3(ring, CP_SET_CONSTANT, 5);
OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE));
OUT_RING(ring, fui((float)gmem->bin_w / 2.0)); /* XSCALE */
OUT_RING(ring, fui((float)gmem->bin_w / 2.0)); /* XOFFSET */
OUT_RING(ring, fui((float)gmem->bin_h / 2.0)); /* YSCALE */
OUT_RING(ring, fui((float)gmem->bin_h / 2.0)); /* YOFFSET */
OUT_RING(ring, fui((float)gmem->bin_w / 2.0f)); /* XSCALE */
OUT_RING(ring, fui((float)gmem->bin_w / 2.0f)); /* XOFFSET */
OUT_RING(ring, fui((float)gmem->bin_h / 2.0f)); /* YSCALE */
OUT_RING(ring, fui((float)gmem->bin_h / 2.0f)); /* YOFFSET */
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL));
@ -359,10 +359,10 @@ fd2_emit_tile_mem2gmem(struct fd_batch *batch,
OUT_PKT3(ring, CP_SET_CONSTANT, 5);
OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE));
OUT_RING(ring, fui((float)bin_w / 2.0)); /* PA_CL_VPORT_XSCALE */
OUT_RING(ring, fui((float)bin_w / 2.0)); /* PA_CL_VPORT_XOFFSET */
OUT_RING(ring, fui(-(float)bin_h / 2.0)); /* PA_CL_VPORT_YSCALE */
OUT_RING(ring, fui((float)bin_h / 2.0)); /* PA_CL_VPORT_YOFFSET */
OUT_RING(ring, fui((float)bin_w / 2.0f)); /* PA_CL_VPORT_XSCALE */
OUT_RING(ring, fui((float)bin_w / 2.0f)); /* PA_CL_VPORT_XOFFSET */
OUT_RING(ring, fui(-(float)bin_h / 2.0f)); /* PA_CL_VPORT_YSCALE */
OUT_RING(ring, fui((float)bin_h / 2.0f)); /* PA_CL_VPORT_YOFFSET */
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL));
@ -635,8 +635,8 @@ fd2_emit_tile_init(struct fd_batch *batch) assert_dt
mul_x = 1.0f / (float)(gmem->bin_w * 8);
mul_y = 1.0f / (float)(gmem->bin_h * 8);
off_x = -pipe->x * (1.0 / 8.0f) + 0.125f - mul_x * gmem->minx;
off_y = -pipe->y * (1.0 / 8.0f) + 0.125f - mul_y * gmem->miny;
off_x = -pipe->x * (1.0f / 8.0f) + 0.125f - mul_x * gmem->minx;
off_y = -pipe->y * (1.0f / 8.0f) + 0.125f - mul_y * gmem->miny;
OUT_RING(ring, fui(off_x * (256.0f / 255.0f)));
OUT_RING(ring, fui(off_y * (256.0f / 255.0f)));

2
src/gallium/drivers/freedreno/a2xx/fd2_rasterizer.c
View file

@ -45,7 +45,7 @@ fd2_rasterizer_state_create(struct pipe_context *pctx,
if (cso->point_size_per_vertex) {
psize_min = util_get_min_point_size(cso);
psize_max = 8192.0 - 0.0625;
psize_max = 8192.0f - 0.0625f;
} else {
/* Force the point size to be as if the vertex output was disabled. */
psize_min = cso->point_size;

20
src/gallium/drivers/freedreno/a3xx/fd3_emit.c
View file

@ -710,10 +710,10 @@ fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
fd_wfi(ctx->batch, ring);
OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
OUT_RING(ring,
A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5));
A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5f));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0]));
OUT_RING(ring,
A3XX_GRAS_CL_VPORT_YOFFSET(ctx->viewport.translate[1] - 0.5));
A3XX_GRAS_CL_VPORT_YOFFSET(ctx->viewport.translate[1] - 0.5f));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(ctx->viewport.scale[1]));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx->viewport.translate[2]));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(ctx->viewport.scale[2]));
@ -816,13 +816,13 @@ fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
if (dirty & FD_DIRTY_BLEND_COLOR) {
struct pipe_blend_color *bcolor = &ctx->blend_color;
OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0) |
OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0f) |
A3XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0) |
OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0f) |
A3XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0) |
OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0f) |
A3XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0) |
OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0f) |
A3XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
}
@ -941,11 +941,11 @@ fd3_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) | A3XX_RB_WINDOW_OFFSET_Y(0));
OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(0) | A3XX_RB_BLEND_RED_FLOAT(0.0));
OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(0) | A3XX_RB_BLEND_GREEN_FLOAT(0.0));
OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(0) | A3XX_RB_BLEND_BLUE_FLOAT(0.0));
OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(0) | A3XX_RB_BLEND_RED_FLOAT(0.0f));
OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(0) | A3XX_RB_BLEND_GREEN_FLOAT(0.0f));
OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(0) | A3XX_RB_BLEND_BLUE_FLOAT(0.0f));
OUT_RING(ring,
A3XX_RB_BLEND_ALPHA_UINT(0xff) | A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
A3XX_RB_BLEND_ALPHA_UINT(0xff) | A3XX_RB_BLEND_ALPHA_FLOAT(1.0f));
for (i = 0; i < 6; i++) {
OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(i), 4);

38
src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
View file

@ -251,7 +251,7 @@ emit_binning_workaround(struct fd_batch *batch) assert_dt
A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0));
OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0f));
OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
OUT_RING(ring, 0); /* VFD_INDEX_MIN */
@ -280,12 +280,12 @@ emit_binning_workaround(struct fd_batch *batch) assert_dt
fd_wfi(batch, ring);
OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(0.0));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(1.0));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(0.0));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(1.0));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(0.0f));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(1.0f));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(0.0f));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(1.0f));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0f));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0f));
OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE |
@ -420,12 +420,12 @@ fd3_emit_tile_gmem2mem(struct fd_batch *batch,
fd_wfi(batch, ring);
OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width / 2.0 - 0.5));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width / 2.0));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb->height / 2.0 - 0.5));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb->height / 2.0));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width / 2.0f - 0.5f));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width / 2.0f));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb->height / 2.0f - 0.5f));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb->height / 2.0f));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0f));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0f));
OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
@ -627,12 +627,12 @@ fd3_emit_tile_mem2gmem(struct fd_batch *batch,
fd_wfi(batch, ring);
OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w / 2.0 - 0.5));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w / 2.0));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)bin_h / 2.0 - 0.5));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)bin_h / 2.0));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w / 2.0f - 0.5f));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w / 2.0f));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)bin_h / 2.0f - 0.5f));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)bin_h / 2.0f));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0f));
OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0f));
OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |

2
src/gallium/drivers/freedreno/a3xx/fd3_rasterizer.c
View file

@ -73,7 +73,7 @@ fd3_rasterizer_state_create(struct pipe_context *pctx,
A3XX_GRAS_SU_POLY_OFFSET_OFFSET(cso->offset_units * 2.0f);
so->gras_su_mode_control =
A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(cso->line_width / 2.0);
A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(cso->line_width / 2.0f);
so->pc_prim_vtx_cntl = A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(
fd_polygon_mode(cso->fill_front)) |

4
src/gallium/drivers/freedreno/a3xx/fd3_texture.c
View file

@ -116,8 +116,8 @@ fd3_sampler_state_create(struct pipe_context *pctx,
* LOD clamp so the HW can decide between min and mag filtering of
* level 0.
*/
so->texsamp1 |= A3XX_TEX_SAMP_1_MIN_LOD(MIN2(cso->min_lod, 0.125)) |
A3XX_TEX_SAMP_1_MAX_LOD(MIN2(cso->max_lod, 0.125));
so->texsamp1 |= A3XX_TEX_SAMP_1_MIN_LOD(MIN2(cso->min_lod, 0.125f)) |
A3XX_TEX_SAMP_1_MAX_LOD(MIN2(cso->max_lod, 0.125f));
}
return so;

2
src/gallium/drivers/freedreno/a3xx/fd3_zsa.c
View file

@ -89,7 +89,7 @@ fd3_zsa_state_create(struct pipe_context *pctx,
so->rb_render_control =
A3XX_RB_RENDER_CONTROL_ALPHA_TEST |
A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(cso->alpha_func);
so->rb_alpha_ref = A3XX_RB_ALPHA_REF_UINT(cso->alpha_ref_value * 255.0) |
so->rb_alpha_ref = A3XX_RB_ALPHA_REF_UINT(cso->alpha_ref_value * 255.0f) |
A3XX_RB_ALPHA_REF_FLOAT(cso->alpha_ref_value);
so->rb_depth_control |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
}

8
src/gallium/drivers/freedreno/a4xx/fd4_emit.c
View file

@ -830,11 +830,11 @@ fd4_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
OUT_RING(ring, 0x00000000);
OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4);
OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(0) | A4XX_RB_BLEND_RED_FLOAT(0.0));
OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(0) | A4XX_RB_BLEND_GREEN_FLOAT(0.0));
OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(0) | A4XX_RB_BLEND_BLUE_FLOAT(0.0));
OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(0) | A4XX_RB_BLEND_RED_FLOAT(0.0f));
OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(0) | A4XX_RB_BLEND_GREEN_FLOAT(0.0f));
OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(0) | A4XX_RB_BLEND_BLUE_FLOAT(0.0f));
OUT_RING(ring,
A4XX_RB_BLEND_ALPHA_UINT(0x7fff) | A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
A4XX_RB_BLEND_ALPHA_UINT(0x7fff) | A4XX_RB_BLEND_ALPHA_FLOAT(1.0f));
OUT_PKT0(ring, REG_A4XX_UNKNOWN_2152, 1);
OUT_RING(ring, 0x00000000);

24
src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
View file

@ -242,12 +242,12 @@ fd4_emit_tile_gmem2mem(struct fd_batch *batch,
OUT_RING(ring, 0x80000); /* GRAS_CL_CLIP_CNTL */
OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)pfb->width / 2.0));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)pfb->width / 2.0));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)pfb->height / 2.0));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)pfb->height / 2.0));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)pfb->width / 2.0f));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)pfb->width / 2.0f));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)pfb->height / 2.0f));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)pfb->height / 2.0f));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0f));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0f));
OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
OUT_RING(ring, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE | 0xa); /* XXX */
@ -408,12 +408,12 @@ fd4_emit_tile_mem2gmem(struct fd_batch *batch,
A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)bin_w / 2.0));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)bin_w / 2.0));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)bin_h / 2.0));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)bin_h / 2.0));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)bin_w / 2.0f));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)bin_w / 2.0f));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)bin_h / 2.0f));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)bin_h / 2.0f));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0f));
OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0f));
OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |

2
src/gallium/drivers/freedreno/a4xx/fd4_rasterizer.c
View file

@ -74,7 +74,7 @@ fd4_rasterizer_state_create(struct pipe_context *pctx,
A4XX_GRAS_SU_POLY_OFFSET_CLAMP(cso->offset_clamp);
so->gras_su_mode_control =
A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(cso->line_width / 2.0);
A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(cso->line_width / 2.0f);
so->pc_prim_vtx_cntl2 = A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(
fd_polygon_mode(cso->fill_front)) |
A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(

4
src/gallium/drivers/freedreno/a4xx/fd4_texture.c
View file

@ -114,8 +114,8 @@ fd4_sampler_state_create(struct pipe_context *pctx,
* LOD clamp so the HW can decide between min and mag filtering of
* level 0.
*/
so->texsamp1 |= A4XX_TEX_SAMP_1_MIN_LOD(MIN2(cso->min_lod, 0.125)) |
A4XX_TEX_SAMP_1_MAX_LOD(MIN2(cso->max_lod, 0.125));
so->texsamp1 |= A4XX_TEX_SAMP_1_MIN_LOD(MIN2(cso->min_lod, 0.125f)) |
A4XX_TEX_SAMP_1_MAX_LOD(MIN2(cso->max_lod, 0.125f));
}
if (cso->compare_mode)

2
src/gallium/drivers/freedreno/a4xx/fd4_zsa.c
View file

@ -87,7 +87,7 @@ fd4_zsa_state_create(struct pipe_context *pctx,
}
if (cso->alpha_enabled) {
uint32_t ref = cso->alpha_ref_value * 255.0;
uint32_t ref = cso->alpha_ref_value * 255.0f;
so->gras_alpha_control = A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE;
so->rb_alpha_control =
A4XX_RB_ALPHA_CONTROL_ALPHA_TEST |

2
src/gallium/drivers/freedreno/a5xx/fd5_draw.c
View file

@ -183,7 +183,7 @@ fd5_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
OUT_RING(ring,
A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(0.0) |
A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(0.0f) |
A5XX_GRAS_SU_CNTL_LINE_MODE(zsbuf->b.b.nr_samples > 1 ?
RECTANGULAR : BRESENHAM));

8
src/gallium/drivers/freedreno/a5xx/fd5_emit.c
View file

@ -292,7 +292,7 @@ setup_border_colors(struct fd_texture_stateobj *tex,
else if (c < 3)
e->rgb565 |= (int)(f_u * 0x1f) << (c ? 11 : 0);
if (c == 3)
e->rgb5a1 |= (f_u > 0.5) ? 0x8000 : 0;
e->rgb5a1 |= (f_u > 0.5f) ? 0x8000 : 0;
else
e->rgb5a1 |= (int)(f_u * 0x1f) << (c * 5);
if (c == 3)
@ -959,9 +959,9 @@ fd5_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
OUT_RING(ring, 0x00000012);
OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
OUT_RING(ring, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0) |
A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0));
OUT_RING(ring, A5XX_GRAS_SU_POINT_SIZE(0.5));
OUT_RING(ring, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0f) |
A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f));
OUT_RING(ring, A5XX_GRAS_SU_POINT_SIZE(0.5f));
OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */

2
src/gallium/drivers/freedreno/a5xx/fd5_rasterizer.c
View file

@ -64,7 +64,7 @@ fd5_rasterizer_state_create(struct pipe_context *pctx,
so->gras_su_poly_offset_clamp =
A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(cso->offset_clamp);
so->gras_su_cntl = A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(cso->line_width / 2.0);
so->gras_su_cntl = A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(cso->line_width / 2.0f);
so->pc_raster_cntl =
A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE(
fd_polygon_mode(cso->fill_front)) |

4
src/gallium/drivers/freedreno/a5xx/fd5_texture.c
View file

@ -114,8 +114,8 @@ fd5_sampler_state_create(struct pipe_context *pctx,
* LOD clamp so the HW can decide between min and mag filtering of
* level 0.
*/
so->texsamp1 |= A5XX_TEX_SAMP_1_MIN_LOD(MIN2(cso->min_lod, 0.125)) |
A5XX_TEX_SAMP_1_MAX_LOD(MIN2(cso->max_lod, 0.125));
so->texsamp1 |= A5XX_TEX_SAMP_1_MIN_LOD(MIN2(cso->min_lod, 0.125f)) |
A5XX_TEX_SAMP_1_MAX_LOD(MIN2(cso->max_lod, 0.125f));
}
if (cso->compare_mode)

2
src/gallium/drivers/freedreno/a5xx/fd5_zsa.c
View file

@ -105,7 +105,7 @@ fd5_zsa_state_create(struct pipe_context *pctx,
}
if (cso->alpha_enabled) {
uint32_t ref = cso->alpha_ref_value * 255.0;
uint32_t ref = cso->alpha_ref_value * 255.0f;
so->rb_alpha_control =
A5XX_RB_ALPHA_CONTROL_ALPHA_TEST |
A5XX_RB_ALPHA_CONTROL_ALPHA_REF(ref) |

2
src/gallium/drivers/freedreno/a6xx/fd6_emit.c
View file

@ -196,7 +196,7 @@ setup_border_colors(struct fd_texture_stateobj *tex,
else if (c < 3)
e->rgb565 |= (int)(f_u * 0x1f) << (c ? 11 : 0);
if (c == 3)
e->rgb5a1 |= (f_u > 0.5) ? 0x8000 : 0;
e->rgb5a1 |= (f_u > 0.5f) ? 0x8000 : 0;
else
e->rgb5a1 |= (int)(f_u * 0x1f) << (c * 5);
if (c == 3)

2
src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c
View file

@ -59,7 +59,7 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx,
.zero_gb_scale_z = cso->clip_halfz));
OUT_REG(ring,
A6XX_GRAS_SU_CNTL(.linehalfwidth = cso->line_width / 2.0,
A6XX_GRAS_SU_CNTL(.linehalfwidth = cso->line_width / 2.0f,
.poly_offset = cso->offset_tri,
.line_mode = cso->multisample ? RECTANGULAR : BRESENHAM,
.cull_front = cso->cull_face & PIPE_FACE_FRONT,

2
src/gallium/drivers/freedreno/a6xx/fd6_zsa.c
View file

@ -194,7 +194,7 @@ fd6_zsa_state_create(struct pipe_context *pctx,
so->alpha_test = true;
}
uint32_t ref = cso->alpha_ref_value * 255.0;
uint32_t ref = cso->alpha_ref_value * 255.0f;
so->rb_alpha_control =
A6XX_RB_ALPHA_CONTROL_ALPHA_TEST |
A6XX_RB_ALPHA_CONTROL_ALPHA_REF(ref) |

4
src/gallium/drivers/freedreno/freedreno_autotune.c
View file

@ -223,7 +223,7 @@ fd_autotune_use_bypass(struct fd_autotune *at, struct fd_batch *batch)
/* Low sample count could mean there was only a clear.. or there was
* a clear plus draws that touch no or few samples
*/
if (avg_samples < 500.0)
if (avg_samples < 500.0f)
return true;
/* Cost-per-sample is an estimate for the average number of reads+
@ -238,7 +238,7 @@ fd_autotune_use_bypass(struct fd_autotune *at, struct fd_batch *batch)
batch->hash, batch->num_draws, total_samples, avg_samples,
sample_cost, total_draw_cost);
if (total_draw_cost < 3000.0)
if (total_draw_cost < 3000.0f)
return true;
}

2
src/gallium/drivers/freedreno/freedreno_context.c
View file

@ -508,7 +508,7 @@ static struct pipe_resource *
create_solid_vertexbuf(struct pipe_context *pctx)
{
static const float init_shader_const[] = {
-1.000000, +1.000000, +1.000000, +1.000000, -1.000000, +1.000000,
-1.000000f, +1.000000f, +1.000000f, +1.000000f, -1.000000f, +1.000000f,
};
struct pipe_resource *prsc =
pipe_buffer_create(pctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,

2
src/gallium/drivers/freedreno/freedreno_screen.c
View file

@ -542,7 +542,7 @@ fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
return 1;
case PIPE_CAPF_POINT_SIZE_GRANULARITY:
case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
return 0.1;
return 0.1f;
case PIPE_CAPF_MAX_LINE_WIDTH:
case PIPE_CAPF_MAX_LINE_WIDTH_AA:
/* NOTE: actual value is 127.0f, but this is working around a deqp