fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-07 02:10:12 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

radv: fix creating BC image views when the base layer is > 0

Browse source 
When the base array layer of the image view is > 0, addrlib computes
the offset (in HwlComputeSubResourceOffsetForSwizzlePattern) which is
then added to the base VA in RADV. But if the driver doesn't reset
the base array layer, the hw will compute incorrect addressing
(ie. base array will be added twice). This also matches AMDVLK.

This fixes a VM fault followed by a GPU hang on RDNA2 when trying
to join a multiplayer game with medium settings in Halo Infinite.

Fixes: 98ba1e0d81 ("radv: Fix mipmap views on GFX10+")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20761>
This commit is contained in:
Samuel Pitoiset 2023-01-17 16:18:24 +01:00 • committed by Marge Bot
parent 18aaa373b7
commit 8d191b2cfb
2 changed files with 7 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/amd/vulkan/radv_device.c
View file

@ -7024,8 +7024,8 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
/* GFX10 field has the same base shift as the GFX6 field. */
uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
cb->cb_color_view =
S_028C6C_SLICE_START(iview->vk.base_array_layer) | S_028C6C_SLICE_MAX_GFX10(max_slice);
uint32_t slice_start = iview->nbc_view.valid ? 0 : iview->vk.base_array_layer;
cb->cb_color_view = S_028C6C_SLICE_START(slice_start) | S_028C6C_SLICE_MAX_GFX10(max_slice);
if (iview->image->info.samples > 1) {
unsigned log_samples = util_logbase2(iview->image->info.samples);

6
src/amd/vulkan/radv_image.c
View file

@ -1980,6 +1980,7 @@ radv_image_view_make_descriptor(struct radv_image_view *iview, struct radv_devic
struct radv_image *image = iview->image;
struct radv_image_plane *plane = &image->planes[plane_id];
bool is_stencil = iview->vk.aspects == VK_IMAGE_ASPECT_STENCIL_BIT;
unsigned first_layer = iview->vk.base_array_layer;
uint32_t blk_w;
union radv_descriptor *descriptor;
uint32_t hw_level = 0;
@ -2001,12 +2002,15 @@ radv_image_view_make_descriptor(struct radv_image_view *iview, struct radv_devic
hw_level = nbc_view->level;
iview->extent.width = nbc_view->width;
iview->extent.height = nbc_view->height;
/* Clear the base array layer because addrlib adds it as part of the base addr offset. */
first_layer = 0;
}
}
radv_make_texture_descriptor(
device, image, is_storage_image, iview->vk.view_type, vk_format, components, hw_level,
hw_level + iview->vk.level_count - 1, iview->vk.base_array_layer,
hw_level + iview->vk.level_count - 1, first_layer,
iview->vk.base_array_layer + iview->vk.layer_count - 1,
vk_format_get_plane_width(image->vk.format, plane_id, iview->extent.width),
vk_format_get_plane_height(image->vk.format, plane_id, iview->extent.height),