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i965/fs: Properly report regs_written from SAMPLEINFO

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The previous behavior would only allocate one register and then write
four thus potentially stomping three innocent bystanders.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
(cherry picked from commit c7a09c0571)
This commit is contained in:
Jason Ekstrand 2015-10-09 18:07:23 -07:00 • committed by Emil Velikov
parent 143161ad97
commit 8d1874bc1c
2 changed files with 9 additions and 2 deletions
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8
src/mesa/drivers/dri/i965/brw_fs_nir.cpp
View file

@ -3060,12 +3060,18 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
case nir_texop_txs: op = ir_txs; break;
case nir_texop_texture_samples: {
fs_reg dst = retype(get_nir_dest(instr->dest), BRW_REGISTER_TYPE_D);
fs_inst *inst = bld.emit(SHADER_OPCODE_SAMPLEINFO, dst,
fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_D, 4);
fs_inst *inst = bld.emit(SHADER_OPCODE_SAMPLEINFO, tmp,
bld.vgrf(BRW_REGISTER_TYPE_D, 1),
texture_reg, texture_reg);
inst->mlen = 1;
inst->header_size = 1;
inst->base_mrf = -1;
inst->regs_written = 4 * (dispatch_width / 8);
/* Pick off the one component we care about */
bld.MOV(dst, tmp);
return;
}
case nir_texop_samples_identical: op = ir_samples_identical; break;

3
src/mesa/drivers/dri/i965/brw_shader.cpp
View file

@ -710,7 +710,8 @@ backend_instruction::is_tex() const
opcode == SHADER_OPCODE_TXS ||
opcode == SHADER_OPCODE_LOD ||
opcode == SHADER_OPCODE_TG4 ||
opcode == SHADER_OPCODE_TG4_OFFSET);
opcode == SHADER_OPCODE_TG4_OFFSET ||
opcode == SHADER_OPCODE_SAMPLEINFO);
}
bool