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intel/compiler: Stop forcing null source <0;1,0> region in brw_asm "compat" mode

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Remove the compatibility handling from gen and update the expected
results for the relevant parser tests.

Assisted-by: Pi coding agent (opus-4.7)
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41413>
This commit is contained in:
Caio Oliveira 2026-05-03 09:17:45 -07:00 • committed by Marge Bot
parent 4a0a34a981
commit 8d0c16e4fc
4 changed files with 65 additions and 74 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

22
src/intel/compiler/brw/tests/gen12/swsb.expected
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@ -5,21 +5,21 @@
62 05 02 80 60 06 85 5a 64 5a 00 56 85 5a 34 00
65 06 04 00 20 02 05 3a 05 10 46 02 05 38 46 00
66 07 04 00 20 02 01 00 05 69 46 22 05 67 46 00
38 90 04 00 a0 0a 05 11 05 0f 46 72 00 00 00 00
38 d2 04 00 a0 0a 05 01 05 1d 46 32 00 00 00 00
38 93 03 00 90 09 05 09 05 06 46 42 00 00 00 00
38 90 04 00 a0 0a 05 11 05 0f 46 72 00 00 10 00
38 d2 04 00 a0 0a 05 01 05 1d 46 32 00 00 10 00
38 93 03 00 90 09 05 09 05 06 46 42 00 00 10 00
38 c4 03 00 60 06 05 67 05 65 46 c6 05 23 46 00
38 a5 13 00 60 06 05 65 05 61 46 d6 05 4c 46 00
38 a6 24 00 a0 0a 05 0a 05 08 46 12 00 00 00 00
38 97 24 00 a0 0a 05 66 05 64 46 22 00 00 00 00
38 f8 04 00 a0 0a 05 4c 05 4a 46 52 00 00 00 00
38 c9 04 00 a0 0a 05 7b 05 79 46 62 00 00 00 00
38 fa 24 00 a0 0a 05 2b 05 2f 46 42 00 00 00 00
38 bb 03 00 90 09 05 67 05 62 46 72 00 00 00 00
38 9c 03 00 90 09 05 36 05 34 46 32 00 00 00 00
38 a6 24 00 a0 0a 05 0a 05 08 46 12 00 00 10 00
38 97 24 00 a0 0a 05 66 05 64 46 22 00 00 10 00
38 f8 04 00 a0 0a 05 4c 05 4a 46 52 00 00 10 00
38 c9 04 00 a0 0a 05 7b 05 79 46 62 00 00 10 00
38 fa 24 00 a0 0a 05 2b 05 2f 46 42 00 00 10 00
38 bb 03 00 90 09 05 67 05 62 46 72 00 00 10 00
38 9c 03 00 90 09 05 36 05 34 46 32 00 00 10 00
38 ad 33 00 60 06 05 23 05 1f 46 c6 05 21 46 00
38 ce 13 00 60 06 05 65 05 61 46 d6 05 63 46 00
38 ef 03 00 90 09 05 66 05 5c 46 12 00 00 00 00
38 ef 03 00 90 09 05 66 05 5c 46 12 00 00 10 00
62 f0 04 00 10 01 05 07 05 07 58 41 06 59 56 00
61 b1 04 80 10 41 01 10 00 00 00 00 e0 03 00 00
40 b2 04 00 60 86 05 64 05 66 46 06 be f7 ff ff

66
src/intel/compiler/brw/tests/gen12/sync.expected
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@ -1,33 +1,33 @@
01 01 04 80 00 02 00 00 00 00 00 00 00 00 00 00
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01 05 00 80 00 02 00 00 00 00 00 00 00 00 00 00
01 06 00 80 00 02 00 00 00 00 00 00 00 00 00 00
01 07 00 80 00 02 00 00 00 00 00 00 00 00 00 00
01 01 10 80 00 02 00 00 00 00 00 00 00 00 00 00
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01 04 10 80 00 02 00 00 00 00 00 00 00 00 00 00
01 05 10 80 00 02 00 00 00 00 00 00 00 00 00 00
01 06 10 80 00 02 00 00 00 00 00 00 00 00 00 00
01 07 10 80 00 02 00 00 00 00 00 00 00 00 00 00
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01 00 04 00 00 02 00 00 00 00 10 30 00 00 00 00
01 00 03 00 00 02 00 00 00 00 10 30 00 00 00 00

42
src/intel/compiler/brw/tests/gen9/math.expected
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@ -1,31 +1,31 @@
38 00 80 04 e8 3a 80 22 40 02 8d 00 00 00 00 00
38 00 60 01 e8 3a e0 2b c0 0b 8d 00 00 00 00 00
38 00 80 01 e8 3a 40 21 00 01 8d 00 00 00 00 00
38 00 80 04 e8 3a 80 22 40 02 8d 00 00 00 20 00
38 00 60 01 e8 3a e0 2b c0 0b 8d 00 00 00 20 00
38 00 80 01 e8 3a 40 21 00 01 8d 00 00 00 20 00
38 00 60 0d 08 02 60 20 20 00 00 02 28 00 00 00
38 10 60 0d 08 02 80 20 20 00 00 02 28 00 00 00
38 00 60 04 e8 3a 00 23 e0 02 8d 00 00 00 00 00
38 00 60 05 e8 3a a0 20 40 00 8d 00 00 00 00 00
38 00 60 04 e8 3a 00 23 e0 02 8d 00 00 00 20 00
38 00 60 05 e8 3a a0 20 40 00 8d 00 00 00 20 00
38 00 60 0a e8 3a 60 21 40 01 8d 3e 66 66 fc 42
38 00 80 0a e8 3a 40 22 00 02 8d 3e 66 66 fc 42
38 00 60 02 e8 3a e0 20 c0 00 8d 00 00 00 00 00
38 00 80 02 e8 3a 60 21 20 01 8d 00 00 00 00 00
38 00 60 07 e8 3a 60 20 40 00 8d 00 00 00 00 00
38 00 80 07 e8 3a 80 20 40 00 8d 00 00 00 00 00
38 00 60 02 e8 3a e0 20 c0 00 8d 00 00 00 20 00
38 00 80 02 e8 3a 60 21 20 01 8d 00 00 00 20 00
38 00 60 07 e8 3a 60 20 40 00 8d 00 00 00 20 00
38 00 80 07 e8 3a 80 20 40 00 8d 00 00 00 20 00
38 00 60 0c 08 02 80 20 20 00 00 02 30 00 00 00
38 10 60 0c 08 02 a0 20 20 00 00 02 30 00 00 00
38 00 60 0c 28 0a 00 23 80 00 00 0a 48 00 00 00
38 00 60 06 e8 3a 40 21 20 01 8d 00 00 00 00 00
38 00 80 05 e8 3a 80 28 40 08 8d 00 00 00 00 00
38 00 60 03 e8 3a 80 2f 40 01 8d 00 00 00 00 00
38 00 80 03 e8 3a 00 2f e0 00 8d 00 00 00 00 00
38 00 60 06 e8 3a 40 21 20 01 8d 00 00 00 20 00
38 00 80 05 e8 3a 80 28 40 08 8d 00 00 00 20 00
38 00 60 03 e8 3a 80 2f 40 01 8d 00 00 00 20 00
38 00 80 03 e8 3a 00 2f e0 00 8d 00 00 00 20 00
38 10 60 0c 28 0a a0 20 40 00 00 0a 50 00 00 00
38 00 80 06 e8 3a 60 20 40 00 00 00 00 00 00 00
38 00 80 06 e8 3a 60 20 40 00 00 00 00 00 20 00
38 00 60 8a e8 3a 60 20 40 00 00 3a 50 00 00 00
38 00 80 8a e8 3a 60 20 40 00 00 3a 50 00 00 00
38 00 60 84 e8 3a 60 20 40 00 00 00 00 00 00 00
38 00 80 84 e8 3a 60 20 40 00 00 00 00 00 00 00
38 00 60 83 e8 3a 60 20 40 00 00 00 00 00 00 00
38 00 80 83 e8 3a 60 20 40 00 00 00 00 00 00 00
38 00 60 85 e8 3a e0 2f e0 20 8d 00 00 00 00 00
38 00 60 81 e8 3a 80 2f 40 00 00 00 00 00 00 00
38 00 60 82 e8 3a e0 2f e0 00 8d 00 00 00 00 00
38 00 60 84 e8 3a 60 20 40 00 00 00 00 00 20 00
38 00 80 84 e8 3a 60 20 40 00 00 00 00 00 20 00
38 00 60 83 e8 3a 60 20 40 00 00 00 00 00 20 00
38 00 80 83 e8 3a 60 20 40 00 00 00 00 00 20 00
38 00 60 85 e8 3a e0 2f e0 20 8d 00 00 00 20 00
38 00 60 81 e8 3a 80 2f 40 00 00 00 00 00 20 00
38 00 60 82 e8 3a e0 2f e0 00 8d 00 00 00 20 00

9
src/intel/compiler/gen/gen_parse.cpp
View file

@ -1124,15 +1124,6 @@ struct gen_parser {
if (!parse_src_region(src.region))
return false;
}
} else if (src.file == GEN_ARF && src.nr == GEN_ARF_NULL &&
debug_get_option_brw_asm_compat_mode()) {
/* TODO(brw_asm-compat): The hardware ignores region bits for
* null operands. Use the all-zero form so we round-trip
* cleanly with the old brw_asm output, which encoded null
* with vstride=0. Drop this gate when the test corpus is
* regenerated against the clean default below.
*/
src.region = { 0, 1, 0 };
} else {
src.region = { 1, 1, 0 };
}