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i965: Flatten if-statements beyond depth 16 on pre-gen6.

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Gen4 and Gen5 hardware can have a maximum supported nesting depth of 16.
Previously, shaders with control flow nested 17 levels deep would
cause a driver assertion or segmentation fault.

Gen6 (Sandybridge) hardware no longer has this restriction.

Fixes fd.o bug #31967.
(cherry picked from commit 634a7dce9c)
This commit is contained in:
Kenneth Graunke 2010-12-27 00:40:26 -08:00 • committed by Ian Romanick
parent 9d3573c905
commit 8cfce0c643
1 changed files with 10 additions and 0 deletions
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10
src/mesa/drivers/dri/i965/brw_fs.cpp
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@ -89,6 +89,9 @@ brw_compile_shader(struct gl_context *ctx, struct gl_shader *shader)
GLboolean
brw_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
{
struct brw_context *brw = brw_context(ctx);
struct intel_context *intel = &brw->intel;
struct brw_shader *shader =
(struct brw_shader *)prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
if (shader != NULL) {
@ -107,6 +110,13 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
SUB_TO_ADD_NEG |
EXP_TO_EXP2 |
LOG_TO_LOG2);
/* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this,
* if-statements need to be flattened.
*/
if (intel->gen < 6)
lower_if_to_cond_assign(shader->ir, 16);
do_lower_texture_projection(shader->ir);
brw_do_cubemap_normalize(shader->ir);