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anv: Write timestamp using MI_FLUSH_DW on blitter

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On Blitter engine, we don't support PIPE_CONTROL, we have to update
memory locations using the MI_FLUSH_DW command.

v2:
- Handle video queue (Lionel)

Fixes: 056b0cb87f ("anv: add video engine support in various places")
Fixes: 5112b42146 ("anv: Handle end of pipe with MI_FLUSH_DW on transfer queue")

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26121>
This commit is contained in:
Sagar Ghuge 2023-11-08 17:33:40 -08:00 • committed by Marge Bot
parent dcb68de656
commit 8c9a7f7730
2 changed files with 20 additions and 8 deletions
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6
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -8164,7 +8164,8 @@ void genX(cmd_emit_timestamp)(struct anv_batch *batch,
* ANV_TIMESTAMP_REWRITE_COMPUTE_WALKER capture type are not set for
* transfer queue.
*/
if (batch->engine_class == INTEL_ENGINE_CLASS_COPY) {
if ((batch->engine_class == INTEL_ENGINE_CLASS_COPY) ||
(batch->engine_class == INTEL_ENGINE_CLASS_VIDEO)) {
assert(type != ANV_TIMESTAMP_CAPTURE_AT_CS_STALL &&
type != ANV_TIMESTAMP_REWRITE_COMPUTE_WALKER);
}
@ -8178,7 +8179,8 @@ void genX(cmd_emit_timestamp)(struct anv_batch *batch,
}
case ANV_TIMESTAMP_CAPTURE_END_OF_PIPE: {
if (batch->engine_class == INTEL_ENGINE_CLASS_COPY) {
if ((batch->engine_class == INTEL_ENGINE_CLASS_COPY) ||
(batch->engine_class == INTEL_ENGINE_CLASS_VIDEO)) {
anv_batch_emit(batch, GENX(MI_FLUSH_DW), fd) {
fd.PostSyncOperation = WriteTimestamp;
fd.Address = addr;

22
src/intel/vulkan/genX_query.c
View file

@ -1403,13 +1403,23 @@ void genX(CmdWriteTimestamp2)(
bool cs_stall_needed =
(GFX_VER == 9 && cmd_buffer->device->info->gt == 4);
genx_batch_emit_pipe_control_write
(&cmd_buffer->batch, cmd_buffer->device->info,
cmd_buffer->state.current_pipeline, WriteTimestamp,
anv_address_add(query_addr, 8), 0,
cs_stall_needed ? ANV_PIPE_CS_STALL_BIT : 0);
emit_query_pc_availability(cmd_buffer, query_addr, true);
if (anv_cmd_buffer_is_blitter_queue(cmd_buffer) ||
anv_cmd_buffer_is_video_queue(cmd_buffer)) {
anv_batch_emit(&cmd_buffer->batch, GENX(MI_FLUSH_DW), dw) {
dw.Address = anv_address_add(query_addr, 8);
dw.PostSyncOperation = WriteTimestamp;
}
emit_query_mi_flush_availability(cmd_buffer, query_addr, true);
} else {
genx_batch_emit_pipe_control_write
(&cmd_buffer->batch, cmd_buffer->device->info,
cmd_buffer->state.current_pipeline, WriteTimestamp,
anv_address_add(query_addr, 8), 0,
cs_stall_needed ? ANV_PIPE_CS_STALL_BIT : 0);
emit_query_pc_availability(cmd_buffer, query_addr, true);
}
}