diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index dd2383aa2e4..60977d35f1f 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -307,6 +307,21 @@ static void si_bind_compute_state(struct pipe_context *ctx, void *state)
 
    sctx->compute_shaderbuf_sgprs_dirty = true;
    sctx->compute_image_sgprs_dirty = true;
+
+   if (unlikely((sctx->screen->debug_flags & DBG(SQTT)) && sctx->thread_trace)) {
+      uint32_t pipeline_code_hash = _mesa_hash_data_with_seed(
+         program->shader.binary.elf_buffer,
+         program->shader.binary.elf_size,
+         0);
+      uint64_t base_address = program->shader.bo->gpu_address;
+
+      struct ac_thread_trace_data *thread_trace_data = sctx->thread_trace;
+      if (!si_sqtt_pipeline_is_registered(thread_trace_data, pipeline_code_hash)) {
+         si_sqtt_register_pipeline(sctx, pipeline_code_hash, base_address, true);
+      }
+
+      si_sqtt_describe_pipeline_bind(sctx, pipeline_code_hash, 1);
+   }
 }
 
 static void si_set_global_binding(struct pipe_context *ctx, unsigned first, unsigned n,
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index f807263357e..78c956b338b 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -1605,10 +1605,10 @@ void si_sqtt_write_event_marker(struct si_context* sctx, struct radeon_cmdbuf *r
                                 uint32_t vertex_offset_user_data,
                                 uint32_t instance_offset_user_data,
                                 uint32_t draw_index_user_data);
-bool si_sqtt_register_pipeline(struct si_context* sctx, uint64_t pipeline_hash, uint64_t base_address);
+bool si_sqtt_register_pipeline(struct si_context* sctx, uint64_t pipeline_hash, uint64_t base_address, bool is_compute);
 bool si_sqtt_pipeline_is_registered(struct ac_thread_trace_data *thread_trace_data,
                                     uint64_t pipeline_hash);
-void si_sqtt_describe_pipeline_bind(struct si_context* sctx, uint64_t pipeline_hash);
+void si_sqtt_describe_pipeline_bind(struct si_context* sctx, uint64_t pipeline_hash, int bind_point);
 void
 si_write_event_with_dims_marker(struct si_context* sctx, struct radeon_cmdbuf *rcs,
                                 enum rgp_sqtt_marker_event_type api_type,
diff --git a/src/gallium/drivers/radeonsi/si_sqtt.c b/src/gallium/drivers/radeonsi/si_sqtt.c
index 19f18db4cca..bb4f04daa70 100644
--- a/src/gallium/drivers/radeonsi/si_sqtt.c
+++ b/src/gallium/drivers/radeonsi/si_sqtt.c
@@ -26,6 +26,7 @@
 
 #include "si_pipe.h"
 #include "si_build_pm4.h"
+#include "si_compute.h"
 
 #include "ac_rgp.h"
 #include "ac_sqtt.h"
@@ -949,7 +950,8 @@ si_sqtt_pipe_to_rgp_shader_stage(struct si_shader_key* key, enum pipe_shader_typ
 
 static bool
 si_sqtt_add_code_object(struct si_context* sctx,
-                        uint64_t pipeline_hash)
+                        uint64_t pipeline_hash,
+                        bool is_compute)
 {
    struct ac_thread_trace_data *thread_trace_data = sctx->thread_trace;
    struct rgp_code_object *code_object = &thread_trace_data->rgp_code_object;
@@ -965,17 +967,23 @@ si_sqtt_add_code_object(struct si_context* sctx,
    record->pipeline_hash[1] = pipeline_hash;
 
    for (unsigned i = 0; i < PIPE_SHADER_TYPES; i++) {
-      if (i != PIPE_SHADER_COMPUTE) {
+      struct si_shader *shader;
+      enum rgp_hardware_stages hw_stage;
+
+      if (is_compute) {
+         if (i != PIPE_SHADER_COMPUTE)
+            continue;
+         shader = &sctx->cs_shader_state.program->shader;
+         hw_stage = RGP_HW_STAGE_CS;
+      } else if (i != PIPE_SHADER_COMPUTE) {
          if (!sctx->shaders[i].cso || !sctx->shaders[i].current)
             continue;
+         shader = sctx->shaders[i].current;
+         hw_stage = si_sqtt_pipe_to_rgp_shader_stage(&shader->key, i);
       } else {
-         /* TODO */
          continue;
       }
 
-      struct si_shader *shader = sctx->shaders[i].current;
-      enum rgp_hardware_stages hw_stage = si_sqtt_pipe_to_rgp_shader_stage(&shader->key, i);
-
       uint8_t *code = malloc(shader->binary.uploaded_code_size);
       if (!code) {
          free(record);
@@ -1008,7 +1016,7 @@ si_sqtt_add_code_object(struct si_context* sctx,
 }
 
 bool
-si_sqtt_register_pipeline(struct si_context* sctx, uint64_t pipeline_hash, uint64_t base_address)
+si_sqtt_register_pipeline(struct si_context* sctx, uint64_t pipeline_hash, uint64_t base_address, bool is_compute)
 {
    struct ac_thread_trace_data *thread_trace_data = sctx->thread_trace;
 
@@ -1022,12 +1030,13 @@ si_sqtt_register_pipeline(struct si_context* sctx, uint64_t pipeline_hash, uint6
    if (!result)
       return false;
 
-   return si_sqtt_add_code_object(sctx, pipeline_hash);
+   return si_sqtt_add_code_object(sctx, pipeline_hash, is_compute);
 }
 
 void
 si_sqtt_describe_pipeline_bind(struct si_context* sctx,
-                               uint64_t pipeline_hash)
+                               uint64_t pipeline_hash,
+                               int bind_point)
 {
    struct rgp_sqtt_marker_pipeline_bind marker = {0};
    struct radeon_cmdbuf *cs = &sctx->gfx_cs;
@@ -1038,7 +1047,7 @@ si_sqtt_describe_pipeline_bind(struct si_context* sctx,
 
    marker.identifier = RGP_SQTT_MARKER_IDENTIFIER_BIND_PIPELINE;
    marker.cb_id = 0;
-   marker.bind_point = 0 /* VK_PIPELINE_BIND_POINT_GRAPHICS */;
+   marker.bind_point = bind_point;
    marker.api_pso_hash[0] = pipeline_hash;
    marker.api_pso_hash[1] = pipeline_hash >> 32;
 
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 38b1f94f6e7..c149f1c122e 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -4176,7 +4176,7 @@ bool si_update_shaders(struct si_context *sctx)
       }
    }
 
-   if (sctx->screen->debug_flags & DBG(SQTT)) {
+   if (unlikely(sctx->screen->debug_flags & DBG(SQTT) && sctx->thread_trace)) {
       /* Pretend the bound shaders form a vk pipeline */
       uint32_t pipeline_code_hash = 0;
       uint64_t base_address = ~0;
@@ -4195,10 +4195,10 @@ bool si_update_shaders(struct si_context *sctx)
 
       struct ac_thread_trace_data *thread_trace_data = sctx->thread_trace;
       if (!si_sqtt_pipeline_is_registered(thread_trace_data, pipeline_code_hash)) {
-         si_sqtt_register_pipeline(sctx, pipeline_code_hash, base_address);
+         si_sqtt_register_pipeline(sctx, pipeline_code_hash, base_address, false);
       }
 
-      si_sqtt_describe_pipeline_bind(sctx, pipeline_code_hash);
+      si_sqtt_describe_pipeline_bind(sctx, pipeline_code_hash, 0);
    }
 
    if (si_pm4_state_enabled_and_changed(sctx, ls) || si_pm4_state_enabled_and_changed(sctx, hs) ||