mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-05 05:18:08 +02:00
Update for extra vertex attributes
This commit is contained in:
parent
5fea663b5f
commit
8c26a521ee
4 changed files with 93 additions and 78 deletions
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@ -3763,7 +3763,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#define NV34TCL_RT_ENABLE_COLOR2 (1 << 2)
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#define NV34TCL_RT_ENABLE_COLOR1 (1 << 1)
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#define NV34TCL_RT_ENABLE_COLOR0 (1 << 0)
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#define NV34TCL_ZETA_PITCH 0x0000022c
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#define NV34TCL_LMA_DEPTH_PITCH 0x0000022c
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#define NV34TCL_LMA_DEPTH_OFFSET 0x00000230
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#define NV34TCL_TX_UNITS_ENABLE 0x0000023c
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#define NV34TCL_TX_UNITS_ENABLE_TX0 (1 << 0)
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@ -4145,14 +4145,16 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#define NV34TCL_DEPTH_TEST_ENABLE 0x00000a74
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#define NV34TCL_POLYGON_OFFSET_FACTOR 0x00000a78
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#define NV34TCL_POLYGON_OFFSET_UNITS 0x00000a7c
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#define NV34TCL_VERTEX_NOR_3I_XY 0x00000a90
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#define NV34TCL_VERTEX_NOR_3I_XY_X_SHIFT 0
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#define NV34TCL_VERTEX_NOR_3I_XY_X_MASK 0x0000ffff
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#define NV34TCL_VERTEX_NOR_3I_XY_Y_SHIFT 16
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#define NV34TCL_VERTEX_NOR_3I_XY_Y_MASK 0xffff0000
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#define NV34TCL_VERTEX_NOR_3I_Z 0x00000a94
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#define NV34TCL_VERTEX_NOR_3I_Z_Z_SHIFT 0
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#define NV34TCL_VERTEX_NOR_3I_Z_Z_MASK 0x0000ffff
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#define NV34TCL_VTX_ATTR_3I_XY(x) (0x00000a80+((x)*8))
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#define NV34TCL_VTX_ATTR_3I_XY__SIZE 0x00000010
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#define NV34TCL_VTX_ATTR_3I_XY_X_SHIFT 0
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#define NV34TCL_VTX_ATTR_3I_XY_X_MASK 0x0000ffff
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#define NV34TCL_VTX_ATTR_3I_XY_Y_SHIFT 16
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#define NV34TCL_VTX_ATTR_3I_XY_Y_MASK 0xffff0000
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#define NV34TCL_VTX_ATTR_3I_Z(x) (0x00000a84+((x)*8))
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#define NV34TCL_VTX_ATTR_3I_Z__SIZE 0x00000010
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#define NV34TCL_VTX_ATTR_3I_Z_Z_SHIFT 0
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#define NV34TCL_VTX_ATTR_3I_Z_Z_MASK 0x0000ffff
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#define NV34TCL_VP_UPLOAD_INST(x) (0x00000b80+((x)*4))
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#define NV34TCL_VP_UPLOAD_INST__SIZE 0x00000004
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#define NV34TCL_CLIP_PLANE_A(x) (0x00000e00+((x)*16))
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@ -4336,48 +4338,38 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#define NV34TCL_FRONT_FACE_CCW 0x00000901
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#define NV34TCL_POLYGON_SMOOTH_ENABLE 0x00001838
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#define NV34TCL_CULL_FACE_ENABLE 0x0000183c
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#define NV34TCL_VERTEX_ATTR_2F_X(x) (0x00001880+((x)*8))
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#define NV34TCL_VERTEX_ATTR_2F_X__SIZE 0x00000010
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#define NV34TCL_VERTEX_ATTR_2F_Y(x) (0x00001884+((x)*8))
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#define NV34TCL_VERTEX_ATTR_2F_Y__SIZE 0x00000010
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#define NV34TCL_VERTEX_ATTR_2I(x) (0x00001900+((x)*4))
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#define NV34TCL_VERTEX_ATTR_2I__SIZE 0x00000010
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#define NV34TCL_VERTEX_ATTR_2I_Y_SHIFT 16
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#define NV34TCL_VERTEX_ATTR_2I_Y_MASK 0xffff0000
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#define NV34TCL_VERTEX_ATTR_2I_X_SHIFT 0
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#define NV34TCL_VERTEX_ATTR_2I_X_MASK 0x0000ffff
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#define NV34TCL_VERTEX_COL_4I(x) (0x0000194c+((x)*4))
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#define NV34TCL_VERTEX_COL_4I__SIZE 0x00000002
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#define NV34TCL_VERTEX_COL_4I_R_SHIFT 0
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#define NV34TCL_VERTEX_COL_4I_R_MASK 0x000000ff
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#define NV34TCL_VERTEX_COL_4I_G_SHIFT 8
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#define NV34TCL_VERTEX_COL_4I_G_MASK 0x0000ff00
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#define NV34TCL_VERTEX_COL_4I_B_SHIFT 16
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#define NV34TCL_VERTEX_COL_4I_B_MASK 0x00ff0000
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#define NV34TCL_VERTEX_COL_4I_A_SHIFT 24
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#define NV34TCL_VERTEX_COL_4I_A_MASK 0xff000000
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#define NV34TCL_VERTEX_POS_4I_XY 0x00001980
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#define NV34TCL_VERTEX_POS_4I_XY_X_SHIFT 0
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#define NV34TCL_VERTEX_POS_4I_XY_X_MASK 0x0000ffff
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#define NV34TCL_VERTEX_POS_4I_XY_Y_SHIFT 16
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#define NV34TCL_VERTEX_POS_4I_XY_Y_MASK 0xffff0000
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#define NV34TCL_VERTEX_POS_4I_ZW 0x00001984
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#define NV34TCL_VERTEX_POS_4I_ZW_Z_SHIFT 0
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#define NV34TCL_VERTEX_POS_4I_ZW_Z_MASK 0x0000ffff
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#define NV34TCL_VERTEX_POS_4I_ZW_W_SHIFT 16
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#define NV34TCL_VERTEX_POS_4I_ZW_W_MASK 0xffff0000
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#define NV34TCL_VERTEX_TX_4I_ST(x) (0x000019c0+((x)*8))
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#define NV34TCL_VERTEX_TX_4I_ST__SIZE 0x00000004
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#define NV34TCL_VERTEX_TX_4I_ST_S_SHIFT 0
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#define NV34TCL_VERTEX_TX_4I_ST_S_MASK 0x0000ffff
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#define NV34TCL_VERTEX_TX_4I_ST_T_SHIFT 16
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#define NV34TCL_VERTEX_TX_4I_ST_T_MASK 0xffff0000
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#define NV34TCL_VERTEX_TX_4I_RQ(x) (0x000019c4+((x)*8))
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#define NV34TCL_VERTEX_TX_4I_RQ__SIZE 0x00000004
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#define NV34TCL_VERTEX_TX_4I_RQ_R_SHIFT 0
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#define NV34TCL_VERTEX_TX_4I_RQ_R_MASK 0x0000ffff
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#define NV34TCL_VERTEX_TX_4I_RQ_Q_SHIFT 16
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#define NV34TCL_VERTEX_TX_4I_RQ_Q_MASK 0xffff0000
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#define NV34TCL_VTX_ATTR_2F_X(x) (0x00001880+((x)*8))
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#define NV34TCL_VTX_ATTR_2F_X__SIZE 0x00000010
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#define NV34TCL_VTX_ATTR_2F_Y(x) (0x00001884+((x)*8))
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#define NV34TCL_VTX_ATTR_2F_Y__SIZE 0x00000010
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#define NV34TCL_VTX_ATTR_2I(x) (0x00001900+((x)*4))
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#define NV34TCL_VTX_ATTR_2I__SIZE 0x00000010
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#define NV34TCL_VTX_ATTR_2I_X_SHIFT 0
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#define NV34TCL_VTX_ATTR_2I_X_MASK 0x0000ffff
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#define NV34TCL_VTX_ATTR_2I_Y_SHIFT 16
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#define NV34TCL_VTX_ATTR_2I_Y_MASK 0xffff0000
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#define NV34TCL_VTX_ATTR_4UB(x) (0x00001940+((x)*4))
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#define NV34TCL_VTX_ATTR_4UB__SIZE 0x00000010
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#define NV34TCL_VTX_ATTR_4UB_X_SHIFT 0
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#define NV34TCL_VTX_ATTR_4UB_X_MASK 0x000000ff
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#define NV34TCL_VTX_ATTR_4UB_Y_SHIFT 8
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#define NV34TCL_VTX_ATTR_4UB_Y_MASK 0x0000ff00
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#define NV34TCL_VTX_ATTR_4UB_Z_SHIFT 16
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#define NV34TCL_VTX_ATTR_4UB_Z_MASK 0x00ff0000
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#define NV34TCL_VTX_ATTR_4UB_W_SHIFT 24
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#define NV34TCL_VTX_ATTR_4UB_W_MASK 0xff000000
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#define NV34TCL_VTX_ATTR_4I_XY(x) (0x00001980+((x)*8))
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#define NV34TCL_VTX_ATTR_4I_XY__SIZE 0x00000010
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#define NV34TCL_VTX_ATTR_4I_XY_X_SHIFT 0
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#define NV34TCL_VTX_ATTR_4I_XY_X_MASK 0x0000ffff
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#define NV34TCL_VTX_ATTR_4I_XY_Y_SHIFT 16
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#define NV34TCL_VTX_ATTR_4I_XY_Y_MASK 0xffff0000
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#define NV34TCL_VTX_ATTR_4I_ZW(x) (0x00001984+((x)*8))
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#define NV34TCL_VTX_ATTR_4I_ZW__SIZE 0x00000010
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#define NV34TCL_VTX_ATTR_4I_ZW_Z_SHIFT 0
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#define NV34TCL_VTX_ATTR_4I_ZW_Z_MASK 0x0000ffff
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#define NV34TCL_VTX_ATTR_4I_ZW_W_SHIFT 16
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#define NV34TCL_VTX_ATTR_4I_ZW_W_MASK 0xffff0000
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#define NV34TCL_TX_OFFSET(x) (0x00001a00+((x)*32))
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#define NV34TCL_TX_OFFSET__SIZE 0x00000004
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#define NV34TCL_TX_FORMAT(x) (0x00001a04+((x)*32))
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@ -4534,14 +4526,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#define NV34TCL_TX_BORDER_COLOR_R_MASK 0x00ff0000
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#define NV34TCL_TX_BORDER_COLOR_A_SHIFT 24
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#define NV34TCL_TX_BORDER_COLOR_A_MASK 0xff000000
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#define NV34TCL_VERTEX_ATTR_4F_X(x) (0x00001c00+((x)*16))
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#define NV34TCL_VERTEX_ATTR_4F_X__SIZE 0x00000010
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#define NV34TCL_VERTEX_ATTR_4F_Y(x) (0x00001c04+((x)*16))
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#define NV34TCL_VERTEX_ATTR_4F_Y__SIZE 0x00000010
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#define NV34TCL_VERTEX_ATTR_4F_Z(x) (0x00001c08+((x)*16))
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#define NV34TCL_VERTEX_ATTR_4F_Z__SIZE 0x00000010
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#define NV34TCL_VERTEX_ATTR_4F_W(x) (0x00001c0c+((x)*16))
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#define NV34TCL_VERTEX_ATTR_4F_W__SIZE 0x00000010
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#define NV34TCL_VTX_ATTR_4F_X(x) (0x00001c00+((x)*16))
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#define NV34TCL_VTX_ATTR_4F_X__SIZE 0x00000010
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#define NV34TCL_VTX_ATTR_4F_Y(x) (0x00001c04+((x)*16))
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#define NV34TCL_VTX_ATTR_4F_Y__SIZE 0x00000010
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#define NV34TCL_VTX_ATTR_4F_Z(x) (0x00001c08+((x)*16))
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#define NV34TCL_VTX_ATTR_4F_Z__SIZE 0x00000010
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#define NV34TCL_VTX_ATTR_4F_W(x) (0x00001c0c+((x)*16))
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#define NV34TCL_VTX_ATTR_4F_W__SIZE 0x00000010
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#define NV34TCL_FP_CONTROL 0x00001d60
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#define NV34TCL_FP_CONTROL_USES_KIL (1 << 7)
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#define NV34TCL_FP_CONTROL_USED_REGS_MINUS1_DIV2_SHIFT 0
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@ -4573,7 +4565,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#define NV34TCL_LINE_STIPPLE_PATTERN_PATTERN_MASK 0xffff0000
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#define NV34TCL_BACK_MATERIAL_SHININESS(x) (0x00001e20+((x)*4))
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#define NV34TCL_BACK_MATERIAL_SHININESS__SIZE 0x00000006
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#define NV34TCL_VERTEX_FOG_1F 0x00001e54
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#define NV34TCL_VTX_ATTR_1F(x) (0x00001e40+((x)*4))
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#define NV34TCL_VTX_ATTR_1F__SIZE 0x00000010
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#define NV34TCL_VP_UPLOAD_FROM_ID 0x00001e9c
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#define NV34TCL_VP_START_FROM_ID 0x00001ea0
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#define NV34TCL_POINT_PARAMETERS(x) (0x00001ec0+((x)*4))
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@ -4986,6 +4979,16 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#define NV40TCL_DEPTH_TEST_ENABLE 0x00000a74
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#define NV40TCL_POLYGON_OFFSET_FACTOR 0x00000a78
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#define NV40TCL_POLYGON_OFFSET_UNITS 0x00000a7c
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#define NV40TCL_VTX_ATTR_3I_XY(x) (0x00000a80+((x)*8))
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#define NV40TCL_VTX_ATTR_3I_XY__SIZE 0x00000010
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#define NV40TCL_VTX_ATTR_3I_XY_X_SHIFT 0
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#define NV40TCL_VTX_ATTR_3I_XY_X_MASK 0x0000ffff
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#define NV40TCL_VTX_ATTR_3I_XY_Y_SHIFT 16
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#define NV40TCL_VTX_ATTR_3I_XY_Y_MASK 0xffff0000
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#define NV40TCL_VTX_ATTR_3I_Z(x) (0x00000a84+((x)*8))
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#define NV40TCL_VTX_ATTR_3I_Z__SIZE 0x00000010
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#define NV40TCL_VTX_ATTR_3I_Z_Z_SHIFT 0
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#define NV40TCL_VTX_ATTR_3I_Z_Z_MASK 0x0000ffff
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#define NV40TCL_UNK0B40(x) (0x00000b40+((x)*4))
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#define NV40TCL_UNK0B40__SIZE 0x00000008
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#define NV40TCL_VP_UPLOAD_INST(x) (0x00000b80+((x)*4))
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@ -5095,22 +5098,32 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#define NV40TCL_VTX_ATTR_2F_Y__SIZE 0x00000010
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#define NV40TCL_VTX_ATTR_2I(x) (0x00001900+((x)*4))
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#define NV40TCL_VTX_ATTR_2I__SIZE 0x00000010
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#define NV40TCL_VTX_ATTR_2I_Y_SHIFT 16
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#define NV40TCL_VTX_ATTR_2I_Y_MASK 0xffff0000
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#define NV40TCL_VTX_ATTR_2I_X_SHIFT 0
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#define NV40TCL_VTX_ATTR_2I_X_MASK 0x0000ffff
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#define NV40TCL_VTX_ATTR_4I_0(x) (0x00001900+((x)*8))
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#define NV40TCL_VTX_ATTR_4I_0__SIZE 0x00000010
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#define NV40TCL_VTX_ATTR_4I_0_Y_SHIFT 16
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#define NV40TCL_VTX_ATTR_4I_0_Y_MASK 0xffff0000
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#define NV40TCL_VTX_ATTR_4I_0_X_SHIFT 0
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#define NV40TCL_VTX_ATTR_4I_0_X_MASK 0x0000ffff
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#define NV40TCL_VTX_ATTR_4I_1(x) (0x00001904+((x)*8))
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#define NV40TCL_VTX_ATTR_4I_1__SIZE 0x00000010
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#define NV40TCL_VTX_ATTR_4I_1_W_SHIFT 16
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#define NV40TCL_VTX_ATTR_4I_1_W_MASK 0xffff0000
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#define NV40TCL_VTX_ATTR_4I_1_Z_SHIFT 0
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#define NV40TCL_VTX_ATTR_4I_1_Z_MASK 0x0000ffff
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#define NV40TCL_VTX_ATTR_2I_Y_SHIFT 16
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#define NV40TCL_VTX_ATTR_2I_Y_MASK 0xffff0000
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#define NV40TCL_VTX_ATTR_4UB(x) (0x00001940+((x)*4))
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#define NV40TCL_VTX_ATTR_4UB__SIZE 0x00000010
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#define NV40TCL_VTX_ATTR_4UB_X_SHIFT 0
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#define NV40TCL_VTX_ATTR_4UB_X_MASK 0x000000ff
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#define NV40TCL_VTX_ATTR_4UB_Y_SHIFT 8
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#define NV40TCL_VTX_ATTR_4UB_Y_MASK 0x0000ff00
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#define NV40TCL_VTX_ATTR_4UB_Z_SHIFT 16
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#define NV40TCL_VTX_ATTR_4UB_Z_MASK 0x00ff0000
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#define NV40TCL_VTX_ATTR_4UB_W_SHIFT 24
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#define NV40TCL_VTX_ATTR_4UB_W_MASK 0xff000000
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#define NV40TCL_VTX_ATTR_4I_XY(x) (0x00001980+((x)*8))
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#define NV40TCL_VTX_ATTR_4I_XY__SIZE 0x00000010
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#define NV40TCL_VTX_ATTR_4I_XY_X_SHIFT 0
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#define NV40TCL_VTX_ATTR_4I_XY_X_MASK 0x0000ffff
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#define NV40TCL_VTX_ATTR_4I_XY_Y_SHIFT 16
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#define NV40TCL_VTX_ATTR_4I_XY_Y_MASK 0xffff0000
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#define NV40TCL_VTX_ATTR_4I_ZW(x) (0x00001984+((x)*8))
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#define NV40TCL_VTX_ATTR_4I_ZW__SIZE 0x00000010
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#define NV40TCL_VTX_ATTR_4I_ZW_Z_SHIFT 0
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#define NV40TCL_VTX_ATTR_4I_ZW_Z_MASK 0x0000ffff
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#define NV40TCL_VTX_ATTR_4I_ZW_W_SHIFT 16
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#define NV40TCL_VTX_ATTR_4I_ZW_W_MASK 0xffff0000
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#define NV40TCL_TEX_OFFSET(x) (0x00001a00+((x)*32))
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#define NV40TCL_TEX_OFFSET__SIZE 0x00000010
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#define NV40TCL_TEX_FORMAT(x) (0x00001a04+((x)*32))
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#define NV40TCL_LINE_STIPPLE_PATTERN_FACTOR_MASK 0x0000ffff
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#define NV40TCL_LINE_STIPPLE_PATTERN_PATTERN_SHIFT 16
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#define NV40TCL_LINE_STIPPLE_PATTERN_PATTERN_MASK 0xffff0000
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#define NV40TCL_VTX_ATTR_1F(x) (0x00001e40+((x)*4))
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#define NV40TCL_VTX_ATTR_1F__SIZE 0x00000010
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#define NV40TCL_VP_UPLOAD_FROM_ID 0x00001e9c
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#define NV40TCL_VP_START_FROM_ID 0x00001ea0
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#define NV40TCL_POINT_SIZE 0x00001ee0
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@ -55,7 +55,7 @@ nv30_vbo_static_attrib(struct nv30_context *nv30, int attrib,
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{
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float *v = map;
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BEGIN_RING(rankine, NV34TCL_VERTEX_ATTR_4F_X(attrib), 4);
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BEGIN_RING(rankine, NV34TCL_VTX_ATTR_4F_X(attrib), 4);
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switch (ncomp) {
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case 4:
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OUT_RINGf(v[0]);
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@ -39,7 +39,7 @@ nv40_render_vertex(struct nv40_context *nv40, const struct vertex_header *v)
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case EMIT_OMIT:
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break;
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case EMIT_1F:
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BEGIN_RING(curie, 0x1e40 + (hw * 4), 1);
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BEGIN_RING(curie, NV40TCL_VTX_ATTR_1F(hw), 1);
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OUT_RING (fui(v->data[idx][0]));
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break;
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case EMIT_2F:
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@ -61,7 +61,7 @@ nv40_render_vertex(struct nv40_context *nv40, const struct vertex_header *v)
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OUT_RING (fui(v->data[idx][3]));
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break;
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case EMIT_4UB:
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BEGIN_RING(curie, 0x1940 + (hw * 4), 1);
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BEGIN_RING(curie, NV40TCL_VTX_ATTR_4UB(hw), 1);
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OUT_RING (pack_ub4(float_to_ubyte(v->data[idx][0]),
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float_to_ubyte(v->data[idx][1]),
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float_to_ubyte(v->data[idx][2]),
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@ -149,7 +149,7 @@ nv40_vbo_static_attrib(struct nv40_context *nv40, struct nouveau_stateobj *so,
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so_data (so, fui(v[1]));
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break;
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case 1:
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so_method(so, curie, 0x1e40 + (attrib * 4), 1);
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so_method(so, curie, NV40TCL_VTX_ATTR_1F(attrib), 1);
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so_data (so, fui(v[0]));
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break;
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default:
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