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brw: add more condition for reducing sampler simdness

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Running
KHR-GL46.sparse_texture_clamp_tests.SparseTextureClampLookupColor test
with Zink on Anv we run into an assert :

assert(inst->mlen <= MAX_SAMPLER_MESSAGE_SIZE * reg_unit(devinfo));

Turns out we've not covered all the cases in the SIMD lowering.

It's a bit of a shame to have both files reproduce the same logic.
Will try to think of a better way to extract the layout of the a send
message but that'll be a much bigger rework.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29118>
(cherry picked from commit d1c01e256d)
This commit is contained in:
Lionel Landwerlin 2024-05-09 13:47:15 +03:00 • committed by Eric Engestrom
parent ee40beb60d
commit 8c0d63bce2
2 changed files with 27 additions and 4 deletions
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2
.pick_status.json
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@ -14,7 +14,7 @@
"description": "brw: add more condition for reducing sampler simdness",
"nominated": true,
"nomination_type": 0,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null,
"notes": null

29
src/intel/compiler/brw_fs_lower_simd_width.cpp
View file

@ -180,15 +180,38 @@ get_sampler_lowered_simd_width(const struct intel_device_info *devinfo,
/* Calculate the total number of argument components that need to be passed
* to the sampler unit.
*/
const unsigned num_payload_components =
inst->components_read(TEX_LOGICAL_SRC_COORDINATE) +
assert(inst->src[TEX_LOGICAL_SRC_GRAD_COMPONENTS].file == IMM);
const unsigned grad_components =
inst->src[TEX_LOGICAL_SRC_GRAD_COMPONENTS].ud;
assert(inst->src[TEX_LOGICAL_SRC_COORD_COMPONENTS].file == IMM);
const unsigned coord_components =
inst->src[TEX_LOGICAL_SRC_COORD_COMPONENTS].ud;
unsigned num_payload_components =
coord_components +
inst->components_read(TEX_LOGICAL_SRC_SHADOW_C) +
(implicit_lod ? 0 : inst->components_read(TEX_LOGICAL_SRC_LOD)) +
inst->components_read(TEX_LOGICAL_SRC_LOD2) +
inst->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX) +
(inst->opcode == SHADER_OPCODE_TG4_OFFSET_LOGICAL ?
inst->components_read(TEX_LOGICAL_SRC_TG4_OFFSET) : 0) +
inst->components_read(TEX_LOGICAL_SRC_MCS);
inst->components_read(TEX_LOGICAL_SRC_MCS) +
inst->components_read(TEX_LOGICAL_SRC_MIN_LOD);
if (inst->opcode == FS_OPCODE_TXB_LOGICAL &&
devinfo->ver >= 20 && inst->has_packed_lod_ai_src) {
num_payload_components += 3 - coord_components;
} else if (inst->opcode == SHADER_OPCODE_TXD_LOGICAL &&
devinfo->verx10 >= 125 && devinfo->ver < 20) {
num_payload_components +=
3 - coord_components + (2 - grad_components) * 2;
} else {
num_payload_components += 4 - coord_components;
if (inst->opcode == SHADER_OPCODE_TXD_LOGICAL)
num_payload_components += (3 - grad_components) * 2;
}
const unsigned simd_limit = reg_unit(devinfo) *
(num_payload_components > MAX_SAMPLER_MESSAGE_SIZE / 2 ? 8 : 16);