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iris: Use separate dirty bits for UBO and SSBO flushes.
This moves UBO+SSBO flushing into a dirty bit separate from the one used for image and sampler views, which saves some CPU overhead in the frequent case where buffers from only one or the other set are updated. Omitting this commit would lead to the following statistically significant Piglit Draw Overhead regressions: 107/DrawArrays (16 VBO| 8 UBO| 8 Tex) w/ 1 UBO change: XXX ±2.31% x22 -> XXX ±1.80% x21 d=-24.31% ±1.91% p=0.00% 78/DrawArrays ( 1 VBO| 8 UBO| 8 Tex) w/ 1 UBO change: XXX ±2.64% x22 -> XXX ±2.21% x21 d=-24.13% ±2.22% p=0.00% 45/DrawElements (16 VBO| 8 UBO| 8 Tex) w/ 1 UBO change: XXX ±2.53% x22 -> XXX ±1.90% x21 d=-23.63% ±2.07% p=0.00% 16/DrawElements ( 1 VBO| 8 UBO| 8 Tex) w/ 1 UBO change: XXX ±2.44% x22 -> XXX ±1.97% x21 d=-23.23% ±2.04% p=0.00% 108/DrawArrays (16 VBO| 8 UBO| 8 Tex) w/ 8 UBOs change: XXX ±2.10% x22 -> XXX ±1.50% x21 d=-22.15% ±1.71% p=0.00% 79/DrawArrays ( 1 VBO| 8 UBO| 8 Tex) w/ 8 UBOs change: XXX ±1.90% x22 -> XXX ±1.70% x21 d=-22.12% ±1.64% p=0.00% 17/DrawElements ( 1 VBO| 8 UBO| 8 Tex) w/ 8 UBOs change: XXX ±2.85% x22 -> XXX ±1.59% x21 d=-21.03% ±2.22% p=0.00% 46/DrawElements (16 VBO| 8 UBO| 8 Tex) w/ 8 UBOs change: XXX ±2.93% x22 -> XXX ±1.09% x21 d=-20.62% ±2.18% p=0.00% 7/DrawElements ( 1 VBO| 8 UBO| 8 Tex) w/ vertex attrib change: XXX ±9.30% x22 -> XXX ±7.02% x21 d=-6.49% ±8.08% p=1.19% 68/DrawArrays ( 1 VBO| 8 UBO| 8 Tex) w/ shader program change: XXX ±1.60% x22 -> XXX ±1.93% x21 d=-2.23% ±1.75% p=0.01% 6/DrawElements ( 1 VBO| 8 UBO| 8 Tex) w/ shader program change: XXX ±2.90% x22 -> XXX ±2.71% x21 d=-2.04% ±2.78% p=2.08% Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12691>
This commit is contained in:
parent
5c44df011f
commit
8be320117b
4 changed files with 63 additions and 39 deletions
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@ -113,8 +113,11 @@ enum {
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#define IRIS_DIRTY_RENDER_BUFFER (1ull << 30)
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#define IRIS_DIRTY_STENCIL_REF (1ull << 31)
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#define IRIS_DIRTY_VERTEX_BUFFER_FLUSHES (1ull << 32)
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#define IRIS_DIRTY_RENDER_MISC_BUFFER_FLUSHES (1ull << 33)
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#define IRIS_DIRTY_COMPUTE_MISC_BUFFER_FLUSHES (1ull << 34)
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#define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES)
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#define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES | \
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IRIS_DIRTY_COMPUTE_MISC_BUFFER_FLUSHES)
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#define IRIS_ALL_DIRTY_FOR_RENDER (~IRIS_ALL_DIRTY_FOR_COMPUTE)
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@ -1045,6 +1048,9 @@ void iris_predraw_resolve_inputs(struct iris_context *ice,
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void iris_predraw_resolve_framebuffer(struct iris_context *ice,
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struct iris_batch *batch,
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bool *draw_aux_buffer_disabled);
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void iris_predraw_flush_buffers(struct iris_context *ice,
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struct iris_batch *batch,
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gl_shader_stage stage);
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void iris_postdraw_update_resolve_tracking(struct iris_context *ice,
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struct iris_batch *batch);
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void iris_cache_flush_for_render(struct iris_batch *batch,
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@ -293,6 +293,11 @@ iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info,
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iris_predraw_resolve_framebuffer(ice, batch, draw_aux_buffer_disabled);
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}
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if (ice->state.dirty & IRIS_DIRTY_RENDER_MISC_BUFFER_FLUSHES) {
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for (gl_shader_stage stage = 0; stage < MESA_SHADER_COMPUTE; stage++)
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iris_predraw_flush_buffers(ice, batch, stage);
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}
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iris_binder_reserve_3d(ice);
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batch->screen->vtbl.update_surface_base_address(batch, &ice->state.binder);
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@ -385,6 +390,9 @@ iris_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info *grid)
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if (ice->state.dirty & IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES)
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iris_predraw_resolve_inputs(ice, batch, NULL, MESA_SHADER_COMPUTE, false);
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if (ice->state.dirty & IRIS_DIRTY_COMPUTE_MISC_BUFFER_FLUSHES)
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iris_predraw_flush_buffers(ice, batch, MESA_SHADER_COMPUTE);
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iris_batch_maybe_flush(batch, 1500);
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iris_update_compiled_compute_shader(ice);
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@ -151,34 +151,6 @@ resolve_image_views(struct iris_context *ice,
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}
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}
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static void
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flush_ubos(struct iris_batch *batch,
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struct iris_shader_state *shs)
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{
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uint32_t cbufs = shs->bound_cbufs;
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while (cbufs) {
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const int i = u_bit_scan(&cbufs);
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struct pipe_shader_buffer *cbuf = &shs->constbuf[i];
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struct iris_resource *res = (void *)cbuf->buffer;
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iris_emit_buffer_barrier_for(batch, res->bo, IRIS_DOMAIN_OTHER_READ);
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}
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}
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static void
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flush_ssbos(struct iris_batch *batch,
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struct iris_shader_state *shs)
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{
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uint32_t ssbos = shs->bound_ssbos;
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while (ssbos) {
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const int i = u_bit_scan(&ssbos);
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struct pipe_shader_buffer *ssbo = &shs->ssbo[i];
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struct iris_resource *res = (void *)ssbo->buffer;
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iris_emit_buffer_barrier_for(batch, res->bo, IRIS_DOMAIN_DATA_WRITE);
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}
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}
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/**
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* \brief Resolve buffers before drawing.
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*
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@ -203,11 +175,7 @@ iris_predraw_resolve_inputs(struct iris_context *ice,
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consider_framebuffer);
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resolve_image_views(ice, batch, shs, info, draw_aux_buffer_disabled,
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consider_framebuffer);
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flush_ssbos(batch, shs);
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}
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if (ice->state.stage_dirty & (IRIS_STAGE_DIRTY_CONSTANTS_VS << stage))
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flush_ubos(batch, shs);
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}
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void
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@ -403,6 +371,48 @@ iris_cache_flush_for_render(struct iris_batch *batch,
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}
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}
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static void
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flush_ubos(struct iris_batch *batch,
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struct iris_shader_state *shs)
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{
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uint32_t cbufs = shs->bound_cbufs;
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while (cbufs) {
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const int i = u_bit_scan(&cbufs);
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struct pipe_shader_buffer *cbuf = &shs->constbuf[i];
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struct iris_resource *res = (void *)cbuf->buffer;
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iris_emit_buffer_barrier_for(batch, res->bo, IRIS_DOMAIN_OTHER_READ);
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}
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}
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static void
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flush_ssbos(struct iris_batch *batch,
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struct iris_shader_state *shs)
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{
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uint32_t ssbos = shs->bound_ssbos;
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while (ssbos) {
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const int i = u_bit_scan(&ssbos);
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struct pipe_shader_buffer *ssbo = &shs->ssbo[i];
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struct iris_resource *res = (void *)ssbo->buffer;
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iris_emit_buffer_barrier_for(batch, res->bo, IRIS_DOMAIN_DATA_WRITE);
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}
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}
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void
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iris_predraw_flush_buffers(struct iris_context *ice,
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struct iris_batch *batch,
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gl_shader_stage stage)
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{
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struct iris_shader_state *shs = &ice->state.shaders[stage];
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if (ice->state.stage_dirty & (IRIS_STAGE_DIRTY_CONSTANTS_VS << stage))
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flush_ubos(batch, shs);
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if (ice->state.stage_dirty & (IRIS_STAGE_DIRTY_BINDINGS_VS << stage))
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flush_ssbos(batch, shs);
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}
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static void
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iris_resolve_color(struct iris_context *ice,
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struct iris_batch *batch,
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@ -3232,8 +3232,8 @@ iris_set_constant_buffer(struct pipe_context *ctx,
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memcpy(map, input->user_buffer, input->buffer_size);
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} else if (input->buffer) {
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if (cbuf->buffer != input->buffer) {
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ice->state.dirty |= (IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES |
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IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES);
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ice->state.dirty |= (IRIS_DIRTY_RENDER_MISC_BUFFER_FLUSHES |
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IRIS_DIRTY_COMPUTE_MISC_BUFFER_FLUSHES);
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}
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if (take_ownership) {
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@ -3405,8 +3405,8 @@ iris_set_shader_buffers(struct pipe_context *ctx,
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}
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}
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ice->state.dirty |= (IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES |
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IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES);
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ice->state.dirty |= (IRIS_DIRTY_RENDER_MISC_BUFFER_FLUSHES |
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IRIS_DIRTY_COMPUTE_MISC_BUFFER_FLUSHES);
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ice->state.stage_dirty |= IRIS_STAGE_DIRTY_BINDINGS_VS << stage;
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}
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@ -7315,8 +7315,8 @@ iris_rebind_buffer(struct iris_context *ice,
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if (res->bo == iris_resource_bo(cbuf->buffer)) {
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pipe_resource_reference(&surf_state->res, NULL);
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ice->state.dirty |= (IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES |
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IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES);
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ice->state.dirty |= (IRIS_DIRTY_RENDER_MISC_BUFFER_FLUSHES |
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IRIS_DIRTY_COMPUTE_MISC_BUFFER_FLUSHES);
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ice->state.stage_dirty |= IRIS_STAGE_DIRTY_CONSTANTS_VS << s;
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}
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}
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