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anv/xe2+: Fix format of scratch space surface address in various 3DSTATE packets.

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This field encodes bits [27:6] of the scratch surface state offset
according to the hardware spec, already on XeHP platforms.  However,
on previous platforms we were passing bits [25:4] instead, which was
apparently okay for two reasons:

 1/ We never used more than 8 MB of scratch surface states apparently.
 2/ A shift right by 2 was implicitly happening while copying the
    value of r0.5 into the address register holding the extended
    descriptor, which with the ExBSO addressing mode disabled
    considered bits [31:12] as the surface state index within the
    pool.

However on Xe2 ExBSO addressing mode is always enabled for the UGM
shared function, so we have to add an extra SHR instruction to format
the extended descriptor regardless, and there is no point in
disobeying the hardware spec passing a left-shifted offset.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29543>
This commit is contained in:
Francisco Jerez 2024-06-17 14:20:40 -07:00 • committed by Marge Bot
parent 0cd927fa92
commit 8bbad903a2
3 changed files with 16 additions and 3 deletions
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12
src/intel/vulkan/anv_private.h
View file

@ -920,6 +920,18 @@ uint32_t anv_scratch_pool_get_surf(struct anv_device *device,
struct anv_scratch_pool *pool,
unsigned per_thread_scratch);
/* Note that on Gfx12HP we pass a scratch space surface state offset
* shifted by 2 relative to the value specified on the BSpec, since
* that allows the compiler to save a shift instruction while
* constructing the extended descriptor for SS addressing. That
* worked because we limit the scratch surface state pool to 8 MB and
* because we relied on the legacy (ExBSO=0) encoding of the extended
* descriptor in order to save the shift, which is no longer supported
* for the UGM shared function on Xe2 platforms, so we no longer
* attempt to do that trick.
*/
#define ANV_SCRATCH_SPACE_SHIFT(ver) ((ver) >= 20 ? 6 : 4)
/** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
struct anv_bo_cache {
struct util_sparse_array bo_map;

5
src/intel/vulkan/genX_cmd_compute.c
View file

@ -70,7 +70,8 @@ genX(cmd_buffer_ensure_cfe_state)(struct anv_cmd_buffer *cmd_buffer,
anv_scratch_pool_get_surf(cmd_buffer->device,
&cmd_buffer->device->scratch_pool,
total_scratch);
cfe.ScratchSpaceBuffer = scratch_surf >> 4;
cfe.ScratchSpaceBuffer =
scratch_surf >> ANV_SCRATCH_SPACE_SHIFT(GFX_VER);
#if GFX_VER >= 20
switch (cmd_buffer->device->physical->instance->stack_ids) {
case 256: cfe.StackIDControl = StackIDs256; break;
@ -1044,7 +1045,7 @@ cmd_buffer_trace_rays(struct anv_cmd_buffer *cmd_buffer,
anv_scratch_pool_get_surf(cmd_buffer->device,
&device->scratch_pool,
pipeline->base.scratch_size);
btd.ScratchSpaceBuffer = scratch_surf >> 4;
btd.ScratchSpaceBuffer = scratch_surf >> ANV_SCRATCH_SPACE_SHIFT(GFX_VER);
}
#if INTEL_NEEDS_WA_14017794102
btd.BTDMidthreadpreemption = false;

2
src/intel/vulkan/genX_pipeline.c
View file

@ -1191,7 +1191,7 @@ get_scratch_surf(struct anv_pipeline *pipeline,
anv_reloc_list_add_bo(pipeline->batch.relocs, bo);
return anv_scratch_pool_get_surf(pipeline->device,
&pipeline->device->scratch_pool,
bin->prog_data->total_scratch) >> 4;
bin->prog_data->total_scratch) >> ANV_SCRATCH_SPACE_SHIFT(GFX_VER);
}
static void