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panfrost: implement indirect draw for CSF-based GPUs
Implement indirect draw by reading the indirect buffer info in CSF and triggering the IDVS operation just like for a normal direct draw. If transform feedback or a query is enabled, we still emulate the indirect draw on the CPU to properly update the XFB buffer offset and primitives statistics. Signed-off-by: Antonino Maniscalco <antonino.maniscalco@collabora.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com> Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30583>
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2 changed files with 59 additions and 21 deletions
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@ -41,7 +41,7 @@
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#include "util/u_prim.h"
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#define PAN_GPU_SUPPORTS_DISPATCH_INDIRECT (PAN_ARCH == 7 || PAN_ARCH >= 10)
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#define PAN_GPU_SUPPORTS_DRAW_INDIRECT 0
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#define PAN_GPU_SUPPORTS_DRAW_INDIRECT (PAN_ARCH >= 10)
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struct panfrost_rasterizer {
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struct pipe_rasterizer_state base;
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@ -717,15 +717,14 @@ csf_get_tiler_desc(struct panfrost_batch *batch)
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return batch->tiler_ctx.bifrost;
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}
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void
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GENX(csf_launch_draw)(struct panfrost_batch *batch,
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const struct pipe_draw_info *info, unsigned drawid_offset,
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const struct pipe_draw_start_count_bias *draw,
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unsigned vertex_count)
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static uint32_t
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csf_emit_draw_state(struct panfrost_batch *batch,
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const struct pipe_draw_info *info, unsigned drawid_offset)
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{
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struct panfrost_context *ctx = batch->ctx;
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struct panfrost_compiled_shader *vs = ctx->prog[PIPE_SHADER_VERTEX];
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struct panfrost_compiled_shader *fs = ctx->prog[PIPE_SHADER_FRAGMENT];
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bool idvs = vs->info.vs.idvs;
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bool fs_required = panfrost_fs_required(
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fs, ctx->blend, &ctx->pipe_framebuffer, ctx->depth_stencil);
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@ -757,20 +756,6 @@ GENX(csf_launch_draw)(struct panfrost_batch *batch,
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cs_move64_to(b, cs_reg64(b, 24), batch->tls.gpu);
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cs_move64_to(b, cs_reg64(b, 30), batch->tls.gpu);
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cs_move32_to(b, cs_reg32(b, 32), 0);
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cs_move32_to(b, cs_reg32(b, 33), draw->count);
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cs_move32_to(b, cs_reg32(b, 34), info->instance_count);
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cs_move32_to(b, cs_reg32(b, 35), 0);
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/* Base vertex offset on Valhall is used for both indexed and
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* non-indexed draws, in a simple way for either. Handle both cases.
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*/
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if (info->index_size) {
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cs_move32_to(b, cs_reg32(b, 36), draw->index_bias);
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cs_move32_to(b, cs_reg32(b, 39), info->index_size * draw->count);
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} else {
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cs_move32_to(b, cs_reg32(b, 36), draw->start);
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cs_move32_to(b, cs_reg32(b, 39), 0);
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}
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cs_move32_to(b, cs_reg32(b, 37), 0);
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cs_move32_to(b, cs_reg32(b, 38), 0);
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@ -936,6 +921,34 @@ GENX(csf_launch_draw)(struct panfrost_batch *batch,
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cfg.draw_mode = pan_draw_mode(info->mode);
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cfg.index_type = panfrost_translate_index_size(info->index_size);
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cfg.secondary_shader = secondary_shader;
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};
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return flags_override;
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}
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void
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GENX(csf_launch_draw)(struct panfrost_batch *batch,
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const struct pipe_draw_info *info, unsigned drawid_offset,
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const struct pipe_draw_start_count_bias *draw,
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unsigned vertex_count)
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{
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struct cs_builder *b = batch->csf.cs.builder;
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uint32_t flags_override = csf_emit_draw_state(batch, info, drawid_offset);
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cs_move32_to(b, cs_reg32(b, 33), draw->count);
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cs_move32_to(b, cs_reg32(b, 34), info->instance_count);
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cs_move32_to(b, cs_reg32(b, 35), 0);
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/* Base vertex offset on Valhall is used for both indexed and
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* non-indexed draws, in a simple way for either. Handle both cases.
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*/
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if (info->index_size) {
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cs_move32_to(b, cs_reg32(b, 36), draw->index_bias);
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cs_move32_to(b, cs_reg32(b, 39), info->index_size * draw->count);
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} else {
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cs_move32_to(b, cs_reg32(b, 36), draw->start);
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cs_move32_to(b, cs_reg32(b, 39), 0);
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}
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cs_run_idvs(b, flags_override, false, true, cs_shader_res_sel(0, 0, 1, 0),
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@ -948,7 +961,32 @@ GENX(csf_launch_draw_indirect)(struct panfrost_batch *batch,
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unsigned drawid_offset,
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const struct pipe_draw_indirect_info *indirect)
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{
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unreachable("draw indirect not implemented yet for CSF");
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struct cs_builder *b = batch->csf.cs.builder;
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assert(indirect->draw_count == 1);
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uint32_t flags_override = csf_emit_draw_state(batch, info, drawid_offset);
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struct cs_index address = cs_reg64(b, 64);
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cs_move64_to(
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b, address,
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pan_resource(indirect->buffer)->image.data.base + indirect->offset);
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if (info->index_size) {
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/* loads vertex count, instance count, index offset, vertex offset */
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cs_load_to(b, cs_reg_tuple(b, 33, 4), address, BITFIELD_MASK(4), 0);
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cs_move32_to(b, cs_reg32(b, 39), info->index.resource->width0);
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} else {
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/* vertex count, instance count */
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cs_load_to(b, cs_reg_tuple(b, 33, 2), address, BITFIELD_MASK(2), 0);
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cs_move32_to(b, cs_reg32(b, 35), 0);
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cs_load_to(b, cs_reg_tuple(b, 36, 1), address, BITFIELD_MASK(1),
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2 * sizeof(uint32_t)); // vertex offset
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cs_move32_to(b, cs_reg32(b, 39), 0);
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}
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cs_wait_slot(b, 0, false);
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cs_run_idvs(b, flags_override, false, true, cs_shader_res_sel(0, 0, 1, 0),
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cs_shader_res_sel(2, 2, 2, 0), cs_undef());
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}
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#define POSITION_FIFO_SIZE (64 * 1024)
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