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radeonsi: remove the _unused parameter in all radeon_xxx macros

Browse source 
I plan to re-use all these macros in RADV, mostly for GFX11 paired
packets and for GFX12.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29130>
This commit is contained in:
Samuel Pitoiset 2024-05-10 10:49:46 +02:00 • committed by Marge Bot
parent 5272a813f2
commit 8b85c58429
10 changed files with 174 additions and 179 deletions
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37
src/gallium/drivers/radeonsi/si_build_pm4.h
View file

@ -36,7 +36,7 @@
#define radeon_emit(value) __cs_buf[__cs_num++] = (value)
#define radeon_packets_added() (__cs_num != __cs_num_initial)
#define radeon_end_update_context_roll(_unused) do { \
#define radeon_end_update_context_roll() do { \
radeon_end(); \
if (radeon_packets_added()) \
sctx->context_roll = true; \
@ -202,35 +202,34 @@
radeon_set_reg(reg, 0, value, SI_CONFIG, PKT3_SET_CONFIG_REG)
/* Packet building helpers for CONTEXT registers. */
/* TODO: Remove the _unused parameters everywhere. */
#define radeon_set_context_reg_seq(reg, num) \
radeon_set_reg_seq(reg, num, 0, SI_CONTEXT, PKT3_SET_CONTEXT_REG, 0)
#define radeon_set_context_reg(reg, value) \
radeon_set_reg(reg, 0, value, SI_CONTEXT, PKT3_SET_CONTEXT_REG)
#define radeon_opt_set_context_reg(_unused, reg, reg_enum, value) \
#define radeon_opt_set_context_reg(reg, reg_enum, value) \
radeon_opt_set_reg(reg, reg_enum, 0, value, SI_CONTEXT, PKT3_SET_CONTEXT_REG)
#define radeon_opt_set_context_reg_idx(_unused, reg, reg_enum, idx, value) \
#define radeon_opt_set_context_reg_idx(reg, reg_enum, idx, value) \
radeon_opt_set_reg(reg, reg_enum, idx, value, SI_CONTEXT, PKT3_SET_CONTEXT_REG)
#define radeon_opt_set_context_reg2(_unused, reg, reg_enum, v1, v2) \
#define radeon_opt_set_context_reg2(reg, reg_enum, v1, v2) \
radeon_opt_set_reg2(reg, reg_enum, v1, v2, SI_CONTEXT, PKT3_SET_CONTEXT_REG)
#define radeon_opt_set_context_reg3(_unused, reg, reg_enum, v1, v2, v3) \
#define radeon_opt_set_context_reg3(reg, reg_enum, v1, v2, v3) \
radeon_opt_set_reg3(reg, reg_enum, v1, v2, v3, SI_CONTEXT, PKT3_SET_CONTEXT_REG)
#define radeon_opt_set_context_reg4(_unused, reg, reg_enum, v1, v2, v3, v4) \
#define radeon_opt_set_context_reg4(reg, reg_enum, v1, v2, v3, v4) \
radeon_opt_set_reg4(reg, reg_enum, v1, v2, v3, v4, SI_CONTEXT, PKT3_SET_CONTEXT_REG)
#define radeon_opt_set_context_reg5(_unused, reg, reg_enum, v1, v2, v3, v4, v5) \
#define radeon_opt_set_context_reg5(reg, reg_enum, v1, v2, v3, v4, v5) \
radeon_opt_set_reg5(reg, reg_enum, v1, v2, v3, v4, v5, SI_CONTEXT, PKT3_SET_CONTEXT_REG)
#define radeon_opt_set_context_reg6(reg, reg_enum, v1, v2, v3, v4, v5, v6) \
radeon_opt_set_reg6(reg, reg_enum, v1, v2, v3, v4, v5, v6, SI_CONTEXT, PKT3_SET_CONTEXT_REG)
#define radeon_opt_set_context_regn(_unused, reg, values, saved_values, num) \
#define radeon_opt_set_context_regn(reg, values, saved_values, num) \
radeon_opt_set_regn(reg, values, saved_values, num, SI_CONTEXT, PKT3_SET_CONTEXT_REG)
/* Packet building helpers for SH registers. */
@ -240,28 +239,28 @@
#define radeon_set_sh_reg(reg, value) \
radeon_set_reg(reg, 0, value, SI_SH, PKT3_SET_SH_REG)
#define radeon_opt_set_sh_reg(_unused, reg, reg_enum, value) \
#define radeon_opt_set_sh_reg(reg, reg_enum, value) \
radeon_opt_set_reg(reg, reg_enum, 0, value, SI_SH, PKT3_SET_SH_REG)
#define radeon_opt_set_sh_reg2(_unused, reg, reg_enum, v1, v2) \
#define radeon_opt_set_sh_reg2(reg, reg_enum, v1, v2) \
radeon_opt_set_reg2(reg, reg_enum, v1, v2, SI_SH, PKT3_SET_SH_REG)
#define radeon_opt_set_sh_reg3(_unused, reg, reg_enum, v1, v2, v3) \
#define radeon_opt_set_sh_reg3(reg, reg_enum, v1, v2, v3) \
radeon_opt_set_reg3(reg, reg_enum, v1, v2, v3, SI_SH, PKT3_SET_SH_REG)
#define radeon_opt_set_sh_reg_idx(_unused, reg, reg_enum, idx, value) do { \
#define radeon_opt_set_sh_reg_idx(reg, reg_enum, idx, value) do { \
assert(sctx->gfx_level >= GFX10); \
radeon_opt_set_reg(reg, reg_enum, idx, value, SI_SH, PKT3_SET_SH_REG_INDEX); \
} while (0)
#define radeon_emit_32bit_pointer(_unused, va) do { \
#define radeon_emit_32bit_pointer(va) do { \
assert((va) == 0 || ((va) >> 32) == sctx->screen->info.address32_hi); \
radeon_emit(va); \
} while (0)
#define radeon_emit_one_32bit_pointer(_unused, desc, sh_base) do { \
#define radeon_emit_one_32bit_pointer(desc, sh_base) do { \
radeon_set_sh_reg_seq((sh_base) + (desc)->shader_userdata_offset, 1); \
radeon_emit_32bit_pointer(_unused, (desc)->gpu_address); \
radeon_emit_32bit_pointer((desc)->gpu_address); \
} while (0)
/* Packet building helpers for UCONFIG registers. */
@ -276,17 +275,17 @@
#define radeon_set_uconfig_reg(reg, value) \
radeon_set_reg(reg, 0, value, CIK_UCONFIG, PKT3_SET_UCONFIG_REG)
#define radeon_opt_set_uconfig_reg(_unused, reg, reg_enum, value) \
#define radeon_opt_set_uconfig_reg(reg, reg_enum, value) \
radeon_opt_set_reg(reg, reg_enum, 0, value, CIK_UCONFIG, PKT3_SET_UCONFIG_REG)
#define RESOLVE_PKT3_SET_UCONFIG_REG_INDEX \
(GFX_VERSION >= GFX10 || (GFX_VERSION == GFX9 && sctx->screen->info.me_fw_version >= 26) ? \
PKT3_SET_UCONFIG_REG_INDEX : PKT3_SET_UCONFIG_REG)
#define radeon_set_uconfig_reg_idx(_unused, _unused2, reg, idx, value) \
#define radeon_set_uconfig_reg_idx(reg, idx, value) \
radeon_set_reg(reg, idx, value, CIK_UCONFIG, RESOLVE_PKT3_SET_UCONFIG_REG_INDEX)
#define radeon_opt_set_uconfig_reg_idx(_unused, _unused2, reg, reg_enum, idx, value) \
#define radeon_opt_set_uconfig_reg_idx(reg, reg_enum, idx, value) \
radeon_opt_set_reg(reg, reg_enum, idx, value, CIK_UCONFIG, RESOLVE_PKT3_SET_UCONFIG_REG_INDEX)
#define radeon_set_privileged_config_reg(reg, value) do { \

14
src/gallium/drivers/radeonsi/si_compute.c
View file

@ -542,23 +542,23 @@ static bool si_switch_compute_shader(struct si_context *sctx, struct si_compute
} else {
radeon_begin(cs);
radeon_set_sh_reg(R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
radeon_opt_set_sh_reg2(sctx, R_00B848_COMPUTE_PGM_RSRC1,
radeon_opt_set_sh_reg2(R_00B848_COMPUTE_PGM_RSRC1,
SI_TRACKED_COMPUTE_PGM_RSRC1,
config->rsrc1, rsrc2);
radeon_opt_set_sh_reg(sctx, R_00B860_COMPUTE_TMPRING_SIZE,
radeon_opt_set_sh_reg(R_00B860_COMPUTE_TMPRING_SIZE,
SI_TRACKED_COMPUTE_TMPRING_SIZE, tmpring_size);
if (shader->scratch_bo &&
(sctx->gfx_level >= GFX11 ||
(sctx->family >= CHIP_GFX940 && !sctx->screen->info.has_graphics))) {
radeon_opt_set_sh_reg2(sctx, R_00B840_COMPUTE_DISPATCH_SCRATCH_BASE_LO,
radeon_opt_set_sh_reg2(R_00B840_COMPUTE_DISPATCH_SCRATCH_BASE_LO,
SI_TRACKED_COMPUTE_DISPATCH_SCRATCH_BASE_LO,
sctx->compute_scratch_buffer->gpu_address >> 8,
sctx->compute_scratch_buffer->gpu_address >> 40);
}
if (sctx->gfx_level >= GFX11) {
radeon_opt_set_sh_reg(sctx, R_00B8A0_COMPUTE_PGM_RSRC3,
radeon_opt_set_sh_reg(R_00B8A0_COMPUTE_PGM_RSRC3,
SI_TRACKED_COMPUTE_PGM_RSRC3,
S_00B8A0_INST_PREF_SIZE_GFX11(si_get_shader_prefetch_size(shader)));
}
@ -924,7 +924,7 @@ static void si_emit_dispatch_packets(struct si_context *sctx, const struct pipe_
SI_TRACKED_COMPUTE_RESOURCE_LIMITS,
compute_resource_limits);
} else {
radeon_opt_set_sh_reg(sctx, R_00B854_COMPUTE_RESOURCE_LIMITS,
radeon_opt_set_sh_reg(R_00B854_COMPUTE_RESOURCE_LIMITS,
SI_TRACKED_COMPUTE_RESOURCE_LIMITS,
compute_resource_limits);
}
@ -1026,7 +1026,7 @@ static void si_emit_dispatch_packets(struct si_context *sctx, const struct pipe_
}
if (sctx->has_graphics) {
radeon_opt_set_sh_reg_idx(sctx, R_00B8BC_COMPUTE_DISPATCH_INTERLEAVE,
radeon_opt_set_sh_reg_idx(R_00B8BC_COMPUTE_DISPATCH_INTERLEAVE,
SI_TRACKED_COMPUTE_DISPATCH_INTERLEAVE, 2, dispatch_interleave);
} else {
gfx12_opt_push_compute_sh_reg(R_00B8BC_COMPUTE_DISPATCH_INTERLEAVE,
@ -1049,7 +1049,7 @@ static void si_emit_dispatch_packets(struct si_context *sctx, const struct pipe_
gfx11_opt_push_compute_sh_reg(R_00B824_COMPUTE_NUM_THREAD_Z,
SI_TRACKED_COMPUTE_NUM_THREAD_Z, num_threads[2]);
} else {
radeon_opt_set_sh_reg3(sctx, R_00B81C_COMPUTE_NUM_THREAD_X,
radeon_opt_set_sh_reg3(R_00B81C_COMPUTE_NUM_THREAD_X,
SI_TRACKED_COMPUTE_NUM_THREAD_X,
num_threads[0], num_threads[1], num_threads[2]);
}

40
src/gallium/drivers/radeonsi/si_descriptors.c
View file

@ -2255,7 +2255,7 @@ void si_shader_change_notify(struct si_context *sctx)
\
radeon_set_sh_reg_seq(sh_offset, count); \
for (int i = 0; i < count; i++) \
radeon_emit_32bit_pointer(sctx->screen, descs[i].gpu_address); \
radeon_emit_32bit_pointer(descs[i].gpu_address); \
} \
} \
} while (0)
@ -2295,31 +2295,31 @@ static void si_emit_global_shader_pointers(struct si_context *sctx, struct si_de
radeon_begin(&sctx->gfx_cs);
if (sctx->gfx_level >= GFX11) {
radeon_emit_one_32bit_pointer(sctx, descs, R_00B030_SPI_SHADER_USER_DATA_PS_0);
radeon_emit_one_32bit_pointer(sctx, descs, R_00B230_SPI_SHADER_USER_DATA_GS_0);
radeon_emit_one_32bit_pointer(sctx, descs, R_00B430_SPI_SHADER_USER_DATA_HS_0);
radeon_emit_one_32bit_pointer(descs, R_00B030_SPI_SHADER_USER_DATA_PS_0);
radeon_emit_one_32bit_pointer(descs, R_00B230_SPI_SHADER_USER_DATA_GS_0);
radeon_emit_one_32bit_pointer(descs, R_00B430_SPI_SHADER_USER_DATA_HS_0);
} else if (sctx->gfx_level >= GFX10) {
radeon_emit_one_32bit_pointer(sctx, descs, R_00B030_SPI_SHADER_USER_DATA_PS_0);
radeon_emit_one_32bit_pointer(descs, R_00B030_SPI_SHADER_USER_DATA_PS_0);
/* HW VS stage only used in non-NGG mode. */
radeon_emit_one_32bit_pointer(sctx, descs, R_00B130_SPI_SHADER_USER_DATA_VS_0);
radeon_emit_one_32bit_pointer(sctx, descs, R_00B230_SPI_SHADER_USER_DATA_GS_0);
radeon_emit_one_32bit_pointer(sctx, descs, R_00B430_SPI_SHADER_USER_DATA_HS_0);
radeon_emit_one_32bit_pointer(descs, R_00B130_SPI_SHADER_USER_DATA_VS_0);
radeon_emit_one_32bit_pointer(descs, R_00B230_SPI_SHADER_USER_DATA_GS_0);
radeon_emit_one_32bit_pointer(descs, R_00B430_SPI_SHADER_USER_DATA_HS_0);
} else if (sctx->gfx_level == GFX9 && sctx->shadowing.registers) {
/* We can't use the COMMON registers with register shadowing. */
radeon_emit_one_32bit_pointer(sctx, descs, R_00B030_SPI_SHADER_USER_DATA_PS_0);
radeon_emit_one_32bit_pointer(sctx, descs, R_00B130_SPI_SHADER_USER_DATA_VS_0);
radeon_emit_one_32bit_pointer(sctx, descs, R_00B330_SPI_SHADER_USER_DATA_ES_0);
radeon_emit_one_32bit_pointer(sctx, descs, R_00B430_SPI_SHADER_USER_DATA_LS_0);
radeon_emit_one_32bit_pointer(descs, R_00B030_SPI_SHADER_USER_DATA_PS_0);
radeon_emit_one_32bit_pointer(descs, R_00B130_SPI_SHADER_USER_DATA_VS_0);
radeon_emit_one_32bit_pointer(descs, R_00B330_SPI_SHADER_USER_DATA_ES_0);
radeon_emit_one_32bit_pointer(descs, R_00B430_SPI_SHADER_USER_DATA_LS_0);
} else if (sctx->gfx_level == GFX9) {
/* Broadcast it to all shader stages. */
radeon_emit_one_32bit_pointer(sctx, descs, R_00B530_SPI_SHADER_USER_DATA_COMMON_0);
radeon_emit_one_32bit_pointer(descs, R_00B530_SPI_SHADER_USER_DATA_COMMON_0);
} else {
radeon_emit_one_32bit_pointer(sctx, descs, R_00B030_SPI_SHADER_USER_DATA_PS_0);
radeon_emit_one_32bit_pointer(sctx, descs, R_00B130_SPI_SHADER_USER_DATA_VS_0);
radeon_emit_one_32bit_pointer(sctx, descs, R_00B330_SPI_SHADER_USER_DATA_ES_0);
radeon_emit_one_32bit_pointer(sctx, descs, R_00B230_SPI_SHADER_USER_DATA_GS_0);
radeon_emit_one_32bit_pointer(sctx, descs, R_00B430_SPI_SHADER_USER_DATA_HS_0);
radeon_emit_one_32bit_pointer(sctx, descs, R_00B530_SPI_SHADER_USER_DATA_LS_0);
radeon_emit_one_32bit_pointer(descs, R_00B030_SPI_SHADER_USER_DATA_PS_0);
radeon_emit_one_32bit_pointer(descs, R_00B130_SPI_SHADER_USER_DATA_VS_0);
radeon_emit_one_32bit_pointer(descs, R_00B330_SPI_SHADER_USER_DATA_ES_0);
radeon_emit_one_32bit_pointer(descs, R_00B230_SPI_SHADER_USER_DATA_GS_0);
radeon_emit_one_32bit_pointer(descs, R_00B430_SPI_SHADER_USER_DATA_HS_0);
radeon_emit_one_32bit_pointer(descs, R_00B530_SPI_SHADER_USER_DATA_LS_0);
}
radeon_end();
}
@ -2498,7 +2498,7 @@ void si_emit_compute_shader_pointers(struct si_context *sctx)
R_00B900_COMPUTE_USER_DATA_0, compute);
if (sctx->compute_bindless_pointer_dirty) {
radeon_emit_one_32bit_pointer(sctx, &sctx->bindless_descriptors,
radeon_emit_one_32bit_pointer(&sctx->bindless_descriptors,
R_00B900_COMPUTE_USER_DATA_0);
sctx->compute_bindless_pointer_dirty = false;
}

60
src/gallium/drivers/radeonsi/si_state.c
View file

@ -283,17 +283,17 @@ static void si_emit_cb_render_state(struct si_context *sctx, unsigned index)
radeon_end(); /* don't track context rolls on GFX11 */
} else {
radeon_begin(cs);
radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK, SI_TRACKED_CB_TARGET_MASK,
radeon_opt_set_context_reg(R_028238_CB_TARGET_MASK, SI_TRACKED_CB_TARGET_MASK,
cb_target_mask);
if (sctx->gfx_level >= GFX8) {
radeon_opt_set_context_reg(sctx, R_028424_CB_DCC_CONTROL, SI_TRACKED_CB_DCC_CONTROL,
radeon_opt_set_context_reg(R_028424_CB_DCC_CONTROL, SI_TRACKED_CB_DCC_CONTROL,
cb_dcc_control);
}
if (sctx->screen->info.rbplus_allowed) {
radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT, SI_TRACKED_SX_PS_DOWNCONVERT,
radeon_opt_set_context_reg3(R_028754_SX_PS_DOWNCONVERT, SI_TRACKED_SX_PS_DOWNCONVERT,
sx_ps_downconvert, sx_blend_opt_epsilon, sx_blend_opt_control);
}
radeon_end_update_context_roll(sctx);
radeon_end_update_context_roll();
}
}
@ -952,11 +952,11 @@ static void si_emit_clip_regs(struct si_context *sctx, unsigned index)
radeon_end(); /* don't track context rolls on GFX11 */
} else {
radeon_begin(&sctx->gfx_cs);
radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL, SI_TRACKED_PA_CL_CLIP_CNTL,
radeon_opt_set_context_reg(R_028810_PA_CL_CLIP_CNTL, SI_TRACKED_PA_CL_CLIP_CNTL,
pa_cl_clip_cntl);
radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL, SI_TRACKED_PA_CL_VS_OUT_CNTL,
radeon_opt_set_context_reg(R_02881C_PA_CL_VS_OUT_CNTL, SI_TRACKED_PA_CL_VS_OUT_CNTL,
pa_cl_vs_out_cntl);
radeon_end_update_context_roll(sctx);
radeon_end_update_context_roll();
}
}
@ -1280,24 +1280,24 @@ static void si_pm4_emit_rasterizer(struct si_context *sctx, unsigned index)
radeon_end(); /* don't track context rolls on GFX11 */
} else {
radeon_begin(&sctx->gfx_cs);
radeon_opt_set_context_reg(sctx, R_0286D4_SPI_INTERP_CONTROL_0,
radeon_opt_set_context_reg(R_0286D4_SPI_INTERP_CONTROL_0,
SI_TRACKED_SPI_INTERP_CONTROL_0,
state->spi_interp_control_0);
radeon_opt_set_context_reg(sctx, R_028A00_PA_SU_POINT_SIZE, SI_TRACKED_PA_SU_POINT_SIZE,
radeon_opt_set_context_reg(R_028A00_PA_SU_POINT_SIZE, SI_TRACKED_PA_SU_POINT_SIZE,
state->pa_su_point_size);
radeon_opt_set_context_reg(sctx, R_028A04_PA_SU_POINT_MINMAX, SI_TRACKED_PA_SU_POINT_MINMAX,
radeon_opt_set_context_reg(R_028A04_PA_SU_POINT_MINMAX, SI_TRACKED_PA_SU_POINT_MINMAX,
state->pa_su_point_minmax);
radeon_opt_set_context_reg(sctx, R_028A08_PA_SU_LINE_CNTL, SI_TRACKED_PA_SU_LINE_CNTL,
radeon_opt_set_context_reg(R_028A08_PA_SU_LINE_CNTL, SI_TRACKED_PA_SU_LINE_CNTL,
state->pa_su_line_cntl);
radeon_opt_set_context_reg(sctx, R_028A48_PA_SC_MODE_CNTL_0, SI_TRACKED_PA_SC_MODE_CNTL_0,
radeon_opt_set_context_reg(R_028A48_PA_SC_MODE_CNTL_0, SI_TRACKED_PA_SC_MODE_CNTL_0,
state->pa_sc_mode_cntl_0);
radeon_opt_set_context_reg(sctx, R_028814_PA_SU_SC_MODE_CNTL,
radeon_opt_set_context_reg(R_028814_PA_SU_SC_MODE_CNTL,
SI_TRACKED_PA_SU_SC_MODE_CNTL, state->pa_su_sc_mode_cntl);
if (sctx->gfx_level >= GFX10) {
radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL, SI_TRACKED_PA_CL_NGG_CNTL,
radeon_opt_set_context_reg(R_028838_PA_CL_NGG_CNTL, SI_TRACKED_PA_CL_NGG_CNTL,
state->pa_cl_ngg_cntl);
}
radeon_opt_set_context_reg(sctx, R_028230_PA_SC_EDGERULE, SI_TRACKED_PA_SC_EDGERULE,
radeon_opt_set_context_reg(R_028230_PA_SC_EDGERULE, SI_TRACKED_PA_SC_EDGERULE,
state->pa_sc_edgerule);
if (state->uses_poly_offset && sctx->framebuffer.state.zsbuf) {
@ -1664,7 +1664,7 @@ static void si_pm4_emit_dsa(struct si_context *sctx, unsigned index)
SI_TRACKED_SPI_SHADER_USER_DATA_PS__ALPHA_REF,
state->spi_shader_user_data_ps_alpha_ref);
} else {
radeon_opt_set_sh_reg(sctx, R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_ALPHA_REF * 4,
radeon_opt_set_sh_reg(R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_ALPHA_REF * 4,
SI_TRACKED_SPI_SHADER_USER_DATA_PS__ALPHA_REF,
state->spi_shader_user_data_ps_alpha_ref);
}
@ -1672,14 +1672,14 @@ static void si_pm4_emit_dsa(struct si_context *sctx, unsigned index)
radeon_end(); /* don't track context rolls on GFX11 */
} else {
radeon_begin(&sctx->gfx_cs);
radeon_opt_set_context_reg(sctx, R_028800_DB_DEPTH_CONTROL, SI_TRACKED_DB_DEPTH_CONTROL,
radeon_opt_set_context_reg(R_028800_DB_DEPTH_CONTROL, SI_TRACKED_DB_DEPTH_CONTROL,
state->db_depth_control);
if (state->stencil_enabled) {
radeon_opt_set_context_reg(sctx, R_02842C_DB_STENCIL_CONTROL, SI_TRACKED_DB_STENCIL_CONTROL,
radeon_opt_set_context_reg(R_02842C_DB_STENCIL_CONTROL, SI_TRACKED_DB_STENCIL_CONTROL,
state->db_stencil_control);
}
if (state->depth_bounds_enabled) {
radeon_opt_set_context_reg2(sctx, R_028020_DB_DEPTH_BOUNDS_MIN,
radeon_opt_set_context_reg2(R_028020_DB_DEPTH_BOUNDS_MIN,
SI_TRACKED_DB_DEPTH_BOUNDS_MIN,
state->db_depth_bounds_min,
state->db_depth_bounds_max);
@ -1688,7 +1688,7 @@ static void si_pm4_emit_dsa(struct si_context *sctx, unsigned index)
if (state->alpha_func != PIPE_FUNC_ALWAYS) {
radeon_begin(&sctx->gfx_cs);
radeon_opt_set_sh_reg(sctx, R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_ALPHA_REF * 4,
radeon_opt_set_sh_reg(R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_ALPHA_REF * 4,
SI_TRACKED_SPI_SHADER_USER_DATA_PS__ALPHA_REF,
state->spi_shader_user_data_ps_alpha_ref);
radeon_end();
@ -1955,21 +1955,21 @@ static void si_emit_db_render_state(struct si_context *sctx, unsigned index)
radeon_end(); /* don't track context rolls on GFX11 */
} else {
radeon_begin(&sctx->gfx_cs);
radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL, SI_TRACKED_DB_RENDER_CONTROL,
radeon_opt_set_context_reg2(R_028000_DB_RENDER_CONTROL, SI_TRACKED_DB_RENDER_CONTROL,
db_render_control, db_count_control);
radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
radeon_opt_set_context_reg(R_028010_DB_RENDER_OVERRIDE2,
SI_TRACKED_DB_RENDER_OVERRIDE2, db_render_override2);
radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL, SI_TRACKED_DB_SHADER_CONTROL,
radeon_opt_set_context_reg(R_02880C_DB_SHADER_CONTROL, SI_TRACKED_DB_SHADER_CONTROL,
db_shader_control);
if (sctx->gfx_level >= GFX11) {
radeon_opt_set_context_reg(sctx, R_0283D0_PA_SC_VRS_OVERRIDE_CNTL,
radeon_opt_set_context_reg(R_0283D0_PA_SC_VRS_OVERRIDE_CNTL,
SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL, vrs_override_cntl);
} else if (sctx->gfx_level >= GFX10_3) {
radeon_opt_set_context_reg(sctx, R_028064_DB_VRS_OVERRIDE_CNTL,
radeon_opt_set_context_reg(R_028064_DB_VRS_OVERRIDE_CNTL,
SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL, vrs_override_cntl);
}
radeon_end_update_context_roll(sctx);
radeon_end_update_context_roll();
}
}
@ -4513,12 +4513,12 @@ static void si_emit_msaa_config(struct si_context *sctx, unsigned index)
radeon_end(); /* don't track context rolls on GFX11 */
} else {
radeon_begin(cs);
radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL, SI_TRACKED_PA_SC_LINE_CNTL,
radeon_opt_set_context_reg2(R_028BDC_PA_SC_LINE_CNTL, SI_TRACKED_PA_SC_LINE_CNTL,
sc_line_cntl, sc_aa_config);
radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA, db_eqaa);
radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1, SI_TRACKED_PA_SC_MODE_CNTL_1,
radeon_opt_set_context_reg(R_028804_DB_EQAA, SI_TRACKED_DB_EQAA, db_eqaa);
radeon_opt_set_context_reg(R_028A4C_PA_SC_MODE_CNTL_1, SI_TRACKED_PA_SC_MODE_CNTL_1,
sc_mode_cntl_1);
radeon_end_update_context_roll(sctx);
radeon_end_update_context_roll();
}
}

12
src/gallium/drivers/radeonsi/si_state_binning.c
View file

@ -393,7 +393,7 @@ static void si_emit_dpbb_disable(struct si_context *sctx)
if (sctx->gfx_level >= GFX12) {
struct uvec2 bin_size = {128, 128};
radeon_opt_set_context_reg(sctx, R_028C44_PA_SC_BINNER_CNTL_0,
radeon_opt_set_context_reg(R_028C44_PA_SC_BINNER_CNTL_0,
SI_TRACKED_PA_SC_BINNER_CNTL_0,
S_028C44_BINNING_MODE(V_028C44_BINNING_DISABLED) |
S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(bin_size.x) - 5) |
@ -417,7 +417,7 @@ static void si_emit_dpbb_disable(struct si_context *sctx)
if (bin_size.y >= 32)
bin_size_extend.y = util_logbase2(bin_size.y) - 5;
radeon_opt_set_context_reg(sctx, R_028C44_PA_SC_BINNER_CNTL_0,
radeon_opt_set_context_reg(R_028C44_PA_SC_BINNER_CNTL_0,
SI_TRACKED_PA_SC_BINNER_CNTL_0,
S_028C44_BINNING_MODE(binning_disabled) |
S_028C44_BIN_SIZE_X(bin_size.x == 16) |
@ -429,7 +429,7 @@ static void si_emit_dpbb_disable(struct si_context *sctx)
S_028C44_OPTIMAL_BIN_SELECTION(optimal_bin_selection) |
S_028C44_FLUSH_ON_BINNING_TRANSITION(1));
} else {
radeon_opt_set_context_reg(sctx, R_028C44_PA_SC_BINNER_CNTL_0,
radeon_opt_set_context_reg(R_028C44_PA_SC_BINNER_CNTL_0,
SI_TRACKED_PA_SC_BINNER_CNTL_0,
S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
S_028C44_DISABLE_START_OF_PRIM(1) |
@ -437,7 +437,7 @@ static void si_emit_dpbb_disable(struct si_context *sctx)
sctx->family == CHIP_VEGA20 ||
sctx->family >= CHIP_RAVEN2));
}
radeon_end_update_context_roll(sctx);
radeon_end_update_context_roll();
}
void si_emit_dpbb_state(struct si_context *sctx, unsigned index)
@ -512,7 +512,7 @@ void si_emit_dpbb_state(struct si_context *sctx, unsigned index)
bin_size_extend.y = util_logbase2(bin_size.y) - 5;
radeon_begin(&sctx->gfx_cs);
radeon_opt_set_context_reg(sctx, R_028C44_PA_SC_BINNER_CNTL_0, SI_TRACKED_PA_SC_BINNER_CNTL_0,
radeon_opt_set_context_reg(R_028C44_PA_SC_BINNER_CNTL_0, SI_TRACKED_PA_SC_BINNER_CNTL_0,
S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
S_028C44_BIN_SIZE_X(bin_size.x == 16) |
S_028C44_BIN_SIZE_Y(bin_size.y == 16) |
@ -526,5 +526,5 @@ void si_emit_dpbb_state(struct si_context *sctx, unsigned index)
S_028C44_FLUSH_ON_BINNING_TRANSITION(sctx->family == CHIP_VEGA12 ||
sctx->family == CHIP_VEGA20 ||
sctx->family >= CHIP_RAVEN2));
radeon_end_update_context_roll(sctx);
radeon_end_update_context_roll();
}

30
src/gallium/drivers/radeonsi/si_state_draw.cpp
View file

@ -931,13 +931,13 @@ static void si_emit_rasterizer_prim_state(struct si_context *sctx)
rast_prim == MESA_PRIM_LINES_ADJACENCY;
/* 0 = no reset, 1 = reset per prim, 2 = reset per packet */
if (GFX_VERSION >= GFX12) {
radeon_opt_set_context_reg(sctx, R_028A44_PA_SC_LINE_STIPPLE_RESET,
radeon_opt_set_context_reg(R_028A44_PA_SC_LINE_STIPPLE_RESET,
SI_TRACKED_PA_SC_LINE_STIPPLE_RESET,
S_028A44_AUTO_RESET_CNTL(reset_per_prim ? 1 : 2));
} else {
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
radeon_opt_set_context_reg(sctx, R_028A0C_PA_SC_LINE_STIPPLE,
radeon_opt_set_context_reg(R_028A0C_PA_SC_LINE_STIPPLE,
SI_TRACKED_PA_SC_LINE_STIPPLE,
rs->pa_sc_line_stipple |
S_028A0C_AUTO_RESET_CNTL(reset_per_prim ? 1 : 2));
@ -946,16 +946,16 @@ static void si_emit_rasterizer_prim_state(struct si_context *sctx)
if (NGG || HAS_GS) {
if (GFX_VERSION >= GFX11) {
radeon_opt_set_uconfig_reg(sctx, R_030998_VGT_GS_OUT_PRIM_TYPE,
radeon_opt_set_uconfig_reg(R_030998_VGT_GS_OUT_PRIM_TYPE,
SI_TRACKED_VGT_GS_OUT_PRIM_TYPE_UCONFIG, sctx->gs_out_prim);
} else {
radeon_opt_set_context_reg(sctx, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
radeon_opt_set_context_reg(R_028A6C_VGT_GS_OUT_PRIM_TYPE,
SI_TRACKED_VGT_GS_OUT_PRIM_TYPE, sctx->gs_out_prim);
}
}
if (GFX_VERSION == GFX9)
radeon_end_update_context_roll(sctx);
radeon_end_update_context_roll();
else
radeon_end();
}
@ -1070,14 +1070,14 @@ static void si_emit_ia_multi_vgt_param(struct si_context *sctx,
if (prim != sctx->last_prim)
BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, SI_TRACKED_IA_MULTI_VGT_PARAM_UCONFIG);
radeon_opt_set_uconfig_reg_idx(sctx, GFX_VERSION, R_030960_IA_MULTI_VGT_PARAM,
radeon_opt_set_uconfig_reg_idx(R_030960_IA_MULTI_VGT_PARAM,
SI_TRACKED_IA_MULTI_VGT_PARAM_UCONFIG,
4, ia_multi_vgt_param);
} else if (GFX_VERSION >= GFX7) {
radeon_opt_set_context_reg_idx(sctx, R_028AA8_IA_MULTI_VGT_PARAM,
radeon_opt_set_context_reg_idx(R_028AA8_IA_MULTI_VGT_PARAM,
SI_TRACKED_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
} else {
radeon_opt_set_context_reg(sctx, R_028AA8_IA_MULTI_VGT_PARAM,
radeon_opt_set_context_reg(R_028AA8_IA_MULTI_VGT_PARAM,
SI_TRACKED_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
}
radeon_end();
@ -1109,7 +1109,7 @@ static void si_emit_draw_registers(struct si_context *sctx,
if (GFX_VERSION >= GFX10)
radeon_set_uconfig_reg(R_030908_VGT_PRIMITIVE_TYPE, vgt_prim);
else if (GFX_VERSION >= GFX7)
radeon_set_uconfig_reg_idx(sctx->screen, GFX_VERSION, R_030908_VGT_PRIMITIVE_TYPE, 1, vgt_prim);
radeon_set_uconfig_reg_idx(R_030908_VGT_PRIMITIVE_TYPE, 1, vgt_prim);
else
radeon_set_config_reg(R_008958_VGT_PRIMITIVE_TYPE, vgt_prim);
@ -1329,8 +1329,7 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw
}
if (GFX_VERSION >= GFX9) {
radeon_set_uconfig_reg_idx(sctx->screen, GFX_VERSION,
R_03090C_VGT_INDEX_TYPE, 2, index_type);
radeon_set_uconfig_reg_idx(R_03090C_VGT_INDEX_TYPE, 2, index_type);
} else {
radeon_emit(PKT3(PKT3_INDEX_TYPE, 0, 0));
radeon_emit(index_type);
@ -1361,8 +1360,7 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw
if (GFX_VERSION >= GFX7)
sctx->last_index_size = -1;
if (GFX_VERSION == GFX10_3 && disable_instance_packing != sctx->disable_instance_packing) {
radeon_set_uconfig_reg_idx(sctx->screen, GFX_VERSION,
R_03090C_VGT_INDEX_TYPE, 2,
radeon_set_uconfig_reg_idx(R_03090C_VGT_INDEX_TYPE, 2,
S_028A7C_DISABLE_INSTANCE_PACKING(disable_instance_packing));
sctx->disable_instance_packing = disable_instance_packing;
}
@ -1497,14 +1495,14 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw
}
} else {
if (set_base_instance) {
radeon_opt_set_sh_reg3(sctx, sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
radeon_opt_set_sh_reg3(sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
tracked_base_vertex_reg, base_vertex, drawid_base,
info->start_instance);
} else if (set_draw_id) {
radeon_opt_set_sh_reg2(sctx, sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
radeon_opt_set_sh_reg2(sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
tracked_base_vertex_reg, base_vertex, drawid_base);
} else {
radeon_opt_set_sh_reg(sctx, sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
radeon_opt_set_sh_reg(sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
tracked_base_vertex_reg, base_vertex);
}
}

2
src/gallium/drivers/radeonsi/si_state_msaa.c
View file

@ -269,7 +269,7 @@ static void si_emit_sample_locations(struct si_context *sctx, unsigned index)
assert(sctx->family >= CHIP_POLARIS10);
radeon_begin(cs);
radeon_opt_set_context_reg(sctx, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
radeon_opt_set_context_reg(R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
S_028830_SMALL_PRIM_FILTER_ENABLE(small_prim_filter_enable) |
/* Small line culling doesn't work on Polaris10-12. */

146
src/gallium/drivers/radeonsi/si_state_shaders.cpp
View file

@ -758,19 +758,19 @@ static void si_emit_shader_es(struct si_context *sctx, unsigned index)
struct si_shader *shader = sctx->queued.named.es;
radeon_begin(&sctx->gfx_cs);
radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
radeon_opt_set_context_reg(R_028AAC_VGT_ESGS_RING_ITEMSIZE,
SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
shader->selector->info.esgs_vertex_stride / 4);
if (shader->selector->stage == MESA_SHADER_TESS_EVAL)
radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
radeon_opt_set_context_reg(R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
shader->vgt_tf_param);
if (shader->vgt_vertex_reuse_block_cntl)
radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
radeon_opt_set_context_reg(R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
shader->vgt_vertex_reuse_block_cntl);
radeon_end_update_context_roll(sctx);
radeon_end_update_context_roll();
}
static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
@ -938,71 +938,71 @@ static void si_emit_shader_gs(struct si_context *sctx, unsigned index)
/* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
* R_028A68_VGT_GSVS_RING_OFFSET_3 */
radeon_opt_set_context_reg3(
sctx, R_028A60_VGT_GSVS_RING_OFFSET_1, SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
R_028A60_VGT_GSVS_RING_OFFSET_1, SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
shader->gs.vgt_gsvs_ring_offset_1, shader->gs.vgt_gsvs_ring_offset_2,
shader->gs.vgt_gsvs_ring_offset_3);
/* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
radeon_opt_set_context_reg(R_028AB0_VGT_GSVS_RING_ITEMSIZE,
SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
shader->gs.vgt_gsvs_ring_itemsize);
/* R_028B38_VGT_GS_MAX_VERT_OUT */
radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
radeon_opt_set_context_reg(R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
shader->gs.vgt_gs_max_vert_out);
/* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
* R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
radeon_opt_set_context_reg4(
sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE, SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
R_028B5C_VGT_GS_VERT_ITEMSIZE, SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
shader->gs.vgt_gs_vert_itemsize, shader->gs.vgt_gs_vert_itemsize_1,
shader->gs.vgt_gs_vert_itemsize_2, shader->gs.vgt_gs_vert_itemsize_3);
/* R_028B90_VGT_GS_INSTANCE_CNT */
radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT,
radeon_opt_set_context_reg(R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT,
shader->gs.vgt_gs_instance_cnt);
if (sctx->gfx_level >= GFX9) {
/* R_028A44_VGT_GS_ONCHIP_CNTL */
radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL,
radeon_opt_set_context_reg(R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL,
shader->gs.vgt_gs_onchip_cntl);
/* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
if (sctx->gfx_level == GFX9) {
radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
radeon_opt_set_context_reg(R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
shader->gs.vgt_gs_max_prims_per_subgroup);
}
if (shader->key.ge.part.gs.es->stage == MESA_SHADER_TESS_EVAL)
radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
radeon_opt_set_context_reg(R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
shader->vgt_tf_param);
if (shader->vgt_vertex_reuse_block_cntl)
radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
radeon_opt_set_context_reg(R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
shader->vgt_vertex_reuse_block_cntl);
}
radeon_end_update_context_roll(sctx);
radeon_end_update_context_roll();
/* These don't cause any context rolls. */
radeon_begin_again(&sctx->gfx_cs);
if (sctx->gfx_level >= GFX7) {
if (sctx->screen->info.uses_kernel_cu_mask) {
radeon_opt_set_sh_reg_idx(sctx, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
radeon_opt_set_sh_reg_idx(R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
3, shader->gs.spi_shader_pgm_rsrc3_gs);
} else {
radeon_opt_set_sh_reg(sctx, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
radeon_opt_set_sh_reg(R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
shader->gs.spi_shader_pgm_rsrc3_gs);
}
}
if (sctx->gfx_level >= GFX10) {
if (sctx->screen->info.uses_kernel_cu_mask) {
radeon_opt_set_sh_reg_idx(sctx, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
radeon_opt_set_sh_reg_idx(R_00B204_SPI_SHADER_PGM_RSRC4_GS,
SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
3, shader->gs.spi_shader_pgm_rsrc4_gs);
} else {
radeon_opt_set_sh_reg(sctx, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
radeon_opt_set_sh_reg(R_00B204_SPI_SHADER_PGM_RSRC4_GS,
SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
shader->gs.spi_shader_pgm_rsrc4_gs);
}
@ -1190,51 +1190,51 @@ static void gfx10_emit_shader_ngg(struct si_context *sctx, unsigned index)
radeon_begin(&sctx->gfx_cs);
if (HAS_TESS) {
radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
radeon_opt_set_context_reg(R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
shader->vgt_tf_param);
}
radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
radeon_opt_set_context_reg(R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
shader->ngg.ge_max_output_per_subgroup);
radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL, SI_TRACKED_GE_NGG_SUBGRP_CNTL,
radeon_opt_set_context_reg(R_028B4C_GE_NGG_SUBGRP_CNTL, SI_TRACKED_GE_NGG_SUBGRP_CNTL,
shader->ngg.ge_ngg_subgrp_cntl);
radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN,
radeon_opt_set_context_reg(R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN,
shader->ngg.vgt_primitiveid_en);
if (sctx->gfx_level < GFX11) {
radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL,
radeon_opt_set_context_reg(R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL,
shader->ngg.vgt_gs_onchip_cntl);
}
radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
radeon_opt_set_context_reg(R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
shader->ngg.vgt_gs_max_vert_out);
radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT,
radeon_opt_set_context_reg(R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT,
shader->ngg.vgt_gs_instance_cnt);
radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG, SI_TRACKED_SPI_VS_OUT_CONFIG,
radeon_opt_set_context_reg(R_0286C4_SPI_VS_OUT_CONFIG, SI_TRACKED_SPI_VS_OUT_CONFIG,
shader->ngg.spi_vs_out_config);
radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
radeon_opt_set_context_reg(R_02870C_SPI_SHADER_POS_FORMAT,
SI_TRACKED_SPI_SHADER_POS_FORMAT,
shader->ngg.spi_shader_pos_format);
radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
radeon_opt_set_context_reg(R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
shader->ngg.pa_cl_vte_cntl);
radeon_end_update_context_roll(sctx);
radeon_end_update_context_roll();
/* These don't cause a context roll. */
radeon_begin_again(&sctx->gfx_cs);
if (sctx->screen->info.uses_kernel_cu_mask) {
radeon_opt_set_sh_reg_idx(sctx, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
radeon_opt_set_sh_reg_idx(R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
3, shader->ngg.spi_shader_pgm_rsrc3_gs);
radeon_opt_set_sh_reg_idx(sctx, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
radeon_opt_set_sh_reg_idx(R_00B204_SPI_SHADER_PGM_RSRC4_GS,
SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
3, shader->ngg.spi_shader_pgm_rsrc4_gs);
} else {
radeon_opt_set_sh_reg(sctx, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
radeon_opt_set_sh_reg(R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
shader->ngg.spi_shader_pgm_rsrc3_gs);
radeon_opt_set_sh_reg(sctx, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
radeon_opt_set_sh_reg(R_00B204_SPI_SHADER_PGM_RSRC4_GS,
SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
shader->ngg.spi_shader_pgm_rsrc4_gs);
}
radeon_opt_set_uconfig_reg(sctx, R_030980_GE_PC_ALLOC, SI_TRACKED_GE_PC_ALLOC,
radeon_opt_set_uconfig_reg(R_030980_GE_PC_ALLOC, SI_TRACKED_GE_PC_ALLOC,
shader->ngg.ge_pc_alloc);
radeon_end();
}
@ -1282,23 +1282,23 @@ static void gfx11_dgpu_emit_shader_ngg(struct si_context *sctx, unsigned index)
shader->gs.spi_shader_pgm_rsrc4_gs);
} else {
if (sctx->screen->info.uses_kernel_cu_mask) {
radeon_opt_set_sh_reg_idx(sctx, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
radeon_opt_set_sh_reg_idx(R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
3, shader->ngg.spi_shader_pgm_rsrc3_gs);
radeon_opt_set_sh_reg_idx(sctx, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
radeon_opt_set_sh_reg_idx(R_00B204_SPI_SHADER_PGM_RSRC4_GS,
SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
3, shader->ngg.spi_shader_pgm_rsrc4_gs);
} else {
radeon_opt_set_sh_reg(sctx, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
radeon_opt_set_sh_reg(R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
shader->ngg.spi_shader_pgm_rsrc3_gs);
radeon_opt_set_sh_reg(sctx, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
radeon_opt_set_sh_reg(R_00B204_SPI_SHADER_PGM_RSRC4_GS,
SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
shader->ngg.spi_shader_pgm_rsrc4_gs);
}
}
radeon_opt_set_uconfig_reg(sctx, R_030980_GE_PC_ALLOC, SI_TRACKED_GE_PC_ALLOC,
radeon_opt_set_uconfig_reg(R_030980_GE_PC_ALLOC, SI_TRACKED_GE_PC_ALLOC,
shader->ngg.ge_pc_alloc);
radeon_end();
}
@ -1332,7 +1332,7 @@ static void gfx12_emit_shader_ngg(struct si_context *sctx, unsigned index)
shader->ngg.pa_cl_vte_cntl);
gfx12_end_context_regs();
radeon_opt_set_uconfig_reg(sctx, R_030988_VGT_PRIMITIVEID_EN,
radeon_opt_set_uconfig_reg(R_030988_VGT_PRIMITIVEID_EN,
SI_TRACKED_VGT_PRIMITIVEID_EN_UCONFIG,
shader->ngg.vgt_primitiveid_en);
radeon_end(); /* don't track context rolls on GFX12 */
@ -1676,50 +1676,50 @@ static void si_emit_shader_vs(struct si_context *sctx, unsigned index)
struct si_shader *shader = sctx->queued.named.vs;
radeon_begin(&sctx->gfx_cs);
radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE, SI_TRACKED_VGT_GS_MODE,
radeon_opt_set_context_reg(R_028A40_VGT_GS_MODE, SI_TRACKED_VGT_GS_MODE,
shader->vs.vgt_gs_mode);
radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN,
radeon_opt_set_context_reg(R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN,
shader->vs.vgt_primitiveid_en);
if (sctx->gfx_level <= GFX8) {
radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF, SI_TRACKED_VGT_REUSE_OFF,
radeon_opt_set_context_reg(R_028AB4_VGT_REUSE_OFF, SI_TRACKED_VGT_REUSE_OFF,
shader->vs.vgt_reuse_off);
}
radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG, SI_TRACKED_SPI_VS_OUT_CONFIG,
radeon_opt_set_context_reg(R_0286C4_SPI_VS_OUT_CONFIG, SI_TRACKED_SPI_VS_OUT_CONFIG,
shader->vs.spi_vs_out_config);
radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
radeon_opt_set_context_reg(R_02870C_SPI_SHADER_POS_FORMAT,
SI_TRACKED_SPI_SHADER_POS_FORMAT,
shader->vs.spi_shader_pos_format);
radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
radeon_opt_set_context_reg(R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
shader->vs.pa_cl_vte_cntl);
if (shader->selector->stage == MESA_SHADER_TESS_EVAL)
radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
radeon_opt_set_context_reg(R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
shader->vgt_tf_param);
if (shader->vgt_vertex_reuse_block_cntl)
radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
radeon_opt_set_context_reg(R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
shader->vgt_vertex_reuse_block_cntl);
/* Required programming for tessellation. (legacy pipeline only) */
if (sctx->gfx_level >= GFX10 && shader->selector->stage == MESA_SHADER_TESS_EVAL) {
radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
radeon_opt_set_context_reg(R_028A44_VGT_GS_ONCHIP_CNTL,
SI_TRACKED_VGT_GS_ONCHIP_CNTL,
S_028A44_ES_VERTS_PER_SUBGRP(250) |
S_028A44_GS_PRIMS_PER_SUBGRP(126) |
S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
}
radeon_end_update_context_roll(sctx);
radeon_end_update_context_roll();
/* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
if (sctx->gfx_level >= GFX10) {
radeon_begin_again(&sctx->gfx_cs);
radeon_opt_set_uconfig_reg(sctx, R_030980_GE_PC_ALLOC, SI_TRACKED_GE_PC_ALLOC,
radeon_opt_set_uconfig_reg(R_030980_GE_PC_ALLOC, SI_TRACKED_GE_PC_ALLOC,
shader->vs.ge_pc_alloc);
radeon_end();
}
@ -1901,19 +1901,19 @@ static void gfx6_emit_shader_ps(struct si_context *sctx, unsigned index)
struct si_shader *shader = sctx->queued.named.ps;
radeon_begin(&sctx->gfx_cs);
radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA, SI_TRACKED_SPI_PS_INPUT_ENA,
radeon_opt_set_context_reg2(R_0286CC_SPI_PS_INPUT_ENA, SI_TRACKED_SPI_PS_INPUT_ENA,
shader->ps.spi_ps_input_ena,
shader->ps.spi_ps_input_addr);
radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL, SI_TRACKED_SPI_BARYC_CNTL,
radeon_opt_set_context_reg(R_0286E0_SPI_BARYC_CNTL, SI_TRACKED_SPI_BARYC_CNTL,
shader->ps.spi_baryc_cntl);
radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL, SI_TRACKED_SPI_PS_IN_CONTROL,
radeon_opt_set_context_reg(R_0286D8_SPI_PS_IN_CONTROL, SI_TRACKED_SPI_PS_IN_CONTROL,
shader->ps.spi_ps_in_control);
radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT, SI_TRACKED_SPI_SHADER_Z_FORMAT,
radeon_opt_set_context_reg2(R_028710_SPI_SHADER_Z_FORMAT, SI_TRACKED_SPI_SHADER_Z_FORMAT,
shader->ps.spi_shader_z_format,
shader->ps.spi_shader_col_format);
radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK, SI_TRACKED_CB_SHADER_MASK,
radeon_opt_set_context_reg(R_02823C_CB_SHADER_MASK, SI_TRACKED_CB_SHADER_MASK,
shader->ps.cb_shader_mask);
radeon_end_update_context_roll(sctx);
radeon_end_update_context_roll();
}
static void gfx11_dgpu_emit_shader_ps(struct si_context *sctx, unsigned index)
@ -4440,7 +4440,7 @@ static void si_emit_vgt_pipeline_state(struct si_context *sctx, unsigned index)
struct radeon_cmdbuf *cs = &sctx->gfx_cs;
radeon_begin(cs);
radeon_opt_set_context_reg(sctx, sctx->gfx_level >= GFX12 ?
radeon_opt_set_context_reg(sctx->gfx_level >= GFX12 ?
R_028A98_VGT_SHADER_STAGES_EN :
R_028B54_VGT_SHADER_STAGES_EN,
SI_TRACKED_VGT_SHADER_STAGES_EN, sctx->vgt_shader_stages_en);
@ -4450,10 +4450,10 @@ static void si_emit_vgt_pipeline_state(struct si_context *sctx, unsigned index)
G_028B54_GS_EN(sctx->vgt_shader_stages_en) &&
!G_028B54_PRIMGEN_EN(sctx->vgt_shader_stages_en); /* !NGG */
radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF, SI_TRACKED_VGT_REUSE_OFF,
radeon_opt_set_context_reg(R_028AB4_VGT_REUSE_OFF, SI_TRACKED_VGT_REUSE_OFF,
S_028AB4_REUSE_OFF(has_legacy_tess_gs));
}
radeon_end_update_context_roll(sctx);
radeon_end_update_context_roll();
if (sctx->gfx_level >= GFX10) {
uint32_t ge_cntl = sctx->ge_cntl;
@ -4464,7 +4464,7 @@ static void si_emit_vgt_pipeline_state(struct si_context *sctx, unsigned index)
}
radeon_begin_again(cs);
radeon_opt_set_uconfig_reg(sctx, R_03096C_GE_CNTL, SI_TRACKED_GE_CNTL, ge_cntl);
radeon_opt_set_uconfig_reg(R_03096C_GE_CNTL, SI_TRACKED_GE_CNTL, ge_cntl);
radeon_end();
}
}
@ -4758,12 +4758,11 @@ static void gfx6_emit_tess_io_layout_state(struct si_context *sctx, unsigned ind
SI_TRACKED_SPI_SHADER_USER_DATA_HS__TCS_OFFCHIP_ADDR,
sctx->tes_offchip_ring_va_sgpr);
} else if (sctx->gfx_level >= GFX9) {
radeon_opt_set_sh_reg(sctx, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
radeon_opt_set_sh_reg(R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
SI_TRACKED_SPI_SHADER_PGM_RSRC2_HS, sctx->ls_hs_rsrc2);
/* Set userdata SGPRs for merged LS-HS. */
radeon_opt_set_sh_reg2(sctx,
R_00B430_SPI_SHADER_USER_DATA_HS_0 +
radeon_opt_set_sh_reg2(R_00B430_SPI_SHADER_USER_DATA_HS_0 +
GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4,
SI_TRACKED_SPI_SHADER_USER_DATA_HS__TCS_OFFCHIP_LAYOUT,
sctx->tcs_offchip_layout, sctx->tes_offchip_ring_va_sgpr);
@ -4777,8 +4776,7 @@ static void gfx6_emit_tess_io_layout_state(struct si_context *sctx, unsigned ind
radeon_emit(sctx->ls_hs_rsrc2);
/* Set userdata SGPRs for TCS. */
radeon_opt_set_sh_reg3(sctx,
R_00B430_SPI_SHADER_USER_DATA_HS_0 +
radeon_opt_set_sh_reg3(R_00B430_SPI_SHADER_USER_DATA_HS_0 +
GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4,
SI_TRACKED_SPI_SHADER_USER_DATA_HS__TCS_OFFCHIP_LAYOUT,
sctx->tcs_offchip_layout, sctx->tes_offchip_ring_va_sgpr,
@ -4803,7 +4801,7 @@ static void gfx6_emit_tess_io_layout_state(struct si_context *sctx, unsigned ind
} else {
bool has_gs = sctx->ngg || sctx->shader.gs.cso;
radeon_opt_set_sh_reg2(sctx, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4,
radeon_opt_set_sh_reg2(tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4,
has_gs ? SI_TRACKED_SPI_SHADER_USER_DATA_ES__BASE_VERTEX
: SI_TRACKED_SPI_SHADER_USER_DATA_VS__BASE_VERTEX,
sctx->tcs_offchip_layout, sctx->tes_offchip_ring_va_sgpr);
@ -4812,13 +4810,13 @@ static void gfx6_emit_tess_io_layout_state(struct si_context *sctx, unsigned ind
radeon_begin_again(cs);
if (sctx->gfx_level >= GFX7) {
radeon_opt_set_context_reg_idx(sctx, R_028B58_VGT_LS_HS_CONFIG,
radeon_opt_set_context_reg_idx(R_028B58_VGT_LS_HS_CONFIG,
SI_TRACKED_VGT_LS_HS_CONFIG, 2, sctx->ls_hs_config);
} else {
radeon_opt_set_context_reg(sctx, R_028B58_VGT_LS_HS_CONFIG,
radeon_opt_set_context_reg(R_028B58_VGT_LS_HS_CONFIG,
SI_TRACKED_VGT_LS_HS_CONFIG, sctx->ls_hs_config);
}
radeon_end_update_context_roll(sctx);
radeon_end_update_context_roll();
}
static void gfx12_emit_tess_io_layout_state(struct si_context *sctx, unsigned index)
@ -4856,7 +4854,7 @@ static void gfx12_emit_tess_io_layout_state(struct si_context *sctx, unsigned in
sctx->tes_offchip_ring_va_sgpr);
radeon_begin(cs);
radeon_opt_set_context_reg_idx(sctx, R_028B58_VGT_LS_HS_CONFIG,
radeon_opt_set_context_reg_idx(R_028B58_VGT_LS_HS_CONFIG,
SI_TRACKED_VGT_LS_HS_CONFIG, 2, sctx->ls_hs_config);
radeon_end(); /* don't track context rolls on GFX12 */
}
@ -4925,14 +4923,14 @@ static void si_emit_spi_map(struct si_context *sctx, unsigned index)
*/
if (sctx->gfx_level >= GFX12) {
radeon_begin(&sctx->gfx_cs);
radeon_opt_set_context_regn(sctx, R_028664_SPI_PS_INPUT_CNTL_0, spi_ps_input_cntl,
radeon_opt_set_context_regn(R_028664_SPI_PS_INPUT_CNTL_0, spi_ps_input_cntl,
sctx->tracked_regs.spi_ps_input_cntl, NUM_INTERP);
radeon_end(); /* don't track context rolls on GFX12 */
} else {
radeon_begin(&sctx->gfx_cs);
radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0, spi_ps_input_cntl,
radeon_opt_set_context_regn(R_028644_SPI_PS_INPUT_CNTL_0, spi_ps_input_cntl,
sctx->tracked_regs.spi_ps_input_cntl, NUM_INTERP);
radeon_end_update_context_roll(sctx);
radeon_end_update_context_roll();
}
}

4
src/gallium/drivers/radeonsi/si_state_streamout.c
View file

@ -350,7 +350,7 @@ static void si_emit_streamout_begin(struct si_context *sctx, unsigned index)
radeon_emit(t[i]->b.buffer_offset >> 2); /* buffer offset in DW */
radeon_emit(0); /* unused */
}
radeon_end_update_context_roll(sctx);
radeon_end_update_context_roll();
}
}
@ -406,7 +406,7 @@ void si_emit_streamout_end(struct si_context *sctx)
* buffer bound. This ensures that the primitives-emitted query
* won't increment. */
radeon_set_context_reg(R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16 * i, 0);
radeon_end_update_context_roll(sctx);
radeon_end_update_context_roll();
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, t[i]->buf_filled_size,
RADEON_USAGE_WRITE | RADEON_PRIO_SO_FILLED_SIZE);

8
src/gallium/drivers/radeonsi/si_state_viewport.c
View file

@ -415,14 +415,14 @@ static void si_emit_guardband(struct si_context *sctx, unsigned index)
radeon_end(); /* don't track context rolls on GFX11 */
} else {
radeon_begin(&sctx->gfx_cs);
radeon_opt_set_context_reg5(sctx, R_028BE4_PA_SU_VTX_CNTL, SI_TRACKED_PA_SU_VTX_CNTL,
radeon_opt_set_context_reg5(R_028BE4_PA_SU_VTX_CNTL, SI_TRACKED_PA_SU_VTX_CNTL,
pa_su_vtx_cntl,
fui(guardband_y), fui(discard_y),
fui(guardband_x), fui(discard_x));
radeon_opt_set_context_reg(sctx, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET,
radeon_opt_set_context_reg(R_028234_PA_SU_HARDWARE_SCREEN_OFFSET,
SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET,
pa_su_hardware_screen_offset);
radeon_end_update_context_roll(sctx);
radeon_end_update_context_roll();
}
}
@ -766,7 +766,7 @@ static void si_emit_window_rectangles(struct si_context *sctx, unsigned index)
radeon_end();
} else {
radeon_begin(cs);
radeon_opt_set_context_reg(sctx, R_02820C_PA_SC_CLIPRECT_RULE, SI_TRACKED_PA_SC_CLIPRECT_RULE,
radeon_opt_set_context_reg(R_02820C_PA_SC_CLIPRECT_RULE, SI_TRACKED_PA_SC_CLIPRECT_RULE,
rule);
if (num_rectangles) {
radeon_set_context_reg_seq(R_028210_PA_SC_CLIPRECT_0_TL, num_rectangles * 2);