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radeonsi: remove the unused cs parameter from radeon_set_(config|context)_reg

Browse source 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13015>
This commit is contained in:
Marek Olšák 2021-09-23 07:17:58 -04:00 • committed by Marge Bot
parent 9f0cd15d6a
commit 8b52fd28c3
9 changed files with 75 additions and 75 deletions
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28
src/gallium/drivers/radeonsi/si_build_pm4.h
View file

@ -73,36 +73,36 @@
__cs_num += __n; \
} while (0)
#define radeon_set_config_reg_seq(cs, reg, num) do { \
#define radeon_set_config_reg_seq(reg, num) do { \
SI_CHECK_SHADOWED_REGS(reg, num); \
assert((reg) < SI_CONTEXT_REG_OFFSET); \
radeon_emit(PKT3(PKT3_SET_CONFIG_REG, num, 0)); \
radeon_emit(((reg) - SI_CONFIG_REG_OFFSET) >> 2); \
} while (0)
#define radeon_set_config_reg(cs, reg, value) do { \
radeon_set_config_reg_seq(cs, reg, 1); \
#define radeon_set_config_reg(reg, value) do { \
radeon_set_config_reg_seq(reg, 1); \
radeon_emit(value); \
} while (0)
#define radeon_set_context_reg_seq(cs, reg, num) do { \
#define radeon_set_context_reg_seq(reg, num) do { \
SI_CHECK_SHADOWED_REGS(reg, num); \
assert((reg) >= SI_CONTEXT_REG_OFFSET); \
radeon_emit(PKT3(PKT3_SET_CONTEXT_REG, num, 0)); \
radeon_emit(((reg) - SI_CONTEXT_REG_OFFSET) >> 2); \
} while (0)
#define radeon_set_context_reg(cs, reg, value) do { \
radeon_set_context_reg_seq(cs, reg, 1); \
#define radeon_set_context_reg(reg, value) do { \
radeon_set_context_reg_seq(reg, 1); \
radeon_emit(value); \
} while (0)
#define radeon_set_context_reg_seq_array(cs, reg, num, values) do { \
radeon_set_context_reg_seq(cs, reg, num); \
#define radeon_set_context_reg_seq_array(reg, num, values) do { \
radeon_set_context_reg_seq(reg, num); \
radeon_emit_array(values, num); \
} while (0)
#define radeon_set_context_reg_idx(cs, reg, idx, value) do { \
#define radeon_set_context_reg_idx(reg, idx, value) do { \
SI_CHECK_SHADOWED_REGS(reg, 1); \
assert((reg) >= SI_CONTEXT_REG_OFFSET); \
radeon_emit(PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); \
@ -179,7 +179,7 @@
unsigned __value = val; \
if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x1) != 0x1 || \
sctx->tracked_regs.reg_value[reg] != __value) { \
radeon_set_context_reg(cs, offset, __value); \
radeon_set_context_reg(offset, __value); \
sctx->tracked_regs.reg_saved |= 0x1ull << (reg); \
sctx->tracked_regs.reg_value[reg] = __value; \
} \
@ -196,7 +196,7 @@
if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x3) != 0x3 || \
sctx->tracked_regs.reg_value[reg] != __value1 || \
sctx->tracked_regs.reg_value[(reg) + 1] != __value2) { \
radeon_set_context_reg_seq(cs, offset, 2); \
radeon_set_context_reg_seq(offset, 2); \
radeon_emit(__value1); \
radeon_emit(__value2); \
sctx->tracked_regs.reg_value[reg] = __value1; \
@ -214,7 +214,7 @@
sctx->tracked_regs.reg_value[reg] != __value1 || \
sctx->tracked_regs.reg_value[(reg) + 1] != __value2 || \
sctx->tracked_regs.reg_value[(reg) + 2] != __value3) { \
radeon_set_context_reg_seq(cs, offset, 3); \
radeon_set_context_reg_seq(offset, 3); \
radeon_emit(__value1); \
radeon_emit(__value2); \
radeon_emit(__value3); \
@ -235,7 +235,7 @@
sctx->tracked_regs.reg_value[(reg) + 1] != __value2 || \
sctx->tracked_regs.reg_value[(reg) + 2] != __value3 || \
sctx->tracked_regs.reg_value[(reg) + 3] != __value4) { \
radeon_set_context_reg_seq(cs, offset, 4); \
radeon_set_context_reg_seq(offset, 4); \
radeon_emit(__value1); \
radeon_emit(__value2); \
radeon_emit(__value3); \
@ -253,7 +253,7 @@
*/
#define radeon_opt_set_context_regn(sctx, offset, value, saved_val, num) do { \
if (memcmp(value, saved_val, sizeof(uint32_t) * (num))) { \
radeon_set_context_reg_seq(&(sctx)->gfx_cs, offset, num); \
radeon_set_context_reg_seq(offset, num); \
radeon_emit_array(value, num); \
memcpy(saved_val, value, sizeof(uint32_t) * (num)); \
} \

2
src/gallium/drivers/radeonsi/si_compute.c
View file

@ -389,7 +389,7 @@ void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf
if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed) {
uint64_t bc_va = sctx->border_color_buffer->gpu_address;
radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8);
radeon_set_config_reg(R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8);
}
}

2
src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c
View file

@ -142,7 +142,7 @@ static void si_set_context_reg_array(struct radeon_cmdbuf *cs, unsigned reg, uns
const uint32_t *values)
{
radeon_begin(cs);
radeon_set_context_reg_seq(cs, reg, num);
radeon_set_context_reg_seq(reg, num);
radeon_emit_array(values, num);
radeon_end();
}

62
src/gallium/drivers/radeonsi/si_state.c
View file

@ -763,7 +763,7 @@ static void si_emit_blend_color(struct si_context *sctx)
struct radeon_cmdbuf *cs = &sctx->gfx_cs;
radeon_begin(cs);
radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
radeon_set_context_reg_seq(R_028414_CB_BLEND_RED, 4);
radeon_emit_array((uint32_t *)sctx->blend_color.color, 4);
radeon_end();
}
@ -797,7 +797,7 @@ static void si_emit_clip_state(struct si_context *sctx)
struct radeon_cmdbuf *cs = &sctx->gfx_cs;
radeon_begin(cs);
radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6 * 4);
radeon_set_context_reg_seq(R_0285BC_PA_CL_UCP_0_X, 6 * 4);
radeon_emit_array((uint32_t *)sctx->clip_state.ucp, 6 * 4);
radeon_end();
}
@ -1164,7 +1164,7 @@ static void si_emit_stencil_ref(struct si_context *sctx)
struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
radeon_begin(cs);
radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
radeon_set_context_reg_seq(R_028430_DB_STENCILREFMASK, 2);
radeon_emit(S_028430_STENCILTESTVAL(ref->ref_value[0]) |
S_028430_STENCILMASK(dsa->valuemask[0]) |
S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
@ -3042,7 +3042,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
cb = (struct si_surface *)state->cbufs[i];
if (!cb) {
radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
radeon_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C,
S_028C70_FORMAT(V_028C70_COLOR_INVALID));
continue;
}
@ -3121,7 +3121,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
S_028EE0_CMASK_PIPE_ALIGNED(1) |
S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.color.dcc.pipe_aligned);
radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 14);
radeon_set_context_reg_seq(R_028C60_CB_COLOR0_BASE + i * 0x3C, 14);
radeon_emit(cb_color_base); /* CB_COLOR0_BASE */
radeon_emit(0); /* hole */
radeon_emit(0); /* hole */
@ -3137,14 +3137,14 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
radeon_emit(tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
radeon_emit(cb_dcc_base); /* CB_COLOR0_DCC_BASE */
radeon_set_context_reg(cs, R_028E40_CB_COLOR0_BASE_EXT + i * 4, cb_color_base >> 32);
radeon_set_context_reg(cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + i * 4,
radeon_set_context_reg(R_028E40_CB_COLOR0_BASE_EXT + i * 4, cb_color_base >> 32);
radeon_set_context_reg(R_028E60_CB_COLOR0_CMASK_BASE_EXT + i * 4,
cb_color_cmask >> 32);
radeon_set_context_reg(cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + i * 4,
radeon_set_context_reg(R_028E80_CB_COLOR0_FMASK_BASE_EXT + i * 4,
cb_color_fmask >> 32);
radeon_set_context_reg(cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4, cb_dcc_base >> 32);
radeon_set_context_reg(cs, R_028EC0_CB_COLOR0_ATTRIB2 + i * 4, cb->cb_color_attrib2);
radeon_set_context_reg(cs, R_028EE0_CB_COLOR0_ATTRIB3 + i * 4, cb_color_attrib3);
radeon_set_context_reg(R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4, cb_dcc_base >> 32);
radeon_set_context_reg(R_028EC0_CB_COLOR0_ATTRIB2 + i * 4, cb->cb_color_attrib2);
radeon_set_context_reg(R_028EE0_CB_COLOR0_ATTRIB3 + i * 4, cb_color_attrib3);
} else if (sctx->chip_class == GFX9) {
struct gfx9_surf_meta_flags meta = {
.rb_aligned = 1,
@ -3166,7 +3166,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
S_028C74_RB_ALIGNED(meta.rb_aligned) |
S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
radeon_set_context_reg_seq(R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
radeon_emit(cb_color_base); /* CB_COLOR0_BASE */
radeon_emit(S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
radeon_emit(cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
@ -3183,7 +3183,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
radeon_emit(cb_dcc_base); /* CB_COLOR0_DCC_BASE */
radeon_emit(S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
radeon_set_context_reg(R_0287A0_CB_MRT0_EPITCH + i * 4,
S_0287A0_EPITCH(tex->surface.u.gfx9.epitch));
} else {
/* Compute mutable surface parameters (GFX6-GFX8). */
@ -3227,7 +3227,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
}
radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
radeon_set_context_reg_seq(R_028C60_CB_COLOR0_BASE + i * 0x3C,
sctx->chip_class >= GFX8 ? 14 : 13);
radeon_emit(cb_color_base); /* CB_COLOR0_BASE */
radeon_emit(cb_color_pitch); /* CB_COLOR0_PITCH */
@ -3249,7 +3249,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
}
for (; i < 8; i++)
if (sctx->framebuffer.dirty_cbufs & (1 << i))
radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
radeon_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
/* ZS buffer. */
if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
@ -3285,10 +3285,10 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
unsigned level = zb->base.u.tex.level;
if (sctx->chip_class >= GFX10) {
radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
radeon_set_context_reg(cs, R_02801C_DB_DEPTH_SIZE_XY, zb->db_depth_size);
radeon_set_context_reg(R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
radeon_set_context_reg(R_02801C_DB_DEPTH_SIZE_XY, zb->db_depth_size);
radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 7);
radeon_set_context_reg_seq(R_02803C_DB_DEPTH_INFO, 7);
radeon_emit(S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
radeon_emit(db_z_info | /* DB_Z_INFO */
S_028038_ZRANGE_PRECISION(tex->depth_clear_value[level] != 0));
@ -3298,19 +3298,19 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
radeon_emit(zb->db_depth_base); /* DB_Z_WRITE_BASE */
radeon_emit(zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
radeon_set_context_reg_seq(cs, R_028068_DB_Z_READ_BASE_HI, 5);
radeon_set_context_reg_seq(R_028068_DB_Z_READ_BASE_HI, 5);
radeon_emit(zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
radeon_emit(zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
radeon_emit(zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
radeon_emit(zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
radeon_emit(zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
} else if (sctx->chip_class == GFX9) {
radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
radeon_set_context_reg_seq(R_028014_DB_HTILE_DATA_BASE, 3);
radeon_emit(zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
radeon_emit(S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
radeon_emit(zb->db_depth_size); /* DB_DEPTH_SIZE */
radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
radeon_set_context_reg_seq(R_028038_DB_Z_INFO, 10);
radeon_emit(db_z_info | /* DB_Z_INFO */
S_028038_ZRANGE_PRECISION(tex->depth_clear_value[level] != 0));
radeon_emit(db_stencil_info); /* DB_STENCIL_INFO */
@ -3323,7 +3323,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
radeon_emit(zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
radeon_emit(S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
radeon_set_context_reg_seq(R_028068_DB_Z_INFO2, 2);
radeon_emit(zb->db_z_info2); /* DB_Z_INFO2 */
radeon_emit(zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
} else {
@ -3343,9 +3343,9 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
}
}
radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
radeon_set_context_reg(R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
radeon_set_context_reg_seq(R_02803C_DB_DEPTH_INFO, 9);
radeon_emit(zb->db_depth_info | /* DB_DEPTH_INFO */
S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile));
radeon_emit(db_z_info | /* DB_Z_INFO */
@ -3359,17 +3359,17 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
radeon_emit(zb->db_depth_slice); /* DB_DEPTH_SLICE */
}
radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
radeon_set_context_reg_seq(R_028028_DB_STENCIL_CLEAR, 2);
radeon_emit(tex->stencil_clear_value[level]); /* R_028028_DB_STENCIL_CLEAR */
radeon_emit(fui(tex->depth_clear_value[level])); /* R_02802C_DB_DEPTH_CLEAR */
radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, db_htile_surface);
radeon_set_context_reg(R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
radeon_set_context_reg(R_028ABC_DB_HTILE_SURFACE, db_htile_surface);
} else if (sctx->framebuffer.dirty_zsbuf) {
if (sctx->chip_class == GFX9)
radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
radeon_set_context_reg_seq(R_028038_DB_Z_INFO, 2);
else
radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
radeon_set_context_reg_seq(R_028040_DB_Z_INFO, 2);
radeon_emit(S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
radeon_emit(S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
@ -3377,7 +3377,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
/* Framebuffer dimensions. */
/* PA_SC_WINDOW_SCISSOR_TL is set in si_init_cs_preamble_state */
radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
radeon_set_context_reg(R_028208_PA_SC_WINDOW_SCISSOR_BR,
S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
if (sctx->screen->dpbb_allowed) {
@ -4625,7 +4625,7 @@ static void si_emit_sample_mask(struct si_context *sctx)
(mask & 1 && sctx->blitter_running));
radeon_begin(cs);
radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
radeon_set_context_reg_seq(R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
radeon_emit(mask | (mask << 16));
radeon_emit(mask | (mask << 16));
radeon_end();

18
src/gallium/drivers/radeonsi/si_state_draw.cpp
View file

@ -759,9 +759,9 @@ static void si_emit_derived_tess_state(struct si_context *sctx, unsigned *num_pa
if (sctx->last_ls_hs_config != ls_hs_config) {
radeon_begin(cs);
if (sctx->chip_class >= GFX7) {
radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
radeon_set_context_reg_idx(R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
} else {
radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
radeon_set_context_reg(R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
}
radeon_end_update_context_roll(sctx);
sctx->last_ls_hs_config = ls_hs_config;
@ -1061,7 +1061,7 @@ static void si_emit_rasterizer_prim_state(struct si_context *sctx)
unsigned gs_out_prim = si_conv_prim_to_gs_out(rast_prim);
if (unlikely(gs_out_prim != sctx->last_gs_out_prim && (NGG || HAS_GS))) {
radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
radeon_set_context_reg(R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
sctx->last_gs_out_prim = gs_out_prim;
}
@ -1164,9 +1164,9 @@ static void si_emit_ia_multi_vgt_param(struct si_context *sctx,
radeon_set_uconfig_reg_idx(cs, sctx->screen, GFX_VERSION,
R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
else if (GFX_VERSION >= GFX7)
radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
radeon_set_context_reg_idx(R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
else
radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
radeon_set_context_reg(R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
radeon_end();
@ -1249,7 +1249,7 @@ static void si_emit_draw_registers(struct si_context *sctx,
else if (GFX_VERSION >= GFX7)
radeon_set_uconfig_reg_idx(cs, sctx->screen, GFX_VERSION, R_030908_VGT_PRIMITIVE_TYPE, 1, vgt_prim);
else
radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, vgt_prim);
radeon_set_config_reg(R_008958_VGT_PRIMITIVE_TYPE, vgt_prim);
sctx->last_prim = prim;
}
@ -1259,12 +1259,12 @@ static void si_emit_draw_registers(struct si_context *sctx,
if (GFX_VERSION >= GFX9)
radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN, primitive_restart);
else
radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, primitive_restart);
radeon_set_context_reg(R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, primitive_restart);
sctx->last_primitive_restart_en = primitive_restart;
}
if (si_prim_restart_index_changed(sctx, primitive_restart, restart_index)) {
radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, restart_index);
radeon_set_context_reg(R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, restart_index);
sctx->last_restart_index = restart_index;
if (GFX_VERSION == GFX9)
sctx->context_roll = true;
@ -1306,7 +1306,7 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw
struct si_streamout_target *t = (struct si_streamout_target *)indirect->count_from_stream_output;
radeon_begin(cs);
radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
radeon_set_context_reg(R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
radeon_end();
si_cp_copy_data(sctx, &sctx->gfx_cs, COPY_DATA_REG, NULL,

14
src/gallium/drivers/radeonsi/si_state_msaa.c
View file

@ -151,13 +151,13 @@ static void si_emit_max_4_sample_locs(struct radeon_cmdbuf *cs, uint64_t centroi
uint32_t sample_locs)
{
radeon_begin(cs);
radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
radeon_set_context_reg_seq(R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
radeon_emit(centroid_priority);
radeon_emit(centroid_priority >> 32);
radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs);
radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs);
radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs);
radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs);
radeon_set_context_reg(R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs);
radeon_set_context_reg(R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs);
radeon_set_context_reg(R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs);
radeon_set_context_reg(R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs);
radeon_end();
}
@ -165,10 +165,10 @@ static void si_emit_max_16_sample_locs(struct radeon_cmdbuf *cs, uint64_t centro
const uint32_t *sample_locs, unsigned num_samples)
{
radeon_begin(cs);
radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
radeon_set_context_reg_seq(R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
radeon_emit(centroid_priority);
radeon_emit(centroid_priority >> 32);
radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0,
radeon_set_context_reg_seq(R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0,
num_samples == 8 ? 14 : 16);
radeon_emit_array(sample_locs, 4);
radeon_emit_array(sample_locs, 4);

2
src/gallium/drivers/radeonsi/si_state_shaders.c
View file

@ -4021,7 +4021,7 @@ static void si_emit_scratch_state(struct si_context *sctx)
struct radeon_cmdbuf *cs = &sctx->gfx_cs;
radeon_begin(cs);
radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE, sctx->spi_tmpring_size);
radeon_set_context_reg(R_0286E8_SPI_TMPRING_SIZE, sctx->spi_tmpring_size);
radeon_end();
if (sctx->scratch_buffer) {

8
src/gallium/drivers/radeonsi/si_state_streamout.c
View file

@ -287,7 +287,7 @@ static void si_flush_vgt_streamout(struct si_context *sctx)
radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
} else {
reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
radeon_set_config_reg(cs, reg_strmout_cntl, 0);
radeon_set_config_reg(reg_strmout_cntl, 0);
}
radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0));
@ -323,7 +323,7 @@ static void si_emit_streamout_begin(struct si_context *sctx)
/* AMD GCN binds streamout buffers as shader resources.
* VGT only counts primitives and tells the shader
* through SGPRs what to do. */
radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16 * i, 2);
radeon_set_context_reg_seq(R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16 * i, 2);
radeon_emit((t[i]->b.buffer_offset + t[i]->b.buffer_size) >> 2); /* BUFFER_SIZE (in DW) */
radeon_emit(stride_in_dw[i]); /* VTX_STRIDE (in DW) */
@ -393,7 +393,7 @@ void si_emit_streamout_end(struct si_context *sctx)
* primitives emitted) may be enabled even if there is not
* buffer bound. This ensures that the primitives-emitted query
* won't increment. */
radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16 * i, 0);
radeon_set_context_reg(R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16 * i, 0);
t[i]->buf_filled_size_valid = true;
}
@ -414,7 +414,7 @@ static void si_emit_streamout_enable(struct si_context *sctx)
assert(!sctx->screen->use_ngg_streamout);
radeon_begin(&sctx->gfx_cs);
radeon_set_context_reg_seq(&sctx->gfx_cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
radeon_set_context_reg_seq(R_028B94_VGT_STRMOUT_CONFIG, 2);
radeon_emit(S_028B94_STREAMOUT_0_EN(si_get_strmout_en(sctx)) |
S_028B94_RAST_STREAM(0) |
S_028B94_STREAMOUT_1_EN(si_get_strmout_en(sctx)) |

14
src/gallium/drivers/radeonsi/si_state_viewport.c
View file

@ -382,7 +382,7 @@ static void si_emit_scissors(struct si_context *ctx)
struct si_signed_scissor *vp = &ctx->viewports.as_scissor[0];
radeon_begin(cs);
radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
radeon_set_context_reg_seq(R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
radeon_end();
si_emit_one_scissor(ctx, cs, vp, scissor_enabled ? &states[0] : NULL);
@ -393,7 +393,7 @@ static void si_emit_scissors(struct si_context *ctx)
* This is a hardware requirement.
*/
radeon_begin(cs);
radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, SI_MAX_VIEWPORTS * 2);
radeon_set_context_reg_seq(R_028250_PA_SC_VPORT_SCISSOR_0_TL, SI_MAX_VIEWPORTS * 2);
radeon_end();
for (unsigned i = 0; i < SI_MAX_VIEWPORTS; i++) {
@ -506,7 +506,7 @@ static void si_emit_viewports(struct si_context *ctx)
/* The simple case: Only 1 viewport is active. */
if (!ctx->vs_writes_viewport_index) {
radeon_begin(cs);
radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
radeon_set_context_reg_seq(R_02843C_PA_CL_VPORT_XSCALE, 6);
radeon_end();
si_emit_one_viewport(ctx, &states[0]);
@ -517,7 +517,7 @@ static void si_emit_viewports(struct si_context *ctx)
* This is a hardware requirement.
*/
radeon_begin(cs);
radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE + 0, SI_MAX_VIEWPORTS * 6);
radeon_set_context_reg_seq(R_02843C_PA_CL_VPORT_XSCALE + 0, SI_MAX_VIEWPORTS * 6);
radeon_end();
for (unsigned i = 0; i < SI_MAX_VIEWPORTS; i++)
@ -548,7 +548,7 @@ static void si_emit_depth_ranges(struct si_context *ctx)
si_viewport_zmin_zmax(&states[0], clip_halfz, window_space, &zmin, &zmax);
radeon_begin(cs);
radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
radeon_set_context_reg_seq(R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
radeon_emit(fui(zmin));
radeon_emit(fui(zmax));
radeon_end();
@ -559,7 +559,7 @@ static void si_emit_depth_ranges(struct si_context *ctx)
* This is a hardware requirement.
*/
radeon_begin(cs);
radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0, SI_MAX_VIEWPORTS * 2);
radeon_set_context_reg_seq(R_0282D0_PA_SC_VPORT_ZMIN_0, SI_MAX_VIEWPORTS * 2);
for (unsigned i = 0; i < SI_MAX_VIEWPORTS; i++) {
si_viewport_zmin_zmax(&states[i], clip_halfz, window_space, &zmin, &zmax);
radeon_emit(fui(zmin));
@ -662,7 +662,7 @@ static void si_emit_window_rectangles(struct si_context *sctx)
return;
}
radeon_set_context_reg_seq(cs, R_028210_PA_SC_CLIPRECT_0_TL, num_rectangles * 2);
radeon_set_context_reg_seq(R_028210_PA_SC_CLIPRECT_0_TL, num_rectangles * 2);
for (unsigned i = 0; i < num_rectangles; i++) {
radeon_emit(S_028210_TL_X(rects[i].minx) | S_028210_TL_Y(rects[i].miny));
radeon_emit(S_028214_BR_X(rects[i].maxx) | S_028214_BR_Y(rects[i].maxy));