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freedreno/a3xx/compiler: fix CMP

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The 1st src to add.s needs (r) flag (repeat), otherwise it will end up:

  add.s dst.xyzw, tmp.xxxx -1

instead of:

  add.s dst.xyzw, tmp.xyzw, -1

Also, if we are using a temporary dst to avoid clobbering one of the src
registers, we actually need to use that as the dst for the sel
instruction.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
Rob Clark 2013-08-20 13:46:30 -04:00
parent 528bee59fe
commit 8b250bb8aa
1 changed files with 2 additions and 2 deletions
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4
src/gallium/drivers/freedreno/a3xx/fd3_compiler.c
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@ -790,13 +790,13 @@ trans_cmp(const struct instr_translater *t,
instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_S);
instr->repeat = 3;
add_dst_reg(ctx, instr, &tmp_dst, 0);
add_src_reg(ctx, instr, &tmp_src, 0);
add_src_reg(ctx, instr, &tmp_src, 0)->flags |= IR3_REG_R;
ir3_reg_create(instr, 0, IR3_REG_IMMED)->iim_val = -1;
/* sel.{f32,f16} dst, src2, tmp, src1 */
instr = ir3_instr_create(ctx->ir, 3, ctx->so->half_precision ?
OPC_SEL_F16 : OPC_SEL_F32);
vectorize(ctx, instr, &inst->Dst[0].Register, 3,
vectorize(ctx, instr, dst, 3,
&inst->Src[2].Register, 0,
&tmp_src, 0,
&inst->Src[1].Register, 0);