radeonsi: optionally run the LLVM IR verifier pass

This is enabled automatically if shader printing is enabled, or separately
by R600_DEBUG=checkir. Catch mal-formed IR before it crashes in a later
pass.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Nicolai Hähnle 2016-09-28 21:44:55 +02:00
parent 1e9476e8c5
commit 8b1f9fd3b3
5 changed files with 38 additions and 9 deletions

View file

@ -622,6 +622,7 @@ static const struct debug_named_value common_debug_options[] = {
{ "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
{ "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
{ "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
{ "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
{ "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
@ -1266,6 +1267,12 @@ bool r600_can_dump_shader(struct r600_common_screen *rscreen,
}
}
bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
{
return (rscreen->debug_flags & DBG_CHECK_IR) ||
r600_can_dump_shader(rscreen, processor);
}
void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
uint64_t offset, uint64_t size, unsigned value,
enum r600_coherency coher)

View file

@ -78,6 +78,7 @@
#define DBG_NO_TGSI (1 << 13)
#define DBG_NO_ASM (1 << 14)
#define DBG_PREOPT_IR (1 << 15)
#define DBG_CHECK_IR (1 << 16)
/* gaps */
#define DBG_TEST_DMA (1 << 20)
/* Bits 21-31 are reserved for the r600g driver. */
@ -716,6 +717,8 @@ bool r600_common_context_init(struct r600_common_context *rctx,
void r600_common_context_cleanup(struct r600_common_context *rctx);
bool r600_can_dump_shader(struct r600_common_screen *rscreen,
unsigned processor);
bool r600_extra_shader_checks(struct r600_common_screen *rscreen,
unsigned processor);
void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
uint64_t offset, uint64_t size, unsigned value,
enum r600_coherency coher);

View file

@ -128,7 +128,8 @@ void radeon_llvm_dispose(struct radeon_llvm_context *ctx);
unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan);
void radeon_llvm_finalize_module(struct radeon_llvm_context *ctx);
void radeon_llvm_finalize_module(struct radeon_llvm_context *ctx,
bool run_verifier);
void build_tgsi_intrinsic_nomem(const struct lp_build_tgsi_action *action,
struct lp_build_tgsi_context *bld_base,

View file

@ -2114,7 +2114,8 @@ void radeon_llvm_create_func(struct radeon_llvm_context *ctx,
LLVMPositionBuilderAtEnd(ctx->gallivm.builder, main_fn_body);
}
void radeon_llvm_finalize_module(struct radeon_llvm_context *ctx)
void radeon_llvm_finalize_module(struct radeon_llvm_context *ctx,
bool run_verifier)
{
struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
const char *triple = LLVMGetTarget(gallivm->module);
@ -2127,6 +2128,9 @@ void radeon_llvm_finalize_module(struct radeon_llvm_context *ctx)
target_library_info = gallivm_create_target_library_info(triple);
LLVMAddTargetLibraryInfo(target_library_info, gallivm->passmgr);
if (run_verifier)
LLVMAddVerifierPass(gallivm->passmgr);
/* This pass should eliminate all the load and store instructions */
LLVMAddPromoteMemoryToRegisterPass(gallivm->passmgr);

View file

@ -6345,7 +6345,9 @@ static int si_generate_gs_copy_shader(struct si_screen *sscreen,
r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
LLVMDumpModule(bld_base->base.gallivm->module);
radeon_llvm_finalize_module(&ctx->radeon_bld);
radeon_llvm_finalize_module(
&ctx->radeon_bld,
r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_GEOMETRY));
r = si_compile_llvm(sscreen, &ctx->shader->binary,
&ctx->shader->config, ctx->tm,
@ -6629,7 +6631,9 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
r600_can_dump_shader(&sscreen->b, ctx.type))
LLVMDumpModule(mod);
radeon_llvm_finalize_module(&ctx.radeon_bld);
radeon_llvm_finalize_module(
&ctx.radeon_bld,
r600_extra_shader_checks(&sscreen->b, ctx.type));
r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
mod, debug, ctx.type, "TGSI shader");
@ -6890,7 +6894,9 @@ static bool si_compile_vs_prolog(struct si_screen *sscreen,
/* Compile. */
si_llvm_build_ret(&ctx, ret);
radeon_llvm_finalize_module(&ctx.radeon_bld);
radeon_llvm_finalize_module(
&ctx.radeon_bld,
r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_VERTEX));
if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
gallivm->module, debug, ctx.type,
@ -6962,7 +6968,9 @@ static bool si_compile_vs_epilog(struct si_screen *sscreen,
/* Compile. */
LLVMBuildRetVoid(gallivm->builder);
radeon_llvm_finalize_module(&ctx.radeon_bld);
radeon_llvm_finalize_module(
&ctx.radeon_bld,
r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_VERTEX));
if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
gallivm->module, debug, ctx.type,
@ -7115,7 +7123,9 @@ static bool si_compile_tcs_epilog(struct si_screen *sscreen,
/* Compile. */
LLVMBuildRetVoid(gallivm->builder);
radeon_llvm_finalize_module(&ctx.radeon_bld);
radeon_llvm_finalize_module(
&ctx.radeon_bld,
r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_TESS_CTRL));
if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
gallivm->module, debug, ctx.type,
@ -7399,7 +7409,9 @@ static bool si_compile_ps_prolog(struct si_screen *sscreen,
/* Compile. */
si_llvm_build_ret(&ctx, ret);
radeon_llvm_finalize_module(&ctx.radeon_bld);
radeon_llvm_finalize_module(
&ctx.radeon_bld,
r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_FRAGMENT));
if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
gallivm->module, debug, ctx.type,
@ -7519,7 +7531,9 @@ static bool si_compile_ps_epilog(struct si_screen *sscreen,
/* Compile. */
LLVMBuildRetVoid(gallivm->builder);
radeon_llvm_finalize_module(&ctx.radeon_bld);
radeon_llvm_finalize_module(
&ctx.radeon_bld,
r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_FRAGMENT));
if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
gallivm->module, debug, ctx.type,