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intel/brw: Update DPAS validation tests for Xe2
The main change is that in Xe2 DPAS instruction requires SIMD16. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31299>
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1 changed files with 16 additions and 1 deletions
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@ -2973,6 +2973,9 @@ TEST_P(validation_test, dpas_sdepth)
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BRW_SYSTOLIC_DEPTH_8,
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};
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brw_set_default_exec_size(p, devinfo.ver >= 20 ? BRW_EXECUTE_16
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: BRW_EXECUTE_8);
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for (unsigned i = 0; i < ARRAY_SIZE(depth); i++) {
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brw_DPAS(p,
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depth[i],
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@ -3005,6 +3008,9 @@ TEST_P(validation_test, dpas_exec_size)
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BRW_EXECUTE_32,
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};
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const brw_execution_size valid_exec_size =
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devinfo.ver >= 20 ? BRW_EXECUTE_16 : BRW_EXECUTE_8;
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for (unsigned i = 0; i < ARRAY_SIZE(test_vectors); i++) {
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brw_set_default_exec_size(p, test_vectors[i]);
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@ -3016,7 +3022,7 @@ TEST_P(validation_test, dpas_exec_size)
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retype(brw_vec8_grf(16, 0), BRW_TYPE_HF),
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retype(brw_vec8_grf(32, 0), BRW_TYPE_HF));
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const bool expected_result = test_vectors[i] == BRW_EXECUTE_8;
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const bool expected_result = test_vectors[i] == valid_exec_size;
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EXPECT_EQ(expected_result, validate(p)) <<
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"Exec size = " << (1u << test_vectors[i]);
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@ -3128,6 +3134,9 @@ TEST_P(validation_test, dpas_sub_byte_precision)
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},
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};
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brw_set_default_exec_size(p, devinfo.ver >= 20 ? BRW_EXECUTE_16
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: BRW_EXECUTE_8);
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for (unsigned i = 0; i < ARRAY_SIZE(test_vectors); i++) {
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brw_inst *inst =
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brw_DPAS(p,
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@ -3220,6 +3229,9 @@ TEST_P(validation_test, dpas_types)
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#undef TV
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brw_set_default_exec_size(p, devinfo.ver >= 20 ? BRW_EXECUTE_16
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: BRW_EXECUTE_8);
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for (unsigned i = 0; i < ARRAY_SIZE(test_vectors); i++) {
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brw_DPAS(p,
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BRW_SYSTOLIC_DEPTH_8,
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@ -3321,6 +3333,9 @@ TEST_P(validation_test, dpas_src_subreg_nr)
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#undef TV
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brw_set_default_exec_size(p, devinfo.ver >= 20 ? BRW_EXECUTE_16
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: BRW_EXECUTE_8);
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for (unsigned i = 0; i < ARRAY_SIZE(test_vectors); i++) {
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struct brw_reg dst =
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retype(brw_vec8_grf( 0, 0), test_vectors[i].dst_type);
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