fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-25 10:50:10 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

anv: Move Wa_1806527549 and enable by default

Browse source 
Move Wa_1806527549 into `init_render_queue_state` and
set HIZ_CHICKEN (7018h) bit = 1 by default.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6717
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17778>
This commit is contained in:
Mykhailo Skorokhodov 2022-08-01 19:06:23 +03:00
parent 6498328210
commit 8b13acd715
2 changed files with 11 additions and 9 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -6019,15 +6019,6 @@ genX(cmd_buffer_emit_gfx12_depth_wa)(struct anv_cmd_buffer *cmd_buffer,
reg.HIZPlaneOptimizationdisablebitMask = true;
}
/* Wa_1806527549
*
* Set HIZ_CHICKEN (7018h) bit 13 = 1 when depth buffer is D16_UNORM.
*/
anv_batch_write_reg(&cmd_buffer->batch, GENX(HIZ_CHICKEN), reg) {
reg.HZDepthTestLEGEOptimizationDisable = fmt_is_d16;
reg.HZDepthTestLEGEOptimizationDisableMask = true;
}
cmd_buffer->state.depth_reg_mode =
fmt_is_d16 ? ANV_DEPTH_REG_MODE_D16 : ANV_DEPTH_REG_MODE_HW_DEFAULT;
#endif

11
src/intel/vulkan/genX_state.c
View file

@ -339,6 +339,17 @@ init_render_queue_state(struct anv_queue *queue)
#endif
}
#if GFX_VERx10 == 120
/* Wa_1806527549 says to disable the following HiZ optimization when the
* depth buffer is D16_UNORM. We've found the WA to help with more depth
* buffer configurations however, so we always disable it just to be safe.
*/
anv_batch_write_reg(&batch, GENX(HIZ_CHICKEN), reg) {
reg.HZDepthTestLEGEOptimizationDisable = true;
reg.HZDepthTestLEGEOptimizationDisableMask = true;
}
#endif
#if GFX_VERx10 < 125
#define AA_LINE_QUALITY_REG GENX(3D_CHICKEN3)
#else