mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-05 13:58:04 +02:00
Port EmitPixelShader from cmdbuf.c to SetupPixelShader in state.c.
This commit is contained in:
parent
e9acd0ca5f
commit
8ad31013b2
4 changed files with 92 additions and 64 deletions
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@ -356,6 +356,8 @@ void r300InitCmdBuf(r300ContextPtr r300)
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ALLOC_STATE( fp, always, R300_FP_CMDSIZE, "fp", 0 );
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r300->hw.fp.cmd[R300_FP_CMD_0] = cmducs(R300_PFS_CNTL_0, 3);
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r300->hw.fp.cmd[R300_FP_CMD_1] = cmducs(R300_PFS_NODE_0, 4);
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ALLOC_STATE( fpt, variable, R300_FPT_CMDSIZE, "fpt", 0 );
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r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmducs(R300_PFS_TEXI_0, 0);
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ALLOC_STATE( unk46A4, always, 6, "unk46A4", 0 );
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r300->hw.unk46A4.cmd[0] = cmducs(0x46A4, 5);
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ALLOC_STATE( fpi[0], variable, R300_FPI_CMDSIZE, "fpi/0", 0 );
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@ -374,6 +376,8 @@ void r300InitCmdBuf(r300ContextPtr r300)
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r300->hw.at.cmd[R300_AT_CMD_0] = cmducs(R300_PP_ALPHA_TEST, 1);
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ALLOC_STATE( unk4BD8, always, 2, "unk4BD8", 0 );
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r300->hw.unk4BD8.cmd[0] = cmducs(0x4BD8, 1);
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ALLOC_STATE( fpp, variable, R300_FPP_CMDSIZE, "fpp", 0 );
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r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmducs(R300_PFS_PARAM_0_X, 0);
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ALLOC_STATE( unk4E00, always, 2, "unk4E00", 0 );
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r300->hw.unk4E00.cmd[0] = cmducs(0x4E00, 1);
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ALLOC_STATE( bld, always, R300_BLD_CMDSIZE, "bld", 0 );
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@ -477,6 +481,7 @@ void r300InitCmdBuf(r300ContextPtr r300)
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insert_at_tail(&r300->hw.atomlist, &r300->hw.unk43A4);
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insert_at_tail(&r300->hw.atomlist, &r300->hw.unk43E8);
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insert_at_tail(&r300->hw.atomlist, &r300->hw.fp);
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insert_at_tail(&r300->hw.atomlist, &r300->hw.fpt);
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insert_at_tail(&r300->hw.atomlist, &r300->hw.unk46A4);
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insert_at_tail(&r300->hw.atomlist, &r300->hw.fpi[0]);
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insert_at_tail(&r300->hw.atomlist, &r300->hw.fpi[1]);
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@ -486,6 +491,7 @@ void r300InitCmdBuf(r300ContextPtr r300)
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insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4BC8);
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insert_at_tail(&r300->hw.atomlist, &r300->hw.at);
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insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4BD8);
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insert_at_tail(&r300->hw.atomlist, &r300->hw.fpp);
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insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4E00);
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insert_at_tail(&r300->hw.atomlist, &r300->hw.bld);
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insert_at_tail(&r300->hw.atomlist, &r300->hw.cmk);
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@ -645,61 +651,3 @@ e32(RADEON_CP_PACKET2);
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e32(RADEON_CP_PACKET2);
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#endif
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}
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void r300EmitPixelShader(r300ContextPtr rmesa)
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{
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int i,k;
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LOCAL_VARS
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if(rmesa->state.pixel_shader.program.tex.length>0){
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reg_start(R300_PFS_TEXI_0, rmesa->state.pixel_shader.program.tex.length-1);
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for(i=0;i<rmesa->state.pixel_shader.program.tex.length;i++)
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e32(rmesa->state.pixel_shader.program.tex.inst[i]);
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}
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if(rmesa->state.pixel_shader.program.alu.length>0){
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#define OUTPUT_FIELD(reg, field) \
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reg_start(reg,rmesa->state.pixel_shader.program.alu.length-1); \
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for(i=0;i<rmesa->state.pixel_shader.program.alu.length;i++) \
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e32(rmesa->state.pixel_shader.program.alu.inst[i].field);
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OUTPUT_FIELD(R300_PFS_INSTR0_0, inst0);
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OUTPUT_FIELD(R300_PFS_INSTR1_0, inst1);
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OUTPUT_FIELD(R300_PFS_INSTR2_0, inst2);
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OUTPUT_FIELD(R300_PFS_INSTR3_0, inst3);
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#undef OUTPUT_FIELD
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}
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reg_start(R300_PFS_NODE_0, 3);
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for(i=0;i<4;i++){
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e32( (rmesa->state.pixel_shader.program.node[i].alu_offset << R300_PFS_NODE_ALU_OFFSET_SHIFT)
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| (rmesa->state.pixel_shader.program.node[i].alu_end << R300_PFS_NODE_ALU_END_SHIFT)
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| (rmesa->state.pixel_shader.program.node[i].tex_offset << R300_PFS_NODE_TEX_OFFSET_SHIFT)
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| (rmesa->state.pixel_shader.program.node[i].tex_end << R300_PFS_NODE_TEX_END_SHIFT)
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| ( (i==3) ? R300_PFS_NODE_LAST_NODE : 0)
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);
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}
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reg_start(R300_PFS_CNTL_0, 2);
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/* PFS_CNTL_0 */
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e32((rmesa->state.pixel_shader.program.active_nodes-1) | (rmesa->state.pixel_shader.program.first_node_has_tex<<3));
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/* PFS_CNTL_1 */
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e32(rmesa->state.pixel_shader.program.temp_register_count);
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/* PFS_CNTL_2 */
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e32( (rmesa->state.pixel_shader.program.alu_offset << R300_PFS_CNTL_ALU_OFFSET_SHIFT)
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| (rmesa->state.pixel_shader.program.alu_end << R300_PFS_CNTL_ALU_END_SHIFT)
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| (rmesa->state.pixel_shader.program.tex_offset << R300_PFS_CNTL_TEX_OFFSET_SHIFT)
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| (rmesa->state.pixel_shader.program.tex_end << R300_PFS_CNTL_TEX_END_SHIFT)
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);
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if(rmesa->state.pixel_shader.param_length>0){
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reg_start(R300_PFS_PARAM_0_X, rmesa->state.pixel_shader.param_length*4-1);
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for(i=0;i<rmesa->state.pixel_shader.param_length;i++){
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efloat(rmesa->state.pixel_shader.param[i].x);
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efloat(rmesa->state.pixel_shader.param[i].y);
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efloat(rmesa->state.pixel_shader.param[i].z);
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efloat(rmesa->state.pixel_shader.param[i].w);
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}
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}
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}
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@ -300,10 +300,18 @@ struct r300_state_atom {
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#define R300_FP_NODE3 8
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#define R300_FP_CMDSIZE 9
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#define R300_FPT_CMD_0 0
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#define R300_FPT_INSTR_0 1
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#define R300_FPT_CMDSIZE 65
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#define R300_FPI_CMD_0 0
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#define R300_FPI_INSTR_0 1
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#define R300_FPI_CMDSIZE 65
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#define R300_FPP_CMD_0 0
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#define R300_FPP_PARAM_0 1
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#define R300_FPP_CMDSIZE (32*4+1)
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#define R300_AT_CMD_0 0
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#define R300_AT_ALPHA_TEST 1
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#define R300_AT_CMDSIZE 2
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@ -398,12 +406,14 @@ struct r300_hw_state {
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struct r300_state_atom unk43A4; /* (43A4) */
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struct r300_state_atom unk43E8; /* (43E8) */
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struct r300_state_atom fp; /* fragment program cntl + nodes (4600) */
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struct r300_state_atom fpt; /* texi - (4620) */
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struct r300_state_atom unk46A4; /* (46A4) */
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struct r300_state_atom fpi[4]; /* fp instructions (46C0/47C0/48C0/49C0) */
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struct r300_state_atom unk4BC0; /* (4BC0) */
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struct r300_state_atom unk4BC8; /* (4BC8) */
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struct r300_state_atom at; /* alpha test (4BD4) */
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struct r300_state_atom unk4BD8; /* (4BD8) */
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struct r300_state_atom fpp; /* 0x4C00 and following */
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struct r300_state_atom unk4E00; /* (4E00) */
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struct r300_state_atom bld; /* blending (4E04) */
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struct r300_state_atom cmk; /* colormask (4E0C) */
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@ -298,8 +298,8 @@ static GLboolean r300_run_immediate_render(GLcontext *ctx,
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| R300_VPORT_Y_SCALE_ENA
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| R300_VPORT_Y_OFFSET_ENA
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| R300_VTX_W0_FMT;
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#endif
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R300_STATECHANGE(rmesa, vte);
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#endif
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/* Magic register - note it is right after 20b0 */
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@ -308,15 +308,12 @@ static GLboolean r300_run_immediate_render(GLcontext *ctx,
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reg_start(0x20b4,0);
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e32(0x0000000c);
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assign_pipeline(rmesa, &SINGLE_TEXTURE_PIPELINE);
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} else {
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assign_pipeline(rmesa, &FLAT_COLOR_PIPELINE);
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}
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r300SetupVertexShader(rmesa);
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r300SetupPixelShader(rmesa);
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r300EmitState(rmesa);
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r300EmitPixelShader(rmesa);
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#if 0
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reg_start(R300_RB3D_COLORMASK, 0);
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@ -1175,6 +1175,78 @@ void r300SetupVertexShader(r300ContextPtr rmesa)
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#endif
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}
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void r300SetupPixelShader(r300ContextPtr rmesa)
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{
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int i,k;
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/* This needs to be replaced by pixel shader generation code */
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/* Watch out ! This is buggy .. but will do for now */
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/* At least one sanity check is in order */
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if(sizeof(rmesa->state.pixel_shader) != sizeof(FLAT_COLOR_PIPELINE.pixel_shader)){
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fprintf(stderr, "Aieee ! pixel_shader sizes don't match.\n");
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exit(-1);
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}
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/* textures enabled ? */
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if(rmesa->state.texture.tc_count>0){
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memcpy(&rmesa->state.pixel_shader, &(SINGLE_TEXTURE_PIPELINE.pixel_shader), sizeof(rmesa->state.pixel_shader));
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} else {
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memcpy(&rmesa->state.pixel_shader, &(FLAT_COLOR_PIPELINE.pixel_shader), sizeof(rmesa->state.pixel_shader));
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}
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R300_STATECHANGE(rmesa, fpt);
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for(i=0;i<rmesa->state.pixel_shader.program.tex.length;i++)
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rmesa->hw.fpt.cmd[R300_FPT_INSTR_0+i]=rmesa->state.pixel_shader.program.tex.inst[i];
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rmesa->hw.fpt.cmd[R300_FPT_CMD_0]=cmducs(R300_PFS_TEXI_0, rmesa->state.pixel_shader.program.tex.length);
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#define OUTPUT_FIELD(st, reg, field) \
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R300_STATECHANGE(rmesa, st); \
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for(i=0;i<rmesa->state.pixel_shader.program.alu.length;i++) \
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rmesa->hw.st.cmd[R300_FPI_INSTR_0+i]=rmesa->state.pixel_shader.program.alu.inst[i].field;\
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rmesa->hw.st.cmd[R300_FPI_CMD_0]=cmducs(reg, rmesa->state.pixel_shader.program.alu.length);
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OUTPUT_FIELD(fpi[0], R300_PFS_INSTR0_0, inst0);
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OUTPUT_FIELD(fpi[1], R300_PFS_INSTR1_0, inst1);
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OUTPUT_FIELD(fpi[2], R300_PFS_INSTR2_0, inst2);
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OUTPUT_FIELD(fpi[3], R300_PFS_INSTR3_0, inst3);
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#undef OUTPUT_FIELD
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R300_STATECHANGE(rmesa, fp);
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for(i=0;i<4;i++){
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rmesa->hw.fp.cmd[R300_FP_NODE0+i]=
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(rmesa->state.pixel_shader.program.node[i].alu_offset << R300_PFS_NODE_ALU_OFFSET_SHIFT)
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| (rmesa->state.pixel_shader.program.node[i].alu_end << R300_PFS_NODE_ALU_END_SHIFT)
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| (rmesa->state.pixel_shader.program.node[i].tex_offset << R300_PFS_NODE_TEX_OFFSET_SHIFT)
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| (rmesa->state.pixel_shader.program.node[i].tex_end << R300_PFS_NODE_TEX_END_SHIFT)
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| ( (i==3) ? R300_PFS_NODE_LAST_NODE : 0);
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}
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/* PFS_CNTL_0 */
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rmesa->hw.fp.cmd[R300_FP_CNTL0]=
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(rmesa->state.pixel_shader.program.active_nodes-1)
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| (rmesa->state.pixel_shader.program.first_node_has_tex<<3);
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/* PFS_CNTL_1 */
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rmesa->hw.fp.cmd[R300_FP_CNTL1]=rmesa->state.pixel_shader.program.temp_register_count;
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/* PFS_CNTL_2 */
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rmesa->hw.fp.cmd[R300_FP_CNTL2]=
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(rmesa->state.pixel_shader.program.alu_offset << R300_PFS_CNTL_ALU_OFFSET_SHIFT)
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| (rmesa->state.pixel_shader.program.alu_end << R300_PFS_CNTL_ALU_END_SHIFT)
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| (rmesa->state.pixel_shader.program.tex_offset << R300_PFS_CNTL_TEX_OFFSET_SHIFT)
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| (rmesa->state.pixel_shader.program.tex_end << R300_PFS_CNTL_TEX_END_SHIFT);
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R300_STATECHANGE(rmesa, fpp);
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for(i=0;i<rmesa->state.pixel_shader.param_length;i++){
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rmesa->hw.fpp.cmd[R300_FPP_PARAM_0+4*i+0]=r300PackFloat32(rmesa->state.pixel_shader.param[i].x);
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rmesa->hw.fpp.cmd[R300_FPP_PARAM_0+4*i+1]=r300PackFloat32(rmesa->state.pixel_shader.param[i].y);
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rmesa->hw.fpp.cmd[R300_FPP_PARAM_0+4*i+2]=r300PackFloat32(rmesa->state.pixel_shader.param[i].z);
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rmesa->hw.fpp.cmd[R300_FPP_PARAM_0+4*i+3]=r300PackFloat32(rmesa->state.pixel_shader.param[i].w);
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}
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rmesa->hw.fpp.cmd[R300_FPP_CMD_0]=cmducs(R300_PFS_PARAM_0_X, rmesa->state.pixel_shader.param_length);
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}
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/**
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* Called by Mesa after an internal state update.
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*/
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@ -1225,6 +1297,7 @@ void r300ResetHwState(r300ContextPtr r300)
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r300_setup_rs_unit(ctx);
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r300SetupVertexShader(r300);
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r300SetupPixelShader(r300);
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r300_set_blend_state(ctx);
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r300AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
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